Volume One

IN-DEPTH ARTICLES Microcontrollers Improve Power Efficiency of 8051-Based Designs 3

Behind the Light Show in Optical Transceivers 11

Securing Electronic Transactions Using SHA-1 15

DESIGN SHOWCASE An EconOscillator to Clock an 8051 Microprocessor 18

Dissecting the Versatile Dallas 1-Wire Network 21

Microcontrollersimprove powerefficiency of 8051-based designsPortable products continue to advance in features andcapabilities. Customers are demanding more performanceout of their products, which requires greater computingpower. At the same time, they want products with lesspower consumption. At the heart of these competingdemands is the microcontroller, which is typically one ofthe largest power consumers in portable instruments.

While many low-power processors exist, they are oftenlimited in performance. The high-speed microcontrollerfamily from Dallas Semiconductor is a good compromiseof power and performance. It is based on the 8051 archi-tecture—one of the most popular microcontrollers in theworld. Designers prize its ease of use, rich I/O structure,and wide acceptance. Its prevalence has carried over intothe portable arena, where it has found a home in manyapplications.

This article addresses approaches to minimizing powerconsumption using 8051 controllers, with emphasis onnew architectural improvements that can extend thebattery life of high-performance 8051-based designs.Integrating peripherals on-chip and selecting the properclock source are discussed as ways to reduce powerconsumption. Software techniques for power conservationare presented, as well as a method of reducing powerconsumption in systems that use Stop mode.

Clock speed

The most important factor in determining powerconsumption in any microcontroller design is the systemclock speed. The power consumption of complementarymetal oxide semiconductor (CMOS) devices is directlyproportional to clock speed. It follows, then, that it isbeneficial from a power standpoint to run a processor atthe slowest speed possible.

Figure 1 shows a typical power curve for a generic 8051microcontroller, a relationship known to all portablesystem designers. In general, the current vs. frequencycharacteristic is linear, with a DC offset. This quiescentcurrent is caused by static circuitry on-chip, such ascomparators, operational amplifiers, etc. While this

number is typically small (<1mA), it is a constant drainthat needs to be considered.

Any power-conscious design will attempt to run asslowly as possible. Determination of the minimumsystem frequency, and hence minimum power consump-tion, is dependent on a number of factors, includingdesired performance and interrupt latency. Whatevercriteria are used, however, the end goal is the same:match the operating frequency of the device as closely aspossible to the requirements of the application.

High-speed core

The most direct approach to decreasing power consump-tion of an 8051-based design is to improve the efficiencyof the microcontroller. The original design of the 8051was based on a 12-clock, 2-fetch-per-machine cyclearchitecture. The high-speed microcontroller family,however, uses a 4- or 1-clock per machine cycle core. Itis more computationally efficient and requires fewerclock cycles to execute an instruction, resulting in fasterexecution times and increased maximum clock rates.

Although the advantages of a high-speed core areusually considered in terms of performance, they haveimportant implications for power consumption as well.When the instruction execution of the processor isoptimized, it takes less time to accomplish the sametask. Many portable products operate in a burst mode,characterized by brief periods of activity, such asrecording environmental data or scanning a bar code,followed by long period of inactivity. Reducing the timethat the processor must be active achieves a corre-sponding reduction in energy consumption.

3

Figure 1. Typical power curve for generic 8051 microcontroller.

0

5

10

15

20

25

1 179 1353 1911 1572 1810 1464 12 168 20

TYPICAL 8051 ICCvs. FREQUENCY CHARACTERISTICS

OPERATING FREQUENCY (MHz)

CURR

ENT

CONS

UMPT

ION

(mA)

4

Another consequence of this improved efficiency is thatcomparable performance can be achieved while reducingclock speed. If a redesigned core uses 4 clocks per cyclerather than 12, this means that the same work can beaccomplished at a reduced crystal speed. Because powerconsumption is directly proportional to crystal speed,power consumption can be reduced without sacrificingperformance.

Figure 2 shows the power consumption of three micro-controllers performing the same task with the same levelof performance. Two microcontrollers are standard80C3x derivatives operating at 12 external clocks permachine cycle, while the second is a DS80C320 micro-controller operating at 4 clocks per machine cycle.Current consumption was measured for all devices andthen compared, assuming a conservative performanceimprovement of 250% (2.5x) for the DS80C320. As isevident from the figure, the reduced clock per cycle coreexhibits a significant current reduction at the samethroughput, most notably at high performance levels.

Integration

Integrating peripherals on-chip is a method of powerconservation. When driving a signal off-chip, the gener-ating device must contend with the switching powerrequired to drive the external loads and any DC losses.Switching power, PSW, is the power consumed when adigital signal changes. The switching power can beapproximated as follows:

PSW α CV2/T (1)

where C is the lumped capacitance of the receiving gateinput buffer and the interconnection between the two

gates, and T is the clock period of the signal. A typicalinput capacitance for a CMOS input is 10pF. Although itis difficult to calculate an exact value of the switchingpower for a system, it is obvious that each additionalexternal load or pin that the microcontroller must driveconsumes additional power.

Microcontroller-based systems typically use a number ofperipherals. These range from external UARTs and power-on reset circuitry to watchdog timers. One of the strengthsof the 8051 product family is the large number of periph-eral functions that are available on-chip. In addition tosimplifying a design by eliminating components, inte-grated peripherals also can reduce power consumption.One can assume that the core functionality of any periph-eral consumes the same amount of power whether locatedinternal or external to the processor. Locating a peripheralon-chip, however, will eliminate the switching powerlosses associated with driving an external bus.

Internal program memory

Another 8051 feature that is not commonly perceived asa peripheral is program memory. All 8051 derivativesincorporate various amounts of on-chip programmemory. This is desired by many system designers as amethod of reducing the component count and boardarea, but it also improves battery life in portablesystems. As mentioned previously, this will reducepower consumption by eliminating the need to drive anexternal bus. There is an additional power savings whenusing on-chip memory. The 8051 architecture requiresthe use of a 74373-type latch to demultiplex the lowerbyte of address. Figure 3 compares the use of internalvs. external program memory. The first uses aDS87C520 High-Speed Microcontroller with a74AC573 latch and a 27C256 EPROM with an accesstime of 70ns. The second system uses the same micro-controller, but operating from internal memory. Bothsystems are operating at 11.0592MHz, executing a short,generic program. From the figure, it is apparent that asmuch as 49mA can be saved at high frequencies by elim-inating the external EPROM and latch from the system.

Internal data memory

As previously mentioned, the use of on-chip memoryinstead of external RAM will save power. The enlargedscratchpad of the 80C32 derivatives (256 bytes) is suffi-cient for stack operations and some data storage in smallprograms, eliminating the need for external RAM.

Figure 2. Reduced clock cycle core uses less current for samethroughput.

0

5

10

15

20

25

1 179 1353 1911 1572 1810 1464 12 168 20

RELATIVE POWER CONSUMPTION

PERFORMANCE RELATIVE TO 1MHz 8051

I CC

(mA)

80C3280C31

DS80C320

For designs requiring more data memory or needing toimplement an external stack, however, additional SRAMmay be required. Although low-power SRAMs areavailable, their power consumption must also includethat associated with a 74373 series latch as well ascapacitive losses driving the external bus. This can bemitigated by using devices with expanded on-chipRAM. Figure 4 shows the power consumption of twosystems using SRAM mapped into the 8051 MOVX dataspace. The first uses a DS87C520 high-speed microcon-troller with a 74AC573 latch and a DS2064 SRAM. Thesecond system uses the same microcontroller but uses1Kbyte of internal MOVX data memory. Both micro-controllers are operating at 11.0592MHz, executing ashort, generic program that reads and writes to MOVXdata memory. From the figure, it is apparent that asmuch as 9mA can be saved at high frequencies by elimi-nating the external SRAM and latch from the system.

Clock source

Another critical system component from a power stand-point is the clock source. Standard 8051 designs typicallyeither excite an external quartz crystal with an internaloscillator amplifier or use an external crystal oscillator. Ifan external crystal oscillator is used, the waveform of theclock can affect power consumption. The input stage ofthe XTAL1 pin, used to drive external clock signals intoan 8051, typically employs complementary drivers. Asthe input clock transitions between high and low, thedrivers will momentarily both be on, causing a significantcurrent rush. With a square wave, the transition betweenhigh and low states is almost instantaneous, and the timein which both devices are on is minimized. A waveform

with a slower rise and fall time, such as a sine or trianglewave, will take longer to complete the transition and willspend more time with both drivers on. This will increasecurrent and power consumption.

Figure 5 shows the relationship of current consumptionto the waveform shape. The clock source was aprogrammable waveform generator, with the ability tooutput sine, triangle, or square waves. The currentconsumption shown is an average of four devices, bothtraditional and high-speed core. The comparison showsthat current consumption is directly proportional to therise (and fall) time of the clock waveform. The trianglewave has the lowest slope and the square wave thehighest slope. The square wave averages 0.75mA lessthan the triangle wave. This implies that currentconsumption in external clock oscillator designs can bereduced by using oscillators with fast rise and fall times.This becomes even more important at lower frequencies,when the device spends more time in transition.

Some 8051 derivatives incorporate an on-chip internalring oscillator. This is typically a chain of inverters thatpropagates a pulse around it. This provides an internalclock source of approximately 2MHz to 4MHz, capableof operating the device. Because it does not require theuse of a crystal, it is a very-low-power clock source.Characterization of a DS87C520 high-speed microcon-troller shows that operation from the ring oscillator candeliver performance comparable to a 7MHz 8051 atapproximately 3.6mA. Although ring oscillators do notexhibit the stability of piezoelectric crystals, their lowpower and negligible power-on delay make them asignificant factor in a power management scheme.

5

Figure 3. Using internal memory significantly reduces currentconsumption.

0

50

40

30

20

10

60

70

80

90

1 17 2595 21133 19 27117 2315 29

COMPARISON OF EXTERNALvs. INTERNAL EPROM

FREQUENCY (MHz)

I CC

(mA)

EXTERNAL

INTERNAL

Figure 4. Eliminating internal SRAM and latch saves power.

0

45

40

35

30

25

20

15

10

5

1 17 2595 21133 19 27117 2315 29

COMPARISON OF EXTERNALvs. INTERNAL SRAM

FREQUENCY (MHz)

I CC

(mA)

EXTERNAL

INTERNAL

Clock management

As mentioned previously, the operating frequency of themicrocontroller is the single largest factor affecting thepower consumption of the device. Although the systemclock frequency is primarily a hardware function, the8051 has the ability to exercise limited control over it.These methods rely on slowing or halting the internaloperating frequency of all or part of the device.Traditional 8051 architecture has used two clock controlmodes: Idle and Stop.

Improving stop mode

Stop mode is the lowest power state available to 8051designers. In this mode, the internal crystal amplifier isstopped, halting operation of the device. Exiting fromStop mode is typically initiated by an external reset.Some variants also support exiting from Stop modeusing external interrupts.

One of the disadvantages associated with Stop mode isthe power consumed during the “dead time” while thecrystal is resuming operation. A crystal oscillator relieson the motion of a quartz crystal for its operation.Physical limitations require a finite amount of time forthe crystal oscillation to achieve sufficient amplitude fordevice operation. This warm-up period is encounteredregardless of whether the clock source is an externalcrystal and internal crystal amplifier, or whether anexternal crystal oscillator is used. This time can be onthe order of 3ms to 12ms, depending on the characteris-tics of the crystal and associated amplifier.

The effect of the warm-up period on power consumptionis that while the device is not performing any usefulwork during this period, it is still consuming power. This

can become significant if the device is entering andexiting Stop mode frequently, or is exiting Stop mode toperform short tasks. In fact, if the task is very short(<5ms), the crystal restart period can consume morepower than the task itself. If a ring oscillator is used toperform a “quick start” from Stop mode, this delay canbe avoided. This will greatly reduce the amount ofpower when out of Stop mode.

Figure 6 shows the operation of two systems exitingfrom Stop mode and performing a short task. One deviceincorporates an internal ring oscillator, and the otheruses a traditional external crystal. The device withoutthe ring oscillator must endure a crystal warm-up period.During this time the device continues to consume power,but no useful work is done. The second device is aDS87C520 high-speed microcontroller that incorporatesan internal ring oscillator. This allows the device toresume operation immediately when exiting Stop mode.In this example, the routine to be executed is less than4ms in duration at approximately 2MHz. As can be seenin the figure, energy consumption can be greatly reducedby using a ring oscillator to perform short tasks whenexiting Stop mode.

In some applications, the stability of a crystal oscillatormay be required shortly after exiting Stop mode. In thiscase, the ring oscillator can still be advantageous.Immediately upon exiting Stop mode, the device shouldrestart the crystal oscillator. The device can theninitialize any data or registers necessary while the crystalis still warming up. Most high-speed microcontrollersincorporate a status bit that indicates whether the crystaloscillator has stabilized or not. Once the initializationroutine for the crystal oscillator code is complete, thesoftware can poll the status bit to determine when thehigh-precision timing operation can commence.

Another method of improving Stop mode efficiency is touse an interrupt to exit instead of reset. This allows theprocessor to resume operation immediately with theinstruction following the setting of the STOP bit, insteadof having to restart from the reset vector. This eliminatesthe need to determine the cause of the reset and allows theprocessor to begin performing useful work in less time.

Idle mode

Idle mode is the second clock management mode used inoriginal 8051 architecture. This mode halts operation ofthe CPU, but keeps the on-chip, general-purpose timersoperational. In a power-sensitive application, thesetimers are used to periodically wake the device toperform a task or to poll if a task should be performed.

6

Figure 5. Oscillator waveforms with sharper edges reduce powerconsumption.

0

5

10

15

20

25

1 5 1510 20

WAVEFORM vs. ICC COMPARISON

FREQUENCY (MHz)

I CC

(mA) SINE

TRIANGLE

SQUARE

Because standard 8051 timers are limited to 16 bits, thisallows a maximum timeout period of 31ms at a clockrate of 16MHz. If longer periods are needed, multipletimer overflows will be required. This will consumeadditional power because the device must resume fulloperation occasionally to increment a counter but notperform any useful work.

For longer periods, use an internal timer with a longerperiod. Some 8051 derivatives incorporate a watchdogtimer, which can also be used to awaken the device.Watchdog timers can be programmed for long time-outperiods, on the order of 226 clock cycles. This wouldallow a maximum timeout period of 4.2 seconds at16MHz. As an example, assume an application wishes toawake from a low power state every 3 seconds toperform a task. If the internal timers are used to time theoperation, the device would have to exit Idle mode 96times without doing useful work. If a watchdog timerwith a long timeout is used, the device would only exitIdle mode once, perform the task, and return to the low-power state.

One other option is to use a microcontroller with a real-time clock (RTC). The DS87C530 high-speed microcon-troller incorporates an RTC capable of generating analarm period as long as 24 hours. The internal interruptgenerated by this alarm can cause the device to exit Idleor Stop mode. Using an RTC to exit Stop mode is the

most efficient way to suspend device operation for longperiods of time.

Power management modes

Although Idle mode reduces power consumption byhalting program execution, the internal timers continue tooperate at the external clock frequency. This consumes aconsiderable amount of power, considering the timers arebasically operating in a “standby” capacity.

A better approach is to reduce the clock rate of the entiredevice. This can be done with an internal clock divisor,which divides the external clock frequency before itenters the CPU. Such a scheme has been implemented inthe DS87C520 High-Speed Microcontroller. This deviceemploys two clock divisor functions: PowerManagement Mode 1, which divides the input clocksource by 64, and Power Management Mode 2, whichdivides the input clock source by 1024. These modes areenabled by setting the appropriate bits in a SpecialFunction Register.

Figure 7 shows a comparison of the clock divisor andclock control modes on the DS87C520 High-SpeedMicrocontroller. The figure contrasts the currentconsumption in full speed (divide by 4), PowerManagement Mode 1 (divide by 64), PowerManagement Mode 2 (divide by 1024), Idle mode, and

7

Figure 6. Comparison of stop mode exit with and without ring.

µC OPERATING µC OPERATING 1

POWERCONSUMPTION

POWER SAVED 2

CRYSTALOSCILLATION

STOP MODE EXIT WITH RING OSCILLATOR START-UP

RINGOSCILLATION

INTx

µC HALTED µC HALTED

ENTER STOPMODE

EXIT STOPMODE

ENTER STOPMODE

µC OPERATING CRYSTAL WARM UP1

1 CRYSTAL WARM UP PERIOD IS 4MS TO 10MS DEPENDING ON CRYSTAL TYPE AND SPEED.

POWERCOMSUMPTION

CRYSTALOSCILLATION

STOP MODE EXIT WITHOUT RING OSCILLATOR START-UP

INTx

µC HALTED

ENTER STOPMODE

EXIT STOPMODE

ENTER STOPMODE

CLOCKSTABLE

2ADDITIONAL POWER SAVINGS DUE TO DECREASED RING OSC. CURRENT COMPARED TO CRYSTAL AMPLIFIER.

µC HALTEDµC OPERATING

Stop Mode. As expected, Stop mode draws the leastcurrent, because all internal clocking is halted. One inter-esting result of this comparison is that the two powermanagement modes draw less current than Idle mode.This not only allows the device to conserve power, butpermits it to function continuously at a low level ofoperation. In the traditional 8051 architecture, performingany type of CPU activity was “all or nothing.” A devicewas forced to operate constantly at the highest perfor-mance level, even if high performance was only requiredfor short periods. This unnecessarily increased powerconsumption. The use of power management modes(PMM) allows the device (and system) to match its powerconsumption to the level of performance needed.

Using interrupts with PMM

One possible consequence of using an internal clockdivisor is that interrupt latencies may be greatlyincreased. In addition, slowing the internal timers wouldaffect the ability of the 8051 serial ports to generate orsynchronize with a standard baud rate. This couldseriously interfere with the device’s ability to respond toexternal stimuli. One solution is to incorporate a featurethat automatically restores the device to full operationwhen an external interrupt or serial port activity is recog-nized. Such a mechanism has been implemented in theDS87C520. That device’s Switchback feature allows thedevice to respond quickly to external interrupts. As soonas the interrupt is acknowledged, the device will auto-matically switch back to full speed (divide by 4) withoutsoftware intervention.

The serial ports operate in a similar fashion. Uponreceipt of a falling edge (start bit) on a serial port

reception pin, the device will automatically switch backto full speed (divide by 4). Because this happens imme-diately at the start of the transmission, the device will beat full speed to correctly receive the rest of the transmis-sion. With a traditional 8051 architecture, the only wayto use the serial ports in a low-power configuration waswith the Idle mode. The use of Power ManagementModes provides a lower power alternative.

Improving burst mode operation

A common mode of operation in power-consciousdesigns is to have the system awake from Stop mode,perform a burst of activity, and then return to Stopmode. One way to decrease power consumption in sucha system is to increase the operating frequency. At first,this may seem counter-intuitive. For the time in whichthe device is operating, it will consume more power thana system operating at a lower frequency. The quiescentcurrent consumed while the system is operating,however, is not a function of frequency. In the finalsystem design, energy is typically evaluated todetermine battery life. This distinction is important whenevaluating a high-performance microcontroller becauseit combines the concept of time and processing power. Ifthe product of power and time is smaller for a givensystem, then it will require less energy, regardless of theindividual terms. In many instances, it can be shown thata high-speed microcontroller can actually reduce energyconsumption by running fast for short periods, as opposedto running more slowly for a longer period of time.

This can be demonstrated by re-examining Figure 7.Assume that upon resuming from Stop mode, aDS87C520 must read an I/O port, perform a mathemat-ical computation, and output the result to another port,requiring 500 machine cycles of CPU time. From thefigure, the current consumption is 12.4mA at 10MHz,and 34.6mA at 30MHz. Table 1 summarizes the resultsof the task at both speeds. As can be seen from the table,operation at 30MHz is the most energy efficient, with amore than 6% reduction in energy consumed.

Hurry up and wait

In many applications, the time out of Stop mode is notentirely speed-dependent. Frequently, a device will haveto access a peripheral with a fixed response time, such asan A/D converter or thermostat. In such a case, themicrocontroller will have a burst of activity, typically toinitiate a process, followed by a period of little or noactivity. In such a case, a combination of power conser-vation techniques can be effective.

8

Figure 7. Full/Idle/Power Management Mode Comparison

0

35

30

25

20

15

10

5

1 17 2595 21133 19 27117 2315 29

FULL/IDLE/POWER MANAGEMENTMODE COMPARISON

FREQUENCY (MHz)

I CC

(mA)

XTAL/4

XTAL/1024XTAL/64IDLE

A practical example can illustrate the advantage of a high-speed microcontroller with PMM in such a system.Suppose that the DS87C520 is interfaced to a DS1620digital thermometer and thermostat. This device isaddressed serially using a standard 8051 serial portoperating in mode 0. A host processor will occasionallywake the DS87C520 from Stop mode using an externalinterrupt and request that it read the temperature from theDS1620. After the data has been retrieved, the DS87C520will store it in internal memory to be transmitted later.The DS1620 functions similarly to many A/D converters:a command is issued to start a conversion, then there is adelay while the conversion is completed, then the data isshifted out. In the case of the DS1620, conversion time isapproximately 1 second. The device is polled to determinewhen the conversion is complete. The DS87C520 is wellsuited to such a task because it can perform the initializa-tion and computation functions quickly. The device can

then place itself in PMM while waiting for the conversionto complete. In a conventional 8051, Idle mode would beused to place the conventional 8051 in a low-power stateonce the conversion was started. The use of this modeallows an internal 16-bit timer to measure the conversionperiod. Operating at 16MHz, the conventional 8051 couldrequire exiting Idle mode as many as 32 times before theconversion was complete.

One further improvement can be made in this example.Because the DS1620 is addressed as a synchronousdevice, high precision timing operations are notrequired. As a result, the microcontroller can operatefrom the ring oscillator while initiating and whenreading the results of the conversion. This results infurther power savings by eliminating the dead timeneeded to stabilize an external crystal.

Figure 8 illustrates the operation of two 8051 systemsimplementing the “hurry up and wait” schemes

9

Table 1. Energy consumed vs. processor speed for a 500 machine cycle task

Clock Machine Cycle Machine Cycles Total ICC Current TimeFrequency Period Required Time Product

10MHz 400ns 500 200s 12.41mA 2.48As

30MHz 133ns 500 66.5s 34.66mA 2.30As

Figure 8. Implementing an 8051 “Hurry Up and Wait” scheme.

POWERCONSUMPTION

CRYSTALOSCILLATION

RINGOSCILLATION

INTx

STOP MODE

ENTER STOPMODE

POWERCONSUMPTION

CRYSTALOSCILLATION

INTx

STOPMODE

STOP MODE

FULLSPEED POWER MANAGEMENT MODE 2

EXIT STOP MODE &RESUME OPERATION

FULLSPEED

- POWER SAVED vs. CONVENTIONAL 8051

RESUMEOPERATION

CRYSTALWARMUP

IDLE MODE STOPMODE

RE-ENTER STOPMODE

ENTER STOPMODE

EXIT STOPMODE

RE-ENTER STOPMODE

PMM/RING OSCILLATOR BURST MODE OPERATION

CONVENTIONAL 8051 BURST MODE OPERATION

mentioned above. As can be seen from the figure, thereis a significant power savings during program executionfollowing the exit from Stop Mode. In addition to thepower saved by using PMM2 instead of Idle mode, theelimination of the crystal warm-up period means that theroutine can return to Stop mode more quickly. Runningfrom the ring oscillator during the 1-second conversiondelay slows the processor speed even more, allowing forgreater power savings.

Summary

The 8051 microcontroller family remains one of themost popular processors in the world. Its ease of use andrelatively high performance make it ideal for manyapplications, including portable and handheld products.The introduction of Dallas Semiconductor high-speedmicrocontrollers allows a way for existing 8051 designsto improve their power efficiency without a costlyredesign.

The benefits of the high-speed microcontrollers thatreduce power consumption can be summarized asfollows:

• A high performance CPU allows the processor clockto be slowed, resulting in the same level of perfor-mance at less power. Alternatively, the performance ofan existing system can be increased without increasingpower consumption.

• The high-speed microcontroller incorporates featuressuch as watchdog timers, additional UARTs, andprecision reset circuits. External components consumemore power.

• The introduction of two new low-power modesprovides a low-power alternative to the Idle mode. Inaddition to reducing current consumption, powermanagement modes such as those used in theDS87C520 allow the processor to perform tasks suchas polling while in a low state. Conventional 8051architectures require the processor to operate at themaximum clock rate, even if only minimal processingpower is required.

• The benefits of a programmable clock rate and high-performance core can be combined with the Stopmode to greatly reduce power consumption. Exampleshave been presented that show how energy consump-tion can be reduced by matching the clock rate of thedevice to the desired performance level.

10

Behind the lightshow in opticaltransceivers In recent years, news about communications networkstechnology always seems to involve some pronounce-ment on the urgent need for more bandwidth. The factsstill bear repeating: an ever-growing number of peoplewith telephones, faxes, modems, and computers are,through the exchange of terabytes of digitized informa-tion (videos, images, modeling procedures, as well asdata and voice) demanding a larger share of the carrierspectrum. In response, high-tech communicationscompanies who thrive on growth are competing to feedthis appetite for bandwidth. Over the past decade, majorresources have gone into developing fiber-opticnetworks in which light waves transport information atrates of gigabits per second through optical fibers finerthan the human hair.

The stakes are very high. In a May 2000 news release,The Aberdeen Group (Boston, MA), an IT consultingfirm, predicted that “The optical network market,excluding SONET elements, will grow to $17.7 billionby 2003. The suppliers that can deliver the technologiesthat solve the problems that carriers face will be the onesto succeed.”

The use of the plural in “suppliers” and “technologies”highlights a key issue in this article.

The burgeoning communications network is highlycomplex. While a few large companies tend to dominatethe global deployment of the optical network, behind thescenes there is a fusion of technologies developed bymultiple companies, each with specialized technologicalexpertise. Dallas Semiconductor falls into this lattercategory; we have designed a family of variable resistorsespecially for optical transceiver modules. A look atwhere Dallas’ resistors fit into the grand scheme ofcommunications networks reveals something about theway the communications industry develops solutions.

Identifying the big picture

Optical transceiver modules are designed and built by avariety of manufacturers. Applications for the modulesinclude Synchronous Optical NETwork (SONET) andSynchronous Digital Hierarchy (SDH), Asynchronous

Transfer Mode (ATM), Fiber Distributed Data Interface(FDDI), Fibre Channel, Fast Ethernet and GigabitEthernet. The names of these systems reflect the rangeof internationally defined transmission protocols andstandards. On the other hand, the modules themselveswere initially developed without definitive physicalcharacteristics.

Recognizing the need for conformity if their productswere to succeed, a group of manufacturers bandedtogether and developed a multi-source agreement (MSA)for transceiver modules in 1998. The group consisted ofAMP Incorporated, Hewlett-Packard Company, LucentTechnologies Microelectronics Group, Nortel (NorthernTelecom), Siemens AG-Fiber Optics, and SumitomoElectric Lightwave Corp. These parties agreed to cut thesize of their modules in half (to 0.535 inch in width) andspecified a set of module packages and pin-outs thatwould be interchangeable among the variety of RJ-45-style (including duplex LC, MT-RJ, and SC/DC) opticalconnectors used in high-speed fibre-channel applications.

Currently, a new consortium is drafting a new MSA fortransceiver modules, reflecting a larger contingent ofmanufacturers and a new generation of modules. Thesemulti-source manufacturers now include AgilentTechnologies, Glaze Network Products, E2OCommunications, Finisar, Fujikura Technology America,Hitachi Cable, Infineon Technologies, IBM, LucentTechnologies, Molex, OCP, Picolight, Stratos Lightwave,Sumitomo Electric Lightwave, and Tyco Electronics. Themodule specification is now called small form-factorpluggable (SFP) and covers expected transmission ratesof up to 5.0Gb/s. The specifications reflect the industry’sdrive for high-density signal transmission in hot-pluggable modules of smaller size and higher speed.

To find where our resistors come into the picture, it helpsto understand some basics about the transceiver module.The module converts incoming light waves to electricalsignals and outgoing electrical signals back to light. Offundamental significance, the optical transceiver is basedon semiconductor laser technology. The module is aprinted circuit board (PCB), and the optical source for thecoveted bandwidth is a tiny semiconductor chip: a light-emitting or laser diode. At frequencies in the near-infrared spectrum, the laser’s output can be modulated intens of GHz, a capacious bandwidth.

The following briefly summarizes a signal path throughthe transceiver module. The receiving port connects toincoming light fibers. A photodetector diode convertsthe light to electrical signals, which are then amplified

11

so that clock and data signals can be recovered, de-multiplexed, and sent out through the electricalinterface. The photodetector requires an automaticallypower-controlled bias circuit to provide a constantoperating voltage (see Figure 1). Meanwhile on thetransmitting side of the module, electrical clock anddata-bit signals are synthesized and latched and sent tothe laser driver. Finally, the laser driver sends the signalas electrical current to the laser diode, which convertselectron energy to light.

In some designs that use laser diodes, a photodetectormonitors the laser diode output and, in a feedback loop,reconverts the light back to electrical circuits thatmeasure the laser’s actual output power. This feedbackstabilizes the laser output power. The optical feedback isa complicating drawback to this design. However, thelatest laser technology, vertical cavity surface emittinglasers (VCSELs), often do not require a photodetectorbecause of exceedingly low current.

The laser driver must do two things: it must maintain aconsistent DC-bias current to set the laser operatingpoint, and it must maintain a modulation current to carrythe signal. As manufacturers strive to increase signalthroughput in transceivers, the laser source must becarefully characterized for operating constants in orderto control the light output.

The laser diode and VCSEL

The Fabry-Perot type of laser diode emits a coherentlight beam from the narrow, beveled edge of the chip,

with reflecting mirrors incorporated at the edges orstationed outside the chip. For the future of the commu-nications industry, however, a more promising lasersource is the VCSEL. As its name suggests, the VCSELvertically emits the laser beam from a circular cavity 5to 25 micrometers in diameter at the top (the bottom is afuture possibility) of the chip. The mirrors are incorpo-rated as an integrated array on both ends of the cavity—a design known as a “distributed Bragg reflector.” In thefuture, parallel optical interconnects using multi-elementVCSEL arrays could enable terabyte throughput.

Academic and corporate institutions are vigorouslydeveloping VCSEL designs for more widespreaddeployment. Compared to edge-emitters, the VCSELrequires less current and has a lower lasing threshold(1mA or 2mA versus 30mA). At this level, simplecurrent control is often sufficient without the extraphotodetector to monitor output. The VCSEL’s emittingaperture is measurably larger, which means that theoutput beam’s angle of divergence (a measure of disper-sion) is significantly smaller. There are several manufac-turing and processing advantages, as well. The die ismuch smaller, allowing more VCSELs to be packed on awafer with more interconnects; all the VCSELs on anentire wafer can be tested at once. Lastly, the VCSEL ismore robust in operation than a laser diode, with alonger life expectancy and lower failure rates.

Whether laser diode or VCSEL, the laser emitter in anyoptical transceiver is a semiconductor whose photoelec-tric effects depend on the interplay of current, voltage,and resistance. Some of the following factors affectsafety and performance:

• Laser output is exceedingly sensitive to temperature.

• Laser power output tends to change over the life of thelaser and this aging increases with temperature.

• As VCSELs operate at significantly lower power andtemperature than diodes, the failure rate over time isproportionately lower.

• The laser emitter needs to be protected from randompower transients as well as transients during power-onand power-off.

• Even though a laser’s near-infrared light is invisible tohumans, a beam entering the eye is still focused on theretina and can cause permanent damage. Because ofpotentially serious effects on personal safety and laserfunction, regulations require that laser power outputbe limited to a few hundred microwatts.

12

Figure 1. Average Power Control Loop—Typical average powercontrol circuit using a monitor photodiode and adjustableresistor to set bias current.

VREF

VAID

IBIAS

L

LASER

OPTICAL FEEDBACK

ADJUSTABLERESISTOR

TO SETIBIAS

MONITOR PHOTODIODE

OUTPUTLIGHT

POWER

IMONITOR

Controlling laser current is not only a safety issue inVCSELs and laser diodes, but it is also a factor inperformance. As is consistent with semiconductorbehavior, the VCSEL’s maximum output powerincreases linearly with decreasing temperatures;conversely, the output wavelength increases withincreasing temperatures. In short, controlling current inresponse to temperature is important in controllingperformance.

From the big-picture viewpoint, we can delineate theaccumulated facts as follows:

• Exploding demand for bandwidth leads to the devel-opment of optical networks.

• Optical networks use optical transceiver modules tophysically convert optical and electrical signals.

• Manufacturers of transceiver modules are driven todecrease physical size and increase signal throughputto multiple gigabits per second.

• Transceiver modules use photodiodes to receive lightsignals and laser diodes or VCSELs to send lightsignals.

• As data rates continually increase, modules’ photo-active components require ever more precise, reliablepower control in order to prevent laser failure, prolonglife expectancy, and/or operate within desired outputparameters.

This finally brings us to Dallas Semiconductor’svariable resistors. The way to control current throughlaser diodes and VCSELs, and thereby to control poweroutput, is to control resistance. At one time, a humantechnician had a full-time job manually adjusting the“trim” potentiometer, trying to get a good “eye pattern.”A better solution to this control and tuning problem is anelectronically programmed device, which can respond totemperature changes.

A niche industry

While not in any strict sense one of the communicationscompanies, Dallas Semiconductor brings expertise to thetable in several pertinent technologies: digitallycontrolled variable resistors and potentiometers,EEPROM, temperature sensors, and extremely low-power CMOS methods. In response to the needs ofgigabit optical technology, Dallas has produced aproduct family with a new range of features.

With the DS1845 Dual Potentiometer with EEPROM,Dallas designed the semiconductor industry’s firstpotentiometer with integrated memory, specifically for

service in pluggable gigabit transceiver modules. TheDS1845 combines two linear-taper potentiometers with256 bytes of EEPROM, which is required by the MSAstandards. The higher-resolution, 256-position poten-tiometer can be used to control modulation current andthe 100-position potentiometer can be used to controlbias current. Users configure both outputs and store thewiper settings and required serial ID data in the on-chip,nonvolatile EEPROM memory for reference duringoperation.

In modules that aim to shrink into SFPs, more denselyintegrated components that combine memory and twoseparately configured potentiometers save space byreplacing multiple parts. Furthermore, the DS1845’s 2-wire interface meets the transceiver producers’ require-ment for in-circuit programmability and is compatiblewith existing 2-wire EEPROM.

To meet more a specialized need, Dallas developed theDS1846, which combines three linear taper potentiome-ters with nonvolatile memory and a CPU supervisor inreduced TSSOP packaging. This level of integration insuch a small chip saves board space and cuts cost andprocurement delays, expediting product development. Aswith the DS1845, the nonvolatile memory is used toconfigure and store application-specific calibration data.And, to control wiper settings for each potentiometer,there’s also memory space available for user-specificdata.

The DS1846’s on-chip micromonitor tracks voltages. Ondetecting an out-of-tolerance voltage level, themicromonitor initiates and holds a system reset until safeoperating conditions return. The micromonitor isprogrammable for various voltage levels and includes amanual reset.

The third potentiometer can be used to monitor anothervariable or to provide a coarse trim for one of the otherresistors.

Intended for demanding laser applications, the DS1847and DS1848 compensate for the laser’s thermal charac-teristics over temperature ranges (see Figure 2). TheDS1848 has an extra 128 bytes of general-purposeEEPROM; otherwise the two are alike. The chips storeresistance characteristics relative to temperature in anonboard look-up table (LUT). An integrated temperaturesensor constantly measures and reports temperaturesduring laser operation. The DS1847 or DS1848compares the reading to the value stored in the LUT andadjusts resistance according to the designer’s definedresistance characteristics. The value determined by the

13

temperature sensor is also stored in EEPROM (updatedevery 10msec), and is available to the user over the 2-wire bus. It should also be noted that the DS1847 andDS1848 operate automatically. As a temperature changeis detected, control circuits automatically adjust resis-tance to achieve the compensating current value withoutany user intervention.

As a whole, all Dallas circuits employ a low-powerCMOS technology that contributes to holding down asensitive power budget. All circuits operate throughoutthe industrial temperature range and with both 3V and5V power supplies.

Clearly, in a huge, complex, driven market like opticalcommunications networks, many players operate atmany levels. The success of the laser, the star in a newand exotic technology, can depend on a comparativelyold and familiar player, the humble resistor. Of course,Dallas’ caveat to the moral of this fable would be, “It’snot your grandfather’s resistor any more.”

14

Figure 2. Optical Transceiver—Variable resistors, designed for optical transceivers like this one, automatically calibrate each diode more accu-rately than the older, mechanical-trim potentiometers.

BUSMASTER

NETWORKOR DIAL-UP

SECUREMEMORY(SHA-1)

15

Securing electronictransactions usingSHA-1Increasingly, the world is turning to portable electronicdevices with cryptographic capabilities to perform verysecure network authentication, virtual private networking,vending system regulation, fare collection, and employeeor citizen identification. The design of such a portabledevice (or token) requires careful study of the methods bywhich cryptographers authenticate and protect sensitivedata and monetary information. Of course, an e-cash oridentification token must be portable, durable, and secure,but it quickly becomes obvious that there are several addi-tional cryptographic, electrical, and physical requirementsthat a secure token must satisfy.

The most critical function for a truly secure token is thatof authentication. A token must be able to prove that it isauthorized by the issuer (the service provider), and that itis authentic. A token can prove that it is authorized simplyby virtue of the fact that it contains encrypted informationthat only the issuing authority could have created. Secureauthentication, however, is a far more difficult issue. Thedevice must be able to prove that it is not a fake orduplicate, and this requires some very special hardwarefunctionality. A device will not be trusted if its designcannot be freely examined, so secrets in design orfunction are all but impossible to keep. If we assume thatthe inner workings of the device are published and widelyknown, then we must also assume that anyone with suffi-cient skill could build an emulation of the device andbypass some of the special controls that the devicehardware imposes. Any token design based on security byobscurity is doomed to failure.

In cryptographic circles, truly secure authentication ishandled by a method called challenge-and-response. Thismethod involves a secret that is known only to valid tokensand hosts, and methods whereby tokens can prove that theyknow the secret, which proves that they are authentic. Ofcourse, the secret must never be revealed in the process,and that is where a cryptographic concept called ZeroKnowledge Proof comes into play. The token must supporta mechanism where it can prove that it knows a secretwithout revealing any information about it. At first glance,this may seem impossible, but it is a common exercise insecure cryptographic systems. Here is how the scheme works:

When a suspect token arrives, the host system creates avery big number, called a challenge, entirely at random,and sends it to the token. The token takes this challengeand, together with an internally stored secret, performs acomplex mathematical operation on it. Then, it returnsthe result of the operation to the host (see Figure 1). Thehost, also knowing the same secret, performs the samespecial mathematical operation internally, and thencompares the results. If the response from the tokenmatches the one computed in the host, then the token hasproven that it knows the secret, without revealing it (theessence of a Zero Knowledge Proof). Eavesdropping onthis conversation is of no use to an attacker who does notknow the secret. This is because the challenge is differenteach time; it is randomly generated. The next challengecan never be predicted. The secret remains safely hiddeninside the token, and the host knows that the token isauthentic (because only authentic tokens know thesecret).

Of course, it is critical that the complex mathematicalalgorithm used is not reversible, since the attacker couldrun the operation in reverse and derive the secret. In fact,the choice of algorithm may be the single most importantfactor in judging the security of a challenge and responsescheme. Electronic tokens have been created in the pastthat use home-brewed algorithms, stream-ciphers,rolling-codes, or cryptographic algorithms that have beencurtailed or reduced for this purpose, but they have notbeen widely accepted. The problem is that withoutextensive peer-review, there is no assurance that thesealgorithms are secure against attack. And there is noguarantee that these algorithms have no “back doors”(intentional or accidental) that may be known only to thedevice manufacturer.

To make a truly secure cryptographic token, thealgorithm selected must be one that is well-known,trusted, time-tested, and widely peer-reviewed in theglobal cryptographic community. An algorithm that takesinput data and irreversibly creates a digest of that data iscalled a one-way hash function. One of the most studiedand trusted one-way hash functions is SHA-1 (SecureHash Algorithm). This government-approved (FIPS 180-1) algorithm is the basis of modern digital signatures anddocument protection schemes. It has a long history in thecryptographic community, is peer-reviewed, and iswidely trusted.

However, SHA-1 is a complex algorithm that involvesmultiple 32-bit 5-way adds, complex logical functions,data shifting, and a great deal of repetition. Implemen-

tations of the SHA-1 algorithm in silicon have generallyrequired large die areas and so made fairly expensivetokens. A new method has been devised to perform thealgorithm in a serialized fashion, reducing the die area bya factor of 10 or more and making a reasonably pricedSHA-1-based token possible.

Another critical feature of a truly secure token is aglobally unique and unalterable identity. Including theunique token serial number as an additional input to theauthentication algorithm binds the physical token and thecontents together, making duplication of monetary valueor credentials among tokens impossible.

When a secure token is used in monetary applications,the data it contains (presumably the account balance) issaid to be dynamic, because the critical value is read,debited, and rewritten each time the device is used. Thistype of usage model introduces a type of attack known bycryptographers as a replay attack. That is to say, anattacker can record the value data from the token, andthen deplete the token making legitimate purchases. Hecan then restore (or replay) the original data, and therebyrestore the monetary value of the token to be spentrepeatedly. This replay can be prevented only if the tokenprovides mechanisms that make each instance of the datathat it contains unique. The truly secure monetary tokentherefore provides a special counter. This counter isincremented each time the device is written to and cannotbe wrapped-around, reset, decremented, or reloaded.Then, by including this counter value in the input to theauthentication algorithm, the monetary data, the device

identity, and the monetary instance are all boundtogether. Should the data be taken from the device andwritten back later, it will be found invalid because thecounter will have changed. It’s the same value, but it isnot the same instance of the value.

An interesting feature of the challenge-and-responseauthentication process is that the data is also protectedwhile en route from the token to the host. Since the data,the token identity, and the instance counter are allincluded in the SHA-1 algorithm input, any attempt toalter or inject data bits into the communications pathbetween the token and the host will also render the trans-action invalid. This means that any number of untrustedintermediaries can handle this challenge-and-responsedata exchange and the process remains secure. A distantserver on the Internet can authenticate a user’s token at ahome computer through a myriad of routers, bridges,hubs, and eavesdroppers, and security is not compro-mised in the slightest bit.

Another important requirement for a secure authentica-tion token is that it is able to protect the secrets that itholds. Plastic cards with embedded silicon chips aredifficult to protect against physical attacks, and typicalmemory devices have no special provisions for securestorage areas where secrets might be kept. A secure tokenmust provide a high level of physical security to protectthe secrets it contains.

Cryptography also provides methods whereby the secretin each device may be derived from another mastersecret, which is not stored in the device, in combination

16

Figure 1. SHA iButton Authentication

SHA iButton Authentication

SERIAL NUMBER

$ 1,234.56

SECRET

SHA-1

SECRET

RANDOMNUMBER

GENERATOR

MATCH?

CHALLENGE

BALANCE

IDENTITY

RESPONSE

iButton

IF RESPONSE MATCHES, THEN iButtonTOKEN MUST BE AUTHENTIC.

ALL DATA TRANSFERRED IS SECURE. ANYALTERATION WILL BE DETECTED.

VENDING MACHINE

SHA-1

with the unique device identity. This provides a uniquesecret for each device and prevents a system-wide break(called a class break) should the secret in any one devicebe compromised. Monetary systems, generally, also useone secret (stored inside the token) for token authentica-tion, and another secret (not stored in the token) for vali-dation of the monetary values stored in the token. Thislimits the scope of a physical attack on a token to just theability to emulate that one, and only that one, token. Thisseverely limits the profitability of a physical attack.

An often overlooked avenue of attack occurs at the serviceprovider’s facilities where an unscrupulous employee gainsaccess to the critical secrets by which the scheme assuresauthenticity. To overcome this problem, cryptographersoffer a method called Secret Sharing. The actual secret doesnot actually exist, but instead is the result of computationsthat combine two or more partial secrets. The serviceprovider maintains these partial secrets on separate systems,at separate locations, and allows no one to have access tomore than one of them. Without all of the partial secretsapplied in the proper sequence, the actual secret cannot becomputed. A truly effective, secure token must provide ameans to combine the partial secrets entirely inside thetoken so that the final secret never actually exists where anyhuman can ever observe it. As the token moves through theservice provider’s initialization process, it is injected witheach subsequent partial secret, and the actual secret is beingcomputed entirely inside each device. As a final step, theunique device identity is also injected into the process, sothe resulting device secret is unique to it, and the mastersecret never actually exists where it could be compromised.

A secure electronic token that can be strongly authenticatedalso makes for a very secure key for door locks, accesscontrol systems, and equipment control lockouts. An elec-tronic key using challenge and response cannot be dupli-cated or altered, and eavesdropping attacks are useless. Inthis application, the data is said to be static because, unlikean e-cash application, it does not change with each use.And the ability to have the token authenticate the personwho presents it adds even more to the security of thesystem—even in systems that have no provisions for suchPIN or password protection.

Peer-to-peer authentication applications allow networkedappliances to authenticate one another. This protects themfrom being operated by outsiders. Tokens that perform theauthentication quickly, and that protect the secrets insidethe token, greatly reduce the physical security requiredaround the appliance. The token can also be used to quicklygenerate unique session keys for the encryption of controlcommands or sensitive data.

The Dallas Semiconductor DS1963S iButton is a secure,electronic token that satisfies all of these requirements.Each token has a globally unique, factory-lasered 64-bitidentity, 512 bytes of lithium-backed NV RAM data storagearea, and eight protected 64-bit secrets. All of this is housedin a small, rugged stainless-steel container. Two-waycommunication with the device is performed on a single dataconductor at up to 140kbps, and SHA-1 is performed inter-nally in under 500 microseconds. The 64-bit secret sizewould require about 9,223,000,000,000,000,000 attempts tobreak by brute-force methods, making a brute-force attackunrealistic. The iButton can be worn like jewelry, attached toan ID card or badge, or carried like a key. It can be attachedto a container or bin, to a product or shipping carton. It canalso be embedded in a component or circuit board.

The Dallas Semiconductor DS1961S iButton is anEEPROM version of the DS1963S. It has 128 bytes ofmemory and provides a write-protection scheme where thehost system must satisfy a SHA authentication before thedevice can be altered.

The DS1963S also has the ability to serve as a coprocessorin vending and toll systems where the processing powerand speed at the host side is usually limited. Used as a co-processor, the DS1963S can safely store and protect thesystem secrets, perform the SHA-1 algorithm very quickly,and store the collected funds safely, as well as providing aglobally unique serial number that identifies the fare box orvending machine. As a co-processor, the DS1963S iButtoncan also hold critical configuration and pricing data used bythe host. The host electronics are reduced to simply movingdata between iButtons. E-cash systems have been demon-strated that use all of the security features described hereinand perform entire monetary transactions in under 50milliseconds.

The DS1961S, which is also available in chip form, canalso be simply embedded in networked devices (usingonly a single port pin for communication). This providesstrong cryptographic authentication between networkeddevices, opening up new possibilities for interrogatingand controlling them using the Internet. Networkeddevices can quickly and reliably authenticate one anotherand generate random number-based session keys for dataencryption, all in a single exchange of messages. Thesystem secrets are safely stored in protected EEPROM,and there is almost no overhead incurred to add strongcryptographic security to networked devices.

17

18

Introduction

EconOscillators have an internal oscillator thatprovides a base frequency, and they use a built-individer chain to lower a base frequency to the desiredrate. Each part number can divide down four basefrequency rates (60MHz, 66.67MHz, 80MHz, or100MHz) for adjustments up to 2052 times slowerthan the base part frequency. EconOscillators can beused for any type of clocked logic, including micro-processor, FPGA, and CPLD circuits, depending onsystem requirements.

8051 microprocessors and RS-232 serialcommunication

When selecting a clock, two factors deserve carefulconsideration: clock rate and clock accuracy over theoperational life span. In an 8051 microprocessorsystem, the use of RS-232 serial communicationsoften determines the system clock rate. Consider, forexample, asynchronous mode 1 serial communica-tion using a 12MHz clock (the maximum clock ratefor the original 8051). Table 1 shows the Timer 1auto-reload values required to establish standardbaud rates.

The actual baud rates in Table 1 were calculatedusing the following formula (reproduced from DallasSemiconductor’s High-Speed Microcontroller User’sGuide):

SMOD = Baud Rate Doubler

fOSC = Oscillator Rate

TH1 = Timer 1 Auto-Reload Value

The table numbers are based on these Timer 1 condi-tions:

• Set to increment 12 clock cycles per timer(DS87C520 can increment Timer 1 each 4 or 12clock cycles)

• Auto reload mode enabled

• Baud rate doubler (SMOD = 0) disabled

Most users of RS-232 serial communication agreethat any baud rate error over 3% is likely to causecommunication errors, which occur in spite ofsynchronization of the start and stop bits during datatransfer. A 3% allowable error limits the maximumcommunication rate with a 12MHz crystal to 2400baud—not bad for the early 1990s, but a little slowfor today’s standards. Luckily, there are crystals thatcater to 8051 serial communications: either an11.059MHz or 22.118MHz crystal. Microprocessorsusing these crystals see a considerable improvementin baud rate (Table 2), achieving data transfer ratesup to 57.6kbps (115.2kbps with a DS87C520 usingthe baud rate doubler, SMOD = 1), which is respect-able for most of today’s microprocessor systems.

Using the DS1075 to clock an 8051 microprocessor

As mentioned above, the DS1075 comes in four basevarieties, with the internal oscillators running at100MHz, 80MHz, 66.667MHz, and 60MHz. Using theinternal divider chain to slow them down enough foran 8051 application, in theory either of these partscould be used. However, if you plan to use the serialport of your 8051, you should select the base part thatbest fits your microprocessor’s needs, depending onboth the baud rate required and baud rate generationformula provided with your microprocessor.

In the case of the 8051 microprocessor in our example,oscillator frequencies of 11.059MHz and 22.118MHzwere desirable, and an approximately 3% error ratewas tolerable for baud rate generation. If you use the66.667MHz base part, you would be able to divide thebase frequency by six down to 11.111MHz. This has asmall error from the ideal frequency of 11.059MHz(0.47%), and the error remains acceptably low evenwith a worst-case deviation of 1% from theprogrammed frequency. Thus, the DS1075-66 allows amaximum error of 1.47% from the desired frequencyof 11.059MHz, which is adequate for communicationat rates up to 28.8kbps.

DESIGN SHOWCASE

An EconOscillator to clock an8051 microprocessor

If you are using an 8051 with a higher allowableclock rate such as the DS87C520 (33MHz maximumclock rate), you could simply divide the clock rate bythree to 22.222MHz. The maximum error is now1.47%—still fine for communication at any of the22.118MHz baud rates. The higher clock rate alsoprovides a higher level of processor performance foryour other application needs as well.

The big advantage in using the DS1075 for an 8051design is flexibility. A design that started out usingan original or equivalent 8051 microprocessor(12MHz maximum clock rate) can be simplyupgraded by reprogramming the oscillator andreplacing the microprocessor. Depending on thedesign, you may even be able to reprogram theDS1075 in-socket. If you are using the 40-pin DIPversion of the 8051 microprocessor, DallasSemiconductor and many other companies make

several 100%-compatible replacement chips. Thefastest of them all, Dallas Semiconductor’sDS89C420, offers a 50x performance increase overthe original 8051 design and has several resourcesavailable, including watchdog timers and powermanagement that were not available on the original8051. Other chips such as the DS87C520 canprovide up to an 11x performance increase. DallasSemiconductor also makes other versions of the 8051that have PWM and A/D converters for controlapplications, but they are not available in the 40-pinDIP package.

Hardware setup

To use the DS1075, you will need to establish a wayto program its EEPROM registers. The easiest way isto purchase the DS1075K Programming/EvaluationKit. The kit’s hardware and Windows® 95 software

19

Baud Rate with Baud Rate withTimer 1 Auto-Reload Value

fOSC = 11.059MHz fOSC = 22.118MHz

255 28,799.5 57598.9254 14399.7 28799.5253 9599.8 19199.6250 4799.91 9599.83244 2399.95 4799.91232 1199.98 2399.95208 599.98 1199.98160 299.99 599.9964 149.99 299.99

Table 2. Baud rates generated using crystal frequencies selected for RS-232 serial communication

Table 1. Baud rate and baud rate error using a 12MHz crystal for an original 8051 microprocessor

Note: Requiring the baud rate to be within 3% of the specified rate also places an accuracy requirement upon your clock. Even with an idealclock rate selected for RS-232 communication, if the clock varies more than 3%, you may not be able to communicate consistently.

Actual Baud RateTimer 1 Auto-Reload Value

(Desired Baud Rate)Baud Rate Error

255 31250 (28800) 8.5%254 15625 (14400) 8.5%253 10417 (9600) 8.4%

249/250 4464/5208 (4800) 7%/8.5%243 2404 (2400) 0.16%

20

with samples provide an easy means to program thedevice and try it out in your application. Otherwise,the data sheet alone (available online atwww.maxim-ic.com) has all of the informationrequired to program the device without a kit.

Once the DS1075 is programmed, the schematic inFigure 1 shows how to wire the DS1075 for properoperation with an 8051 microprocessor. Note that theoutput of the DS1075 goes into XTAL1, and XTAL2

is not connected. XTAL2 is normally the crystaloscillator output of the 8051. Connecting anything tothis pin will just load the microprocessor down,which is not necessary when any auxiliary clockeddevice can be connected in parallel with the micro-processor on XTAL1. This is assuming that the jointloading of the auxiliary device and the 8051 does notexceed the output current specification of theDS1075.

Figure 1. Hardware setup for using a DS075 oscillator to clock an 8051 microprocessor.

Windows is a registered trademark of Microsoft Corporation.

74F373LATCH

DS123OY-70

32k x 8NV RAM

DS87C520

DS10751 I/O

2 OUT0 NC

3 VCC

4 GND

OSCIN 8

XTAL 7NC

NC

VCC VCCOE 6

PDNSELX

5

PO.X

P2.X

ALE

(8)

(8)

(7)

OE

WE

RD (P3.7)XTAL2

XTAL1WR (P3.6)

LBS ADDRESS

DATA BUS

MSB ADDRESS

CE

21

DESIGN SHOWCASE

Dissecting the versatile Dallas 1-Wire network

The Dallas 1-Wire bus is a simple signaling schemethat performs two-way communications with periph-eral devices over a single electrical connection. In any1-Wire system, there is a single master and one ormore slaves sharing a common data line. On this singledata line are multiplexed address, control, and datainformation. Most of the devices operate entirely frompower robbed from the data bus, although some opt touse local power if it is available. Charge is stored inter-nally during periods when the data line is high, and the device operates using this charge during periodswhen the data line is low. An array of devices can be attached to a microprocessor on a single port pin. 1-Wire devices are available that store data (NV RAM,EPROM, and EEPROM), read and log temperaturesand voltages, adjust resistance, count, control andsense, interface to other systems, and perform time-keeping and cryptographic functions.

The most basic feature that all 1-Wire bus devicesshare is that each device has a factory-lasered address(like a serial number) that will never be repeated in anyother device. That is to say, every device is unique.This allows any single device to be individuallyselected from among many that may be connected tothe same bus wire. Because one, two, or even dozensof 1-Wire devices can share a single wire for commu-nications, a binary searching algorithm is used to findeach device in turn. Once each device address isknown, any device can be uniquely selected forcommunication using that address.

Electrically, the 1-Wire bus is a wired-OR configura-tion. A typical master consists of an open-drain pull-down and a resistor pull-up to 3 to 5 volts. Slaveshave an open drain output and are only able to pullthe bus down.

The 1-Wire data waveform is similar to pulse-widthmodulation. The bus master issues a reset (the longestlow period) that synchronizes the entire bus. Themaster then initiates each bit time period, or time slot,and writes zero or one bits using wide or narrow

pulse widths. To read data, the master initiates timeslots using narrow pulses, and the slaves return alogical 0 bit by holding the line low and therebyextending the pulse, or a logical 1 bit by leaving thepulse unchanged.

Most 1-Wire devices support two data rates. Thelower (standard) data rate is about 14kbps and thehigher data rate is about 140kbps. An even higherdata rate, 1Mbps, is in development. The protocol isself-clocking and tolerant of long inter-bit delays,making for easy operation in interrupted softwareenvironments.

The first part of any communication involves theselection of a slave device for subsequent communica-tions. This can be done by selecting all slaves,selecting a specific slave (using the serial number ofthe device), or discovering the next slave on the bususing a binary search algorithm. Once a specificdevice has been selected, all other devices drop outand ignore subsequent communications until the nextreset is issued.

Once a device has been isolated for bus communica-tion, the master can issue device-specific commandsto it, send data to it, or read data from it.

An integral part of the unique ID number in each slaveis an 8-bit family code. This code is specific to thedevice type. Because each device type performsdifferent functions, this code is used to select theprotocol that will be used to control or interrogate it.Because each device type performs a differentfunction and serves a different purpose, each has aunique protocol once it has been selected.

Because slave devices may have timed processes ormonitor real-world (asynchronous) data sources, theysometimes need to be able to gain the attention of themaster quickly. A poll of several dozen connectedslaves, addressing each by unique ID number andthen reading its internal registers, is somewhat slowand can be CPU-intensive. A special type of devicesearch, called a conditional search, is also supported

22

for this purpose. Slave devices will appear in thisspecial search only if they are in a condition, or havehad an event, that matches preset criteria. The masterperforms this conditional search at regular intervals,and any device that is found is a device in need ofservice.

Most 1-Wire devices are available in durable, stainlesssteel containers about the size of four stacked dimescalled iButtons. Some iButtons contain tiny lithiumcells that power internal real-time clocks or dataloggers and maintain NV SRAM data or configurationinformation for well over 10 years. Some haveEEPROM technology that requires no backup power.

These stainless steel iButtons also have their uniqueserial number laser-etched into the lid so humans canidentify them. Many 1-Wire devices are also availablein standard SOIC, TSOC, or TO packages for PCboard mounting. Chip-scale packaging (flip chip)forms are also available for some devices.

1-Wire peripherals include various serial- and parallel-port adaptors for PCs, probes, fob and holders, and awide array of iButton attachments.

Extensive 1-Wire software examples and APIs areavailable that implement standards for file communica-tions, structure, and error control at www.ibutton.com.

The 1-Wire® Bus

Thermochron, 1-Wire, and iButton are registered trademarks of Dallas Semiconductor.

BUSMASTER

SERIALNUMBER

THERMOCHRON®

TEMPERATURELOGGER

ANALOGSIGNALS

SENSEAND

CONTROL

NETWORKOR DIAL-UP

SECUREMEMORY(SHA-1) TEMPERATURE

iButton®

PROBE

DS2401DS2406 DS2450

DS1921DS1920

Figure 1. Various 1-Wire devices store data (NV RAM, EPROM, and EEPROM), read and log temperature and voltage, adjust resistance, count, control and sense, interface to other systems, and perform timekeeping and cryptographic functions.