Title Univers Bold Italic, 36pt Align LeftIra A. Fulton Schools of Engineering
Arizona State University, Tempe, AZ
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Degradation in integrated circuits due to ionizing radiation exposure can deteriorate the circuit characteristics, potentially leading to system failure
Most space electronics, implantable medical devices, and radiation/accelerator facility instrumentation therefore require hardness to total ionizing dose (TID)
The Total Ionizing Dose Problem
2012 MAXIM
Effects in Bulk CMOS
Effects in SOI CMOS
Effects in Bipolar Junction Transistors
Enhanced Low Dose Rate Sensitivity (ELDRS)
Modeling Approaches
2012 MAXIM
Effects in Bulk CMOS
Effects in SOI CMOS
Effects in Bipolar Junction Transistors
Enhanced Low Dose Rate Sensitivity (ELDRS)
Modeling Approaches
2012 MAXIM
Electronic Stopping or
radiation
of energy and radiation
measure of energy deposited
A unit of TID is a rad or a gray
(100 rad = 1 gray)
Units of Rad (Si) = (radg/MeV)(cm-2)(MeVcm2/g)
K = (106ev/MeV)(1.6x10-12 erg/eV)(1radg/100erg)
Example: 100MeV protons in SiO2
- The LET for a 100 MeV protons in SiO2 is 6.13 MeVcm2/g
(from SRIM code)
- To get total dose [rad(SiO2)] from a 100 MeV proton fluence (fp),
multiply fp by (6.13)x(1.6x10-8)
Ans. If the total fluence of 100 MeV protons for the mission is
1012 protons/cm2, the part will receive ~ 100 krad(SiO2) from
these particles
Note: to compute the dose across the full proton energy spectrum, we must take into account all LETs as well as the energy attenuation of lower energy particles
2012 MAXIM
(after McLean and Oldham, HDL-TR-2129 1987)
Processes
generated in SiO2 is computed as
follows:
(after Srour, DNA-TR-82-20 August 1982)
Ev
EC
Fraction of holes surviving
electric field.
(steady state)
(No saturation or annealing
and traps at interface)
Model Parameters
fy - field dependent hole yield [hole/ehp]
fot - trapping efficiency [trapped hole/hole]
tox - oxide thickness [cm]
2012 MAXIM
fit
D
(steady state)
and traps at interface)
Model Parameters
fy - field dependent hole yield [hole/ehp]
fDH - hole, D’H reaction efficiency [H+/hole]
fit - H+, SiH de-passivation efficiency [interface trap/H+]
tox - oxide thickness [cm]
D centers to generate more DH centers
DH
centers
H
(after Chen et al. TNS 2007)
DNit [cm-2]
H2 [cm-3]
2012 MAXIM
Effects in Bulk CMOS
Effects in SOI CMOS
Effects in Bipolar Junction Transistors
Enhanced Low Dose Rate Sensitivity (ELDRS)
Modeling Approaches
2012 MAXIM
n
n
p
Gate
Body
Drain
Source
Dielectric
DNot
Not effects on MOSFET I-V
Trapped holes in contribute net positive charge in the oxide, leading to a parallel, negative shift in MOSFET I-V characteristics
(Not)
(after Meisenheimer and Fleetwood, IEEE TNS 1990)
Trapped holes near interface can act as slow “border” traps that exchange charge with semiconductor and increase 1/f noise
2012 MAXIM
(p-channel example)
Traps cause increase in subthreshold swing, threshold voltage shifts, and reduced drive current via mobility degradation
2012 MAXIM
CMOS is defect buildup
in thicker field oxides
tox
DVT/tox2 a Dose
TID defect build-up in “thick” isolation oxides (LOCOS or STI)
create edge and inter-device leakage parasitics in bulk ICs
> 300 nm
< 3 nm
Trapped charge
NMOS D/S to NWELL
Charge build-up
Drain-source
Effects in Bulk CMOS
Effects in SOI CMOS
Effects in Bipolar Junction Transistors
Enhanced Low Dose Rate Sensitivity (ELDRS)
Modeling Approaches
2012 MAXIM
n+
n+
p
*
*
The configuration memory is spread throughout the device in a large array.
Each logic block contains its own configuration cells locally.
A data frame is a one bit vertical slice through the array.
The configuration logic identifies each frame with a unique address “minor” as
well as a unique address for the column that it lies in.
Configuration data is loaded serially or in byte-parallel into the interface where
it is assembled into a frame in a shift register.
The entire frame is loaded into memory all at once.
2012 MAXIM
*
*
The configuration memory is spread throughout the device in a large array.
Each logic block contains its own configuration cells locally.
A data frame is a one bit vertical slice through the array.
The configuration logic identifies each frame with a unique address “minor” as
well as a unique address for the column that it lies in.
Configuration data is loaded serially or in byte-parallel into the interface where
it is assembled into a frame in a shift register.
The entire frame is loaded into memory all at once.
2012 MAXIM
uniform charge build-up
and impact ionization
(not discussed here)
*
The configuration memory is spread throughout the device in a large array.
Each logic block contains its own configuration cells locally.
A data frame is a one bit vertical slice through the array.
The configuration logic identifies each frame with a unique address “minor” as
well as a unique address for the column that it lies in.
Configuration data is loaded serially or in byte-parallel into the interface where
it is assembled into a frame in a shift register.
The entire frame is loaded into memory all at once.
2012 MAXIM
Coupling Effect (Data)
Front gate
Vt shift
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*
Drain current increase with
negative gate bias via gate induced drain leakage (GIDL) enhancement
after Schwank et al., IEEE TNS 2000
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drain-body region generates
After J-H Chen, IEEE TED 2001
*
after Adell et al., IEEE NSREC 2007
-
+
*
Electrons back-injected into body increase electron concentration along back gate, enhancing back channel leakage
after Adell et al., IEEE NSREC 2007
-
+
*
interface is weakly depleted
Trapped charge increases back-side surface potential, back channel concentration and current
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The BAD News
*
Charge buildup in the buried oxide continues to be a significant total ionizing dose threat in SOI technologies
The threats include:
Front gate threshold voltage reduction due to electrostatic coupling form the back gate.
Drain-to-source leakage caused by back-side inversion enhanced by GIDL and/or impact ionization (latch)
Traditional radiation-hardening-by-design techniques do not
address the effects caused by damage to the Box
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The Good News
*
Commercial manufacturers typically increase doping along the back channel to reduce static power in CMOS circuits. This may mitigate the impact of charge buildup in the Box
The use of body ties not only improves SEE effects in SOI parts but there is strong evidence that they also suppress latching and GIDL enhancement
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Effects in Bulk CMOS
Effects in SOI CMOS
Effects in Bipolar Junction Transistors
Enhanced Low Dose Rate Sensitivity (ELDRS)
Modeling Approaches
2012 MAXIM
2012 MAXIM
PN Junctions
When forward biased (VAC > 0V), recombination (R) is maximized within the
depletion region
Depl.
region
x
x
R
X X X X X X X X X X X
Interface Trap Effects
Depl.
region
x
x
R
X X X X X X X X X X X
Fixed Oxide Charge Effects
reversed biased junctions (VAC < 0V)
Depl.
region
x
x
G
X X X X X X X X X X X
Reverse Bias Generation
Base current increases when BJTs are irradiated
Main reason for reduced current gain with radiation
Increasing
radiation
dose
*
Not (+) depletes the p-type base surface, increasing
area of recombination
Nit buildup alone
After Witczak et al,
*
This phenomenon is known as Enhanced-Low-Dose-Rate- Sensitivity (ELDRS)
ELDRS radiation bias
dependence an important
Besides radiation bias,
Effect of hydrogen on ELDRS
The transition dose rates and low dose rate saturation limit can be changed by H2 concentration in the oxide
2012 MAXIM
Effects in Bulk CMOS
Effects in SOI CMOS
Effects in Bipolar Junction Transistors
Enhanced Low Dose Rate Sensitivity (ELDRS)
Modeling Approaches
2012 MAXIM
Step 1
DNot , DDit
If DNot and DDit are able to be measured experimentally as a function
of bias stress and time, can their effects be simulated in SPICE at the
circuit level?
Apply external sources with defect generators that are functions of
bias stress and time.
August 21, 1998
The drain current expression in both the subthreshold and strong inversion regimes are functions of Vgs – Vth for nFETs or Vsg + Vth for pFETs.
Not modeled by
shift in Vth0
Dit modeled by
shift in Cit
*
*
The configuration memory is spread throughout the device in a large array.
Each logic block contains its own configuration cells locally.
A data frame is a one bit vertical slice through the array.
The configuration logic identifies each frame with a unique address “minor” as
well as a unique address for the column that it lies in.
Configuration data is loaded serially or in byte-parallel into the interface where
it is assembled into a frame in a shift register.
The entire frame is loaded into memory all at once.
2012 MAXIM
No Not and Dit
Not = 1.2x1012 cm-2; Dit = 1012 cm-2/eV
.MODEL PMOD PMOS (LEVEL=11 TOX=5e-9 K1=0 K2=0 NCH=5E17 NSUB=5E17 VTH0=-0.4631 IS=1E-18
+VOFF=-.055 U0=300 NFACTOR=1 NLX=0 K3=0 DVT0W=0 DVT0=0 ETA0=0 ETAB=0 UA=0 UB=0 UC=0
+JSGBR=1E-8 JSDBR=1E-8 JSGSR=1E-8 JSDSR=1E-8 JSGGR=1E-8 JSDGR=1E-8 DIOMOD=0 PSCBE1=0 PSCBE2=0
+BF=.0001 CIT=0)
.MODEL PMOD PMOS (LEVEL=11 TOX=5e-9 K1=0 K2=0 NCH=5E17 NSUB=5E17 VTH0=-0.8473 IS=1E-18
+VOFF=-.055 U0=300 NFACTOR=1 NLX=0 K3=0 DVT0W=0 DVT0=0 ETA0=0 ETAB=0 UA=0 UB=0 UC=0
+JSGBR=1E-8 JSDBR=1E-8 JSGSR=1E-8 JSDSR=1E-8 JSGGR=1E-8 JSDGR=1E-8 DIOMOD=0 PSCBE1=0 PSCBE2=0
+BF=.0001 CIT=1.6e-3)
To experimental data but …
*
*
The configuration memory is spread throughout the device in a large array.
Each logic block contains its own configuration cells locally.
A data frame is a one bit vertical slice through the array.
The configuration logic identifies each frame with a unique address “minor” as
well as a unique address for the column that it lies in.
Configuration data is loaded serially or in byte-parallel into the interface where
it is assembled into a frame in a shift register.
The entire frame is loaded into memory all at once.
2012 MAXIM
Parametric Adjustment of Compact Model
.MODEL PMOD PMOS (LEVEL=11 TOX=5e-9 K1=0 K2=0 NCH=5E17 NSUB=5E17 VTH0=-0.8473 IS=1E-18
+VOFF=-.055 U0=300 NFACTOR=1 NLX=0 K3=0 DVT0W=0 DVT0=0 ETA0=0 ETAB=0 UA=0 UB=0 UC=0
+JSGBR=1E-8 JSDBR=1E-8 JSGSR=1E-8 JSDSR=1E-8 JSGGR=1E-8 JSDGR=1E-8 DIOMOD=0 PSCBE1=0 PSCBE2=0
+BF=.0001 CIT=1.6e-3)
… how can temporal information about defects be readily incorporated into
BSIM compact model files (provided in PDKs) without significant modifications to tools?
THIS IS A PROBLEM FOR THE DESIGNERS!
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*
The configuration memory is spread throughout the device in a large array.
Each logic block contains its own configuration cells locally.
A data frame is a one bit vertical slice through the array.
The configuration logic identifies each frame with a unique address “minor” as
well as a unique address for the column that it lies in.
Configuration data is loaded serially or in byte-parallel into the interface where
it is assembled into a frame in a shift register.
The entire frame is loaded into memory all at once.
2012 MAXIM
Ext. voltage sources w/ defect generators
Is it possible to utilize external voltages (DV) in series with the transistor gate stimulus that mimic effects of time and bias dependent defects?
Concept (sub-Vt example)
Similar concept would be valid for BSIM strong inversion current equations
Pre-stress
*
*
The configuration memory is spread throughout the device in a large array.
Each logic block contains its own configuration cells locally.
A data frame is a one bit vertical slice through the array.
The configuration logic identifies each frame with a unique address “minor” as
well as a unique address for the column that it lies in.
Configuration data is loaded serially or in byte-parallel into the interface where
it is assembled into a frame in a shift register.
The entire frame is loaded into memory all at once.
2012 MAXIM
Not = 1.5x1012 cm-2; Dit = 1.2X1012 cm-2/eV
Use of external sources produces equally (compared to compact model adjustment) accurate simulation of effect of defects in DC
External source ckt can be
made into subcircuit and fixed
in series with gate contact
and external gate voltage.
*
*
The configuration memory is spread throughout the device in a large array.
Each logic block contains its own configuration cells locally.
A data frame is a one bit vertical slice through the array.
The configuration logic identifies each frame with a unique address “minor” as
well as a unique address for the column that it lies in.
Configuration data is loaded serially or in byte-parallel into the interface where
it is assembled into a frame in a shift register.
The entire frame is loaded into memory all at once.
2012 MAXIM
Drain
Current
*
*
The configuration memory is spread throughout the device in a large array.
Each logic block contains its own configuration cells locally.
A data frame is a one bit vertical slice through the array.
The configuration logic identifies each frame with a unique address “minor” as
well as a unique address for the column that it lies in.
Configuration data is loaded serially or in byte-parallel into the interface where
it is assembled into a frame in a shift register.
The entire frame is loaded into memory all at once.
2012 MAXIM
during PBTI in n-channel (for the temporal
defect profile selected). This may have an
important effect on the balance between
n- and p-channels in inverters and other logic cells.
*
*
The configuration memory is spread throughout the device in a large array.
Each logic block contains its own configuration cells locally.
A data frame is a one bit vertical slice through the array.
The configuration logic identifies each frame with a unique address “minor” as
well as a unique address for the column that it lies in.
Configuration data is loaded serially or in byte-parallel into the interface where
it is assembled into a frame in a shift register.
The entire frame is loaded into memory all at once.
2012 MAXIM
Inverter Modeling
propagation delay
*
*
The configuration memory is spread throughout the device in a large array.
Each logic block contains its own configuration cells locally.
A data frame is a one bit vertical slice through the array.
The configuration logic identifies each frame with a unique address “minor” as
well as a unique address for the column that it lies in.
Configuration data is loaded serially or in byte-parallel into the interface where
it is assembled into a frame in a shift register.
The entire frame is loaded into memory all at once.
2012 MAXIM
Inverter Modeling
charge/discharge current
Reduced charging
*
*
The configuration memory is spread throughout the device in a large array.
Each logic block contains its own configuration cells locally.
A data frame is a one bit vertical slice through the array.
The configuration logic identifies each frame with a unique address “minor” as
well as a unique address for the column that it lies in.
Configuration data is loaded serially or in byte-parallel into the interface where
it is assembled into a frame in a shift register.
The entire frame is loaded into memory all at once.
2012 MAXIM
Ring Oscillator Circuit
*
The configuration memory is spread throughout the device in a large array.
Each logic block contains its own configuration cells locally.
A data frame is a one bit vertical slice through the array.
The configuration logic identifies each frame with a unique address “minor” as
well as a unique address for the column that it lies in.
Configuration data is loaded serially or in byte-parallel into the interface where
it is assembled into a frame in a shift register.
The entire frame is loaded into memory all at once.
2012 MAXIM
Modeling Summary
Technique enables:
Effects of defects to be captured in time domain without modification to post-fabrication (vendor supplied) compact model.
Density vs. time functions to be incorporated as defect generators.
Simulates effect of time dependent stress in circuits.
*
The configuration memory is spread throughout the device in a large array.
Each logic block contains its own configuration cells locally.
A data frame is a one bit vertical slice through the array.
The configuration logic identifies each frame with a unique address “minor” as
well as a unique address for the column that it lies in.
Configuration data is loaded serially or in byte-parallel into the interface where
it is assembled into a frame in a shift register.
The entire frame is loaded into memory all at once.
3
#ehp1
=LET•
HP 0.5 µm/9.4 nm
HP 0.5 µm/9.4 nm
ox
t
t
via
tradeoff
x
0.0E+00
5.0E+10
1.0E+11
1.5E+11
2.0E+11
2.5E+11
3.0E+11
3.5E+11
0.0E+00
5.0E+10
1.0E+11
1.5E+11
2.0E+11
2.5E+11
3.0E+11
3.5E+11
-2.00E+110.00E+002.00E+114.00E+116.00E+118.00E+111.00E+121.20E+121.40E+12Defects (cm-2)time (a.u)Not inputDit inputNot (ext)Dit (ext)
Step 2
-0.200.20.40.60.811.21.41.61.80.0E+005.0E-091.0E-081.5E-082.0E-08Voltage (V)Time (s)vinvout strvout no str