MAX127-MAX128B

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General Description

T he M A X127/M A X128 are multirange, 12-bit dataacquisition systems (D A S) that require only a single

+ 5V supply for operation, yet accept signals at their

analog inputs that may span above the power-supply

rail and below ground. These systems provide eight

analog input channels that are independently software

programmable for a variety of ranges: 10V, 5V, 0 to

+ 10V, 0 to + 5V for the M AX127; and V REF, VREF/2, 0

to + VR EF , 0 to + VR EF/2 for the M A X128. T his range

switching increases the effective dynamic range to 14

bi ts and provides the flexibility to interface 420mA ,

12V, and 15V-powered sensors directly to a single

+ 5V system. I n add ition, these converters are fault pro-

tected to 16.5V; a fault condition on any channel will

not affect the conversion result of the selected channel.O ther features include a 5M Hz bandwidth track/hold,

an 8ksps throughput rate, and the option of an internal

4.096V or external reference.

The M AX127/M AX128 feature a 2-wire, I2C -compatible

serial interface that allows communication among multi-

ple devices using SD A and SC L lines.

A hardware shutdown input (SHDN) and two software-programmable power-down modes (standby and full

power-down) are provided for low-current shutdown

between conversions. In standby mode, the reference-

buffer remains active, eliminating start-up delays.

T he M A X127/M A X128 are available in 24-pin D IP or

space-saving 28-pin SSO P packages.

Applications

Industrial C ontrol Systems

Data-Acquisition Systems

Robotics

Automatic Testing

Battery-Powered Instruments

M edical Instruments

Features

o 12-Bit Resolution, 1/2 LSB Linearityo +5V Single-Supply Operation

o I2C-Compatible, 2-Wire Serial Interface

o Four Software-Selectable Input Ranges

MAX127: 0 to +10V, 0 to +5V, 10V, 5VMAX128: 0 to +VREF, 0 to +VREF/2, VREF,

VREF/2

o 8 Analog Input Channels

o 8ksps Sampling Rate

o 16.5V Overvoltage-Tolerant Input Multiplexer

o Internal 4.096V or External Reference

o Two Power-Down Modes

o 24-Pin Narrow DIP or 28-Pin SSOP Packages

EVALUATIO

NKIT

AVAILABLE

For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.For small orders, phone 408-737-7600 ext. 3468.

MAX127/MAX12

8

Multirange, +5V, 12-Bit DAS with2-Wire Serial Interface

________________________________________________________________Maxim Integrated Products 1

VDD

CH0CH1CH2CH3CH4CH5CH6CH7

DGND0.01F

C

4.7F

0.1F

1k

SHDN

MAX127

MAX128

+5V

ANALOGINPUTS

SCLSDA

A0A1A2

REFREFADJ

AGND

SCL SDA

Typical Operating Circuit

19-4773; R ev 0; 7/98

Ordering Information continued at end of data sheet.

PART

MAX127ACNG

MAX127ACNG 0C to +70C

0C to + 70C

TEMP. RANGE PIN-PACKAGE

24 Narrow Plastic DI P

24 Narrow Plastic DIP 1

1/2

INL(LSB)

Pin Configurations appear at end of data sheet.

Ordering Information

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2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

Stresses beyond those listed under A bsolute M aximum R atings may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

VD D to AG ND ............................................................-0.3V to +6V

AG ND to DG ND .....................................................-0.3V to + 0.3V

C H0CH 7 to AG ND .... . .. . . . . . .. . . . . .. . . . . . .. . . . . .. . . . . .. . . . . . .. . . . . .. . . . . . 16.5V

REF to AG ND ..............................................-0.3V to (VD D + 0.3V)

REFA DJ to AG ND .......................................-0.3V to (V D D + 0.3V)

A0, A 1, A2 to DG ND ...................................-0.3V to (V D D + 0.3V)

SHDN, SCL , SDA to DG ND ......................................-0.3V to +6V

M ax C urrent into Any Pin ....................................................50mA

C ontinuous Power D issipation ( TA = +70C)

24-Pin Narrow D IP (derate 13.33mW/C above + 70C ) ..1067mW

28-Pin SSO P (derate 9.52mW/C above +70C) ......... ......762mW

O perating Temperature Ranges

M AX127_ C _ _/M AX128_ C_ _... . . . . . . .. . . . . . .. . . . . .. . . . . .0C to +70C

M AX127_ E_ _/M AX128_ E_ _ ... . . . .. . . . . .. . . . . .. . . . . . .-40C to + 85C

Storage Temperature Range ...... ..... ...... ...... ..... -65C to +150C

Lead T emperature (soldering, 10sec) ...... ..... ...... ...... .....+ 300C

M AX 127A/M AX 128A

4kHz, V IN = 5V (N ote 3)

Up to the 5th harmonic

Bipolar

M AX 127B/M AX 128B

Unipolar

CONDITIONS

10Aperture Jitter

ns200Aperture D elay

dB-86

C hannel-to-C hannel C rosstalk

dB81SFDRSpurious-Free Dynamic Range

dB-87 -80THDTotal H armonic D istortion

dB70

LSB1/2

IN LIntegral Nonlinearity

Bits12Resolution

0.3 LSB

0.1C hannel-to-C hannel O ffset

Error M atching

10

5

1

LSB1DN LD ifferential Nonlinearity

LSB

3

O ffset Error5

UNITSMIN TYP MAXSYMBOLPARAMETER

Bipolar

Unipolar

5ppm/C

3G ain Tempco (N ote 2)

10

7LSB

7

G ain Error (N ote 2)10

SINADSignal-to-Noise plus D istortion

Ratio

ns

Bipolar

U nipolar

Bipolar

M AX 127B/M AX 128B

M AX 127B/M AX 128B

U nipolar

M AX 127B/M AX 128B

M AX 127B/M AX 128B

M AX 127A/M AX 128A

M AX 127A/M AX 128A

M AX 127A/M AX 128A

M AX 127A/M AX 128A

ELECTRICAL CHARACTERISTICS(VD D = + 5V 5% ; unipolar/bipolar range; external reference mode, VR EF = 4.096V; 4.7F at REF; external clock, fC LK = 400kHz;

TA = TM IN to TM A X; unless otherwise noted. Typical values are at T A = +25C.)

DYNAMIC SPECIFICATIONS (800Hz sine-wave input, 10Vp-p (M AX127) or 4.096Vp-p (M AX128), fSAMPLE = 8ksps)

DC , V IN = 16.5V -96

ACCURACY (N ote 1)

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ELECTRICAL CHARACTERISTICS (continued)(VD D = + 5V 5% ; unipolar/bipolar range; external reference mode, VR EF = 4.096V; 4.7F at REF p in; external clock, fC LK = 400kHz;


M AX128

M AX127

M AX127

-600 360

I IN -1200 720 A

VR EF/2 range

V R EF range

5V range

-1200 10

10V range

-600 10

Bipolar

Input Voltage Range V IN-10 10

TC VR EF

-5 5M AX127

-VR EF VR EF

-VR EF/2 VR EF/2M AX128

Bipolar,

Table 3

M AX127

M AX128

0 to 5V or 0 to VREF/2 range

0 to 10V or 0 to VR EF range

5V or VR EF/2 range

10V or VR EF range

Buffer Voltage G ain 1.638 V/V

REFAD J Adjustment Range 1.5 %Figure 12

C apacitive Bypass at REF 4.7 F

REFAD J O utput Voltage 2.465 2.500 2.535 V

Load Regulation (Note 5) 10 mV0 to 0.5mA output current

0 VR EF

0 VR EF/2

U nipolar,

Table 3

Input Resistance VIN

I IN21 k16

-10 360

U nipolar

Input C urrent

-10 720

Bipolar

M AX128

0 to 5V range

-10 0.1 10

0 to 10V range

U nipolar

2.5Small-Signal Bandwidth

5

M Hz

PARAMETER SYMBOL MIN TYP MAX UNITS

2.5

-3dB

rolloff

1.25

0 10

V

0 5

Track/Hold Acquisition T ime 3 s

Input C apacitance 40 pF

REFO U T Voltage VR EF 4.076 4.096 4.116 V

REFO UT Tempco15

ppm/C

O utput Short-C ircuit C urrent 30 mA

CONDITIONS

(N ote 4)

TA = +25C

M AX 127_C /M AX 128_C

30M AX 127_E/M AX 128_E

ANALOG INPUT

INTERNAL REFERENCE

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ELECTRICAL CHARACTERISTICS (continued)(VD D = + 5V 5% ; unipolar/bipolar range; external reference mode, VR EF = 4.096V; 4.7F at REF p in; external clock, fC LK = 400kHz;

TA = TM IN to TM A X; unless otherwise noted. Typical values are at TA = +25C.)

V2.4 4.18Input Voltage R ange

VVD D - 0.5REFADJ Threshold for

Buffer Disable

Normal or STANDBY power-down mode k10Input Resistance

FULL power-down mode 5 M

External reference = 4.096V

CONDITIONS

FUL L power-down mode

LSB0.1 0.5

PSRRPower-Supply Rejection Ratio

(N ote 7)

s

V4.75 5.25VDDSupply Voltage

6.0 7.7 10.0tC O N VC onversion Ti me

120 220

Normal mode, bipolar ranges

700 850

Normal mode, unipolar ranges

UNITSMIN TYP MAXSYMBOLPARAMETER

STA N DBY power-down mode (N ote 6)

mA18

ID DSupply C urrent6 10

A

Internal reference 0.5

0.4fC LKExternal C lock Frequency Range M Hz

Power-up (Note 8) s200Bandgap ReferenceStart-Up Time

ksps8Throughput Rate

C IN 15 pF(N ote 4)

Input Leakage C urrent I IN 0.1 10 AV IN = 0 or VD D

Input Low T hreshold Voltage V IL 0.8 V

Input H igh T hreshold Voltage VIH 2.4 V

Input C apacitance

VHY S 0.2 VInput H ysteresis

400VR EF =

4.18VA

1

Input C urrent

FULL power-down mode

Normal, or STANDBY

power-down mode

To 0.1mV, REF bypass

capacitor fully dischargedms

8Reference Buffer Settling Time

POWER REQUIREMENTS

TIMING

REFERENCE INPUT (buffer disabled, reference input applied to R EF)

DIGITAL INPUTS (SHDN, A 2, A 1, A 0)

C R EF = 4.7F

C R EF = 33F 60

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ELECTRICAL CHARACTERISTICS (continued)(VD D = + 5V 5% ; unipolar/bipolar range; external reference mode, VR EF = 4.096V; 4.7F at REF pi n; external clock, fC LK = 400kHz;


Input H ysteresis VHYS 0.05 x VDD V

Input Low T hreshold Voltage V IL 0.3 x VD D V

Input H igh T hreshold Voltage VIH 0.7 x VD D V

PARAMETER SYMBOL MIN TYP MAX UNITSCONDITIONS

TIMING CHARACTERISTICS(VD D = + 4.75V to + 5.25V; unipolar/bipolar range; external reference mode, VR EF = 4.096V; 4.7F at REF pin; TA = TM IN to T M A X;

unless otherwise noted. Typical values are at TA = +25C.)

Input C apacitance C IN 15 pF(N ote 4)

Input Leakage C urrent I IN 0.1 10 AV IN = 0 or VD D

Three-State O utput Capacitance C O U T 15 pF(N ote 4)

O utput Low Voltage VO L0.4

VISINK = 3mA

2-WIRE FAST MODE

Hold Time (Repeated)

START ConditiontHD,STA 0.6 s

Bus Free Time Between a

STO P and STAR T C onditiontBU F 1.3 s

SC L C lock Frequency f SC L 400 kH z

PARAMETERS SYMBOL MIN TYP MAX UNITSCONDITIONS

Set-U p T ime for a R epeated

START ConditiontSU,STA 0.6 s

H igh P eriod of the SC L C lock tH I G H 0.6 s

Low Period of the SC L C lock tLO W 1.3 s

R ise Time for Both SD A and SCL

Signals (Receiving)tR

20 + 300

0.1 x C bnsC b = Total capacitance of one bus line in pF

D ata Setup T ime tSU ,DAT 100 ns

D ata Hold T ime tHD,DAT 0 0.9 s

DIGITAL INPUTS (SDA, SCL)

DIGITAL OUTPUTS (SDA)

ISINK = 6mA 0.6

Fall Time for Both SDA and SC L

Signals (Receiving)tF C b = Total capacitance of one bus line in pF

20 + 300

0.1 x C bns

Fall Time for Both SDA and SC L

Signals ( Transmitting)tF C b = Total capacitance of one bus line in pF

20 + 250

0.1 x C bns

Set-Up T ime for STOP Condition tSU,STO 0.6 s

C apacitive Load for Each

Bus LineC b 400 pF

Pulse Width of Spike Suppressed tSP 0 50 ns

2-WIRE FAST MODE

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TIMING CHARACTERISTICS (continued)(VD D = + 4.75V to + 5.25V; unipolar/bipolar range; external reference mode, VR EF = 4.096V; 4.7F at REF pin; TA = TM IN to T M A X ;unless otherwise noted. Typical values are at T A = + 25C.)

Note 1: Accuracy speci fications tested at VD D = 5.0V. Performance at power-supply tolerance limi ts is guaranteed by Power-Supply Rejection test.

Note 2: External reference: VR EF = 4.096V, offset error nulled, id eal last-code transition = FS - 3/2LSB .Note 3: G round on channel, sine wave applied to all off channels.Note 4: G uaranteed by design. N ot tested.Note 5: Use static external load during conversion for specified accuracy.Note 6: Tested using internal reference.Note 7: PS RR measured at full scale. Tested for the 10V (M AX127) and 4.096V (M AX128) input ranges.Note 8: Not subject to production testing. Provided for design guidance only.

PARAMETERS SYMBOL MIN TYP MAX UNITSCONDITIONS

Low Period of the SC L C lock tLO W 4.7 s

H igh P eriod of the SC L C lock tH I G H 4.0 s

Setup T ime for a Repeated

START ConditiontSU, STA 4.7 s

D ata Hold T ime tHD, DAT 0 0.9 s

D ata Setup T ime tSU , DAT 250 ns

R ise Time for Both SD A and SCL

Signals (Receiving)tR 1000 ns

Fall Time for Both SD A and SC L

Signals (Receiving)tF 300 ns

Fall Time for Both SD A and SC L

Signals ( Transmitting)tF

C b = total capacitance of one bus line in pF,

up to 6mA sink

20 + 250

0.1 x C bns

Setup T ime for STOP Condition tSU, STO 4.0 s

C apacitive Load for Each

Bus LineC b 400 pF

Pulse Width of Spike Suppressed tSP 0 50 ns

Hold Time (R epeated) STA RT

C onditiontHD,STA 4.0 s

Bus Free Time B etween a STO P

and STAR T C onditiontBU F 4.7 s

SC L C lock Frequency f SC L 100 kHz

2-WIRE STANDARD MODE

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0

5

15

10

20

25

0 21 3 4 5 6 7

SUPPLY CURRENT vs. SUPPLY VOLTAGE

max127/8-01

SUPPLY VOLTAGE (V)

SUPPLYCURRENT(mA)

5.5

5.7

6.1

5.9

6.3

6.5

-40 10-15 35 60 85

SUPPLY CURRENT vs. TEMP ERATURE

M

AX127/8-02

TEMPERATURE (C)

SUPPLYCURRENT(mA)

50

150

450

350

250

650

550

750

-40 10-15 35 60 85

STANDBY SUPPLY CURRENT

vs. TEM PERATURE

M

AX127/8-03

TEMPERATURE (C)

STANDBYSUPPLYCURRENT(A)

INTERNALREFERENCE

EXTERNALREFERENCE

50

70

110

90

130

150

-40 10-15 35 60 85

FULL POWER-DOWN SUPPLY CURRENT

vs. TEM PERATURE

M

AX127/8-04

TEMPERATURE (C)

FULLPOWE

R-DOWNSUPPLYCURRENT(A)

INTERNALREFERENCE

EXTERNALREFERENCE

0.1

0.2

0.6

0.5

0.4

0.3

0.7

0.8

-40 10-15 35 60 85

CHANNEL-T O-CHANNEL GAIN-ERROR

M ATCHING vs. TEM PERATURE

M

AX127/8-07

TEMPERATURE (C)

CHANNEL-TO-CHANNELGAIN

-ERRORMATCHING(LSB)

BIPOLAR MODE

UNIPOLAR MODE

0.996

0.997

0.999

0.998

1.000

1.001

-40 10-15 35 60 85

NORMALIZED REFERENCE V OLTAGE

vs. TEM PERATURE

M

AX127/8-05

TEMPERATURE (C)

NORMA

LIZEDREFERENCEVOLTAGE

0

0.05

0.25

0.20

0.15

0.10

0.30

0.35

-40 10-15 35 60 85

CHANNEL-TO- CHANNEL OFFSET-ERROR

M ATCHING vs. TEM PERATURE

M

AX127/8-06

TEMPERATURE (C)

CHANNEL-TO-CHA

NNELOFFSET-ERRORMATCHING(LSB)

BIPOLAR MODE

UNIPOLAR MODE

-0.15

-0.10

0.05

0

-0.05

0.10

0.15

0 1638819 2457 3276 4095

INTEGRAL NONLINEARITY vs.

DIGITAL CODE

M

AX127/8-08

DIGITAL CODE

INTEGRALNONLINEARITY(LSB)

-110

-100

-4 0

-6 0

-8 0

-2 0

0

0 1600800 2400 3200 4000

FFT PLOT

M

AX127/8-09

FREQUENCY (Hz)

AMPLITUD

E(dB)

VDD = 5VfIN = 800HzfSAMPLE = 8kHz

Typical Operating Characteristics(VDD = + 5V, external reference mode, VREF = 4.096V; 4.7F at REF; external clock, fC LK = 400kHz; TA = + 25C; unless otherwise noted.)

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Pin Description

PIN NAME FUNCTIONDIP SSOP

1, 2 1, 2 VD D + 5V Supply. Bypass with a 0.1F capacitor to AG ND .

3, 9, 22, 244, 7, 8, 11, 22,

24, 25, 28N.C . No Connect. No internal connection.

4 3 DG ND D igital G round

5 5 SC L Serial C lock Input

6, 8, 10 6, 10, 12 A0, A2, A1 Address Select Inputs

7 9 SDA

O pen-Drain Serial Data I/O . Input data is clocked in on the rising edge of SCL ,

and output data is clocked out on the falling edge of SC L. External pull-up

resistor required.

11 13 SHDN

Shutdown Input. When low, device is in full power-down (FU LL PD ) mode.

C onnect high for normal operation.

12 14 AG ND Analog G round

1320 1521, 23 C H 0C H7 Analog Input C hannels

21 26 REFAD JBandgap Voltage-Reference O utput/External Adjust Pin. Bypass with a 0.01F

capacitor to AG ND . C onnect to VD D when using an external reference at R EF.

23 27 REF

Reference Buffer O utput/AD C Reference Input. In internal reference mode, the

reference buffer provides a 4.096V nominal output, externally adjustable a t

REFA DJ. In external reference mode, disable the internal reference by pulling

REFA DJ to VD D and applying the external reference to RE F.

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Detailed Description

Converter OperationThe M A X127/M A X128 multirange, fault-tolerant A D C s

use successive approximation and internal track/hold

(T/H) circuitry to convert an analog signal to a 12-bit

digital output. Figure 1 shows the block diagram for

these devices.

Analog-Input Track/HoldThe T/H circuitry enters its track ing/acquisition mode on

the falling edge of the sixth clock in the 8-bit input con-

trol word and enters its hold/conversion mode when themaster issues a ST O P condition. For timing information,

see the Start a Conversionsection.

Input Range and ProtectionThe M AX127/M A X128 have software-selectable input

ranges. Each analog input channel can be indepen-

dently programmed to one of four ranges by setting the

appropriate control bits (RNG , BI P) in the control byte

( Table 1). T he M A X127 has selectable input ranges

extending to 10V (VREF x 2.441), while the M AX128

has selectable input ranges extending to V REF. Note

that when an external reference is applied at R EFA D J,

the voltage at REF is given by VREF = 1.638 x VREFADJ(2.4 < VR EF < 4.18). Figure 2 shows the equiva lent

input circuit.

A resistor network on each analog input provides a

16.5V fault protection for all channels. This circuit lim-

its the current going into or out of the pin to less than

1.2mA , whether or not the channel is on. T his provides

an added layer of protection when momentary over-

voltages occur at the selected input channel, and when

a negative signal is applied at the input even though

the device may be configured for unipolar mode.

O vervoltage protection is active even if the device is in

power-down mode or VDD = 0.

Digital InterfaceThe M AX127/M AX128 feature a 2-wire serial interface

consisting of the SDA and SC L pins. SDA is the data

I/O and SC L is the serial clock input, controlled by the

master device. A 2A0 are used to program the

M A X127/M A X128 to different slave addresses. ( T heM A X127/M A X128 only work as slaves.) The two bus

lines (SD A and SC L) must be high when the bus is not

in use. External pull-up resistors (1kor greater) are

required on SDA and SC L to maintain I2C compatibility.

Table 1 shows the input control-byte format.

Figure 1. Block Diagram

CH2

CH1

CH0

SHDN

CH3

CH4

CH5

CH6

CH7

REFADJ

REF

VDD

AGND

DGND

MAX127

MAX128

12-BIT SAR ADC

IN

REF

CLOCKOUT

T/H

2.5VREFERENCE

ANALOGINPUTM UX

AND SIGNALCONDITIONING

AV =1.638

INTCLOCK

SDA A2 A1 A0 SCL

SERIAL INTERFACE LOGIC

10k

Figure 2. Equivalent Input C ircuit

5.12k

R2

R1

CH_

S1

S2

S3

S4

BIPOLAR

UNIPOLAR

VOLTAGEREFERENCE

T/HOUT

HOLDTRACK

TRACKHOLD

OFF

ON

CHOLD

S1 = BIPOLAR/UNIPOLAR SWITCHS2 = INPUT MUX SWITCHS3, S4 = T/H SWITCH

R1 = 12.5k (MAX127) OR 5.12k (MAX128)R2 = 8.67k (MAX127) OR (MAX128)

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BIT 7(MSB)

BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0(LSB)

START SEL2 SEL1 SEL0 RNG BIP PD 1 PD0

Table 1. Control-Byte Format

BIT NAME DESCRIPTION

7 (M SB) STARTThe logic "1" received after acknowledge of a write bit (R /W= 0) defines the

beginning of the control byte.

6, 5, 4SEL2, SEL1,

SEL0These three bits select the desired "O N" channel (Table 2).

3 RN G Selects the full-scale input voltage range (Table 3).

2 BIP Selects unipolar or bipolar conversion mode (Table 3).

1, 0 (LSB) PD 1, PD0 These two bi ts select the power-down mod es (Table 4).

SEL2 SEL1 SEL0 CHANNEL

0 0 0 C H0

0 0 1 C H1

0 1 0 C H2

0 1 1 C H3

1 0 0 C H4

1 0 1 C H5

1 1 0 C H6

1 1 1 C H7

Table 2. Channel Selection

Table 3. Range and Polarity Selection

INPUT RANGE (V) RNG BIPNEGATIVE FULL

SCALE (V)ZERO

SCALE (V)FULL SCALE (V)

0 to 5 0 0 0 VR EF x 1.2207

0 to 10 1 0 0 VR EF x 2.4414

5 0 1 -VR EF x 1.2207 0 VR EF x 1.2207

10 1 1 -VR EF x 2.4414 0 VR EF x 2.4414

Table 4. Power-Down and ClockSelection

PD1 PD0 MODE

0 X N ormal O peration (always on)

1 0 Standby P ower-D own M ode ( STBY PD )

1 1 Full Power-D own M ode (FU LLPD )

0 to VR EF 1 0 0 VR EF

V R EF/2 0 1 -VR EF/2 0 VR EF/2

VR EF 1 1 -VR EF 0 VR EF

0 to VR EF/2 0 0 0 VR EF/2

MAX127

MAX128

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Slave AddressThe M AX127/M AX128 have a 7-bit-long slave address.

T he first four bits (M SB s) of the slave address havebeen factory programmed and are always 0101. The

logic state of the address input pins (A 2A0) determine

the three LSB s of the device address (Figure 3) . A max-

imum of eight M AX127/M AX128 devices can therefore

be connected on the same bus at one time.

A 2A0 may be connected to VD D or D G ND , or they

may be actively driven by TTL or C M O S logic levels.

The eighth bit of the address byte determines whether

the master is writing to or reading from the M A X127/

M AX128 (R/W = 0 selects a write condition. R /W = 1selects a read condition).

Conversion ControlThe master signals the beginning of a transmission with

a START condition (S) , which is a high-to-low transitionon SD A while SC L is high. When the master has fin-

ished communicating with the slave, the master issues

a ST O P condition (P ) , which is a low-to-high transition

on SDA while SC L is high (Figure 4) . T he bus is then

free for another transmission. Figure 5 shows the timing

diagram for signals on the 2-wire interface. The

address-byte, control-byte, and data-byte are transmit-

ted between the STA RT and STO P conditions. T he SDA

state is allowed to change only while SC L is low, except

for the START and STO P conditions. D ata is transmitted

in 8-bit words. N ine clock cycles are required to trans-

fer the data in or out of the M AX127/M AX128. (Figures

9 and 10) .

MAX127/MAX12

8


______________________________________________________________________________________ 11

SCL

SDA

SLAVE ADDRESS BITS A2, A1, AND A0 CORRESPOND TO THE LOGIC STATE

OF THE ADDRESS INPUT PINS A2, A1, AND A0.

00 1 A21 R/WA1 A0

LSB

ACK

SLAVE ADDRESS

Figure 3. Address Byte

SCL

SDA

tLOW

tHIGH

tFtR

tHD, STA

tHD, DAT

tHD, STA

tSU, DAT tSU, STAtBUF

tSU, STO

START CONDITIONSTOP CONDITIONREPEATED START COND ITIONSTART CONDITION

Figure 5. 2-Wire Serial-Interface T imi ng D iagram

SCL

SDA

START CONDITION STOP CONDITION

Figure 4. STA RT and STO P C onditions

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M

AX127/MAX12

8 Start a Conversion (Write Cycle)A conversion cycle begins with the master issuing aST A R T condition followed by seven address bits(Figure 3) and a write bit (R/W= 0). O nce the eighth bithas been received and the address matches, the

M A X127/M A X128 (the slave) issues an acknowledge

by pulling SD A low for one clock cycle (A = 0). T he

master then writes the input control byte to the slave

(Fig ure 8) . A fter this byte of data, the slave issues

another acknowledge, pulling SD A low for one clock

cycle. The master ends the write cycle by issuing a

STO P condition (Figure 6) .

When the write bit is set (R /W= 0), acquisition starts assoon as Bit 2 (BIP) of the input control-byte has been

latched and ends when a STO P condition has been

issued. C onversion starts immediately after acquisition.

The M AX127/M A X128s internal conversion clock fre-quency is 1.56M H z, resulting in a typical conversion

time of 7.7s. Figure 9 shows a complete write cycle.

Read a Conversion (Read Cycle)O nce a conversion starts, the master does not need to

wait for the conversion to end before attempting to read

the data from the slave. D ata access begins with the

master issuing a START condition followed by a 7-bit

address (Figure 3) and a read bit (R/W = 1). O nce theeighth bit has been received and the address matches,

the slave issues an acknowledge by pulling low on SD A

for one clock cycle (A = 0) followed by the first byte of

serial data (D11D4, M SB first). A fter the first byte has

been issued by the slave, it releases the bus for themaster to issue an acknowledge (A = 0). A fter receiv-

ing the acknowledge, the slave issues the second byte

(D 3D0 and four zeros) followed by a N O T acknowl-

edge (A= 1) from the master to indicate that the lastdata byte has been received. Finally, the master issues

a ST O P condition (P ) , ending the read cycle (Figure 7).


12 ______________________________________________________________________________________

LSBM SB

SDA

SCL

START SEL2 SEL1 SEL0 RNG BIP PD1 PD0 ACK

START: FIRST LOGIC 1 RECEIVED AFTER ACKNOWL EDGE OF A WRITE.

ACK: ACKNOWLEDGE BIT. THE MAX12 7/M AX128 PULL SDA LOW DURING THE9TH CLOCK PULSE.

Figure 8. C ommand Byte

Figure 9. C omplete 2-Wire Serial Write Transmission

STARTCONDITION

STOPCONDITION

CONTROL BYTESLAVE ADDRESS BYTE

SCL

A/D STATE

SDA

M SB M SBLSB LSB

W

1 2 7 8 9 10 11 15 16 17 18

BIPS

10

PD1 PD0 AA

ACQUISITION CONVERSION

MASTER TO SLAVESLAVE TO MASTER

NO. OF BITS

S SLAVE ADDRESS W A CONTROL-BYTE A P

1 7 1 1 8 1 1

START CONDITION WRITEACKNOWLEDGEACKNOWLEDGE

STOP CONDITION

MASTER TO SLAVESLAVE TO MASTER

NO. OF BITSS SLAVE ADDRESS R A DATA-BYTE A

1 7 1 1 8 1

DATA-BYTE A P

8 1 1

START CONDITION READ NOT ACKNOWLEDGEACKNOWLEDGE STOP CONDITION

Figure 6. Write C ycle

Figure 7. Read Cycle

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The M AX127/M A X128 ignore acknowledge and NO T-

acknowledge conditions issued by the master during

the read cycle. The device waits for the master to read

the output data or waits until a ST O P condition is

issued. Figure 10 shows a complete read cycle.

In unipolar input mode, the output is straight binary. For

bipolar input mode, the output is twos complement. For

output binary codes see the Transfer Functionsection.

Applications Information

Power-On ResetT he M A X127/M A X128 power up in normal operating

mode, waiting for a ST A RT condi tion followed by the

appropriate slave address. The contents of the inputand output data registers are cleared at power-up.

Internal or External ReferenceThe M AX127/M AX128 operate with either an internal or

an external reference (Figures 11a11c). A n external

reference is connected to either REF or to REFADJ.

The REFA D J internal buffer gain is trimmed to 1.6384 to

provide 4.096V at REF from a 2.5V reference.

Internal ReferenceThe internally trimmed 2.50V reference is amplified

through the R EFA D J buffer to provide 4.096V at R EF.

Bypass REF with a 4.7F capacitor to AG ND and bypass

REFAD J with a 0.01F capacitor to AG ND (Figure 11a).The internal reference voltage is adjustable to 1.5%

(65 LSB s) with the reference-adjust circuit of Figure 12.

External ReferenceTo use the REF input directly, disable the internal buffer

by connecting R EFA DJ to VD D (Figure 11b) . U sing the

REFA D J input eliminates the need to buffer the refer-

ence externally. When the reference is applied at

REFA D J, bypass REFA D J with a 0.01F capacitor to

AG ND (Figure 11c).

At REF and REFADJ, the input impedance is a mini-

mum of 10k for DC currents. D uring conversions, an

external reference at R EF must be able to drive a

400A DC load, and must have an output impedance

of 10 or less. If the reference has higher input imped-

ance or is noisy, bypass REF with a 4.7F capacitor to

AG ND as close to the chip as possible.

With an external reference voltage of less than 4.096V

at REF or less than 2.5V at R EFA D J, the increase in

RM S noise to the LSB value (full-scale voltage/4096)

results in performance degradation and loss of effec-

tive bi ts.

Power-Down ModeTo save power, put the converter into low-current shut-

down mode between conversions. Two programmable

power-down modes are available, in addition to the

hardware shutdown. Select STBY PD or FULLPD by pro-

gramming PD0 and PD1 in the input control byte (Table

4). When software power-down is asserted, it becomes

effective only after the end of conversion. In all power-

down modes, the interface remains active and conver-sion results may be read. Input overvoltage protection

is active in all power-down modes.

MAX127/MAX12

8


______________________________________________________________________________________ 13

Figure 10. C omplete 2-Wire Serial Read Transmission

STARTCONDITION

STOPCONDITION

LSB DATA BYTEMSB DATA BYTESLAVE ADDRESS BYTE

M SB M SB M SBLSB LSB LSB

0 1

1 2 7 8 9 10 11 17 18 19 22 23 26 27

R A D11 D4 A D3 D0 A

FILLED WITH4 ZEROS

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M

AX127/MAX12

8

To power-up from a software initiated power-down, a

ST ART condition followed by the correct slave address

must be received (with R/W = 0). T he M AX 127/M AX 128power-up after receiving the next bit.

For hardware-controlled power-down (FU LL PD ) , pull

SHDN low. When hardware shutdown is asserted, itbecomes effective immediately and any conversion in

progress is aborted.

Choosing Power-Down ModesThe bandgap reference and reference buffer remain

active in STBYPD mode, maintaining the voltage on the

4.7F capacitor at REF. This is a DC state that does

not degrade after standby power-down of any duration.

In FU LLPD mode, only the bandgap reference is active.

C onnect a 33F capacitor between REF and A G ND to

maintain the reference voltage between conversions

and to reduce transients when the buffer is enabled

and disabled. Throughput rates down to 1ksps can be

achieved without allotting extra acquisition time for ref-

erence recovery prior to conversion. This allows con-

version to begin immediately after power-down ends. If

the discharge of the R EF capacitor during FUL LP D

exceeds the desired limits for accuracy (less than a

fraction of an LSB ) , run a STBY PD power-down cycle

prior to starting conversions. Take into account that the

reference buffer recharges the bypass capacitor at an

80mV/ms slew rate, and add 50s for settling time.

Auto-ShutdownSelecting STBY PD on every conversion automatically

shuts the M AX127/MAX128 down after each conversion

without requiring any start-up time on the next conversion.


14 ______________________________________________________________________________________

REF

10k

2.5V

CREF4.7F

2.5VREFADJ

AV = 1.638

0.01F

MAX127

MAX128

Figure 11c. External Reference, Reference at REFADJ

100k510k

24k

REFADJ

+5V

0.01FMAX127

MAX128

Figure 12. Reference-Adjust C ircuit

REF

10k

2.5V

CREF4.7F

0.01F

REFADJ

AV = 1.638

MAX127

MAX128

Figure 11a. Internal Reference

REF

VDD

10k

2.5V

4.096V

CREF4.7F

REFADJ

AV = 1.638

MAX127

MAX128

Figure 11b. External Reference, Reference at REF

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Transfer FunctionO utput data coding for the M AX127/M AX128 is binary

in unipolar mode with 1LSB = ( FS/4096) a ndtwos complement binary in bipolar mode with 1LSB =

[ (2 x | FS |) /4096]. C ode transitions occur halfwaybetween successive-integer LSB values. Figures 13a

and 13b show the input/output (I /O ) transfer functions

for unipolar and bipolar operations, respectively. For

full-scale (FS) values, refer to Table 3.

Layout, Grounding, and BypassingC areful printed circuit board layout is essential for best

system performance. For best performance, use aground plane. To reduce crosstalk and noise injection,

keep analog and digital signals separate. C onnect ana-

log grounds and D G N D in a star configuration to

A G N D . For noise-free operation, ensure the ground

return from AG ND to the supply ground is low imped-

ance and a s short as possible. C onnect the logic

grounds directly to the supply ground. Bypass V D D with

0.1F and 4.7F capacitors to AG ND to minimize high-

and low-frequency fluctuations. If the supply is exces-

sively noisy, connect a 5 resistor between the supply

and VDD , as shown in Figure 14.

MAX127/MAX12

8


______________________________________________________________________________________ 15

OUTPUT CODE

INPUT VOLTAGE (LSB)

0 FS

FS - 3/2 LSB

1 LSB =FULL-SCALETRANSITION

1 2 3

11... 111

11... 110

11... 101

00... 011

00... 010

00... 001

00... 000

FS4096

Figure 13a. Unipolar Transfer Function

OUTPUT CODE

INPUT VOLTAGE (LSB)

0 +FS - 1 LSB

1 LSB =

-FS

011... 111

011... 110

000... 001

000... 000

111... 111

100... 010

100... 001

100... 000

2FS4096

Figure 13b. Bipolar Transfer Function

VDD

GND

DGNDDGNDAGND

+5V

+5V

SUPPLY

R* = 5

DIGITALCIRCUITRY

4.7F

0.1F

MAX127

MAX128

**

* OPTIONAL** CONNECT AGND AND DGND WITH A GROUND PLANE OR A SHORT TRACE.

Figure 14. Power-Supply G rounding C onnection

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28

27

26

25

24

23

22

21

20

19

18

17

16

15

1

2

3

4

5

6

7

8

9

10

11

12

13

14

N.C.

REF

REFADJ

N.C.

N.C.

CH7

CH0

N.C.

CH6

CH5

CH4

CH3

CH2

CH1

AGND

SHDN

A1

N.C.

A2

SDA

N.C.

N.C.

A0

SCL

N.C.

DGND

VDD

VDD

SSOP

TOP VIEW

MAX127

MAX128

M

AX127/MAX12

8


M axim cannot assume responsibi lity for use of any circuitry other than circuitry entirely embodied in a M axim product. N o circuit patent licenses are

implied. M axim reserves the right to change the circuitry and specifications without notice at any time.

16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

1998 Maxi m I ntegrated Prod ucts P ri nted US A i s a reg istered trad emark of Maxim I ntegrated Products.













24

23

22

21

20

19

18

17

1

2

3

4

5

6

7

8

N.C.

REF

N.C.

REFADJDGND

N.C.

VDD

VDD

CH7

CH6

CH5

CH4A2

SDA

A0

SCL

16

15

14

13

9

10

11

12

CH3

CH2

CH1

CH0AGND

SHDN

A1

N.C.

DIP

MAX127

MAX128

Pin Configurations

Ordering Information (continued) Chip Information

TRA NSISTO R C O UNT: 4219SUBSTRATE C O NNECTED to AGND

PART

M AX127AC AI

MAX 127BC A I 0C to + 70C

0C to + 70C

TEMP. RANGE PIN-PACKAGE

28 SSO P

28 SSO P 1

1/2

INL(LSB)

M AX127AEN G

M AX127BENG -40C to +85C

-40C to + 85C 24 Narrow Plastic DIP


1/2

M AX127AEA I

M AX127BEAI -40C to +85C

-40C to +85C 28 SSOP

28 SSO P 1

1/2

MAX128ACNG

M AX128BC NG

M AX128AC AI

M AX128BCA I

0C to + 70C

0C to +70C 24 Narrow Plastic DIP

24 Narrow Plastic DI P

0C to + 70C

0C to + 70C

1

1/2

28 SSO P

28 SSO P 1

1/2

M AX128AEN G

M AX128BENG -40C to +85C

-40C to + 85C 24 Narrow Plastic DIP


1/2

M AX128AEA I

M AX128BEAI -40C to +85C

-40C to +85C 28 SSOP

28 SSO P 1

1/2

MAX127-MAX128B

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