MAX110-MAX111
Transcript of MAX110-MAX111
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MAX110/MAX1
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Low-Cost, 2-Channel, 14-Bit Serial ADCs
________________________________________________________________Maxim Integrated Products 1
General Description
T he M A X 110/M A X 111 analog-to-dig ital converters
(A D C s) use an internal auto-calibration technique to
achieve 14-bit resolution plus overrange, with no exter-
nal comp onents. O perating supply current is only
550A (M A X110) and reduces to 4A in power-down
mode, making these AD C s ideal for high-resolution bat-
tery-powered or remote-sensing applications. A fast
serial interface simplifies signal routing and opto-isola-
tion, saves microcontroller pins, and offers compatibility
with SPI , Q SPI , and M ICRO WIRE . The MA X110
operates with 5V supplies, and converts differential
analog signals in the -3V to +3V range. The M A X111
operates with a single + 5V supply and converts differ-
ential analog signals in the 1.5V range, or single-
ended signals in the 0V to +1.5V range.
Internal calibration allows for both offset and gain-error
correction under microprocessor (P) control. Both
devices are available in space-saving 16-pin D IP and
SO packages, as well as an even smaller 20-pin SSO P
package.
________________________Applications
Process Control
Weigh Scales
Panel M eters
Data-Acquisition Systems
Temperature M easurement
____________________________Featureso Single +5V Supply (MAX111)
o Two Differential Input Channels
o 14-Bit Resolution Plus Sign and Overrange
o 0.03% Linearity (MAX110)0.05% Linearity (MAX111)
o Low Power Consumption:550A (MAX110)640A (MAX111)4A Shutdown Current
o Up to 50 Conversions/sec
o 50Hz/60Hz Rejection
o Auto-Calibration Mode
o
No External Components Requiredo 16-Pin DIP/SO, 20-Pin SSOP
Ordering Information
19-0283; R ev 5; 11/98
Typical Operating Circuit Pin Configurations
IN1+
IN1-
REF+REF-
CS
RCSEL
SCLK
DIN
DOUT
IN2+
IN2-
VDD
+5V
-5V (0V)
FROM C
MAX110
MAX111
( ) ARE FOR M AX111
VSS(AGND)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
IN1+
REF-
REF+
VDD
RCSEL
XCLK
SCLK
BUSY
IN1-
IN2+
IN2-
VSS (AGND)
GND
DIN
DOUT
CS
TOP VIEW
MAX110
MAX111
DIP/SO( ) ARE FOR MAX1 11
PART
MAX110AC PE
M AX110BC PE
M A X 110A C WE 0C to + 70C
0C to + 70C
0C to + 70C
TEMP. RANGE PIN-PACKAGE
16 Plastic DI P
16 Plastic DI P
16 Wide SO
M A X110BC WE 0C to + 70C 16 Wide SO
M AX110AC AP 0C to + 70C 20 SSO P
M AX110BC AP 0C to + 70C 20 SSO P
EVALUATIO
NKIT
AVAILABLE
M AX110BC /D 0C to + 70C D ice*
Ordering Information continued at end of data sheet.
* C ontact factory for dice speci fications.
SPI and Q SPI are trademarks of M otorola, I nc. M IC RO WIR E is a trademark of National Semiconductor Corp.
Pin C onfigurations continued at end of data sheet.
INL(%)
0.03
0.05
0.03
0.05
0.03
0.05
0.05
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
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AX110/MAX111
Low-Cost, 2-Channel, 14-Bit Serial ADCs
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ABSOLUTE MAXIMUM RATINGSVD D to G ND ...........................................................................+ 6V
VSS to G ND (M AX 110)..............................................+ 0.3V to -6V
AG ND to DG ND .....................................................-0.3V to + 0.3V
V IN1+ , V IN1-......................................(V D D + 0.3V) to (VSS - 0.3V)
V IN2+ , V IN2-......................................(V D D + 0.3V) to (VSS - 0.3V)
VREF+ , VREF- ....................................(V D D + 0.3V) to (VSS - 0.3V)
D igital Inputs and O utputs ...... ..... ...... ...... ..( VD D + 0.3V) to -0.3V
C ontinuous Power D issipation
16-Pin Plastic D IP ( derate 10.53mW/C above + 70C ) ... ..842mW
16-Pi n Wide SO (derate 9.52mW/C above +70C) ...... 762mW
20-Pi n SSO P ( derate 8.00mW/C above +70C ) ..... ...... 640mW
16-Pi n CE RD IP (derate 10.00mW/C above +70C) ...... 800mW
O perating Temperature Ranges
M AX 11_ _C_ _ ......................................................0C to +70C
M AX 11_ _E_ _ ...................................................-40C to + 85C
M AX 11_BM JE .................................................-55C to + 125C
Storage Temperature Range ...... ...... ..... ...... ..... .-65C to +160C
Lead T emperature (soldering, 10sec) ...... ...... ..... ...... ..... .+ 300C
Stresses beyond those listed under A bsolute M aximum R atings may cause permanent damage to the device. These are stress ratings only, and functionaloperation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure toabsolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICSMAX110(VD D = 5V 5% , VSS = -5V 5% , fXCLK = 1M Hz, 2 mode (D V2 = 1), 81,920 CL K cycles/conv, V REF+ = 1.5V, V REF- = -1.5V,
TA = TM IN to TM A X , unless otherwise noted. T ypical values are at TA = + 25C.)
LSB
nA500
CONDITIONS
I IN + , I IN -Input Bias C urrent
(Note 3) pF10
-0.83 x VR EF V IN 0.83 x VR EF
-VR EF V IN VR EF
-0.83 x VR EF V IN 0.83 x VR EF
Input C apacitance
-VR EF V IN VR EF
VVSS + VD D -
2.25 2.25
V IN + ,
V IN -
Absolute Input Voltage
Range
V-VR EF + VR EFV IND ifferential Input Voltage
Range
ppm30
Power-Supply Rejection15
ppm/C8Full-Scale Error
Temperature D rift
%0.1
V/C0.003O ffset Error
Temperature D rift
(N ote 6)
UNITSMIN TYP MAXSYMBOLPARAMETER
mV4O ffset Error
0.018
0.03 0.06
0.015 0.03
0.04
V IN + = V IN - = 0V
M AX 110BC/E
M AX110AC/E
A fter gain calibration (Note 5)
A fter offset null
VSS = -5V, VDD = 4.75V to 5.25V
VD D = 5V, VSS = -4.75V to -5.25V
(Notes 3, 4) 2DN LDifferential N onlinearity
ppm/V6C M R RC ommon-M ode R ejection
Ratio-2.5V (V IN + = V IN -) 2.5V
Uncalibrated
-8 0Full-Scale Error
Uncalibrated
0.02
-VR EF V IN VR EF-0.83 x VR EF V IN 0.83 x VR EF
% FS RIN LRelative A ccuracy
(N otes 3, 57)
0.10.05
M AX110BM
(Note 2)14 + P O L
+ O FLRESResolution Bits
No-M issing-C odes
Resolution(N ote 3)
13 + P O L
+ O FLBits
ACCURACY (N ote 1)
ANALOG INPUTS
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ELECTRICAL CHARACTERISTICSMAX110 (continued)(VD D = 5V 5% , VSS = -5V 5% , fXCLK = 1M Hz, 2 mode (DV2 = 1), 81,920 C LK cycles/conv, VREF+ = 1.5V, V REF- = -1.5V,TA = TM IN to TM A X , unless otherwise noted. T ypical values are at TA = + 25C.)
V
V4.75 5.25VD DPositive Supply Voltage
0.8V IL
V-4.75 -5.25VSSN egative Supply Voltage
A
Input Low Voltage
550 950
780
IDDPositive Supply C urrent VD D = 5.25V,VSS = -5.25V
320 650
Performance guaranteed by supply rejection test
Performance guaranteed by supply rejection test
pF10
0.4
VD D - 0.5VO HO utput H igh Voltage
Input C apacitance
fXCLK = 500kHz,
continuous-conversion mode
A
AISSN egative Supply CurrentVD D = 5.25V,
VSS = -5.25V
1
20.48
4 10IDD
ILK GInput Leakage C urrent
XC LK unloaded,
continuous-conversion mode, RC
oscillator operational (N ote 9)
fXCLK = 500kHz,
continuous-conversion mode
(N ote 3)
A10ILK GLeakage C urrent
pF10O utput C apacitance
A0.05 2
D igi tal inputs at 0V or 5V
Power-D own Current
D O U T , BUSY, VD D = 4.75V, ISO U R C E = 1.0mA
VD D = 5.25V, VSS = -5.25V, V XCLK = 0V , PD = 1
VO U T = 5V or 0V
(N ote 3)
10,240 clock-cycles/conversion
D O U T , BUSY, ISINK = 1.6mA
CONDITIONS UNITSMIN TYP MAXSYMBOLPARAMETER
ms204.80
tC O N VSynchronous C onversion
Time ( Note 7) 102,400 clock-cycles/conversion
M Hz0.25 1.25fO SCO versampling C lock
Frequency(N ote 8)
V2.4V IHInput High Voltage
ISS
V0 3.0VR EFD ifferential Reference
Input Voltage R ange
pF10Reference Input
C apacitance(N ote 3)
V0.4
VO LO utput Low VoltageXCLK , ISINK = 200A
V
VD D - 0.5XCLK , VD D = 4.75V, ISO U R C E = 200A
nA500IREF+ ,
IREF-Reference Input C urrent VREF+ = 2.5V, VREF- = 0V
VVSS + VD D -
2.25 2.25
VREF+ ,
VREF-
Absolute Reference Input
Voltage Range
CONVERSION TIME
DIGITAL OUTPUTS ( DO UT , BUSY, and XC LK when RC SEL = VD D )
POWER REQUIREMENTS (all digital inputs at 0V or 5V)
REFERENCE INPUTS
DIGITAL INPUTS (CS, SCLK , DIN , and XCLK when RC SEL = 0V)
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ELECTRICAL CHARACTERISTICSMAX111(VD D = 5V 5% , f XCLK = 1MH z, 2 mode (D V2 = 1), 81,920 CLK cycles/conv, VREF+ = 1.5V, VREF- = 0V, TA = TM IN to TM A X ,unless otherwise noted. Typical values are at T A = +25C.)
LSB
nA500
CONDITIONS
I IN + , I IN -Input Bias C urrent
(Note 3) pF10
-0.667 x VREF V IN 0.667 x VR EF
-VR EF V IN VR EF
-0.667 x VREF V IN 0.667 x VR EF
Input C apacitance
-VR EF V IN VR EF
V0 VD D - 3.2V IN + ,
V IN -
Absolute Input Voltage
Range
V-VR EF + VR EFV IND ifferential Input Voltage
Range
-VR EF V IN VR EF
ppm15VD D = 4.75V to 5.25VPower-Supply Rejection
% FS RIN L
ppm/C8Full-Scale Error
Temperature D rift
Relative Accuracy,
D ifferential Input
(N otes 3, 57)
(N otes 3, 4)
0.25
2
%0.2
0.20
DNLDifferential Nonlinearity
(N ote 6)
UNITSMIN TYP MAXSYMBOL
ppm/V6
(Note 2)
PARAMETER
14 + P O L
+ O FLRESResolution
C M R R
mV4O ffset Error
C ommon-M ode R ejection
Ratio10mV (V IN + = V IN -) 2.0V
Bits
No-M issing-C odes
Resolution
0.10
(N ote 3)
-8 0
0.05 0.10
Full-Scale ErrorU ncalibrated
0.03 0.05
M AX111BM
13 + P O L
+ O FLBits
0.18
V IN + = V IN - = 0V
M AX111BC /E
M AX111AC /E
A fter gain calibration (N ote 5)
V IN 0.667 x VR EF
0V V IN VR EF
V IN 0.667 x VR EF
0V V IN VR EF
0V V IN VR EF
V IN 0.667 x VR EF
% FS RIN L
Relative Accuracy,
Single-Ended Input
( IN- = G ND)
0.25
0.15
0.10
0.1
0.06
M AX111BM
0.18M AX111BC /E
M AX111AC /E
ACCURACY (Note 1)
ANALOG INPUTS
-0.667 x VREF V IN 0.667 x VR EF
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ELECTRICAL CHARACTERISTICSMAX111 (continued)(VD D = 5V 5% , f XCLK = 1MH z, 2 mode (D V2 = 1), 81,920 CLK cycles/conv, VREF+ = 1.5V, V REF- = 0V, TA = TM IN to TM A X ,unless otherwise noted. Typical values are at TA = + 25C.)
V
V
V4.75 5.25VD DPositive Supply Voltage
0.4
ms
VO L
0.8V IL
204.80
O utput Low Voltage
A
Input Low Voltage
640 1200
tC O N VSynchronous C onversion
Time ( N ote 7) 102,400 clock-cycles/conversion
XCLK , ISINK = 200A
pF10Reference Input
C apacitance
M Hz0.25 1.25
nA
fO SCO versampling Clock
Frequency(N ote 8)
V2.4V IHInput High Voltage
(N ote 3)
V0 1.5VR EF
960
ID DSupply C urrent VD D = 5.25V
D ifferential Reference
Input Voltage R ange
Performance guaranteed by supply rejection test
500IREF+ ,
IREF-Reference Input Current
pF10
VREF+ = 1.5V, VREF- = 0V
0.4
V0 VD D - 3.2VREF+ ,
VREF-
VDD - 0.5VO HO utput H igh Voltage
Input C apacitance
Absolute Reference Input
Voltage Range
V
VDD - 0.5
fXCLK = 500kHz,
continuous-conversion mode
A1
XCLK , VD D = 4.75V, ISO U R C E = 200A
20.48
4 10ID D
ILK GInput Leakage C urrent
XC LK unloaded,
continuous-conversion mode, RCoscillator operational (N ote 9)
(N ote 3)
A1ILK GLeakage C urrent
pF10O utput C apacitance
A
D igi tal inputs at 0V or 5V
Power-Down Current
D O U T , BUSY, VD D = 4.75V, ISO U R C E = 1.0mA
VD D = 5.25V, VXCLK = 0V , PD = 1
VO U T = 5V or 0V
(N ote 3)
10,240 clock-cycles/conversion
D O U T , BUSY, ISINK = 1.6mA
CONDITIONS UNITSMIN TYP MAXSYMBOLPARAMETER
CONVERSION TIME
DIGITAL OUTPUTS ( DO UT , BUSY, and XC LK when RC SEL = VD D )
POWER REQUIREMENTS (all digital inputs at 0V or 5V)
REFERENCE INPUTS
DIGITAL INPUTS (CS, SCLK , DIN , and XCLK when RC SEL = 0V)
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Note 10: T imi ng specifications are guaranteed by design. A ll input control signals are specified with tr = tf= 5ns(10% to 90% of +5V) and timed from a + 1.6V voltage level.
Note 1: These speci fications app ly after auto-null and gain calibration. P erformance at power-supply tolerance limits is guaranteed
by power-supply rejection tests. Tests are performed at VD D = 5V and VSS = -5V (M AX110).Note 2: 32,768 LSBs cover an input voltage range of VR EF (15 bits). A n additional bit (O FL) is set for VIN > VR EF.Note 3: G uaranteed by design. N ot subject to production testing.Note 4: D NL i s less than 2 counts (LSBs) out of 215 counts (14 bits) . T he major source of DN L is noise, and this can be further
improved by averaging.
Note 5: See 3-Step C alibrationsection in text.Note 6: VR EF = (VREF+ - VREF-) , V IN = (V IN1+ - V IN1-) or (V IN2+ - VIN2-). The voltage is interpreted as negative when the voltage at
the negative input terminal exceeds the voltage at the positive input terminal.
Note 7: C onversion time is set by control bits C O N V1C O NV4.Note 8: Tested at clock frequency of 1M Hz with the divide-by-2 mode ( i.e. oversampling clock of 500kH z). See Typical O perating
C haracteristicssection for the effect of other clock frequencies. A lso read the C lock Frequencysection.
Note 9: This current depends strongly on CXCLK (see Applications Informationsection).
TIMING CHARACTERISTICS (see Figure 6)
(VD D = 5V, VSS = -5V (M AX110), T A = TM IN to TM A X , unless otherwise noted. T ypical values are at TA = + 25C.)
M H z
1.1 3.0M AX11_ BM
RC O scillator Frequency 1.3 2.8M AX 11_ _C /E
2.0TA = +25C
PARAMETER SYMBOL MIN TYP MAX UNITS
80
60
CSto SCLK Hold Time
(Note 10)tC SH 0 ns
D IN to SC LK Setup Time
(Note 10)tD S
100
ns
DIN to SCLK Hold Time
(Note 10)tD H 0 ns
100
60
80CSto SCL K Setup Time
(Note 10)tC SS
100
ns
120SCLK , XC LK Pulse Width
(Note 10)tC K
160
ns
0 35 80
0 100D ata Access Time
(Note 10)tD A
0 120
ns
0 60 100
0 120SCLK to DO UT Valid
D elay (Note 10)tD O
0 140
ns
35 80Bus Relinquish Time
(Note 10)tD H
120ns
M AX11_ BM
M AX 11_ _C/E
TA = +25C
M AX11_ BM
M AX 11_ _C/E
CONDITIONS
M AX 11_ _C /E
M AX 11_ _C /E
M AX11_ BM
TA = +25C
M AX11_ BM
TA = +25C
C L O A D = 50pF
TA = +25C
C L O A D = 50pF
M AX 11_ _C /E
TA = +25C
M AX11_ BM
TA = + 25C
M AX 11_ _C /E/M
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-0.10
0
-0.05
0.05
0.10
-4 -2 0 2 4
M AX110 RELATIVE ACCURACY
(-V REF< VIN< VREF)
M
AX110toc01
VIN (V)
RELATIVEACCURANCY(%FSR)
,
-40C TA +85CRANGE OF INL VALUES(200 PIECE SAMPLE SIZE)
-0.10
0
-0.05
0.05
0.10
-4 -2 0 2 4
M AX110 RELATIVE ACCURACY
(-0.83 VREF< VIN < 0.83 VREF)
M
AX110toc02
VIN (V)
R
ELATIVEACCURANCY(%FSR)
-40C TA +85CRANGE OF INL VALUES(200 PIECE SAMPLE SIZE)
,
0.07
0.06
0.05
MAX110-TOC03
0.02
0.01
0
0 0.25 0.50 0.75 1.00 1.25
0.04
0.03
fOSC (MHz)
RELATIVEACCURACY(%FSR)
1 MODE
2 MODE
4 MODE
VDD=4.75V
VSS =-4.75V
TA =+85C
M AX11 0 RELATIVE ACCURACY vs.
OVERSAMPLING FREQUENCY ( fOSC)
0.10
MAX110-TOC04
0.04
0.02
0
-50 -25 0 25 50 75 100
0.08
0.06
TEMPERATURE (C)
RELATIVEACCURACY(%FSR)
M AX110 RELATIVE ACCURACY
vs. TEMPERATURE
8
6
7 MAX110-TOC05
3
2
0 0.25 0.50 0.75 1.00 1.25
4
5
fOSC(MHz)
POWERDISSIPATION(mW)
4 MODE
2 MODE 1 MODE
MAX110 POWER DISSIPATION vs.
OVERSAM PLING FREQUENCY ( fOSC)
VDD=5.25V
VIN =0V
TA =-40C
__________________________________________Typical Operating Characteristics(M AX110, VD D = 5V, VSS = -5V, VREF+ = 1.5V, V REF- = -1.5V, differential input (V IN + = -V IN -) , fXCLK = 1M Hz, 2 mode (DV2 = 1),
81,920 clocks/conv, TA = + 25C , unless otherwise noted.)
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____________________________Typical Operating Characteristics (continued)(M AX111, VD D = 5V, VREF+ = 1.5V, VREF- = 0V, d ifferential input (V IN + = -V IN -) , fXCLK = 1M Hz, 2 mode (DV2 = 1),
81,920 clocks/conv, TA = + 25C , unless otherwise noted.)
0.14
0.12
0.1
MAX110-TOC08
0.04
0.02
0
0 0.25 0.50 0.75 1.00
0.08
0.06
fOSC (MHz)
RELATIVE
ACCURACY(%FSR)
4 MODE2 MODE
1 MODE
VDD=4.75V
TA =+85C
MAX111 RELATIVE ACCURACY vs.
OVERSAMPLING FREQUENCY (fOSC)
0.10
MAX110-TOC09
0.04
0.02
0
-50 -25 0 25 50 75 100
0.08
0.06
TEMPERATURE (C)
RELATIVE
ACCURACY(%FSR)
MAX111 RELATIVE ACCURACY
vs. TEMPERATURE
7
6
5
MAX110-TOC10
2
1
0
0 0.25 0.50 0.75 1.00 1.25
4
3
fOSC (MHz)
POWERDISSIPATION(mW)
4 MODE
2 MODE 1 MODE
MAX111 POWER DISSIPATION vs.
OVERSAMPLING FREQUENCY (fOSC)
VDD=5.25V
VIN =0V
TA =-40C
0.10
0.05
0
-0.05
-0.10
MAX110-TOC6
VIN (V)
-2.0 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0
M AX111 RELATIVE ACCURACY
(-0.667VREF < V IN < 0.667VREF)
RE
LATIVEACCURACY(%FSR)
0.10
0.05
0
-0.05
-0.10
MAX110-TOC7
VIN (V)
-2.0 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0
M AX111 RELATIVE ACCURACY
(-V REF < V IN < VREF)
REL
ATIVEACCURACY(%FSR)
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_______________Detailed Description
T he M A X110/M A X111 AD C converts low-frequency
analog signals to a 16-bit serial digital output (14 data
bits, a sign bit, and an overrange bit) using a first-order
sigma-delta loop (Figure 1). The differential input volt-
age is internally connected to a precision voltage-to-current converter. T he resulting current is integrated
and applied to a comparator. The comparator output
then drives an up/down counter and a 1-bit DA C . When
the D AC output is fed back to the integrator input, the
sigma-delta loop is completed.
During a conversion, the comparator output is a VREF-to VREF+ square wave; its duty cycle is proportional to
the magnitude of the differential input voltage applied
to the AD C . T he up/down counter clocks data in from
the comparator at the oversampling clock rate and
averages the pulse-width-modulated (P WM ) square
wave to produce the conversion result. A 16-bit static
shift register stores the result at the end of the conver-
sion. Figure 2 shows the AD C waveforms for a differen-
tial analog input equal to 1/2 (V REF+ - VREF-) . Theresulting comparator and 1-bit D A C outputs are high
for seven cycles and low for three cycles of the over-
sampling clock.
Since the analog input signal is integrated over many
clock cycles, much of the signal and quantization noise
is attenuated. The more clock cycles allowed during
each conversion, the greater the noise attenuation (see
Programming C onversion Time) .
______________________________________________________________Pin Description
C lock Input / RC O scillator O utput. TTL /CM O S-compatible oversampling clock input
when RC SEL = G N D . C onnects to the internal RC oscillator when RC SEL = VDD . XCLKmust be connected to V DD or GND through a resistor (1M or less) when RC O SC
mode is selected.
XCLK8
Serial C lock I nput. T TL /CM O S-compatible clock input for serial-interface data I/O .SCLK9
Busy O utput. G oes low at conversion start, and returns high at end of conversion.BUSY10
Positive P ower-Supply Input connect to + 5VVD D6
RC Select Input. C onnect to G ND to select external clock mode. C onnect to VD D to
select RC O SC mode. XC LK must be connected to VD D or G ND through a resistor
(1M or less) when RC O SC mode is selected.
RCSEL7
Positive R eference InputREF+3
Negative Reference InputREF-2
C hannel 1 Positive Analog InputIN1+1
FUNCTIONNAMESSOP
6
7
8
4
5
3
2
PIN
1
DIP/SO
C hip-Select Input. Pull this input low to perform a control-word-write/data-read opera-
tion. A conversion begins whenCSreturns high, provided NO-OP is a 1. See the sec-
tion Using the M AX 110/M AX111 with SPI , Q SPI , and M IC RO WIR E Serial Interfaces.
CS119
Serial Data O utput. High-impedance whenCS is high.D O U T1210
Serial Data Input. See C ontrol Registersection.D IN1311
D igital G roundG ND1612
M AX110 Negative Power-Supply Input connect to -5VVSS
C hannel 2 Negative Analog InputIN2-1814
C hannel 2 Positive Analog InputIN2+1915
C hannel 1 Negative Analog InputIN1-2016
No C onnect there is no internal connection to this pinN .C .4, 5, 14, 15
M AX111 Analog G roundA G N D
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Oversampling ClockXC LK internally connects to a clock-frequency divider
network, whose output is the AD C oversampling clock,fO SC . T his allows the selected clock source ( internal R C
oscillator or external clock applied to XC LK ) to be
divided by one, two, or four (see C lock D ivider-R atio
C ontrol Bits) .
Figure 3 shows the two methods for providing the over-
sampling clock to the M A X110/M A X111. In external-
clock mode ( Figure 3a), the internal R C oscillator is
disabled and XC LK accepts a TT L/CM O S-level clock to
provide the oversampling clock to the A D C .
Select external-clock mode (Figure 3a) by connecting
RC SEL to G ND and a TT L/CM O S-compatible clock to
X C L K ( s e e Select ing the O versampl ing C lock
Frequency) .
In RC -oscillator mode ( Figure 3b), the internal RC oscil-
lator is active and i ts output is connected to XC LK
(Figure 1). Select RC -oscillator mode by connecting
RCSEL to VDD . This enables the internal oscillator and
connects it to XC LK for use by the AD C and external
system components. M inimize the capacitive loading on
XC LK when using the internal RC oscillator.
DIFFERENTIALANALOG
INPUT
VREF+
DC LEVEL AT 1/2 VREF
VREF-
VREF+
VREF-
OUTPUT FROM1-BIT DAC
OVERSAMPLINGCLOCK
MAX110
MAX111
Figure 2. AD C Waveforms During a Conversion
Figure 1. Functional D iagram
IN1+
IN+
IN-INPUTM UX
IN1-
IN2+
IN2-
REF+
Gm
REF-
Gm
INTEGRATOR
UP/DOWNCOUNTER-
DITHERGENERATOR
SERIALSHIFT
REGISTER
DIN SCLK CS
16 16
16 16
CONTROLREGISTER
DOUT
BUSY
RCSEL
XCLK
OSC
TIMER + CONTROLLOGIC + CLOCK GENERATOR
DIVIDERNETWORK,DIVIDE BY1, 2, OR 4
RCOSCILLATOR
MAX110
MAX111
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ADC OperationThe output data from the M AX110/M AX111 is arranged
in twos-complement format (Figures 4, 5). The sign bit
(PO L) is shifted out first, followed by the overrange bit
(O R ) , and the 14 data bits (M SB first) (see Figure 6) .
The M AX110 operates from 5V power supplies andconverts low-frequency analog signa ls in the 3V
range when using the maximum reference voltage of
VREF = 3V (VREF = VREF+ - VREF-). Within the 3V input
range, greater accuracy is obtained within 2.5V (see
Electrical C haracteristicsfor details). Note that a nega-
tive input voltage is defined as V IN - > V IN + . For the
M AX110, the absolute voltage at any analog input pin
must remain within the (VSS + 2.25V) to (VDD - 2.25V)
range.
The M AX111 operates from a single +5V supply and
converts low-frequency differential analog signals in the
1.5V range when using the maximum reference volt-
age of VR EF = 1.5V. A s indicated in the Electrical
C haracteristics, greater accuracy is achieved within the1.2V range. The absolute voltage at any analog input
pin for the M AX111 must remain within 0V to VDD - 3.2V.
When V IN - > V IN + the input is interpreted as negative.
The overrange bit (O FL) is provided to sense when the
input voltage level has exceeded the reference voltage
level. T he converter does not saturate until the input
voltage is typically 20% larger. The linearity is not guar-
anteed in this range. N ote that the overrange bi t works
properly if the reference voltage remains within the rec-
ommended voltage range (see Reference Inputs). If the
reference voltage exceeds the recommended input
range, the overrange bit may not operate properly.
Digital InterfaceStarting a Conversion
D ata is transferred into and out of the serial I/O shiftregister by pulling CS low and applying a serial clockat SC LK . T his fully static shift register allows SC LK to
range from D C to 2M Hz. O utput data from the AD C is
clocked out on SC LK s falling edge and should be read
on SCL K s rising edge. Input data to the AD C at DIN is
clocked in on SC LK s rising edge. A new conversion
begins when CS returns high, provided the M SB in theinput control word (NO-OP) is a 1 (see U sing theM AX110/M AX 111 with M IC RO WIRE, SPI , and Q SPI
Serial Interfaces). Figure 6 shows the detailed serial-
interface timing diagram.
CS must remain high during the conversion (whileBUSYremains low) . Bringing CS low during the conver-
sion causes the A D C to stop converting, and mayresult in erroneous output data.
Using the MAX110/MAX111 with SPI, QSPI, andMICROWIRE Serial Interfaces
Figure 7 shows the most common serial-interface con-
nections. The M A X110/M A X111 are compatible with
SP I, Q SP I (CPHA = 0, CPO L = 0) , and M IC RO WIRE
serial-interface standards.
XCLK
TTL/CMOS
RCSEL
GND
+5V
-5V (0V)
( ) ARE FOR MAX 111.
VDD
VSS (AGND)
MAX110
MAX111
Figure 3b. C onnection for Internal RC -O scillator M ode XC LK
connects to the internal RC oscillator. N ote, the pull-up resistor
is not necessary if the internal oscillator is never shut down.
XCLK
RCSEL
1M
GND
+5V
-5V (0V)
VDD
+5V
VSS (AGND)
MAX110
MAX111
( ) ARE FOR MAX1 11.
Figure 3a. C onnection for External-C lock M ode
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OUTPUTCODE +OVERFLOW
TRANSITION
-OVERFLOWTRANSITION
POL OFL D13...D0
0 1 00 . . .000
1 1 00 . . .001
1 1 00 . . .000
1 1 00 . . .010
1 0 11 . . .111
VREF -1LSBINPUT VOLTAGE (LSBs)
- V REF
0 0 11 . . .111
0 0 11 . . .110
0 0 11 . . .101
0 0 11 . . .100
+OVERFLOW
0 0 00 . . .001
0 0 00 . . .001
0 0 00 . . .000
1 1 11 . . .111
1 1 11 . . .110
1 1 00 . . .011
-OVERFLOW
Figure 4. D ifferential Transfer Function
OUTPUTCODE OVERFLOW
TRANSITION
POL OFL D13...D00 1 00 . . .000
0 0 00 . . .001
0 0 00 . . .000
0 0 00 . . .010
1 1 11 . . .111
VREF -1LSBINPUT VOLTAGE (LSBs)
0 1 2 3
0 0 11 . . .111
0 0 11 . . .110
0 0 11 . . .101
0 0 11 . . .100
+OVERFLOW
0 0 00 . . .011
Figure 5. U nipolar Transfer Function
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CS
SCLK
tCSH
tCSS
tCK
tDH
M SB LSB
tDS
DIN
DOUT
BUSY
tDH
tCK
tDO
tDA
POL OFL M SB DO
END OFCONVERSION
START OFCONVERSION
Figure 6. Detailed Serial-Interface T iming
The AD C serial interface operates with just SC LK , D IN ,
and D O U T (allow sufficient time for the conversion to
complete between read/write operations). Achieve con-
tinuous operation by connecting BUSYto an uncommit-ted P I/O or interrupt, to signal the processor when the
conversion results are ready. Figures 8a and 8b showthe timing for SPI/M IC RO WIRE and Q SPI operation.
T he fully static 16-bi t I/O register allows infinite time
between the two 8-bit read/write operations necessary
to obtain the full 16 bits of data with SPI and
M I C R O W I R E . CS must remain low during the entiretwo-byte transfer (Figure 8a) . Q SP I allows a full 16-bit
data transfer (Figure 8b).
Interfacing to the 80C32 Microcontroller FamilyFigure 7c shows the general 80C 32 connection to the
M AX110/M AX111 using Port 1. For a more detailed dis-
cussion, see the M AX110 evaluation kit manual.
I/O Shift RegisterSerial data transfer is accomplished with a 16-bit fullystatic shift register. T he 16-bit control word shifted into
this register during a data-transfer operation controls
the A D C s various functions. T he M SB (NO -OP)enables/disables transfer of the control word within the
AD C . A logic 1 causes the remaining 15 bits in the con-
trol word to be transferred from the I/O register into the
control register when CS goes high, updating theAD C s configuration and starting a new conversion. I f
I/O
SCK
MISO
MOSIMASKABLEINTERRUPT
SS
a. SPI/QSPI
+5V
P
CS
SCLK
DOUT
DINBUSY
MAX110
MAX111
I/O
SK
SI
SO
MASKABLEINTERRUPT or I/ O
b. MICROWIRE
P
CS
SCLK
DOUT
DIN
BUSY
P1.0
P1.1
P1.2
P1.3
P1.4
c. 80C51/80C32
P
CS
SCLK
DIN
DOUT
BUSY
MAX110
MAX111
MAX110
MAX111
Figure 7. C ommon Serial-Interface C onnections
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BUSY
1ST BYTE READ/WRITE 2ND BYTE READ/WRITE
CS
SCLK
DOUTPOL OFL D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
NO OP NU NU CONV4 CONV3 CONV2 CONV1 DV4 DV2 NU NU CHS CAL NUL PDX PDDIN
MAX110
MAX111
Figure 8a. SPI /M IC RO WIR E-Interface Timing
BUSY
CS
SCLK
DOUT POL OFL D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
NO OP NU NU CONV4 CONV3 CONV2 CONV1 DV4 DV2 NU NU CHS CAL NUL PDX PDDIN
MAX110
MAX111
Figure 8b. Q SP I Serial-Interface Ti ming
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NO-OP is a zero, the control word is not transferred tothe control register, the AD C s configuration remains
unchanged, and no new conversion is initiated. This
allows specific AD C s in a daisy chain arrangement tobe reconfigured while leaving the remai ning AD C s
unchanged. T able 1 lists the various AD C control word
functions.
O utput data is shifted out of DO U T at the same time the
input control word for the next conversion is shifted in
(Figure 8).
O n power-up, all internal registers reset to zero.
T herefore, when writing the first control word to the
ADC , the data simultaneously shifted out will be zeros.
The first conversion begins when CSgoes high (NO-OP= 1). The results are placed in the 16-bit I /O register for
access on the next data-transfer operation.
Power-Down ModeBits 0 and 1 control the AD C s power-down mode. I f bit
0 (PD) is a logic high, power is removed from all analog
circuitry except the RC oscillator. A logic high at bit 1
(PD X) removes power from the RC oscillator. I f both bits
PD and PDX are a logic high, or if PD is high and
RC SEL is low, the supply currents reduce to 4A. I f an
external XC LK clock continues to run in power-down
mode, the supply current will depend on the clock rate.
When PD X is set high, the internal RC oscillator stops
shortly after CS returns high. If the next control wordwritten to the device has NO-OP = 1 instructing the
AD C to convert, B U SY will go low, but because the RCoscillator is stopped, BU SY will remain low and will not
allow a new conversion to begin. To avoid this situation,
write a dummy control word with NO-OP= 0 and anycombination of bits 14-0 in the control word following
the control word with PD X = 0. With NO-OP= 0, bits 14-0 are ignored and the internal state machine resets.
Next, perform a normal 3-step calibration (see Table 3).
N ote that XC LK must be connected to VD D or GN D
through a resistor (suggested value is 1M ) when the
R C oscillator mode is selected (R C SEL = VD D ). This
resistor is not necessary if the external oscillator mode
is used, or if the internal oscillator is not shut down.
Selecting the Analog InputsBit 4 (C HS) controls which of the two differential inputs
connect to the internal AD C inputs (see the Functional
Diagram) . A logic high selects IN2+ and IN 2- while a
logic low selects IN 1+ and I N 1-. T able 2 shows the
allowable input multiplexer configurations.
Table 1. Input Control-Word Bit Map
First bit clocked in.
PDPD XNU LCALCHSNUNUDV2DV4CONV1CONV2CONV3CONV4NUNUNO-OP
0123456789101112131415
Analog Power-Down. Set this bit high to power down the analog section.PD0
O scillator Power-Down. Set this bit high to power down the RC oscillator.PDX1
Internal O ffset-N ull Bit. A logic high selects offset-null mode. See T able 3.NUL2
G ain-C alibration Bi t. A logic high selects gain-calibration mode. See Table 3.C AL3
Input C hannel Select. A logic high selects channel 2 (IN 2+ and IN2-), while a logic low
selects channel 1 (I N1+ and IN 1-). See T ables 2 and 3.C H S4
XC LK to O versampling C ock R atio Control Bits. See T able 5.DV2, DV47, 8
C onversion Time C ontrol Bi ts. See T able 4.CONV1CONV4912
U sed for test purposes only. Set these bits low.NU5, 6, 13, 14
If this bit is a logic high, the remaining 15 LSBs are transferred to the control register and a
new conversion b egins whenCSreturns high. If this bit is set low, the control word is not
passed to the control register, the ADC configuration remains unchanged, and no new con-
version begins whenCSreturns high.
NO-OP15
DESCRIPTIONNAMEBIT
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X = D on't C are
Table 3. Procedure to Calibrate the ADC
0010
0
or
1
00XXNo
C hange001
Performs an offset-null conversion with the
internal A D C inputs shorted to the selected
input channel's negative input (IN1- or IN2-).
The next operation performs the first signal
conversion with the new setup.
3
0001X00XXNo
C hange001
Performs a gain-calibration conversion with
the null register contents as the starting value.
The result is stored in the calibration register.
2
0011X00XXNew
Data001
Sets the new conversion speed ( if required)
and performs an offset correction conversion
with the internal A DC inputs shorted to R EF-.
The result is stored in the null register.
(This step also selects the speed/resolution
for the ADC .)
1
PDPDXNULCALCHSNot
UsedDV2 &DV4
CONV1-CONV4
NotUsed
NO-OPDESCRIPTIONSTEP
CONTROL WORD
X = D on't C are
Table 2. Allowable Input Multiplexer Configurations
Input control word is not transferred to the control register. AD C
configuration remains unchanged and no new conversion starts whenCS
returns high.
No
C hange
No
C hange0XXX
REF+ and R EF- connected to the ADC inputs; gain-calibration mode
selected. A utocal conversion begi ns whenCSreturns high, and the results are
stored in the 16-bit I /O register.
REF-REF+1X01
REF- connected to the ADC inputs; offset-null mode selected. Autonull conversion
begins whenCSreturns high, and the results are stored in the null register.REF-REF-1X11
IN 2- connected to the ADC inputs; offset-null mode selected. Autonull conversion
begins whenCSreturns high, and the results are stored in the null register.IN2-IN2-1110
IN 1- connected to the ADC inputs; offset-null mode selected. Autonull conversion
begins whenCSreturns high, and the results are stored in the null register.IN1-IN1-1010
C hannel 2 connected to AD C inputs. Conversion begins whenCSreturns high.IN2-IN2+1100
C hannel 1 connected to AD C inputs. Conversion begins whenCSreturns high.IN1-IN1+1000
DESCRIPTIONADC IN-ADC IN+NO-OPCHSNULCAL
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3-Step Calibration
T he data sheet electrical specifications apply to thedevice after optional calibration of gain error and offset.
U ncalibrated, the gain error is typically 2% .
Table 3 describes the three steps required to calibrate
the AD C completely.
O nce the AD C is calibrated to the selected channel, set
C AL = 0 and NU L = 0 and leave CH S unchanged in the
next control word to perform a signal conversion on the
selected analog input channel.
C alibrate the AD C after the following operations:
when power is first applied
if the reference common-mode voltage changes
if the common-mode voltage of the selected inputchannel varies significantly. T he C M RR of the analog
inputs is 0.25LSB/V.
after changing channels (if the common-mode volt-
ages of the two channels are different)
after changing conversion speed/resolution.
after significant changes in temperature. The offset
drift with temperature is typically 0.003V/C .
Automatic gain calibration is not allowed in the
102,400 cycles per conversion mode (seeProgramming Conversion Time). In this mode, calibra-
tion can be achieved by connecting the reference volt-
age to one input channel and performing a normal
conversion. Subsequent conversion results can be cor-
rected by software. Do not issue a NO-OP commanddirectly following the gain calibration, as the cali-bration data will be lost.
Programming Conversion TimeThe M AX110/M AX111 are specified for 12 bits of accu-
racy and up to 14 bits of resolution. T he ADC s resolu-
tion depends on the number of clock cycles allowed
during ea ch conversion. C ontrol-register bi ts 912
(C O N V1CO N V4) determine the conversion time by
controlling the nominal number of oversampling clock
cycles required for each conversion (O SC C /C O N V) .
Table 4 lists the available conversion times and result-
ing resolutions.
To program a new conversion time, perform a 3-step
calibration with the appropriate C O N V1C O N V4 data
used in T able 3. The ADC is now calibrated at the new
conversion speed/resolution.
Table 4. Available Conversion Times
* G ain-calibration mode is not available with 102,400 clock cycles/conversion selected.
C lock duty cycles of 50% 10% are recommended.
Table 5. Clock Divider-Ratio Control
CONV4 CONV3 CONV2 CONV1CLOCK CYCLES
PERCONVERSION
NOMINAL CONVERSION TIMERCSEL = GND, DV2 = DV4 = 0, XCLK = 500kHz
(ms)
CONVERSIONRESOLUTION
(Bits)
1 0 0 1 10,240 20.48 12 + PO L
0 0 1 1 20,480 40.96 13 + PO L
0 1 1 0 81,920 163.84 14 + PO L
0 0 0 0 102,400* 204.80 14 + PO L
N ot allowed11
XC LK or internal RC oscillator is divided by 2 and connects to the ADC ; fO SC = fXCLK 2.01
XC LK or internal RC oscillator is divided by 4 and connects to the ADC ; fO SC = fXCLK 4.10
XC LK or internal RC oscillator connects directly to the ADC ; fO SC = fXCLK .00
DESCRIPTIONDV4DV2
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18 ______________________________________________________________________________________
Selecting the OversamplingClock Frequency
C hoose the oversampling frequency, fO SC , carefully to
achieve the best relative-accuracy performance from the
M AX110/M AX111 (see Typical O perating Characteristics) .
Clock Divider-Ratio Control BitsBi ts 7 and 8 ( D V2 and D V4) program the clock-
frequency divider network. The divider network sets the
frequency ratio between fXCLK (the frequency of theexternal TT L/C M O S clock or internal RC oscillator) and
fO SC ( the oversampling frequency used by the AD C ) .
An oversampling clock frequency between 450kH z and
700kH z is optimum for the converter. Best perfor-mance over the extended temperature range isobtained by choosing 1MHz or 1.024MHz with thedivide-by-2 option (DV2 = 1) (see the section Effectof Dither on INL). To determine the converters accura-cy at other clock frequencies, see the Typical
O perating C haracteristicsand Table 5.
Effect of Dither on Relative AccuracyFirst-order sigma-delta converters require dither for
randomizing any systematic tone being generated in
the modulator. The frequency of the dither source playsan important role in linearizing the modulator. The ratio
of the dither generators frequency to that of the modu-
lators oversampling clock can be changed by setting
the DV2/DV4 bits. T he XC LK clock is directly used by
the dither generator while the DV2/DV4 b its reduce the
oversampling clock by a ratio of 2 or 4. O ver the com-
mercial temperature range, any ratio (i.e., 1, 2, or 4)
between the dither frequency and the oversampling
clock frequency can be used for best performance.
O ver the extended and mi litary temperature ranges, the
ratio of 2 or 4 gives the best performance. See the
Typical O perating C haracteristicsto observe the effect
of the clock divider on the converters linearity.
50Hz/60Hz Line Frequency RejectionH igh rejection of 50Hz or 60Hz is obtained by using an
oversampling clock frequency and a clock-cycles/con-
version setting so the conversion time equals an inte-gral number of line cycles, as in the following equation:
fO SC = fLINE x m / n
where fO SC is the oversampling clock frequency, fLINE= 50Hz or 60Hz, m is the number of clock cycles per
conversion (see Table 4), and n is the number of line
cycles averaged every conversion.
This noise rejection is inherent in integrating and
sigma-delta A D C s, and follows a SIN (X) / X function
(Figure 9) . Notches in this function represent extremely
high rejection, and correspond to frequencies with an
integral number of cycles in the M A X110/M A X111s
selected conversion time.
T he shortest conversion time resulting in maximumsimultaneous rejection of both 60Hz and 50Hz line fre-
quencies is 100ms. When using the M A X111, use a
200ms conversion time for maximum 60Hz and 50Hz
rejection and optimum performance. For either device,select the appropriate oversampling clock frequency
and either an 81,240 or 102,400 clock cycles per con-
version (C C PC ) ratio. T able 6 suggests the possible
configurations.
0
-10
-20
-30
-40
-50
-60
0.1
1
CONVERSION TIME
LINE CYCLE PERIOD
SIGNAL FREQUENCY IN HzFOR 100ms CONVERSION
TIME (see Table 6)
1
10 20 30 40 50 60708090100
2 3 4 5 6 7 8 910
GAIN(dB)
Figure 9. M AX110/M AX111 Noise Rejection Follows SIN (X) / X Function
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A 100ms conversion time cannot be achieved with either
10,240 C C PC or 20,480 C C PC modes because fO SCwould be below the minimum 250kHz requirement.
When the gain calibration is performed, the conversion
times change approximately 1% to compensate for the
modulators gain error. This slightly degrades the line-
frequency rejection, because the corrected conversion
time is no longer an exact multiple of the line frequency.Typically, the rejection of 50Hz/60Hz from the converter
is 55dB; i.e., if there is 100mV injection at the reference
or the analog input pin, it will cause an uncertainty of
0.006% . If the system has large 50Hz/60Hz noise, the
use of internal auto gain calibration is not recommend-
ed. Instead, gain calibration should be done off-chip,
using numerical computation methods.
If you wish to use a configuration other than those sug-
gested in Table 6, you can accomplish similar 50Hz
and 60Hz line-frequency rejection off-chip by averag-
ing several conversions.
__________Applications Information
Layout, Grounding, Bypassing
For minimal noise, bypass each supply to G ND with a0.1F capacitor. A ground plane should also be placed
under the analog circuitry. To minimize the coupling
effects of stray capacitance, keep digital lines as far
from analog components and lines as possible. Figure
10 shows the suggested power-supply and ground-
plane connections.
*R = 10
*OPTIONAL
DIGITALCIRCUITRY
POWERSUPPLIES
VDD VSS +5V DGND
+5V -5V GND
GND
4.7F
0.1F 0.1F
4.7F
MAX110
Figure 10a. M AX110 Power-Supply G rounding C onnections
*R = 10
*OPTIONAL
DIGITALCIRCUITRY
POWERSUPPLIES
VDD AGND +5V DGND
+5V GND
GND
4.7F
0.1F
MAX111
Figure 10b. M AX111 Power-Supply G rounding C onnections
C C PC = C lock C ycles per C onversion
Table 6. Suggested XCLK Frequencies to Achieve Maximum Rejection of Both 50Hz/60Hz LineFrequencies
MAX111 (tCONVERT = 200ms)
81,240 CCPC 102,400 CCPC
DIVIDERRATIO fXCLK
(MHz)
RELATIVEACCURACY
(%)
fXCLK(MHz)
RELATIVEACCURACY
(%)
1:1 0.4062 0.030 0.512 0.030
2:1 0.8124 0.025 1.024 0.025
4:1 1.6248 0.022 2.048 0.023
MAX110 (tCONVERT = 100ms)
81,240 CCPC 102,400 CCPC
DIVIDERRATIO fXCLK
(MHz)
RELATIVEACCURACY
(%)
fXCLK(MHz)
RELATIVEACCURACY
(%)
1:1 0.8124 0.025 1.024 0.065
2:1 1.6248 0.018 2.048 0.045
4:1 3.2496 0.016 4.096 0.030
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Capacitive Loading Effects of XCLK in
Internal RC-Oscillator ModeWhen using the internal RC oscillator, capacitive load-
ing effects on the XC LK pin must be minimized. Stray
capacitance causes the VD D power consumption to
increase by an amount p = 12C V2f, where C = stray
capacitance, V is the supply voltage, and f is the fre-
quency of the internal R C oscillator.
External ReferenceThe reference inputs to the ADC are high impedance,
allowing both an external voltage reference and ratio-
metric applications without loading effects. T he fully dif-
ferential analog signal and reference inputs are
advantageous for performing ratiometric conversions
(Figures 11 and 12). For example, when measuring
load cells, the bridge excitation and the AD C referenceinput both share the same voltage source. A s the exci-
tation changes with temperature or voltage, the output
of the load cell will change. But since the differential
reference voltage also changes, the conversion results
remain constant, all else remaining equal.
Weigh Scale Application
The fully differential analog signal and reference inputsmake the M AX111 easy to interface to transducers with
differential outputs, such as the load cell in Figure 11.
Because the ADC input is differential, the load cell only
requires differential gain, eliminating the need for the
difference amplifier (differential to single-ended con-
verter) of the standard three op-amp instrumentation-
amplifier realization.
The 30mV full-scale bridge output is amplified to 2V
full-scale and ap plied to the M A X111 channel-one
input. The reference voltage to the AD C is created by a
voltage divider connected to the + 5V rail. T he same 5V
provides excitation for the bridge; therefore, as the
excitation voltage varies, the reference voltage to the
AD C also varies, providing an AD C output that doesnot depend on the supply voltage.
The two 121k resistors connected to the +5V supplies
shift the common-mode voltage from 2.5V (5V/2) to
1.5V to ensure linearity. M atch these two resistors to
avoid introducing differential offset, or trim the resistor
mismatch with a potentiometer. In practice, the scale is
zeroed or tared by storing the average of several
conversions in a memory location while the scale is
+5V
30mVFULL-SCALE
121k
2k
121k
49.9k
1k
22k
10k
1k
1k
1/2 MAX492
1/2 MAX492
1F
1F
REF+
REF-
IN1+
IN1-
AGND
CS
DIN
DOUT
SCLK
49.9k
VDD
+5V
0.1F
MAX111
+5V
+5V
+5V
GND
Figure 11. Weigh Scale Application
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21/24
unloaded, and subtracting this value from actual weightmeasurements. The lowpass filtering action of the
M AX111s sigma-delta converter helps minimize noise.
T he resolution of the weigh scale ca n be further
increased by averaging several conversions.
Thermocouple Circuit with SoftwareCompensation
A thermocouple is created by the junction of dissimilar
metals, and generates a voltage proportional to temper-
ature (Seebeck voltage), making it useful for tempera-
ture-measurement instruments. When a thermocouple
probe is connected to a measurement instrument, other
thermoelectric potentials are created between the alloys
of the probe and the copper connectors of the instru-
ment. T hese potentials introduce a temperature-depen-dent error that must be subtracted from the temperature
measurement to obtain an accurate result. According to
the law of intermediate metals, the junction of the ther-
mocouple-probe alloys with the copper of the instrument
junction block can be treated as another thermocouple
of the same type. The voltage measured by the instru-
ment can be expressed as:
V = (T1 - TREF)
where
is the Seebeck constant for the type of thermo-couple, T1 is the temperature being measured, and
TREF is the temperature of the junction block. A lthough
one method to obtain T REF is to force the junction block
to a known temperature ( 0C ) , a more popular
approach is to measure TREF directly using a thermistor
or PN junction voltage.
The circuit in Figure 12 shows a k-type thermocouple
going through a 54dB gain stage to channel 1 of the
M A X110. A M AX874 voltage reference provides both
the 3V reference voltage and reference junction tem-
perature information to the M A X110. A rmed with the
temperature information provided by the M AX874, the
thermocouple voltage created at the junction block can
be subtracted out in software. The TEM P output of theM AX874 is nominally 690mV at room temperature, and
increases with temperature at about 2.3mV/C . Place
the M AX874 as close as possible to the terminal block,
and ensure good thermal contact between them. This
circuit employs a common k-type thermocouple and,
with the component values shown, can indicate tem-
peratures in the range of -150C to +125C .
MAX110/MAX1
11
Low-Cost, 2-Channel, 14-Bit Serial ADCs
______________________________________________________________________________________ 21
243k
1k
1k
10k
1F
1F
IN1+
IN1-
REF-
REF+
VSS
-5 V
CS
DIN
DOUT
SCLK
243k
1M
1k
10k 10k
K-TYPE
VDD
+5V
IN2-
IN2+
MAX1101/4 MAX479
1/4 MAX479
1/4 MAX479
TEMP
OUT
VIN
MAX874
+5V
Figure 12. Thermocouple C ircuit with Software C ompensation
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M
AX110/MAX111
Low-Cost, 2-Channel, 14-Bit Serial ADCs
22 ______________________________________________________________________________________
TOP VIEW
1
2
3
4
5
6
7
8
20
19
18
17
16
15
14
13
IN1+
REF-
REF+
N.C.
N.C.
VDD
RCSEL
XCLK
IN1-
IN2+
IN2-
VSS (AGND)
GND
N.C.
N.C.
DIN
9
10
12
11
SCLK
BUSY
DOUT
CS
MAX110
MAX111
SSOP( ) ARE FOR MAX11 1
____Pin Configurations (continued)
_Ordering Information (continued) __________________Chip Topography
TRA NSISTO R C O UNT: 5849
SUBSTRATE CO NNECTED TO VD D
V SS( AG ND)
RCSEL
REF+
DO UTXCLK
0 . 1 6 8 "
( 4 . 2 7 m m )
0 . 1 2 1 "
( 3 . 0 7 m m )
SCLK BU S Y CS D I N
V SS( AG ND)
GN D
GN D
R EF- I N1 + I N 1 - I N 2 + I N 2 -
V D D
V D D
( ) ARE F O R M AX 11 1
0.0516 Plastic DIP-40C to + 85CM AX110BEPE
0.05
0.05
0.03
0.05
0.03
0.03
INL(%)
16 C ERD IP**-55C to + 125CM AX110BM JE
20 SSO P-40C to + 85CM AX110BEAP
20 SSO P-40C to + 85CM AX110AEA P
16 Wide SO
16 Wide SO
16 Plastic DIP
PIN-PACKAGETEMP. RANGE
-40C to + 85C
-40C to + 85C
-40C to + 85CM AX 110BEWE
M AX 110AEWE
M AX110AEPE
PART
MAX111AC PE 0C to + 70C 16 Plastic D IP 0.03
M A X111BC PE 0C to + 70C 16 Plastic D IP 0.05
M AX111AC WE 0C to + 70C 16 Wide SO 0.03
M AX111BC WE 0C to + 70C 16 Wide SO 0.05
M AX111AC AP 0C to + 70C 20 SSO P 0.03
M AX111BC AP 0C to + 70C 20 SSO P 0.05
M AX111BC /D 0C to + 70C D ice* 0.05
M A X111A EP E -40C to + 85C 16 P lastic D IP 0.03
M A X111B EP E -40C to + 85C 16 P lastic D IP 0.05
M A X111A EWE -40C to + 85C 16 Wide SO 0.03
M A X111BEWE -40C to + 85C 16 Wide SO 0.05
M AX111AEAP -40C to + 85C 20 SSO P 0.03
M AX111BEAP -40C to + 85C 20 SSO P 0.05
M A X111B M JE -55C to + 125C 16 C ER D IP ** 0.05
* C ontact factory for dice specifications.
** C ontact factory for availabili ty.
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MAX110/MAX1
11
Low-Cost, 2-Channel, 14-Bit Serial ADCs
______________________________________________________________________________________ 23
_______________________________________________________Package Information
PDIPN.EPS
SOICW.EPS
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M
AX110/MAX111
Low-Cost, 2-Channel, 14-Bit Serial ADCs
___________________________________________Package Information (continued)
CDIPS.EPS
M axim cannot assume responsibili ty for use of any circuitry other than circuitry entirely embodied in a M axim product. N o circuit patent licenses are
implied. M axim reserves the right to change the circuitry and specifica tions without notice at any time.
24 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
1998 M i I t t d P d t P i t d US A i i t d t d k f M i I t t d P d t
SSOP.E
PS