Maskless Device Fabrication Technology Using an Integrated Microwave CAD/CAM System (Invited Art i c I e)

Takashi Yamada, Kaoru Nogawa, Madoka Nishikawa, and Yasoo Harada

Sanyo Electric Co., Ltd., Semiconductor Research Center, 1-1 8-1 3 Hashiridani, Hirakata-shi, Osaka 573, Japan Received December 16. 1992; revised February 1 1 , 1993.

ABSTRACT

A maskless process for MMICs using highly sensitive posi-type EB resists was developed using our integrated microwave CAD/CAM system. The process can fabricate fine patterns with 0.1-pm levels and align layer-to-layer and field-to-field within an accuracy below 0.05 pm (a) using two types of alignment marks. Topography simulation of EB lithography using the Monte Carlo method was also added to the system to obtain the profiles of posi-type single- and double-layer resist structures used for the process. The maskless process was successfully applied to an L-band low-noise amplifier with a 0.5-pm gate length MESFET and reduced its TAT significantly. 0 1993 John Wiley & Sons, Inc.

1. INTRODUCTION

In Japan, in order to satisfy the increasing demand for personal communication services in the future, digital-cellular and -cordless phone services using the 1.5- and 1.9-GHz bands, respectively, are scheduled to start in the mid-1990s in addition to the existing analogue mobile telephone services using the 800-MHz band [ l ] . These services will require low-power-consumption GaAs MMICs operating at a low applied voltage in order to achieve systems with a small volume, low weight, and long operating time. The systems will also require rapid upgrading for the MMICs, which makes it extremely important to reduce the de- velopment TAT (Turn Around Time) of MMICs as well as improving their performance.

In order to reduce the TAT, i t is necessary to shorten both the sequence period of design, fab- rication and measurement, and the repetition times of the sequence. The most feasible way to satisfy these requirements is to apply accurate mi-

crowave circuit simulations to the development of MMICs. However, their successful application is difficult because the software commercially avail- able at this time is not sufficient to use for practical MMIC development without revising or improv- ing their models, which have new device structures and circuits.

A maskless wafer process for GaAs MMICs using an EB (Electron-Beam) direct drawing method might also satisfy the above requirements because it does not need photo-masks, whose de- livery time and cost are relatively long and ex- pensive. Therefore, we have constructed an in- tegrated microwave CAD / CAM system including an EB direct drawing subsystem [2 ,3 ] to satisfy the above requirements, and we have started to develop a maskless wafer process for GaAs MMICs.

This article first describes the architecture and features of the integrated microwave CAD/CAM system briefly. Next, the maskless fabrication techniques are described, which include an ac-

International Journal of Microwave and Millimeter-Wave Computer-Aided Engineering, Vol. 3, No. 3, 262-270 (1993)

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0 I993 John Wiley & Sons. Inc. CCC 10.50- 18271931030262-09

Maskless Device Fabrication Technology 263

curate alignment method; a topography simula- tion of EB lithography and its application; and the fabrication of an L-band low-noise amplifier with a 0.5-pm gate MESFET, and its TAT.

2. AN INTEGRATED MICROWAVE CAD/CAM SYSTEM

Figure 1 shows a block diagram of the integrated microwave CAD/CAM system. The system con- sists of an EB direct drawing, microwave circuit simulator, DC and RF on-wafer automatic mea- surement, and pattern generator subsystems. These subsystems are connected through an Eth- ernet LAN (Local Area Network) made in the research laboratory and controlled by a host com- puter. A topography simulation which calculates using a super-minicomputer is also added to the system.

The drawing subsystem is the key to realize the maskless process because it can easily generate EB from 8 nm to 1 pm by regulating the electron optics [4]; hence, it can draw various MMIC pat- terns, extending from nanometer sizes like those of gate electrodes to large sizes like those of pad electrodes and microstrip-line patterns quickly and easily.

The system can offer the following main ad- vantages.

0 First, a maskless process for both active and passive devices of MMICs, and for MMIC themselves is possible.

0 Second, when upgraded or newly designed MMICs such as those for a higher frequency band are required, the performance of active

Ethernet LAN

devices and MMICs can be improved in or- der to meet the requirement because their gate length can be easily reduced to below 0.25 pm.

0 Third, highly accurate matching circuits for MMICs can be fabricated because the cir- cuits can be simulated and formed to match the measured RF characteristics of the active devices after their fabrication, which also im- proves the yield of MMIC fabrication. Fourth, it is possible to improve the accuracy of the simulation models because the se- quence and repetition can be done quickly using the first and third features above. In addition to that many kinds of circuit pat- terns can be designed on the wafers at once, as will be discussed later.

3. MASKLESS PROCESS

3.1. Accurate Alignment In order to successfully apply the maskless wafer process to MMIC development in which there are more than ten photo-mask levels, it is most im- portant to align both field-to-field and layer-to- layer as they correspond to mask-to-mask pre- cisely and speedily, because the CAD data (pat- tern data) for each layer is divided into many fields whose size is from 80 x 80 to 1600 X 1600 pm2, and the EB drawing of each layer is completed by repeating the field drawing.

As is well known, the alignment accuracy and speed are mainly determined by the S /N ratio of a detector attached to the EB drawing subsystem, which is sensitive to the reflection- and secondary-

.................

...............

Offce (4F)

Figure 1. Block diagram of an integrated microwave CAD/CAM system.

264 Yumada et ul.

electrons from an alignment mark fabricated on the wafer. So it is very important to form a mark which is capable of reflecting a great number of secondary electrons in order to enhance the align- ment accuracy and speed.

We found experimentally that the following two kinds of patterns are available for alignment mark use because they can generate the number of re- flection- and secondary-electrons needed for highly sensitive detection. One is a crosshair- shaped trench pattern with a 10-pm width and 1.2- pm depth, which was sharply etched by the RIE (Reactive lon Etching) method on a GaAs sub- strate. This was capable of generating a sharp re- flection signal at the trench edge and was used until high-temperature processes above 500°C were completed from the starting process. The other is a metallized crosshair-shaped mesa pat- tern covered with gold, which also provided a sharp signal at the mesa edge. These provided an accuracy to a level below 0.05 pm (standard de- viation: a) during the alignment.

3.2. Topography Simulation of Electron-Beam Lithography It is also important to shorten the drawing time of EB lithography in order to reduce the TAT of MMICs. The drawing time ( tE) of EB resist is simply expressed by the following equation [5].

where S is the resist sensitivity (pC/cm2) defined as the EB dose required to pattern a minimum applicable feature size and type, and k is the ratio of actual scanning area to field area A . The value of k is determined by the pattern and the scanning form ( k = 0.2-0.4 in the vector scanning scheme). J is the EB current density, and a is the spot size of the EB. It is necessary to use high sensitivity EB resist and/or to increase the EB current (J *

a) in order to reduce the tE. Highly sensitive single layer posi-type resists

with a thickness ranging from 0.2 to 3.2 km were successfully used for all maskless processes except those of T-shaped gate formations of active de- vices, in which we used a posi-type two-layer resist with different sensitivities. These resists easily provide overhang profiles that are suitable for the lift-off process, and vertical profiles for chemical and dry etching processes. The tEof the total single layer process was reduced to about one third by

improving the developing conditions of EB resists such as ZEP-520 (Nippon Zeon Co., Ltd.) with S 5 15 pC/cm2, which was compared with the conventional process using a PMMA (Poly- Methy-Methacrylate) resist (Tokyo Ohka Kogyo Co., Ltd.).

In addition, we developed a topography sim- ulation of EB lithography, which was applied to the improvement or development of all the mask- less wafer processes needed for newly designed or upgraded MMICs in order to minimize the ex- periments required for the improvement or de- velopment.

The simulation of EB lithography was divided into two steps. The first is analyzing the electron scattering and energy deposition in the resist, which was simulated by the Monte Carlo method using a scattering model based on Kyser and Mur- ata [6-81. The second is the development (solu- tion) of the resist represented by its differential solubility, which was simulated using the String model [9] that provides the solved front profiles described by the nodes and the strings connected to each node, and whose shiftings were calculated

I I 1 I I

E M - 9 0 T=60sec n T=180sec 0 T=BOOsec

2 4 6 8 10 12 14 i

Exposure Dose ( pC/cm2 )

I I I

PMMA 0 T=180sec A T=BOOsec 0 T=420sec 0 T=630sec

I

0 20 40 60 80

Exposure Dose ( BC/cm2 )

Figure 2. The dissolution characteristics of EBR-9 and PMMA resists.

Maskless Device Fabrication Technology 265

TABLE 1. Development Constants for EBR-9 and PMMA Resists

Constants EBR-9 PMMA

cm 0.1 0.1 (Y 2.4 1.5 DO (J/cm3) 140 x lo6 199 x lo6

Rl ( W W 9.4 x 10-4 5.9 x 10-4

h

6

i t

0.0

0.2

0.4

0.6

0.8

1 .o 0.0 0.5 1.0

LENGTH ( m )

0.0 0.5 1 .o

LENGTH ( ~ m )

Figure 3. Simulated profiles of a T-shaped 0.1-pm gate electrode. (a) Developed profile of a two-layer resist structure. (b) Etched profile of a recess structure after (a). (c) Deposited profile of a gate electrode after (b).

based on the following solubility rate equation.

R = R I - (C, + g)a where R is the solubility rate equation; D is the absorbed energy density; and R, , C,, a, and Do are constants.

The development constants (R , , C,, a, and Do) have to be changed when the resists or their de- velopment conditions are changed. They were ob- tained by the following steps. First, the dissolution characteristics of the resist were obtained by mea- suring the thickness of resist solved by exposing different doses under constant development con- ditions. Figure 2 shows the measured dissolution characteristics of EBR-9 (Toray Industries, Inc.) and PMMA resists as a parameter of different development times (the resist thickness normal- ized by its initial thickness versus the exposure dose of EB). Finally, R, , C,, and a were calcu- lated by the method of least squares using the Newton method under the condition that Do was fixed. Table I shows their calculated development parameters. The simulation can provide accurate profiles as shown in the example in Figure 3, which was a simulated sequential development process for an EBR-9(6500 A)/PMMA(4300 A) two-layer resist structure [ 101, chemical recess-etching (800

(b) Drain Gate Source

SIN

M 0.10 wn

Figure 4. (a) Cross-sectional SEM micrograph of a T- shaped 0.1-pm gate electrode. (b) Cross-sectional view of a T-shaped O.l-km gate electrode.

266 Yamada et al.

1.0

1.5

2.0t

0.0 I I

, . I . , : .. 120sec

: : 180 sec I : '2 240 sec

9 300 sec

:. '. ... . . . ... -

I . , . . , , ,

. , . . . . . ,

- . .

, . ,' I

.....I ,,'+Is Urn ,, '. ...

Y E b i - 1 a

DISTANCE ( prn )

Figure 5. (PMMA resist).

Simulated profile of a 1.5-pm dummy-gate

A), and deposition of a gate electrode (Ti/Al: 5500 A), using the 3000 trajectory electrons to fabricate a 0.1-pm-length gate electrode with a T- shaped cross-sectional profile. Figure 4 shows a cross-sectional photograph of a fabricated 0.1-ym T-shaped gate electrode covered with Si,N4 pas- sivation film, which agrees well with the simulated results.

Figure 5 also shows the accurately simulated profile of a 1.5-pm length dummy-gate resist (PMMA), which was used in a self-aligned MES- FET process as described below.

3.3. Maskless Process An L-band LNA (Low-Noise Amplifier) which has a 0.5-pm gate length MESFET and passive devices composed of spiral and meander-line type

inductors and MIM capacitors and resistors was fabricated by a maskless process using the im- proved highly sensitive single layer posi-type re- sists (ZEP-520 mentioned above, etc.) extending through all process steps.

Figure 6 shows a schematic process flow of a dummy-gate self-aligned MESFET which has a 0.5-pm gate length and a buried p-layer.

First, a 1.2-pm deep trench/crosshair shape alignment mark as mentioned above was formed on the wafer by RIE. After the through ion im- plantation of n and p- active layers using the ECR (Electron Cyclotron Resonance)-CVD Si3N4 film, a 1.5-pm length dummy-gate pattern was formed using PMMA EB resist (A) instead of the highly sensitive resist, because PMMA is capable of de- fining the dummy-gate length precisely. After the n+ implant (B), the dummy-gate was reduced to a 0.5-pm length with O2 plasma etching (C). The ECR-CVD Si02 film was deposited (D) to form the revised dummy-gate precisely using a lift-off method. After the lift-off process, the wafer was annealed by the RTA (Rapid 7hermal Annealing) method with ECR-CVD Si02/Si3N4 double-layer cap films [ll] at 850°C (E) followed by the ohmic metallization (F), and then the T-shaped gate elec- trode (Ti/Pd/Au) was formed by the lift-off method (H). After the passivation film was de- posited, the pad and passive device patterns were continuously formed by the lift-off method. The trench mark was used until the annealing steps (E), after which metallized mesa marks which were fabricated in both the ohmic (F) and pad electrode steps were used. The MESFET had a noise figure and associated gain of 0.4 dB and 14.2

I I

1-1

Figure 6. Process steps for GaAs MESFETs.

Maskless Device Fabrication Technology 267

dB at 2.0 GHz, respectively, when VDs = 3.0 V and IDS = 4 mA.

The passive devices, with the exception of re- sistors, were simulated in order to match the mea-

sured RF characteristics of MESFETs fabricated on the wafer (see Fig. 7a), and then their simu- lated patterns were directly exposed on the wafer (see Fig. 7b). The circuit simulation was per-

Figure 7. (a) Designed MMIC pattern (active devices). (b) Designed MMIC pattern (active devices and passive devices).

268 Yamada et al.

formed by adding our defined models to the orig- inal models of commercial software. The line width/space of the inductors was 10/10 pm and their metallization (Ti/Pd/Au) thickness was in- creased to 2.2 pm in order to reduce their resist- ance. The metallization of MIM capacitors and spiral inductors was formed by a lift-off method using a 3.2-pm-thick single-layer EB resist.

An alignment accuracy to a level of less than 0.05 pm was achieved by using two kinds of marks, and a 1.5-pm length dummy-gate (PMMA resist pattern), whose length determined the char- acteristics of the MESFET, was precisely formed based on the result of a topography simulation. The total drawing time for the maskless processes was reduced by more than one third by using highly sensitive EB resists, and the sequence pe- riod was also reduced.

A circuit diagram for LNA is shown in Figure 8a and a top-view micrograph is shown in Figure 8b. The measured and simulated noise figures (NF) are shown in Figure 9a while the input return loss ( S , , ) , output return loss (&), and gain (&,) are shown in Figure 9b, which all agreed well.

3.4. TAT

Figure 10 shows a schematic design and fabrica- tion flow for MMICs using our maskless and con- ventional processes using photo-masks.

V d

Figure 8. (a) An equivalent circuit of the L-band am- plifier. (b) Top-view micrograph of the L-band ampli- fier.

The conventional MMIC process sequence consists of circuit and layout designs using the developed active devices, the fabrication of photo- masks, the wafer process and the on-wafer mea- surements. This sequence is repeated if excellent RF characteristics are not obtained, or if good agreement is not obtained between the measure- ments and the simulations.

On the other hand, the first sequence of the maskless MMIC process starts at the wafer process of the active devices, after the rough circuit and layout designs, and then redesigns and fabricates the passive devices based on the measured elec- trical characteristics of the fabricated active de- vices. The second sequence can start redesigning of the matching circuits.

The first sequence period of the maskless pro- cess was reduced to about 16 days (about 3 weeks), because it eliminated the delivery time for the photo-masks. The second sequence was greatly reduced, to less than 1 week, because the accuracy of the passive device simulation was im- proved based on the first results, thereby allowing

MEASUREMENT

SIMULATION

- 3

1t

0 1.5 2.0 2.5

FREQUENCY ( GHz )

(b) 20 I I I 1 I - MEMEASUREMENT - ---- SlMULATlON

h

v)

-30 0.5 1 1.5 2 2.5 3 3.5

FREQUENCY ( GHz )

Figure 9. (a) Noise figure (NF) versus frequency for the L-band amplifier. (b) SI1, Sz2, and SZI versus fre- quency for the L-band amplifier.

Maskless Device Fabrication Technology 269

(Maskless Process) (Conventional Process)

I

Photo-Mask Fabrication

Preparation Of CAD DATA

Reticule Fabrication .1

.1 Photo-Mask Fabrication

.1 Wafer Process

Active & Passive Device Y

On-Wafer Measurement

Redesign (simulation) .1

Fabrications

EB Direct Drawing

Passive Device Fabncation

NG NG

- 1st sequence - rn43i-d sequence -

GO

Figure 10. Comparison of the design and fabrication flows of our maskless process and conventional pro- cesses.

the sequence to start the redesigning of the passive devices, as shown in Figure 10. These reductions are a major advantage in that the system can easily fabricate various kinds of not only active devices, such as those with different structures and ge- ometries, but also matching circuits, such as those with different configurations and parameters on the same wafer, which were designed using revised or developed simulation models against the mea- sured characteristics corresponding to each active device. A large amount of simulated and mea- sured results, such as MMIC-layout patterns, MMIC-electrical characteristics, circuit-configu- rations, and circuit-models and -parameters against each of the above active devices, could be achieved in every sequence. Therefore, by in- creasing the sequences, the system can enhance the improvement and optimization of the device structures and their matching circuits so as to im- prove the performance of the MMICs.

The TAT of the LNA was about 18 days (less than 4 weeks) with two repetitions of MMIC fab- rication. It is also possible to reduce this further

when new MMICs are designed using these re- sults.

4. CONCLUSION

A maskless process for MMICs was developed using an integrated microwave CAD/CAM sys- tem including an E B direct drawing subsystem. The process also used highly sensitive posi-type, single- and double-layer EB resists, and our im- proved highly accurate alignment marks and to- pography simulation of EB lithography to obtain accurate resist profiles. The process provided ex- cellent RF characteristics for an L-band low-noise amplifier with a 0.5-krn gate MESFET, which agreed well with simulations and also greatly shortened the TAT of the amplifier compared with the conventional process using photo-masks.

ACKNOWLEDGMENT

The authors would like to thank T. Sawai, T. Imaoka, and H. Nakamoto for developing the simulation technologies, and for their helpful ad- vice concerning MMIC design.

REFERENCES

1. S. Kamihashi, J . Ozaki, and S. Watanabe, “GaAs MMIC Applications for System Applications,” MWE ’92 Microwave Workshop Dig. 1992, pp. 261- 265.

2. T. Yamada, M. Nishida, T. Sawai, Y. Harada, and T. Nakakado, “An Improved MMIC Design Sys- tem Composed of an Electron Beam Direct Draw- ing, Microwave Simulation and On-Wafer Mea- surement Subsystems,” I990 IEEE GaAs IC Symp. Tech. Dig., October 1990, pp. 77-80.

3. T. Yamada, M. Nishida, T. Sawai, and Y. Harada, “An Integrated MMIC CAD System,” IElCE Trans, Electron., Vol. E75-C, No. 6 June 1992, pp.

4. M. Isobe, T. Yuasa, and N. Goto, “Electron Beam Lithography System JBX-SDII,” JEOL News, 1986, Vol. 24E, No. 2.

5. W. M. Moreau, Semiconductor Lithography. Plenum Press, New York, 1988, pp. 427-431.

6. D. F. Kyser and K. Murata, “Monte Carlo Simu- lation of Electron Beam Scattering and Energy Loss in Thin Films on Thick Substrates,” Proceed- ings of the 6th International Conference on Electron and Ion Beam Science and Technology. Electro- chemical Society, 1974, pp. 205-223.

7. D. F. Kysey and R. Pyle, “Computer Simulation

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NO. 6, 1977, pp. 381-386.

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11. D. Inoue, S. Matushita, S. Murai, M. Sawada, and Y. Harada, “Rapid Thermal Annealing of Im- planted GaAs Using Double-Layered SiN Films Formed by ECR Plasma CVD,” The 175th Elec- trochemical Society Meeting, No. 668, SOA, 1989.

BIOGRAPHY

Takashi Yamada was born in Gifu, Japan, on October 1, 1959. He received the BC degree in Nuclear Engineering from Na- goya University, Nagoya, Japan, in 1983. He joined the Semiconductor Research Center of Sanyo Electric Co., Ltd., Osaka, in 1983, where he is currently en- gaged in the research and development of GaAs microwave devices and nanofabri-

cation techniques. He is a member of the Institute of Elec- tronics, Information and Communication Engineering (IEICE) and the Japan Society of Applied Physics.

Kaoru Nogawa was born in Ishikawa, Ja- pan, on January 1, 1961. He received the BC degree in Industrial Chemistry and the MC degree in Molecular Engineering from Kyoto University, Kyoto, Japan, in 1984 and 1986, respectively. He joined the Semiconductor Research Center of Sanyo Electric Co., Ltd., Osaka, in 1986, where he is currently engaged in the research and

development of GaAs microwave devices.

Madoka Nishikawa was born in Aichi, Ja- pan, on March 11, 1967. He received the BC degree in Electrical Engineering from Nagoya University, Nagoya, Japan, in 1990. He joined the Semiconductor Re- search Center of Sanyo Electric Co., Ltd., Osaka, in 1990, where he is currently en- gaged in the research and development of GaAs microwave devices. He is a member

of the Japan Society of Applied Physics.

Yasoo Harada was born in Aichi, Japan. on May 30, 1943. He received the BS de- gree in Physics from Nagoya University, Nagoya, Japan, in 1967, and the PhD de- gree in Electrical Engineering from To- hoku University, Sendai, Japan, in 1989. He joined the Research Center of Sanyo Electric Co., Ltd., Osaka, in 1967, where he is currently engaged in the research and

development of GaAs microwave devices. He is manager of the Ultra High Speed Electronics Department, Semiconductor Research Center. He is a member of the IEICE and the Japan Society of Applied Physics.