BiTS 2017 Poster Session

March 5-8, 2017 Burn-in & Test Strategies Workshop www.bitsworkshop.org

Archive – Poster

March 5 - 8, 2017

Hilton Phoenix / Mesa Hotel

Mesa, Arizona

© 2017 BiTS Workshop – Image: tonda / iStock

BiTS 2017

March 5-8, 2017 Burn-in & Test Strategies Workshop www.bitsworkshop.org

Copyright Notice

The presentation(s)/poster(s) in this publication comprise the Proceedings of the 2017 BiTS Workshop. The content reflects the opinion of the authors and their respective companies. They are reproduced here as they were presented at the 2017 BiTS Workshop. This version of the presentation or poster may differ from the version that was distributed in hardcopy & softcopy form at the 2017 BiTS Workshop. The inclusion of the presentations/posters in this publication does not constitute an endorsement by BiTS Workshop or the workshop’s sponsors. There is NO copyright protection claimed on the presentation/poster content by BiTS Workshop. However, each presentation/poster is the work of the authors and their respective companies: as such, it is strongly encouraged that any use reflect proper acknowledgement to the appropriate source. Any questions regarding the use of any materials presented should be directed to the author(s) or their companies. The BiTS logo and ‘Burn-in & Test Strategies Workshop’ are trademarks of BiTS Workshop. All rights reserved.

BiTS 2017 Poster Session

Burn-in & Test Strategies Workshop

www.bitsworkshop.org March 5-8, 2017

Enabling Temperature Margining Solutions for

Validating Automotive Electronics in Lab

Automation Environment

Ying-feng Pang, Hagai Wertheim, Rahima Mohammed, Amy Xia

Intel Corporation

Introduction

The growth of automotive electronics due to its wide use in automotive for

powering the in-vehicle infotainment system (IVI), navigation system,

autonomous driving platform, and advanced driver assistance systems

(ADAS) has inherently increased the need for automotive electronics to

be designed and tested to meet more stringent industrial specs.

Consequently, the need for new and reliable testing strategies are critical

to accommodate the lab automation environment for meeting industrial

temperature spec from -40°C to 130°C.

Challenges & Proposed Solution

• Thermal margining solution that can enable localized temperature

control on the device under test (DUT) from -40°C to 130°C

Solution: A multi-stage thermoelectric module (TEC) as part of

the liquid-cooled thermal solution with resistance temperature

detector (RTD) sensor embedded on the pedestal served as the

temperature feedback to the thermal controller

• Condensation management solution inside the automation cell

Solution: A purge chamber where dry air is pumped into the

automation cell to control the humidity level around the DUT and

thermal solution

• Leak detection solutions

Solution: Customized flex circuit film and leak detection wire for

detecting condensation and leak around DUT in the automation cell

BiTS 2017 Poster Session

Burn-in & Test Strategies Workshop

www.bitsworkshop.org March 5-8, 2017

• Innovative pedestal and gimbaling mechanism design to ensure good

alignment of thermal solution on DUT, thermal conduction and electrical

contact.

Solution: a gimbaling design to compensate on parallelism

mismatch with DUT to ensure good electrical and thermal contact

and a plate with mounting holes to fit onto the existing mounting

hardware inside the automation cell

Solution: A pedestal with floating X-Y plane compensation

mechanism to compensate the parallelism mismatch with DUT

Impact of Ionizer & Dry Air Purge on Thermal Performance

BiTS 2017 Enabling Temperature Margining Solutions for Validating Automotive Electronics in Lab Automation Environment 2

-60

-40

-20

0

20

40

60

0 10 20 30 40 50 60Power [W]

Thermal Performance (Tcoolant 13°C)

Ion on, 6[l/m] Purge, Bare Die

Ion Off, 6[l/m] purge, Bare Die

Ion Off, 3[l/m] purge, Bare Die

Ion Off, 3[l/m] purge, W/ VcTIM

Tca

se

[ºC

]

Flex circuit leak detector thru I2C sensor

communication with thermal controller

Gimbaling design with parallelism

compensation with DUT

Challenges & Proposed Solution

Ionizer is used to prevent electro-static discharge (ESD) in the automation cell

-40ºC at boot can be achieved with the proposed thermal solution

Minimum of 3 [l/m] dry air purge is required to prevent condensation during test

Higher dry air purge flow rate would reduce the thermal performance, but can

be improved with having the ionizer on

Ionizer reduces thermal performance at cold temperatures, but can improve

thermal performance at higher temperatures

BiTS 2017 Poster Session

Burn-in & Test Strategies Workshop

www.bitsworkshop.org March 5-8, 2017

BiTS 2017 Enabling Temperature Margining Solutions for Validating Automotive Electronics in Lab Automation Environment 3

Liquid detector resistance on different wetness condition was tested

Resistance value is measured high when the condition is dry (no

droplet/water detected)

Resistance value is measured the lowest when water is detected

System can be turned off and notified users when leak is detected during

test

Pressure Paper Test

• Uniformity of pressure

on DUT

Socket Contact Resistance Measurement (CRES)

• Shows good resistance of ~0.5 per pin on daisy

chain boards

Thermal Interface Contact and Socket CRES

Verification of Leak Detection

A combination of innovative mechanical and thermal designs is required for

achieving a solution that can meet industrial spec temperature testing in a lab

automation environment

Thermal performance, leak detection verification, thermal interface contact, and

socket contact were evaluated and verified for the lab automation environment

Summary

0

2000

4000

6000

8000

10000

12000

14000

16000

1 2 3 4 5 6 7 8 9 10 11 12 13 14

Test Sequence

Heat from -5°C

& -40°C to 20°C

DRY

WET

DROPLET

Water evaporated

after 45 second

@ -40°C: no purge, water

frozen and no droplet

@ 3°C: no purge

@ -40°C: with purge

@ -5°C (heating from

-40°C): ice melted

Wetn

es

s D

ete

cti

on

Me

asu

rem

en

t

Location Per Pin

TOP-RIGHT 0.45

TOP-LEFT 0.55

TOP1 0.25

LEFT2 0.05

CEN 0.05

BOT-LEFT 0.55