Manual RH850/U2A 516pin - renesas.com

Cover

All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp. through various means, including the Renesas Electronics Corp. website (https://www.renesas.com)

Y-RH850-U2A-516PIN-PB-T1-V1

RH850/U2A 516pin User's Manual: PiggyBack Board

www.renesas.comwww.renesas.comwww.renesas.com Rev.1.00 Feb 2019

User's

Ma

nu

al

32

RH850 Evaluation Platform

The newest version of this document can be obtained from the following web location: Y-RH850-U2A-516PIN-PB-T1-V1 Documents

https://www.renesas.com/

http://www.renesas.eu/updates?oc=Y-RH850-U2A-516PIN-PB-T1-V1#documentInfo

Notice

Notice

1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of

semiconductor products and application examples. You are fully responsible for the incorporation or any other use of the circuits,

software, and information in the design of your product or system. Renesas Electronics disclaims any and all liability for any losses and

damages incurred by you or third parties arising from the use of these circuits, software, or information.

2. Renesas Electronics hereby expressly disclaims any warranties against and liability for infringement or any other claims involving patents,

copyrights, or other intellectual property rights of third parties, by or arising from the use of Renesas Electronics products or technical

information described in this document, including but not limited to, the product data, drawings, charts, programs, algorithms, and

application examples.

3. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas

Electronics or others.

4. You shall not alter, modify, copy, or reverse engineer any Renesas Electronics product, whether in whole or in part. Renesas Electronics

disclaims any and all liability for any losses or damages incurred by you or third parties arising from such alteration, modification,

copying or reverse engineering.

5. Renesas Electronics products are classified according to the following two quality grades: “Standard” and “High Quality”. The intended

applications for each Renesas Electronics product depends on the product’s quality grade, as indicated below.

“Standard”: Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment;

home electronic appliances; machine tools; personal electronic equipment; industrial robots; etc.

“High Quality”: Transportation equipment (automobiles, trains, ships, etc.); traffic control (traffic lights); large-scale communication

equipment; key financial terminal systems; safety control equipment; etc.

Unless expressly designated as a high reliability product or a product for harsh environments in a Renesas Electronics data sheet or other

Renesas Electronics document, Renesas Electronics products are not intended or authorized for use in products or systems that may pose a

direct threat to human life or bodily injury (artificial life support devices or systems; surgical implantations; etc.), or may cause serious

property damage (space system; undersea repeaters; nuclear power control systems; aircraft control systems; key plant systems; military

equipment; etc.). Renesas Electronics disclaims any and all liability for any damages or losses incurred by you or any third parties arising

from the use of any Renesas Electronics product that is inconsistent with any Renesas Electronics data sheet, user’s manual or other

Renesas Electronics document.

6. When using Renesas Electronics products, refer to the latest product information (data sheets, user’s manuals, application notes, “General

Notes for Handling and Using Semiconductor Devices” in the reliability handbook, etc.), and ensure that usage conditions are within the

ranges specified by Renesas Electronics with respect to maximum ratings, operating power supply voltage range, heat dissipation

characteristics, installation, etc. Renesas Electronics disclaims any and all liability for any malfunctions, failure or accident arising out of

the use of Renesas Electronics products outside of such specified ranges.

7. Although Renesas Electronics endeavors to improve the quality and reliability of Renesas Electronics products, semiconductor products

have specific characteristics, such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Unless

designated as a high reliability product or a product for harsh environments in a Renesas Electronics data sheet or other Renesas

Electronics document, Renesas Electronics products are not subject to radiation resistance design. You are responsible for implementing

safety measures to guard against the possibility of bodily injury, injury or damage caused by fire, and/or danger to the public in the event

of a failure or malfunction of Renesas Electronics products, such as safety design for hardware and software, including but not limited to

redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures.

Because the evaluation of microcomputer software alone is very difficult and impractical, you are responsible for evaluating the safety of

the final products or systems manufactured by you.

8. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each

Renesas Electronics product. You are responsible for carefully and sufficiently investigating applicable laws and regulations that regulate

the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive, and using Renesas Electronics

products in compliance with all these applicable laws and regulations. Renesas Electronics disclaims any and all liability for damages or

losses occurring as a result of your noncompliance with applicable laws and regulations.

9. Renesas Electronics products and technologies shall not be used for or incorporated into any products or systems whose manufacture, use,

or sale is prohibited under any applicable domestic or foreign laws or regulations. You shall comply with any applicable export control

laws and regulations promulgated and administered by the governments of any countries asserting jurisdiction over the parties or

transactions.

10. It is the responsibility of the buyer or distributor of Renesas Electronics products, or any other party who distributes, disposes of, or

otherwise sells or transfers the product to a third party, to notify such third party in advance of the contents and conditions set forth in this

document.

11. This document shall not be reprinted, reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas

Electronics.

12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or

Renesas Electronics products.

(Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its directly or indirectly

controlled subsidiaries.

(Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.

(Rev.4.0-1 November 2017)

General Precautions in the Handling of Microprocessing Unit and Microcontroller Unit Products

The following usage notes are applicable to all Microprocessing unit and Microcontroller unit products from Renesas.

For detailed usage notes on the products covered by this document, refer to the relevant sections of the document as

well as any technical updates that have been issued for the products.

1. Handling of Unused Pins

Handle unused pins in accordance with the directions given under Handling of Unused Pins in the manual.

− The input pins of CMOS products are generally in the high-impedance state. In operation with an

unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an

associated shoot-through current flows internally, and malfunctions occur due to the false recognition of

the pin state as an input signal become possible. Unused pins should be handled as described under

Handling of Unused Pins in the manual.

2. Processing at Power-on

The state of the product is undefined at the moment when power is supplied.

− The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are

undefined at the moment when power is supplied.

In a finished product where the reset signal is applied to the external reset pin, the states of pins are not

guaranteed from the moment when power is supplied until the reset process is completed.

In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are

not guaranteed from the moment when power is supplied until the power reaches the level at which

resetting has been specified.

3. Prohibition of Access to Reserved Addresses

Access to reserved addresses is prohibited.

− The reserved addresses are provided for the possible future expansion of functions. Do not access these

addresses; the correct operation of LSI is not guaranteed if they are accessed.

4. Clock Signals

After applying a reset, only release the reset line after the operating clock signal has become stable. When

switching the clock signal during program execution, wait until the target clock signal has stabilized.

− When the clock signal is generated with an external resonator (or from an external oscillator) during a

reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover,

when switching to a clock signal produced with an external resonator (or by an external oscillator) while

program execution is in progress, wait until the target clock signal is stable.

5. Differences between Products

Before changing from one product to another, i.e. to a product with a different part number, confirm that the

change will not lead to problems.

− The characteristics of Microprocessing unit or Microcontroller unit products in the same group but

having a different part number may differ in terms of the internal memory capacity, layout pattern, and

other factors, which can affect the ranges of electrical characteristics, such as characteristic values,

operating margins, immunity to noise, and amount of radiated noise. When changing to a product with a

different part number, implement a system-evaluation test for the given product.

Table of Contents

1. Overview ..................................................................................................................... 6

1.1 Package Components ........................................................................................................................... 6

1.2 Supported MainBoards .......................................................................................................................... 7

1.3 Main features ......................................................................................................................................... 7

1.4 PiggyBack Board views ......................................................................................................................... 8

1.5 Mounting of the device ........................................................................................................................ 10

2. Jumpers, Connectors and LEDs ................................................................................ 11

2.1 Jumpers overview ............................................................................................................................... 12

2.2 Connectors overview ........................................................................................................................... 16

2.3 LEDs overview .................................................................................................................................... 17

3. Power Supply ............................................................................................................ 18

3.1 Board power connection ...................................................................................................................... 18

3.2 Voltage distribution .............................................................................................................................. 19

3.3 Device core voltages (xVDD) selection ............................................................................................... 21

3.4 Current measurement bridges............................................................................................................. 22

3.5 Power supply LEDs ............................................................................................................................. 22

4. Clock Supply ............................................................................................................. 23

4.1 MainOsc .............................................................................................................................................. 23

4.2 Programmable oscillator ...................................................................................................................... 23

4.3 X1 and X2 on CN15 ............................................................................................................................ 24

5. Debug, Trace and Flash Programming Interfaces ..................................................... 25

5.1 Debug connector ................................................................................................................................. 25

5.2 Aurora trace connector ........................................................................................................................ 25

5.3 EVTI and EVTO signals ...................................................................................................................... 25

6. Other Circuitry ........................................................................................................... 26

6.1 Operation mode selection ................................................................................................................... 26

6.2 RESET switch ..................................................................................................................................... 27

6.3 RESETZ-EVA signal ........................................................................................................................... 27

6.4 Signaling LEDs .................................................................................................................................... 28

6.5 Pull-up/Pull-down pin header .............................................................................................................. 28

6.6 Gigabit Ethernet interface .................................................................................................................... 28

6.7 Renesas High-Speed Serial I/F (RHSIF) / Multichannel Serial Peripheral Interface (MSPI) .............. 30

7. Connectors ................................................................................................................ 31

7.1 Connectors to the MainBoard CN1 to CN3 ......................................................................................... 31

7.1.1 MainBoard connector CN1 ........................................................................................................... 31



7.2 Debug connector CN4 ......................................................................................................................... 36

7.3 RHSIF/MSIP connector CN5 ............................................................................................................... 36

7.4 Aurora interface connector CN6 .......................................................................................................... 37

7.5 Device ports connectors CN13 to CN16 ............................................................................................. 38

7.5.1 Device ports connector CN13 ...................................................................................................... 38




7.6 Pull-up/Pull-down pin header CN12 .................................................................................................... 42

7.7 Ethernet connector CN17 .................................................................................................................... 42

8. Jumper Configuration Examples ............................................................................... 43

8.1 Stand-alone operation with power supply by the tool ......................................................................... 43

8.2 RH850/U2A-EVA vs. RH850/U2A16 ................................................................................................... 43

8.3 Configuration examples ....................................................................................................................... 43

8.3.1 General settings ........................................................................................................................... 43

8.3.2 Jumper indicators ......................................................................................................................... 44

8.3.3 Stand-alone operation with single external power supply: minimum configuration ..................... 45

8.3.4 Stand-alone operation with all external power supplies: maximum configuration ....................... 46

8.3.5 Operation on the MainBoard: no external supply......................................................................... 47

9. Precautions ............................................................................................................... 48

9.1 Power-Off sequence ............................................................................................................................ 48

9.2 Gigabit Ethernet interface .................................................................................................................... 49

9.3 Generation of AURORA RESETx Signals .......................................................................................... 50

9.4 Erroneous Silkscreen print of CN15 and CN16................................................................................... 51

9.5 Erroneous Silkscreen print of part name ............................................................................................. 51

9.6 CAN0RX is shared with FLASH Programmer signal FLMD1 .............................................................. 51

9.7 Displacement of JP39 and CN6 .......................................................................................................... 52

10. Mechanical Dimensions............................................................................................. 53

11. Schematics ................................................................................................................ 54

11.1 Page 1 ................................................................................................................................................. 55

11.2 Page 2 ................................................................................................................................................. 56

11.3 Page 3 ................................................................................................................................................. 57

11.4 Page 4 ................................................................................................................................................. 58

11.5 ................................................................................................................................................. 59

11.6 Page 6 ................................................................................................................................................. 60

RH850/U2A 516pin

RENESAS MCU

R20UT4371ED0100 Rev.1.00 of 64 Feb 20, 2019

R20UT4371ED0100

Rev.1.00

Feb 20, 2019

1. Overview

The RH850/U2A 516pin PiggyBack Board is part of the RH850 Evaluation Platform and serves as a simple and easy to

use platform for evaluating the features and performance of Renesas Electronics' 32-bit RH850/U2A 516pin

microcontrollers.

Notes

1. This document describes the functionality of the PiggyBack Board and guides the user through its operation.

For details regarding the operation of the microcontroller, refer to the device's Hardware User’s Manual.

2. In this document low active signals are marked by an appended ‘Z’ to the pin or signal name. E.g. the reset pin is named RESETZ.

3. In this document following abbreviations are used:

− H level, L level: high or low signal level of a digital signal, the absolute voltage value depends on the signal

1.1 Package Components

The Y-RH850-U2A-516PIN-PB-T1-V1 product package consists of the following items. After you have unpacked the

box, check if your Y-RH850-U2A-516PIN-PB-T1-V1 package contains all of these items. Table 1.1 Package

Components for the Y-RH850-U2A-516PIN-PB-T1-V1 shows the packing components of the Y-RH850-U2A-

516PIN-PB-T1-V1 package.

Table 1.1 Package Components for the Y-RH850-U2A-516PIN-PB-T1-V1

Item Description Quantity

D016345#0080 RH850/U2A 516pin Adapter Board 1

D016563 Documentation CD 1

D010816-24 China RoHS document 1

D016345-24 Product contents List 1

Jumpers (2-way, 0.1”) In the bag 49

Red Hirschmann 4 mm power lab

sockets

In the bag 3

Black Hirschmann 4 mm power lab

sockets

In the bag 1

16MHz Resonator In the bag 1



Note

Please keep the Y-RH850-U2A-516PIN-PB-T1-V1 packing box at hand for later reuse in sending the product for repairs or for other purposes. Always use the original packing box when transporting the Y-RH850-U2A-516PIN-PB-T1-V1. If packing of your product is not complete, it may be damaged during transportation.

RH850/U2A 516pin 1. Overview

R20UT4371ED0100 Rev.1.00 of 64 Feb 20, 2019

1.2 Supported MainBoards

This PiggyBack Board can be used as a standalone board, or it can be mated with a MainBoard. The following

MainBoards are supported:

• Y-RH850-X1X-MB-T1-V1

• Y-RH850-X1X-MB-T2-Vx

• Y-RH850-X2X-MB-T1-V1

1.3 Main features

• Burn-in socket for mounting of the device

• Several power setup-up options

− Combined operation with powering from Main board

− Stand-alone operation with single power supply (e.g. 3.3 V or 5.0 V only)

− Stand-alone operation with flexible, individual power supply (typ. 1.12 V, 3.3 V, 5.0 V)

Refer to 3.3 Device core voltages (xVDD) selection for further details about xVDD voltages.

• Debugging, tracing and programming capability via two interfaces:

− 14-pin LPD/JTAG Debug Connector (e.g. for using E2 OCD Emulator or PG-FP6 Flash Programmer)

− 34-pin ERF8 AURORA Trace Connector (e.g. for using 3rd Party Off-chip Trace Emulator Solutions)

• Pin headers for direct access to each device pin

• Reset switch

• External clock circuit with an exchangeable 16/20/24/40 MHz Crystal Resonator

• General purpose signaling LEDs

• Jumpers for device mode selection and other configuration options

• Gigabit Ethernet Port 100/1000BASE-TX

• On-board interface connector for

− Renesas High-Speed Serial I/F (RHSIF)

or

− Multichannel Serial Peripheral Interface (MSPI)

• Operating temperature from 0 °C to +40 °C


R20UT4371ED0100 Rev.1.00 of 64 Feb 20, 2019

1.4 PiggyBack Board views

Following figures provide the top and bottom views of the PiggyBack Board.

Figure 1.2 PiggyBack Board bottom view

A1

Figure 1.1 PiggyBack Board top view


R20UT4371ED0100 Rev.1.00 of 64 Feb 20, 2019

Following figures provide the top and bottom views of the PiggyBack Board.

R142

C130

R112

R126

C65

L2

TR9

TR3

X2

R143

OSC1

R109

X3

R125

R110

R111

TR11

C49

R113

C46

IC17

TR10

R6

R21

D3

R18

MP2

R17

IC5

R1

6

MP5

R1

5

TR8

TR7

CN

3

CN

1

MP1

CN

2

IC2

R3

L1

IC8

MP4

R23

R58

IC9

MP3

C97C98

D4

MP6

IC7TR6

IC3

R11

R22

R7

IC16

Figure 1.4 PiggyBack Board bottom view

15

10

51

510152025 130

5V

GNDVDD

VD

D

VC

C

5V

5V

P11 _7_0

92 LED

GND

GND

D016345_06_V02

RH850-U2A-516PIN-T1-V1

RoHS-compliant

Made in Europe

DVDD

ERAMVDD

MODE0

FLMD2

FL

MD

1

EV

OT

Z

EV

ITZ

ER

AM

VC

C

DV

CC

GETHORVCC

SVRAVCC

SVRDRVCC

A2VREFH

A0VREFH

FL

MD

0

EMUVCC

PULL_UP_PIN1-9PULL_UP_PIN11-19

LVDVCC

E2

VC

C

3.3

V

Anti_Static

Aurora InterfaceEmulator Interface

5.0V 3.3V

GETHOBVCC

VD

DS

A5.0V

SYSVCC

E1

VC

C

VMONOUT

GETHOPVCC

A2VCC

VDDIOF

E0

VC

C

A1VREFH

A1VCC

A0VCC

EMUVDD

3.3

V

3.3

V

PULL_DOWN

ERROROUT_M

Reset LED1

5.0V

20

10

5

15

10 20

30

20

R114

1

TP3

C78

TP4

D1

CN

9

R106

C113

R1

37

C133

TP1

TP9

CN17

TP2

A

2

JP16

CN

8

JP10

LED13

JP25

TR5

JP24

IC19

R107

GND

B

REG

SVR

5

CN

10

LED10

JP11

3.3V

JP15

EV

A-R

ES

JP13

C

JP2

1

B

LED11

JP

36

A

JP28

GND

B C

IC12

LED14

CN

13

CN15

SW ON

JP

30

LED15

A3.3V

JP21

3.3V

5V

3.3V

3.3

VReset

1

VDDS

CN11

PWRCTL

JP

31

RH

SIF

/ M

SP

I

CN

16

3.3V

IC18

5V

JP

35

VDD

JP29

JP1

R1

04

GND

25

3.3V

30

JP38

15

16

B

IC1

JP40

X1

CN14

TP7

JP

4

JP7

CN4

JP9

TP5

15

JP19

JP42

R14

0

JP

34

CN7

25

A

LED12

Se

ria

l

R12

9

TR

14

IC6

JP22

CN

11

SW1

R14

1

R1

28

TR4

JP20

JP39

JP17

JP

33

JP18

C

JP

32

TP6JP8

R1

27

JP6

JP26

A

R13

9

CN

12

TP8TP10

IC4

JP14

JP12

JP41

2

1

C

5V

R1

38

5V

JP

23

R1

05

C24

IC11

JP3

CN5

JP

5

C21

20

JP

37

C116

TR15

IC10

2

CN6

IC13

19 1

IC15

R136

Figure 1.3 PiggyBack Board top view


R20UT4371ED0100 Rev.1.00 of 64 Feb 20, 2019

1.5 Mounting of the device

The board is designed for use with the following devices:

• R7F702Z19EDBG (RH850/U2A-EVA)

• R7F702300EABG (RH850/U2A16)

The device must be placed inside the socket IC1. To insert the device, align the device package A1 pin with the A1 pin

of the socket.

The A1pin of the socket is marked with a circle near to the “IC1” label (see also red A1 circle in Figure 1.1 PiggyBack

Board top view).

The A1 pin of the device is marked by a white triangle on the package (see white circle in the figure below).

CAUTION

Be careful with the device placement in the socket to avoid damage of the device.

Figure 1.5 Enplas OTP-516(961RS)-0.8-048S-00 socket with mounted device

RH850/U2A 516pin 2. Jumpers, Connectors and LEDs

R20UT4371ED0100 Rev.1.00 of 64 Feb 20, 2019

2. Jumpers, Connectors and LEDs

This section provides complete lists of all jumpers, connectors and LEDs.

The placement of these components on the board is depicted in the figure below.

The placement of these components on the board is depicted in the figure below.

15

10

51

510152025 130

5V

GNDVDD

VD

D

VC

C

5V

5V

P11 _7_0

92 LED

GND

GND

D016345_06_V02


RoHS-compliant

Made in Europe

DVDD

ERAMVDD

MODE0

FLMD2

FL

MD

1

EV

OT

Z

EV

ITZ

ER

AM

VC

C

DV

CC

GETHORVCC

SVRAVCC

SVRDRVCC

A2VREFH

A0VREFH

FL

MD

0

EMUVCC


LVDVCC

E2

VC

C

3.3

V

Anti_Static


5.0V 3.3V

GETHOBVCC

VD

DS

A5.0V

SYSVCC

E1

VC

C

VMONOUT

GETHOPVCC

A2VCC

VDDIOF

E0

VC

C

A1VREFH

A1VCC

A0VCC

EMUVDD

3.3

V

3.3

V

PULL_DOWN

ERROROUT_M

Reset LED1

5.0V

20

10

51

510 20

30

20

R114

1

TP3

C78

TP4

D1

CN

9

R106

C113

R1

37

C133

TP1

TP9

CN17

TP2

A

2

JP16

CN

8

JP10

LED13

JP25

TR5

JP24

IC19

R107

GND

B

REG

SVR

5

CN

10

LED10

JP11

3.3V

JP15

EV

A-R

ES

JP13

C

JP2

1

B

LED11

JP

36

A

JP28

GND

B C

IC12

LED14

CN

13

CN15

SW ON

JP

30

LED15

A3.3V

JP21

3.3V

5V

3.3V

3.3

VReset

1

VDDS

CN11

PWRCTL

JP

31

RH

SIF

/ M

SP

I

CN

16

3.3V

IC18

5V

JP

35

VDD

JP29

JP1

R1

04

GND

25

3.3V

30

JP38

15

16

B

IC1

JP40

X1

CN14

TP7

JP

4

JP7

CN4

JP9

TP5

15

JP19

JP42

R14

0

JP

34

CN7

25

A

LED12

Se

ria

l

R12

9

TR

14

IC6

JP22

CN

11

SW1

R14

1

R1

28

TR4

JP20

JP39

JP17

JP

33

JP18

C

JP

32

TP6JP8

R1

27

JP6

JP26

A

R13

9

CN

12

TP8TP10

IC4

JP14

JP12

JP41

2

1

C

5V

R1

38

5V

JP

23

R1

05

C24

IC11

JP3

CN5

JP

5

C21

20

JP

37

C116

TR15

IC10

2

CN6

IC13

19 1

IC15

R136

Figure 2.1 Placement of jumpers, connectors and LEDs

R142

C130

R112

R126

C65

L2

TR9

TR3

X2

R143

OSC1

R109

X3

R125

R110

R111

TR11

C49

R113

C46

IC17

TR10

R6

R21

D3

R18

MP2

R17

IC5

R1

6

MP5

R1

5

TR8

TR7

CN

3

CN

1

MP1

CN

2

IC2

R3

L1

IC8

MP4

R23

R58

IC9

MP3

C97C98

D4

MP6

IC7TR6

IC3

R11

R22

R7

IC16

Figure 2.2 Placement of connectors on bottom side


R20UT4371ED0100 Rev.1.00 of 64 Feb 20, 2019

2.1 Jumpers overview

The following table provides an overview of all jumpers.

Table 2.1 Jumpers overview (cont'd)

Jumper Function Remark

JP1 RHSIF I/F Rx/Tx signals swap

• JP1[2-1]: RXDP/RXDN at pins 7 and 9 of CN5, TXDP/TXDN at pins 1 and 3 of CN5

• JP1[2-3]: RXDP/RXDN at pins 1 and 3 of CN5, TXDP/TXDN at pins 7 and 9 of CN5

refer to 6.7 Renesas High-Speed Serial I/F (RHSIF) / Multichannel Serial Peripheral Interface (MSPI)

JP2 Nexus I/F EVTIZ level

• JP2[2-1]: EVTIZ = H level

• JP2[OPEN]: EVTIZ = CN6 pin 16 level

refer to 5.2 Aurora trace

JP3 Nexus I/F EVTO level

• JP3[2-1]: EVTO = H level

• JP3[OPEN]: EVTO = CN6 pin 18 level

JP4 Current measurement bridge of 5.0 V power rail refer to 3.4 Current measurement bridges

JP5 Current measurement bridge of 3.3 V power rail refer to 3.4 Current measurement bridges

JP6 voltage selection for E0VCC

• JP6[2-1]: 5.0 V

• JP6[2-3]: 3.3 V

refer to 3.2 Voltage distribution


• JP7[2-1]: 5.0 V

• JP7[2-3]: 3.3 V



• JP8[2-1]: 5.0 V

• JP8[2-3]: 3.3 V


JP9 voltage selection for LVDVCC

• JP9[2-1]: 5.0 V

• JP9[2-3]: 3.3 V


JP10 voltage selection for SYSVCC

• JP10[2-1]: 5.0 V

• JP10[2-3]: 3.3 V


JP11 voltage selection for VCC

• JP11[2-1]: 5.0 V

• JP11[2-3]: 3.3 V


JP12 voltage selection for SVRDRVCC

• JP12[2-1]: 5.0 V

• JP12[2-3]: 3.3 V


JP13 voltage selection for SVRAVCC

• JP13[2-1]: 5.0 V

• JP13[2-3]: 3.3 V


JP14 voltage selection for VDDIOF

• JP14[2-1]: 5.0 V

• JP14[2-3]: 3.3 V



R20UT4371ED0100 Rev.1.00 of 64 Feb 20, 2019



JP15 voltage selection for Pull-up/Pull-down pin header CN12 pins 11, 13, 15, 17, 19

• JP15[2-1]: 5.0 V

• JP15[2-3]: 3.3 V

refer to 6.5 Pull-up/Pull-down pin header

JP16 voltage selection for 1.12 V VDDs *

• JP16[2-1]: reg_vcc_VDD

• JP16[2-3]: IN_1v12

refer to 3.3 Device core voltages (xVDD) selection

JP17 voltage selection for EMUVCC

• JP17[2-1]: 3.3 V

• JP17[OPEN]: off


JP18 voltage selection for ERAMVCC

• JP18[2-1]: 3.3 V

• JP18[OPEN]: off


JP19 voltage selection for DVCC

• JP19[2-1]: 3.3 V

• JP19[OPEN]: off


JP20 voltage selection for GETH0BVCC

• JP20[2-1]: 3.3 V

• JP20[OPEN]: off


JP21 voltage selection for GETH0PVCC

• JP21[2-1]: 3.3 V

• JP21[OPEN]: off


JP22 voltage selection for GETH0RVCC

• JP22[2-1]: 5.0 V

• JP22[2-3]: 3.3 V


JP23 voltage selection for VDD

• JP23[2-1]: VDDs

• JP23[2-3]: SVR_OUTPUT

refer to 3.3 Device core voltages (xVDD) selection

JP24 voltage selection for DVDD

• JP24[2-1]: VDDs

• JP24[OPEN]: off


JP25 voltage selection for Pull-up/Pull-down pin header CN12 pins 1, 3, 5, 7, 9

• JP25[2-1]: 5.0 V

• JP25[2-3]: 3.3 V

refer to 6.5 Pull-up/Pull-down pin header


R20UT4371ED0100 Rev.1.00 of 64 Feb 20, 2019



JP26 Device Ethernet I/F Rx/Tx signals swap

• JP26[OPEN]:

− device pins N21/P21 used as Ethernet Tx signals

− device pins P22/R22 used as Ethernet Rx signals

• JP26[2-1]:

− device pins N21/P21 used as Ethernet Rx signals

− device pins P22/R22 used as Ethernet Tx signals

refer to 6.6 Gigabit Ethernet interface

JP28 voltage selection for ERAMVDD

• JP28[2-1]: VDDs

• JP28[OPEN]: off


JP29 voltage selection for EMUVDD

• JP29[2-1]: VDDs

• JP29[OPEN]: off


JP30 Current measurement bridge of 5.0 V A/D Converter power supply

refer to 3.4 Current measurement bridges

JP31 Current measurement bridge of 3.3 V A/D Converter power supply

refer to 3.4 Current measurement bridges

JP32 voltage selection for A0VCC

• JP32[2-1]: 5.0 V

• JP32[2-3]: 3.3 V


JP33 voltage selection for A0VREFH

• JP33[2-1]: 5.0 V

• JP33[2-3]: 3.3 V



• JP34[2-1]: 5.0 V

• JP34[2-3]: 3.3 V



• JP35[2-1]: 5.0 V

• JP35[2-3]: 3.3 V



• JP36[2-1]: 5.0 V

• JP36[2-3]: 3.3 V



• JP37[2-1]: 5.0 V

• JP37[2-3]: 3.3 V


JP38 MODE0 level selection

• JP38[2-1]: H level

• JP38[2-3]: L level

refer to 6.1 Operation mode selection


R20UT4371ED0100 Rev.1.00 of 64 Feb 20, 2019



JP39 FLMD1 level selection


• JP39[OPEN]: L level




• JP40[2-3]: L level




• JP41[OPEN]:

− if no debug/programming tool connected: L level

− controlled by debug/programming tool, if tool connected:


JP42 RESETZ_EVA connection

• JP42[2-1]: RESETZ_EVA = RESETZ

• JP42[OPEN]: RESETZ_EVA ≠ RESETZ

refer to 6.3 RESETZ-EVA signal

Note: * Refer to 3.3 Device core voltages (xVDD) selection for further details about xVDD voltages.


R20UT4371ED0100 Rev.1.00 of 64 Feb 20, 2019

2.2 Connectors overview

The following table provides an overview of all connectors.

Table 2.2 Connectors overview (cont'd)

Connector Function Remark

CN1 MainBoard connectors refer to 7.1 Connectors to the MainBoard CN1 to CN3

CN2

CN3

CN4 debug connector refer to 5.1 Debug connector and 7.2 Debug connector CN4

CN5 RHSIF & MSPI connector refer to 6.7 Renesas High-Speed Serial I/F (RHSIF) / Multichannel Serial Peripheral Interface (MSPI) and 7.3 RHSIF/MSIP connector CN5

CN6 Aurora trace unit connector refer to 5.2 Aurora trace and 7.4 Aurora interface connector CN6

CN7 Signaling LEDs pin header refer to 6.4 Signaling LEDs

CN8 GND for external power supply refer to 3.1 Board power connection,

connectors are not assembled on the board CN9 +5.0 V external power supply

CN10 +3.3 V external power supply

CN11 +1.12 V external power supply *

CN12 Pull-up/Pull-down pin header refer to 6.5 Pull-up/Pull-down pin header and 7.6 Pull-up/Pull-down pin header CN12

CN13 Device ports connectors refer to 7.5 Device ports connectors CN13 to CN16

CN14

CN15

CN16

CN17 Ethernet interface connector refer to 6.6 Gigabit Ethernet interface and 7.7 Ethernet connector CN17



R20UT4371ED0100 Rev.1.00 of 64 Feb 20, 2019

2.3 LEDs overview

The following table provides an overview of all LEDs.

Table 2.3 LEDs overview

LED Function Color Remark

LED1 device ERROROUT signal red

LED2 Signaling LED yellow connection via CN7,

refer to 6.4 Signaling LEDs LED3 Signaling LED

LED4 Signaling LED

LED5 Signaling LED

LED6 Signaling LED

LED7 Signaling LED

LED8 Signaling LED

LED9 Signaling LED

LED10 1.09 V device core voltage VDD

green refer to 3.5 Power supply LEDs

LED11 5.0 V power supply P5V0 green

LED12 3.3 V power supply P3V3 green

LED13 reset switch SW1 on red

LED14 device VMONOUT signal red

LED15 device PWRCTL signal red

RH850/U2A 516pin 3. Power Supply

R20UT4371ED0100 Rev.1.00 of 64 Feb 20, 2019

3. Power Supply

3.1 Board power connection

The device and the board require various power supply voltages:

• 3.3 V for most of the digital circuitry on the device and on the board

• 5 V in case some ports shall be operated with 5 V I/O voltage

• 1.12 V for the device's VDD core voltage supply


Note

Within this document all voltage values are considered as ‘typical’.

Refer to the 'Electrical Characteristics' section of the Hardware User's Manual for allowed voltage ranges.

The following connectors are available to supply external voltages:

• Four 4 mm ‘banana-type’ connectors are used to connect external power supplies:

− black connector CN8 for GND (VSS)

− red connector CN9 for 5 V

− red connector CN10 for 3.3 V

− red connector CN11 for 1.12 V


These connectors are not assembled at delivery of the board, but separately supplied with the board package.

In case the PiggyBack Board is mounted on a MainBoard, all voltages are supplied by the MainBoard.

CAUTION

Do not supply the 5 V (CN9) and 3.3 V (CN10) voltage directly to the PiggyBack Board in case it is mounted on the MainBoard.

Connecting external 1.12 V via CN11 (and GND via CN8) is still an option also in this case.

For some general power supply scenarios, the jumper settings are described in 8 Jumper Configuration Examples.


R20UT4371ED0100 Rev.1.00 of 64 Feb 20, 2019

3.2 Voltage distribution

The following table shows the required device power supply pins and their function:

Table 3.1 Device power supply pins (cont'd)

Device power supply pin Voltage Function

E0VCC, E1VCC, E2VCC 3.3 V, 5 V power supply for I/O ports

LVDVCC 3.3 V, 5 V power supply for LVDS ports

SYSVCC 3.3 V, 5 V power supply for

• system Logic and internal voltage regulator power

• I/O ports

VCC 3.3 V, 5 V power supply for on-chip flash memory

SVRDRVCC 3.3 V, 5 V power supply for on-chip Switching Voltage Regulator (SVR)

SVRAVCC 3.3 V, 5 V

VDDIOF 3.3 V, 5 V I/O voltage supply for the MainBoard

GETH0PVCC 3.3 V power supply for Ethernet domain

GETH0BVCC 3.3 V

GETH0RVCC 3.3 V

A0VCC, A1VCC, A2VCC 3.3 V, 5 V A/D Converter's power supplies and reference voltages

A0VREFH, A1VREFH, A2VREFH,

3.3 V, 5 V

DVDD 1.12 V * power supply for on-chip debug circuits

DVCC 3.3 V

EMUVDD 1.12 V * power supply for Aurora emulator interface signals

EMUVCC 3.3 V

ERAMVDD 1.12 V * ERAM circuits of FLASH

ERAMVCC 3.3 V


Each of the above voltages can be selected from

• 5.0 V, 3.3 V (where applicable, see table above)

• off

by a set of jumpers. For details refer to the figure below and Table 2.1 Jumpers overview (cont'd).


R20UT4371ED0100 Rev.1.00 of 64 Feb 20, 2019

Figure 3.1 Voltage distribution

P3V3 A3V3A5V0P5V0

A0VCC

A0VREFH

A1VCC

A1VREFH

A2VCC

A2VREFH

3.3V5.0V5.0V

1u

3v3 or 5V

3.3 or 5V

1u

3v3 or 5V

3.3V

1u

1u

3.3 or 5V

1u

3v3 or 5V

1u

3.3 or 5V

C109

C108

C107

C106

C105

C104

JP37

JP36

JP35

JP34

JP33

JP32

JP31

JP30

321

321

321

321

321

321

21

21

321

321

321

321

321

321

21

21

3.3V or 5V

VDDIOF

3.3V or 5VSVRAVCC

E2VCC

3V35V0P5V0

SYSVCC

SVRDRVCC

P3V3

E0VCC

EMUVCC

3.3V 5.0V

1u

3.3V or 5V

5.0V

3.3V or 5V

1u

3.3V

3.3V

3.3V or 5V

3.3V

3.3VDVCC

3.3VERAMVCC

GETH0BVCC3.3V or 5V

1u

3.3VGETH0PVCC

3.3V or 5VE1VCC

3.3V or 5VLVDVCC

GETH0RVCC3.3V or 5V

3.3V or 5VVCC

JP22

JP21

JP19

JP18

JP20

JP17

JP14

JP13

JP12

JP11

JP10

JP9

JP8

JP7

JP6

JP5

JP4

C94

C95

C96

321

21

21

21

21

21

321

321

321

321

321

321

321

321

321

21

21

321

21

21

21

21

21

321

321

321

321

321

321

321

321

321

21

21


R20UT4371ED0100 Rev.1.00 of 64 Feb 20, 2019

3.3 Device core voltages (xVDD) selection

The following VDD voltages must be supplied to the devices:

• RH850/U2A16: VDD

• RH850/U2A-EVA: VDD, DVDD, ERAMVDD, EMUVDD

The device core voltage VDD (typ.1.09 V) can be

• supplied from external via CN11 (voltage In_1v12)

• generated from the P3V3 power rail by use of the on-board voltage regulator IC16 (voltage reg_vss_VDD)

• generated by the on-chip Switching Voltage Regulator (SVR) in combination with device external power transistors

TR1, TR2 (voltage SVR_OUTPUT)

Note

The In_1v12 and reg_vss_VDD voltages have a level of typical 1.12 V, which is higher than the typical device core voltages VDD of 1.09 V. The 30 mV difference is supposed to compensate voltage drops over the power rails on the board, in particular over the jumpers.

Selection of the VDD source is achieved by use of the jumpers JP23 and JP16:

• JP23[2-1]: VDD = 1.12 V (VDDs) from

− JP16[2-1]: VDDs = reg_vss_VDD from on-board voltage regulator IC16

− JP16[2-3]: VDDs = IN_1v12 from external supply CN11

• JP23[2-3]: VDD = 1.09 V (SVR_OUTPUT)

Note

All other - RH850/U2A-EVA related - VDD voltages are always sourced from the 1.12 V voltages reg_vss_VDD (JP16[2-1]) or IN_1v12 (JP16[2-3]).

Note that the nominal voltages DVDD, ERAMVDD and EMUVDD at the device pins are also 1.09 V.

Notes:

* These xVDD voltages refer to the voltage at the device pins, thus have a nominal value of 1.09 V.

VDD*1.09 V

JP24

JP28

JP23

JP29

JP16

21

21321

21

321

21

21

321

21

321

SVR_OUTPUT1.09 V

VDDs1.12 V

reg_vcc_VDD1.12 V

IN_1v121.12 V

ERAMVDD*1.09 V

DVDD*1.09 V

EMUVDD*1.09 V

Figure 3.2 Device core voltages (xVDD) selection


R20UT4371ED0100 Rev.1.00 of 64 Feb 20, 2019

3.4 Current measurement bridges

The total current of the 5V0 and 3V3 power rails can be measured by replacing the jumpers JP4 and JP5 with a current

meter.

Accordingly, the total current via the A/D Converter's supply voltages A5V0 and A3V3 can be measured via the

jumpers JP30 and JP31 respectively.

The current of particular power supply pins of the device can be measured via their respective supply selection jumpers,

refer to Figure 3.1 Voltage distribution.

3.5 Power supply LEDs

The following green LEDs indicate the presence of various voltages on the PiggyBack Board:

• LED11 for 5.0 V power rail P5V0

• LED12 for 3.3 V power rail P3V3

• LED10 for 1.09 V device core voltage VDD

RH850/U2A 516pin 4. Clock Supply

R20UT4371ED0100 Rev.1.00 of 64 Feb 20, 2019

4. Clock Supply

The device's operation clock can be generated by

• the on-chip oscillator MainOsc circuit in combination with an off-chip resonator, connected to the X1, X2 terminals

• an off-chip oscillator, the clock is fed into the X1 terminal

4.1 MainOsc

For operating the on-chip MainOsc the PiggyBack Board provides a socket (X1) for a resonator.

Optionally a resonator (X3) can be soldered on the board, refer to the figure above.

Several resonators for various MainOsc frequencies (16 MHz, 20 MHz, 24 MHz, 40 MHz) are included in the board

package. For package content please refer to 1.1 Package Components

4.2 Programmable oscillator

Instead of using the on-chip MainOsc a programmable crystal oscillator (OSC1) circuit can be soldered on the board.

The available footprint and circuitry is designed for a SG-8002CE programmable crystal oscillator from Epson

Toyocom. The output of this oscillator can be connected to X1 terminal via resistor R2.

The SG-8002CE is neither mounted on nor provided with the board. For details about the available circuitry, refer to

Figure 4.1 Clock supply.

CAUTION

A resonator mounted on socket X1 or soldered on X3 must not be used in parallel to another clock source.

24 MHz provide additional

16 MHz provide additional20 MHz provide additional

100n

SG8002CE-20MHzDNF/DNB

3.3VP3V3

1K0 0

8pF

DNF/DNBDNF/DNB

18pF40.000 MHz + socket

DN

F/D

NB

DN

F/D

NB

DNF/DNB

22p

22p

0

0

16MHz

DNF/DNB

C98

R2OSC1

R1

R4

X1

X3

C16

C97

R3

2D2

2D2

X2X1

X1_C

X2_C

L25K25

4

1

2

3

X2X1

OE

VCCGND

CLK

OUT

IN

Figure 4.1 Clock supply

RH850/U2A 516pin 4. Clock Supply

R20UT4371ED0100 Rev.1.00 of 64 Feb 20, 2019

4.3 X1 and X2 on CN15

To minimize disturbance on the resonator signal the signals X1 and X2 are by default not connected to a pin header. If

needed the signals can be connected to CN15 via 0 Ω resistors:

• X1: A19 pin of CN15 to supply an external clock to the device via R3

• X2: A18 pin of CN15 for measurement purposes of the clock via R4

Note

By default the X1 and X2 signals are not connected to CN15 in order to minimize signal integrity disturbance. Upon demand they can be connected via 0 Ω resistors R3 and R4.

RH850/U2A 516pin 5. Debug, Trace and Flash Programming Interfaces

R20UT4371ED0100 Rev.1.00 of 64 Feb 20, 2019

5. Debug, Trace and Flash Programming Interfaces

5.1 Debug connector

For debugging and flash programming purposes debug and flash programming tools can be connected to the CN4

connector.

Refer to 7.2 Debug connector CN4 for details about the CN4 pin assignment.

5.2 Aurora trace connector

A trace unit can be connected via the CN6 connector.

Refer to 7.4 Aurora interface connector CN6 for details about the CN4 pin assignment.

5.3 EVTI and EVTO signals

Depending on the used tool output it might be necessary to pull the EVTI and/or EVTO signal to H level via a pull-up

resistor:

• JP2 set: EVTI pulled up to H level

• JP3 set: EVTO pulled up to H level

Note

Please refer to the documentation of the used tool, whether this is needed.

RH850/U2A 516pin 6. Other Circuitry

R20UT4371ED0100 Rev.1.00 of 64 Feb 20, 2019

6. Other Circuitry

6.1 Operation mode selection

The PiggyBack Board gives the possibility to configure the following jumpers for selection of the device operation

mode:

Table 6.1 Device operation mode selection jumpers (cont'd)

Jumper Function

JP38 MODE0 pin level

• JP38[2-1]: MODE0 = H level

• JP38[2-3]: MODE0 = GND

JP41 FLMD0 pin level

• JP41[SHORT]: FLMD0 = H level

• JP41[OPEN]: FLMD0

− controlled by debugger or programming tool, if a tool is connected via CN4 or CN6

− GND, if no tool connected


• JP39[SHORT]: FLMD1 = H level

• JP39[OPEN]: FLMD1 = GND


• JP40[2-1]: FLMD2 = H level

• JP40[2-3]: FLMD2 = GND

CAUTION

Be careful in configuration of the operation mode related pins. The wrong configuration and operation of the device outside of its specification can cause irregular behavior of the device and long-term damage cannot be excluded. Be sure to check the corresponding Hardware User’s Manual for details, which modes are specified for the used device.

Note

In the very most cases the ‘Normal operating mode’ of the device will be used. This mode is for execution of the user program. The on-chip debug functions also use this mode.

To select the ‘Normal operating mode’ of the device, the FLMD0 pin must be pulled low. To do so, remove the jumper JP41.

All other jumpers related to the mode selection can be left open.


R20UT4371ED0100 Rev.1.00 of 64 Feb 20, 2019

6.2 RESET switch

The SW1 is used to issue a RESET to the device.

The SW1 toggle switch allows to activate the RESET in two different ways:

• SW1 in left '2-1(ON)' position: temporary reset

Releasing the switch's lever returns the switch into its middle 'OFF' position and thus releases the reset.

• SW1 in right '2-3 ON' position: permanent reset

For reset release the switch has to be moved back manually into its middle 'OFF' position.

The left and right switch position is defined from the side of the part number marking, which is highlighted with a red

arrow in the figure below.

The lighted red LED13 indicates that SW1 is "on", i.e. in position '2-1 (ON)' or '2-3 ON'.

Note

LED13 does not light up when RESET is asserted by any other means than SW1.

6.3 RESETZ-EVA signal

By closing the jumper JP42 the device reset RESETZ asserts also following other resets (RESETZ_EVA):

• AURORES1Z

• AURORES2Z

• ERAMRESPDZ

• ERAMRES2Z

Note

The RESETZ_EVA signal affects board components which are used by an Aurora debugger interacting with the RH850/U2A-EVA device.

Thus, remove JP42 when the board is equipped with the RH850/U2A16 device.

Refer to chapter 9.3 for precautions possibly affecting your board revision.

Part No. marking side

Figure 6.1 RESET switch SW1


R20UT4371ED0100 Rev.1.00 of 64 Feb 20, 2019

6.4 Signaling LEDs

Eight LEDs are provided to allow visual observation of the output state of device port pins.

Device pins P11_0 to P11_7 are connected to the odd pins of the pin header CN7, while the LEDs 2 to 9 are connected

to the even CN7 pins.

Thus, the LEDs can be either connected to

• the device port pins P11_0 to P11_7 by closing the connection on CN7 using a jumper, or

• any device pin by connecting directly with the even CN7 pins using a separate cable.

6.5 Pull-up/Pull-down pin header

The Pull-up/Pull-down pin header CN12 provides fixed voltage levels at its pins, that can be used to pull-up/pull-down

a signal on the board or the device, respectively, by connecting a CN12 pin to the signal via a separate cable.

The CN12 pins have following pull-up or pull-down voltage levels:

• all even numbered pins are connected to L level, i.e. to GND

• odd numbered pins 1, 3, 5, 7, 9, can be connected to

− 5.0 V, if JP25[2-1] is set

− 3.3 V, if JP25[2-3] is set

• odd numbered pins 11, 13, 15, 17, can be connected to

− 5.0 V, if JP15[2-1] is set

− 3.3 V, if JP15[2-3] is set

Refer to 7.6 Pull-up/Pull-down pin header CN12 for CN12 details.

6.6 Gigabit Ethernet interface

The PiggyBack Board features a Marvell 88E1112-XX-NNC-I000 Gigabit Ethernet PHY (IC14) for using the device's

Gigabit Ethernet SGMII interface (ETNB1) via the RJ45 type connector CN17.

Notes

1. For ETNBx initial setup please refer to the device UM. For ETNB1 operation the ETNB1SGCLKSEL register must be set to ETNB1SGCLKSEL=0x01 to select the Internal MOSC clock of 20MHz. For an internal MOSC clock of 20MHz the crystal X1 has to be replaced by the 20MHz crystal included in the package. For package content please refer to Table 1.1 Package Components for the Y-RH850-U2A-516PIN-PB-T1-V1

2. The signals of the device's Fast Ethernet (R)MII interface (ETNB0) are available on the MainBoard connectors. Thus, ETNB0 can control an Ethernet PHY on the MainBoard.

3. Alternatively, ETNB1 can also be used to operate the MainBoard's 100 MB Ethernet PHY. In this case the ETNB1 Fast Ethernet mode is selected by Option Bytes settings and the pin multiplexing needs to be configured accordingly.

Refer to 7.7 Ethernet connector CN17 for the CN17 pin assignment.

The device's LVDS Rx and Tx signals of the Ethernet interface can be swapped towards the Ethernet PHY by setting

the jumper JP26. The correct JP26 setting depends on the device on the PiggyBack Board:

• JP26[OPEN]: for RH850/U2A-EVA

− device pins N21/P21 (TX_DATAP/TX_DATAN) used as Ethernet Tx signals

− device pins P22/R22 (RX_DATAP/RX_DATAN) used as Ethernet Rx signals

• JP26[2-1]: for RH850/U2A16


R20UT4371ED0100 Rev.1.00 of 64 Feb 20, 2019

− device pins N21/P21 (TX_DATAP/TX_DATAN) used as Ethernet Rx signals

− device pins P22/R22 (RX_DATAP/RX_DATAN) used as Ethernet Tx signals


R20UT4371ED0100 Rev.1.00 of 64 Feb 20, 2019

6.7 Renesas High-Speed Serial I/F (RHSIF) / Multichannel Serial Peripheral

Interface (MSPI)

The CN5 connector can be used to connect to the device's RHSIF and MSPI0 interface.

Refer to 7.3 RHSIF/MSIP connector CN5 for the CN5 pin assignment.

The MSPI0 interface at CN5 is operated in LVDS mode.

The CN5 Rx and Tx signals of the RHSIF can be swapped by setting the jumper JP1:

• JP1[2-1]:

− RXDP/RXDN at CN5 pins 1 and 3

− TXDP/TXDN at CN5 pins 7 and 9

• JP1[2-3]:

− RXDP/RXDN at CN5 pins 7 and 9

− TXDP/TXDN at CN5 pins 1 and 3

Notes

1. By default all signals are not connected to the CN5 in order to minimize signal integrity disturbance. Upon demand they can be connected via 0 Ω resistors R15 to R18 and R21 to R23.

2. Swapping the Rx/Tx signals allows board-to-board communication e.g. with another PiggyBack Board via separate cables.

RH850/U2A 516pin 7. Connectors

R20UT4371ED0100 Rev.1.00 of 64 Feb 20, 2019

7. Connectors

7.1 Connectors to the MainBoard CN1 to CN3

Three connectors (CN1 to CN3) are available to connect the PiggyBack Board to a MainBoard.

The signals of each connector are summarized in the following tables.

Note

Regarding the function on the MainBoard, please refer to the User's Manual of any supported MainBoard.

Refer to 1.2 Supported MainBoards for a list of supported MainBoards.

7.1.1 MainBoard connector CN1

Table 7.1 MainBoard connector CN1 (cont'd)

Pin MainBoard function PiggyBack Board

device port


device port

1 VDDA ‒ 2 VDDA ‒

3 VDDA ‒ 4 VDDA ‒

5 RESET RESETZ 6 NMI P4_7

7 ‒ ‒ 8 ‒ ‒

9 INT0 P10_12 10 INT1 P22_0

11 INT2 P21_7 12 INT3 P2_8

13 ‒ ‒ 14 ‒ ‒

15 UART0TX P6_6 16 UART1TX P6_3

17 UART0RX P6_5 18 UART1RX P6_2

19 LIN0TX P4_8 20 LIN1TX P2_5

21 LIN0RX P4_9 22 LIN1RX P2_4

23 IIC0SCL P17_3 24 IIC1SCL P22_4

25 IIC0SDA P17_2 26 IIC1SDA P22_3

27 CAN0TX P6_14 28 CAN1TX P6_8

29 CAN0RX P6_13 30 CAN1RX P6_7

31 SENT0RX P21_1 32 SENT1RX P21_0

33 SENT0SPCO P24_6 34 SENT1SPCO P24_7

35 PSI5SRX0 P3_6 36 PSI5RX0 P5_4

37 PSI5STX0 P3_7 38 PSI5TX0 P5_6

39 PSI5SCLK0 P3_8 40 ‒ ‒

41 FLX0TX P20_7 42 FLX0EN P20_5

43 FLX0RX P20_2 44 FLXSTPWT P20_4

45 FLX1TX P20_6 46 FLX1EN P20_8

47 FLX1RX P20_3 48 FLX CLK P10_8

49 ‒ ‒ 50 ‒ ‒

51 ETH0MDIO P20_3 52 ETH0MDC P20_6


R20UT4371ED0100 Rev.1.00 of 64 Feb 20, 2019



device port


device port

53 ETH0RXD0 P10_3 54 EH0TXD0 or ETNB0TXD0

P20_9


P20_10


P20_12


P20_13

61 ETH0RXCLK P10_2 62 ETH0TXCLK P10_1

63 ETH0RXER P10_0 64 ETH0TXER P20_8

65 ETH0CRSDV P20_7 66 ETH0TXEN P20_14

67 ETH0RXDV P10_7 68 ETH0COL ‒

69 ETH0RESET P20_0 70 ETH0LINK P20_1

71 ‒ ‒ 72 ‒ ‒

73 USB0UDMF ‒ 74 USB0UDMH ‒

75 USB0UDPF ‒ 76 USB0UDPH ‒

77 ‒ ‒ 78 ‒ ‒

79 ‒ ‒ 80 ‒ ‒

81 ‒ ‒ 82 ‒ ‒

83 ‒ ‒ 84 ‒ ‒

85 DIGIO_0 P21_2 86 DIGIO_1 P21_3

87 DIGIO_2 P21_4 88 DIGIO_3 P21_5

89 DIGIO_4 P21_6 90 DIGIO_5 P21_7

91 DIGIO_6 P22_0 92 DIGIO_7 P22_1

93 DIGIO_8 P22_2 94 DIGIO_9 P22_3

95 DIGIO_10 P10_8 96 DIGIO_11 P10_9

97 DIGIO_12 P10_10 98 DIGIO_13 P10_11

99 DIGIO_14 P10_12 100 DIGIO_15 P10_13

101 ‒ ‒ 102 ‒ ‒

103 MUX0 P6_0 104 MUX1 P6_2

105 MUX2 P6_3 106 ‒ ‒

107 ADC0 AP4_0 108 ADC1 AP4_1

109 ADC2 AP4_2 110 ADC3 AP4_3

111 ADC4 AP4_4 112 ADC5 AP4_5

113 ADC6 AP4_6 114 ADC7 AP4_7

115 VDDIOF ‒ 116 VDDIOF ‒

117 VDDB ‒ 118 VDDB ‒

119 VDDB ‒ 120 VDDB ‒


R20UT4371ED0100 Rev.1.00 of 64 Feb 20, 2019



Pin Function Device port Pin Function Device port













25 LIN10TX P6_5 26 LIN11TX P3_8

27 LIN10RX P6_4 28 LIN11RX P3_7

29 LIN12TX P0_1 30 LIN13TX P0_4

31 LIN12RX P0_0 32 LIN13RX P0_2

33 LIN14TX P0_5 34 LIN15TX P0_7

35 LIN14RX P0_3 36 LIN15RX P0_6

37 ‒ ‒ 38 ‒ ‒

39 CAN12Tx P1_8 40 CAN13Tx P1_10

41 CAN12Rx P1_9 42 CAN13Rx P1_11

43 CAN14Tx P8_0 44 CAN15Tx P8_2

45 CAN14Rx P8_1 46 CAN15Rx P8_3





55 CAN10TX P1_4 56 CAN11TX P1_6

57 CAN10RX P1_5 58 CAN11RX P1_7

59 ‒ ‒ 60 ‒ ‒

61 LIN16TX P0_10 62 LIN17TX P0_11

63 LIN16RX P0_8 64 LIN17RX P0_9

65 LIN18TX P1_13 66 LIN19TX P1_15

67 LIN18RX P1_12 68 LIN19RX P1_14

69 LIN20TX P3_1 70 LIN21TX P3_10

71 LIN20RX P3_0 72 LIN21RX P3_9

73 LIN22TX P3_12 74 LIN23TX P3_14

75 LIN22RX P3_11 76 LIN23RX P3_13


R20UT4371ED0100 Rev.1.00 of 64 Feb 20, 2019



77 ‒ ‒ 78 ‒ ‒

79 SFMA0CLK P17_5 80 SFMA0SSL P17_4

81 SFMA0IO0 P17_3 82 SFMA0IO1 P17_2

83 SFMA0IO2 P17_1 84 SFMA0IO3 P17_0

85 ‒ ‒ 86 ‒ ‒

87 MMCA0CLK P24_4 88 MMCA0CMD P24_5

89 MMCA0DAT0 P24_6 90 MMCA0DAT1 P24_7




97 ‒ ‒ 98 ‒ ‒

99 ETH1MDIO P3_7 100 ETH1MDC P3_6

101 ETH1RXD0 P23_3 102 ETH1TXD0 P23_10

103 ETH1RXD1 P23_4 104 ETH1TXD1 P23_11

105 ETH1RXD2 P23_5 106 ETH1TXD2 P23_12

107 ETH1RXD3 P23_6 108 ETH1TXD3 P23_13

109 ETH1RXCLK P23_2 110 ETH1TXCLK P23_9

111 ETH1RXER P23_0 112 ETH1TXER P23_7

113 ETH1CRSDV ‒ 114 ETH1TXEN P23_8

115 ETH1RXDV P23_1 116 ETH1COL ‒

117 ETH1RESET P9_0 118 ETH1LINK P21_13

119 ‒ ‒ 120 ‒ ‒




1 CSI0CS0 P21_7 2 CSI0CLK P22_4

3 CSI0CS1 P21_6 4 CSI0SI P22_1

5 CSI0CS2 P21_5 6 CSI0SO P22_0

7 CSI0CS3 P21_4 8 ‒ ‒

9 ‒ ‒ 10 CSI1CS1 P24_8

11 ‒ ‒ 12 ‒ ‒

13 PSI5SRX1 P6_13 14 PSI5RX1 P5_2

15 PSI5STX1 P6_14 16 PSI5TX1 P5_3

17 PSI5SCLK1 P6_15 18 ‒ ‒

19 ‒ ‒ 20 ‒ ‒

21 CSI1CS2 P24_9 22 CSI1CS3 P4_8


R20UT4371ED0100 Rev.1.00 of 64 Feb 20, 2019



23 ‒ ‒ 24 CSI1CS0 P24_7

25 ‒ ‒ 26 DIGIO_24 P17_6

27 ‒ ‒ 28 CSI1SO P24_6

29 CSI1SCLK P24_4 30 CSI1SI P24_5

31 ‒ ‒ 32 ‒ ‒

33 ‒ ‒ 34 ‒ ‒

35 ‒ ‒ 36 ‒ ‒

37 ‒ ‒ 38 ‒ ‒

39 ‒ ‒ 40 ‒ ‒

41 ‒ ‒ 42 ‒ ‒

43 ‒ ‒ 44 ‒ ‒

45 ‒ ‒ 46 ‒ ‒

47 ‒ ‒ 48 ‒ ‒

49 ‒ ‒ 50 ‒ ‒

51 ‒ ‒ 52 ‒ ‒

53 ‒ ‒ 54 ‒ ‒

55 AD1_0 AP2_0 56 AD1_1 AP2_1

57 AD1_2 AP2_2 58 AD1_3 AP2_3

59 AD1_4 AP2_4 60 AD1_5 AP2_5

61 AD1_6 AP2_6 62 AD1_7 AP2_7

63 PWM0 P24_4 64 PWM1 P24_5

65 PWM2 P24_6 66 PWM3 P24_7

67 PWM4 P24_8 68 PWM5 P24_9

69 PWM6 P24_10 70 PWM7 P24_11

71 DIGIO16 P11_8 72 DIGIO17 P11_9

73 DIGIO18 P11_10 74 DIGIO19 P11_11

75 DIGIO20 P11_12 76 DIGIO21 P11_13

77 DIGIO22 P11_14 78 DIGIO23 P11_15

79 ENC0 P10_8 80 ENC1 P10_9

81 ‒ ‒ 82 ‒ ‒

83 ‒ ‒ 84 ‒ ‒

85 ‒ ‒ 86 ‒ ‒

87 ‒ ‒ 88 ‒ ‒

89 ‒ ‒ 90 ‒ ‒

91 ‒ ‒ 92 ‒ ‒

93 ‒ ‒ 94 ‒ ‒

95 ‒ ‒ 96 ‒ ‒

97 ‒ ‒ 98 ‒ ‒

99 ‒ ‒ 100 ‒ ‒


R20UT4371ED0100 Rev.1.00 of 64 Feb 20, 2019



101 ‒ ‒ 102 ‒ ‒

103 ‒ ‒ 104 ‒ ‒

105 ‒ ‒ 106 ‒ ‒

107 ‒ ‒ 108 ‒ ‒

109 ‒ ‒ 110 ‒ ‒

111 ‒ ‒ 112 ‒ ‒

113 ‒ ‒ 114 ‒ ‒

115 ‒ ‒ 116 ‒ ‒

117 ‒ ‒ 118 ‒ ‒

119 ‒ ‒ 120 ‒ ‒

7.2 Debug connector CN4

Table 7.4 On-Chip Debugger connector CN4


1 TDCK / LPDCLK / FPCK

JP0_2 2 GND

3 TRSTZ 4 FLMD0

5 TDO / LPDO / FPDT JP0_1 6 ‒

7 TDI / LPDIO / FPDR JP0_0 8 E0VCC

9 TMS JP0_3 10 EVTOZ

11 RDY / LPDCLKOUT JP0_5 12 GND

13 RESETZ 14 GND

7.3 RHSIF/MSIP connector CN5

Table 7.5 RHSIF/MISP connector CN5 cont'd

Pin JP1[2-1] JP1[2-3]

Device port Function Device port Function

1 P2_13 HSIF0_TXDP / MSPI0_SOP P2_11 HSIF0_RXDP / MSPI0_SIP

2 P2_15 MSPI0_SCKP P2_15 GND

3 P2_12 HSIF0_TXDN / MSPI0_SON P2_10 HSIF0_RXDN / MSPI0_SIN

4 P2_14 MSPI0_SCKN P2_14 MSPI0_SCKN

5 ‒ GND ‒ GND

6 P2_9 HSIF0_REFCLK / MSPI0CSS4 P2_9 HSIF0_REFCLK

7 P2_11 HSIF0_RXDP / MSPI0_SIP P2_13 HSIF0_TXDP / MSPI0_SOP

8 ‒ GND ‒ GND


R20UT4371ED0100 Rev.1.00 of 64 Feb 20, 2019

Table 7.5 RHSIF/MISP connector CN5 cont'd

Pin JP1[2-1] JP1[2-3]

Device port Function Device port Function

9 P2_10 HSIF0_RXDN / MSPI0_SIN P2_12 HSIF0_TXDN / MSPI0_SON

10 ‒ GND ‒ GND

11 ‒ GND ‒ GND

12 ‒ GND ‒ GND

Note

By default all signals are not connected to CN5 in order to minimize signal integrity disturbance. Upon demand they can be connected via 0 Ω resistors R15 to R18 and R21 to R23.

7.4 Aurora interface connector CN6

Table 7.6 Aurora interface connector CN6 (cont'd)


1 TODP0 2 E0VCC

3 TODN0 4 TCK / LPDCLKI JP0_2

5 GND 6 RMS JP0_3

7 TODP1 8 TDI / LPDI JP0_0

9 TODN1 10 TDO / LPDO JP0_1

11 GND 12 TRSTZ

13 TODP2 14 FLMD0

15 TODN2 16 EVTIZ

17 GND 18 EVTOZ

19 TODP3 20 FLMD1 P6_13

21 TODN3 22 RESETZ

23 GND 24 GND

25 NC 26 CICREFP

27 NC (WDTDIS) ‒ 28 CICREFN

29 GND 30 GND

31 NC (ETK-BREQ) ‒ 32 RDYZ / LPDCLKO JP0_5

33 NC (ETK-BGNT) ‒ 34 RESETOUTZ P6_10


R20UT4371ED0100 Rev.1.00 of 64 Feb 20, 2019

7.5 Device ports connectors CN13 to CN16

The device port connectors enable easy connection to almost all ports of the device.

CAUTION

The pin headers are directly connected to the pins, therefore special care must be taken to avoid any electrostatic or other damage to the device.

7.5.1 Device ports connector CN13

Table 7.7 Device ports connector CN13

Pin Device port Pin Device port Pin Device port

A1 P1_1 B1 P1_0 C1 P1_3

A2 P1_2 B2 AP0_7 C2 P1_5

A3 P1_4 B3 AP0_13 C3 P1_7

A4 P1_6 B4 AP0_12 C4 P1_9

A5 P1_8 B5 AP0_10 C5 P1_11

A6 P1_10 B6 AP0_9 C6 P1_13

A7 P1_12 B7 P3_2 C7 P24_7

A8 P24_4 B8 AP0_11 C8 P1_14

A9 P3_3 B9 P4_0 C9 P4_1

A10 P4_4 B10 P24_5 C10 P4_5

A11 P4_6 B11 P24_6 C11 P24_11

A12 P24_8 B12 P24_9 C12 P1_15

A13 P4_8 B13 P24_10 C13 P4_3

A14 P4_2 B14 P4_7 C14 P4_9

A15 P4_10 B15 P24_12 C15 P4_11

A16 P4_12 B16 P24_13 C16 P3_15

A17 P3_14 B17 P4_14 C17 P3_13

A18 P3_12 B18 P4_13 C18 P3_11

A19 P3_10 B19 P4_15 C19 P3_1

A20 GND B20 ‒ C20 ‒


R20UT4371ED0100 Rev.1.00 of 64 Feb 20, 2019




A1 P11_15 B1 P19_1 C1 P19_0

A2 P21_5 B2 P19_3 C2 P19_2

A3 P21_6 B3 P19_5 C3 P19_4

A4 P21_7 B4 P18_14 C4 P18_15

A5 P17_6 B5 P18_12 C5 P18_13

A6 P17_5 B6 P18_10 C6 P18_11

A7 P17_2 B7 P18_8 C7 P18_9

A8 P17_4 B8 P18_6 C8 P18_7

A9 P17_3 B9 P18_4 C9 P18_5

A10 P18_2 B10 P18_3 C10 P10_9

A11 P18_1 B11 P10_10 C11 P10_11

A12 P18_0 B12 P10_12 C12 P10_13

A13 P9_8 B13 P10_14 C13 P17_0

A14 AP2_6 B14 P17_1 C14 AP2_13

A15 AP2_4 B15 AP2_10 C15 AP2_11

A16 AP2_2 B16 AP2_8 C16 AP2_9

A17 P9_7 B17 P9_6 C17 AP2_7

A18 P9_5 B18 P9_4 C18 AP2_5

A19 P9_3 B19 P9_2 C19 AP2_3

A20 P9_1 B20 P9_0 C20 AP2_1

A21 AP2_0 B21 AP2_14 C21 AP3_2

A22 AP3_0 B22 AP2_15 C22 P12_5

A23 P12_4 B23 AP3_3 C23 P12_3

A24 P12_2 B24 AP3_1 C24 P12_1

A25 P12_0 B25 AP2_12 C25 AP0_1

A26 AP0_0 B26 AP1_3 C26 AP1_1

A27 AP0_2 B27 AP1_2 C27 AP0_3

A28 AP0_4 B28 AP1_0 C28 ERAMRESPDZ

A29 AP0_5 B29 AP0_6 C29 AP0_15

A30 AP0_8 B30 ERAMRES2Z C30 AP0_14


R20UT4371ED0100 Rev.1.00 of 64 Feb 20, 2019




A1 AP4_12 B1 P3_0 C1 P3_9

A2 AP4_10 B2 AP5_3 C2 AP5_2

A3 AP4_8 B3 AP4_11 C3 AP5_1

A4 AP4_6 B4 AP4_9 C4 AP5_0

A5 P3_5 B5 AP4_7 C5 AP4_15

A6 P6_11 B6 AP4_5 C6 AP4_14

A7 P6_2 B7 P3_4 C7 AP4_13

A8 P6_3 B8 P6_4 C8 AP4_4

A9 P6_5 B9 P6_6 C9 AP4_0

A10 P6_7 B10 P6_8 C10 AP4_3

A11 P6_9 B11 P6_12 C11 AP4_2

A12 P6_15 B12 P6_10 C12 AP4_1

A13 P6_13 B13 P6_14 C13 P6_0

A14 JP0_5 B14 JP0_3 C14 P3_6

A15 JP0_2 B15 JP0_1 C15 P3_7

A16 JP0_0 B16 TRSTZ C16 RESETZ

A17 GETH0VCL B17 GND C17 P3_8

A18 X2_C * B18 PWRCTL C18 VMONOUTZ

A19 X1_C * B19 P5_2 C19 P5_3

A20 AURORES1Z B20 P5_4 C20 FLMD0

A21 AURORES2Z B21 P0_11 C21 P0_12

A22 AURORESPDZ B22 P0_9 C22 P0_10

A23 P2_1 B23 P0_7 C23 P0_8

A24 P0_4 B24 P0_5 C24 P0_6

A25 P0_3 B25 P0_1 C25 P0_2

A26 P5_6 B26 AWOVCL C26 P0_0

A27 P2_0 B27 MSYNZ C27 P2_4

A28 P2_2 B28 EVTIZ C28 P2_6

A29 P2_3 B29 AUDATA0 C29 EVTOZ

A30 P2_5 B30 AUDATA2 C30 AUDATA1

Note * By default these signals are not connected to CN15 in order to minimize signal integrity disturbance. Upon demand they can be connected via 0 Ω resistors R3 and R4.


R20UT4371ED0100 Rev.1.00 of 64 Feb 20, 2019




A1 P2_7 B1 AUDATA3 C1 AUDRSTZ

A2 CN_P2_9 * B2 AUDSYNCZ C2 AUDCK

A3 P2_8 B3 CN_P2_10 * C3 P8_9

A4 CN_P2_12 * B4 CN_P2_14 * C4 P8_7

A5 CN_P2_11 * B5 P8_10 C5 P8_5

A6 CN_P2_13 * B6 P8_8 C6 P8_3

A7 CN_P2_15 * B7 P8_6 C7 P8_1

A8 P22_3 B8 P8_4 C8 P8_0

A9 P22_4 B9 P8_2 C9 P21_0

A10 P22_1 B10 P20_1 C10 P21_1

A11 P22_2 B11 P20_3 C11 P21_2

A12 P22_0 B12 P20_5 C12 P21_3

A13 P20_0 B13 P20_7 C13 P21_4

A14 P20_2 B14 P20_9 C14 P23_13

A15 P20_4 B15 P20_12 C15 P23_11

A16 P20_6 B16 P23_12 C16 P23_9

A17 P20_8 B17 P23_10 C17 P23_7

A18 P20_10 B18 P23_8 C18 P23_5

A19 P20_13 B19 P23_6 C19 P23_3

A20 P20_14 B20 P23_4 C20 P23_1

A21 ERROROUTZ B21 P23_2 C21 P23_0

A22 P21_12 B22 P20_15 C22 P21_13

A23 P11_0 B23 P10_1 C23 P10_0

A24 P11_2 B24 P10_2 C24 P11_1

A25 P11_4 B25 P10_3 C25 P11_3

A26 P11_6 B26 P10_4 C26 P11_5

A27 P11_8 B27 P10_5 C27 P11_7

A28 P11_10 B28 P10_6 C28 P11_9

A29 P11_12 B29 P10_7 C29 P11_11

A30 P11_14 B30 P10_8 C30 P11_13

Note * By default these signals are not connected to CN16 in order to minimize signal integrity disturbance. Upon demand they can be connected via 0 Ω resistors R15 to R18 and R21 to R23.


R20UT4371ED0100 Rev.1.00 of 64 Feb 20, 2019

7.6 Pull-up/Pull-down pin header CN12

Pin Function Pin Function

1 fixed H level, depends on JP25:

• JP25[2-1]: 5.0 V

• JP25[2-3]: 3.3 V

2 fixed L level

3 4

5 6

7 8

9 10

11 fixed H level, depends on JP15:

• JP15[2-1]: 5.0 V

• JP15[2-3]: 3.3 V

12

13 14

15 16

17 18

19 20

7.7 Ethernet connector CN17

Table 7.11 Ethernet connector CN17

Pin Function Pin Function Pin Function

1 TRCT3 8 TRD4_PLUS 15 ORN_MINUS

2 TRD3_MINUS 9 TRD4_MINUS 16 COM_PLUS

3 TRD3_PLUS 10 TRD1_MINUS 17 GRN_MINUS

4 TRD2_PLUS 11 TRD1_PLUS 18 GND

5 TRD2_MINUS 12 TRCT1 19 GND

6 TRCT2 13 YEL_MINUS

7 TRCT4 14 YEL_PLUS

RH850/U2A 516pin 8. Jumper Configuration Examples

R20UT4371ED0100 Rev.1.00 of 64 Feb 20, 2019

8. Jumper Configuration Examples

Several functions of the board can be configured via jumpers.

The board is shipped without any jumpers set on the board.

For a complete list of jumpers refer to 2.1 Jumpers overview.

For jumper settings related to the device operation mode, refer to 6.1 Operation mode selection.

The following sections show some jumper settings, that allow to operate the PiggyBack Board in different power supply

configurations.

8.1 Stand-alone operation with power supply by the tool

In principle the PiggyBack Board can also exclusively be powered via a connected debugger. However the debug tool

would need to deliver sufficient currents on the power supply rails in order to operate the board in a useful manner.

Due to the limited current capability of Renesas' E2 Emulator, powering the board only via this debugger is not feasible.

In case of using another debug tool check its specification whether powering the PiggyBack Board with the tool is

possible.

CAUTION

If a debugger or a programming tool is connected disable the 3.3 V/5 V voltage output of the tool.

8.2 RH850/U2A-EVA vs. RH850/U2A16

The following voltages are only used when the board is equipped with a RH850/U2A-EVA device and thus the

mentioned jumpers must be set:

EMUVCC (JP17), ERAMVCC (JP18), - DVCC (JP19), DVDD (JP24), ERAMVDD (JP28), EMUVDD (JP29)

If the board is equipped with a RH850/U2A16 device remove the above jumpers.

8.3 Configuration examples

8.3.1 General settings

All of the following board configurations are based on these conditions:

• Normal device operation mode (JP41[OPEN]: FLMD0 = L).

• All voltages for all functions are activated.

• Current measurements are not carries out, hence JP4, JP5, JP30 and JP31 are set.

• Clock supply: assuming one of the resonators, coming with the board, are plugged into X1 socket.

• For connection to external power supplies the 'banana-type' connectors CN8 to CN11 must be assembled on the

board.


R20UT4371ED0100 Rev.1.00 of 64 Feb 20, 2019

8.3.2 Jumper indicators

• The green jumper JP41 for FLMDO0 must always be open for a ‘normal’ (user mode and debug) operation of the

device.

• The red jumpers are related to the power supply configuration.

• The blue jumpers are only set if the board is equipped with a RH850/U2A-EVA device.

Following jumper symbols are used:

− : open jumper

− : jumper must be set in the indicated position

− : jumper must be set, italic position indicator is optional, see description above the figure

Note

The pin 1 of a jumper can be identified by a

• small circle near the jumper

• square soldering pad.


R20UT4371ED0100 Rev.1.00 of 64 Feb 20, 2019

15

10

51

510152025 130

5V

GNDVDD

VD

D

VC

C

5V

5V

P11 _7_0

92 LED

GND

GND

D016345_06_V02


RoHS-compliant

Made in Europe

DVDD

ERAMVDD

MODE0

FLMD2

FL

MD

1

EV

OT

Z

EV

ITZ

ER

AM

VC

C

DV

CC

GETHORVCC

SVRAVCC

SVRDRVCC

A2VREFH

A0VREFH

FL

MD

0

EMUVCC


LVDVCC

E2

VC

C

3.3

V

Anti_Static


5.0V 3.3V

GETHOBVCC

VD

DS

A5.0V

SYSVCC

E1

VC

C

VMONOUT

GETHOPVCC

A2VCC

VDDIOF

E0

VC

C

A1VREFH

A1VCC

A0VCC

EMUVDD

3.3

V

3.3

V

PULL_DOWN

ERROROUT_M

Reset LED1

5.0V

20

10

5

15

10 20

30

20

R114

1

TP3

C78

TP4

D1

CN

9

R106

C113

R1

37

C133

TP1

TP9

CN17

TP2

A

2

JP16

CN

8

JP10

LED13

JP25

TR5

JP24

IC19

R107

GND

B

REG

SVR

5

CN

10

LED10

JP11

3.3V

JP15

EV

A-R

ES

JP13

C

JP2

1

B

LED11

JP

36

A

JP28

GND

B C

IC12

LED14

CN

13

CN15

SW ON

JP

30

LED15

A3.3V

JP21

3.3V

5V

3.3V3

.3VReset

1

VDDS

CN11

PWRCTL

JP

31

RH

SIF

/ M

SP

I

CN

16

3.3V

IC18

5V

JP

35

VDD

JP29

JP1

R1

04

GND

25

3.3V

30

JP38

15

16

B

IC1

JP40

X1

CN14

TP7

JP

4

JP7

CN4

JP9

TP5

15

JP19

JP42

R14

0

JP

34

CN7

25

A

LED12

Se

ria

l

R12

9

TR

14

IC6

JP22

CN

11

SW1

R14

1

R1

28

TR4

JP20

JP39

JP17

JP

33

JP18

C

JP

32

TP6JP8

R1

27

JP6

JP26

A

R13

9

CN

12

TP8TP10

IC4

JP14

JP12

JP41

2

1

C

5V

R1

38

5V

JP

23

R1

05

C24

IC11

JP3

CN5

JP

5

C21

20

JP

37

C116

TR15

IC10

2

CN6

IC13

19 1

IC15

R136

8.3.3 Stand-alone operation with single external power supply: minimum configuration

This example enables to operate the board with only the 3.3 V external power supply.

Since no 5 V voltage is available, all I/O ports can only use 3.3 V.

• CN8: GND connection

• CN10: 3.3 V

• CN9: not connected, no 5.0 V

− jumpers JP6 to JP14 and JP32 to JP37 are set to 3.3 V position [2-3]

• CN11: not connected, no IN_1v12

− JP16[2-1]: use reg_vcc_VDD from on-board voltage regulator xVDD voltages

− VDD from reg_vcc_VDD (JP23[2-1]) or from SVR_OUTPUT (JP23[2-3]) from on-chip Switching Voltage

Regulator


Figure 8.1 Stand-alone operation with minimum external power supply

1 2 3

1 2

1 2

1

2

1

2

2 1

2 1

1

2

3

2 1

2 1

2 1

2 1

2 1

2

1

2 1

1

2

3 2

3 2

3 2

3 2

3 2

2

3

2

3

2

3

2

3

3 2

3 2

3 2

3 2

3 2

3 2

2 1


R20UT4371ED0100 Rev.1.00 of 64 Feb 20, 2019

15

10

51

510152025 130

5V

GNDVDD

VD

D

VC

C

5V

5V

P11 _7_0

92 LED

GND

GND

D016345_06_V02


RoHS-compliant

Made in Europe

DVDD

ERAMVDD

MODE0

FLMD2

FL

MD

1

EV

OT

Z

EV

ITZ

ER

AM

VC

C

DV

CC

GETHORVCC

SVRAVCC

SVRDRVCC

A2VREFH

A0VREFH

FL

MD

0

EMUVCC


LVDVCC

E2

VC

C

3.3

V

Anti_Static


5.0V 3.3V

GETHOBVCC

VD

DS

A5.0V

SYSVCC

E1

VC

C

VMONOUT

GETHOPVCC

A2VCC

VDDIOF

E0

VC

C

A1VREFH

A1VCC

A0VCC

EMUVDD

3.3

V

3.3

V

PULL_DOWN

ERROROUT_M

Reset LED1

5.0V

20

10

5

15

10 20

30

20

R114

1

TP3

C78

TP4

D1

CN

9

R106

C113

R1

37

C133

TP1

TP9

CN17

TP2

A

2

JP16

CN

8

JP10

LED13

JP25

TR5

JP24

IC19

R107

GND

B

REG

SVR

5

CN

10

LED10

JP11

3.3V

JP15

EV

A-R

ES

JP13

C

JP2

1

B

LED11

JP

36

A

JP28

GND

B C

IC12

LED14

CN

13

CN15

SW ON

JP

30

LED15

A3.3V

JP21

3.3V

5V

3.3V

3.3

VReset

1

VDDS

CN11

PWRCTL

JP

31

RH

SIF

/ M

SP

I

CN

16

3.3V

IC18

5V

JP

35

VDD

JP29

JP1R

10

4

GND

25

3.3V

30

JP38

15

16

B

IC1

JP40

X1

CN14

TP7

JP

4

JP7

CN4

JP9

TP5

15

JP19

JP42

R14

0

JP

34

CN7

25

A

LED12

Se

ria

l

R12

9

TR

14

IC6

JP22

CN

11

SW1

R14

1

R1

28

TR4

JP20

JP39

JP17

JP

33

JP18

C

JP

32

TP6JP8

R1

27

JP6

JP26

A

R13

9

CN

12

TP8TP10

IC4

JP14

JP12

JP41

2

1

C

5V

R1

38

5V

JP

23

R1

05

C24

IC11

JP3

CN5

JP

5

C21

20

JP

37

C116

TR15

IC10

2

CN6

IC13

19 1

IC15

R136

8.3.4 Stand-alone operation with all external power supplies: maximum configuration

This example assumes all external power supplies are connected and used.

• CN8: GND connection

• CN10: 3.3 V

• CN9: 5 V

− select desired 3.3 V/5.0 V via jumpers JP6 to JP14 and JP32 to JP37

• CN11: 1.12 V (IN_1v12)

− JP16[2-3], JP23[2-1]: use IN_1v12 for all xVDD voltages


Figure 8.2 Stand-alone operation with maximum external power supply

1 2 3

1 2

1 2

1

2

1

2

3 2 1

3 2 1

3 2 1

3 2 1

3 2 13 2 1

1

2

3 3 2 1

3 2 1

3 2 1

3 2 1

3 2 1

1

2

3

1

2

3

1

2

3

2 1

2 1

1

2

2 1

2 1

2 1

2 1

2 1

2

1

2 1

2

3

1

2


R20UT4371ED0100 Rev.1.00 of 64 Feb 20, 2019

15

10

51

510152025 130

5V

GNDVDD

VD

D

VC

C

5V

5V

P11 _7_0

92 LED

GND

GND

D016345_06_V02


RoHS-compliant

Made in Europe

DVDD

ERAMVDD

MODE0

FLMD2

FL

MD

1

EV

OT

Z

EV

ITZ

ER

AM

VC

C

DV

CC

GETHORVCC

SVRAVCC

SVRDRVCC

A2VREFH

A0VREFH

FL

MD

0

EMUVCC


LVDVCC

E2

VC

C

3.3

V

Anti_Static


5.0V 3.3V

GETHOBVCC

VD

DS

A5.0V

SYSVCC

E1

VC

C

VMONOUT

GETHOPVCC

A2VCC

VDDIOF

E0

VC

C

A1VREFH

A1VCC

A0VCC

EMUVDD

3.3

V

3.3

V

PULL_DOWN

ERROROUT_M

Reset LED1

5.0V

20

10

5

15

10 20

30

20

R114

1

TP3

C78

TP4

D1

CN

9

R106

C113

R1

37

C133

TP1

TP9

CN17

TP2

A

2

JP16

CN

8

JP10

LED13

JP25

TR5

JP24

IC19

R107

GND

B

REG

SVR

5

CN

10

LED10

JP11

3.3V

JP15

EV

A-R

ES

JP13

C

JP2

1

B

LED11

JP

36

A

JP28

GND

B C

IC12

LED14

CN

13

CN15

SW ON

JP

30

LED15

A3.3V

JP21

3.3V

5V

3.3V

3.3

VReset

1

VDDS

CN11

PWRCTL

JP

31

RH

SIF

/ M

SP

I

CN

16

3.3V

IC18

5V

JP

35

VDD

JP29

JP1

R1

04

GND

25

3.3V

30

JP38

15

16

B

IC1

JP40

X1

CN14

TP7

JP

4

JP7

CN4

JP9

TP5

15

JP19

JP42

R14

0

JP

34

CN7

25

A

LED12

Se

ria

l

R12

9

TR

14

IC6

JP22

CN

11

SW1

R14

1

R1

28

TR4

JP20

JP39

JP17

JP

33

JP18

C

JP

32

TP6JP8

R1

27

JP6

JP26

A

R13

9

CN

12

TP8TP10

IC4

JP14

JP12

JP41

2

1

C

5V

R1

38

5V

JP

23

R1

05

C24

IC11

JP3

CN5

JP

5

C21

20

JP

37

C116

TR15

IC10

2

CN6

IC13

19 1

IC15

R136

8.3.5 Operation on the MainBoard: no external supply

This example assumes the PiggyBack Board is plugged onto a MainBoard, which provides 3.3 V and 5.0 V.

• CN8 to CN11: not connected, no external 5.0 V, 3.3 V, 1.12 V

• select desired 3.3 V/5.0 V via jumpers JP6 to JP14 and JP32 to JP37

• xVDD supply:

− JP16[2-1]: use reg_vcc_VDD from on-board voltage regulator xVDD voltages

− VDD from reg_vcc_VDD (JP23[2-1]) or SVR_OUTPUT (JP23[2-3]) from on-chip Switching Voltage

Regulator


Note

This configuration still allows to utilize an external IN_1v12 voltage (connected to CN8, CN11) as the source for all xVDD voltages. In this case set JP16[2-3] and JP23[2-1].

Figure 8.3 Main board operation without external power supply

1 2 3

1 2

1 2

1

2

1

2

3 2 1

3 2 1

3 2 1

3 2 1

3 2 13 2 1

1

2

3 3 2 1

3 2 1

3 2 1

3 2 1

3 2 1

1

2

3

1

2

3

1

2

3

2 1

2 1

1

2

3

2 1

2 1

2 1

2 1

2 1

2

1

2 1

1

2

1

2

RH850/U2A 516pin 9. Precautions

R20UT4371ED0100 Rev.1.00 of 64 Feb 20, 2019

9. Precautions

9.1 Power-Off sequence

A dedicated sequence needs to be applied, when the power supplied to the board is turned off.

Please follow the below sequence:

1. At first turn the RESET switch SW1 into '2-3 ON' position, so that RESET is permanently asserted.

Alternatively keep SW1 manually in' 2-1 (ON)' position.

2. Turn off the board power supply.

3. After the power supply has shut down, deassert RESET by returning SW1 into the 'OFF' position.

For details how to apply a RESET, please refer to section 6.2 RESET switch.


R20UT4371ED0100 Rev.1.00 of 64 Feb 20, 2019

9.2 Gigabit Ethernet interface

• Affected products: Some boards with hardware version D016345_06_V01

• Not affected products: All boards with hardware version D016345_06_V02 and above

For using the Ethernet interface (CN17) 0 Ω resistors R127 to R129 and R137 to R141 must be soldered onto the board.

The following figure shows the related schematics excerpt and indicate the resistor's locations on the board.

C

Figure 9.1 0 Ω resistors R127 to R129 and R137 to R141


R20UT4371ED0100 Rev.1.00 of 64 Feb 20, 2019

9.3 Generation of AURORA RESETx Signals

The generation of the signals AURORES1Z and AURORESPDZ is different for board version V01 and V02

For board version D016345_06_V01 the signal generation is shown in figure Figure 9.2:

For board version D016345_06_V02 the signal generation is shown in figure Figure 9.3:

Figure 9.2 AURORES1Z generation board version V01

Figure 9.3 AURORES1Z and AURORESPDZ generation board version V02 and above


R20UT4371ED0100 Rev.1.00 of 64 Feb 20, 2019

9.4 Erroneous Silkscreen print of CN15 and CN16

• Affected products: Boards with hardware version D016345_06_V01

• Not affected products: Boards with hardware version D016345_06_V02 and above

The numbering along CN15 and CN16 indicating the pin number is slipped one digit beginning with number “5”.

9.5 Erroneous Silkscreen print of part name

• Affected products: All boards

The product name is missing “PB” in the middle.

It must be “RH850-U2A-512PIN-PB-T1-V1”

9.6 CAN0RX is shared with FLASH Programmer signal FLMD1

When using this product plugged into a motherboard where CAN0 is connected to the CAN-transceiver the FLASH

programmer will not work.

This is because the CAN0RX function is shared with the FLMD1 function on the same device PIN.

Most CAN-transceiver are driving the RX line actively and the FLASH programmer then is not able to change signal

level as required for flashing.

510

1520

25

510152025

Figure 9.4 Numbering of CN15 and CN16 board version V01


R20UT4371ED0100 Rev.1.00 of 64 Feb 20, 2019

9.7 Displacement of JP39 and CN6

• Affected products: Boards with hardware version D016345_06_V01

• Not affected products: Boards with hardware version D016345_06_V02 and above

JP39 is located very close to CN6. To plug the AURORA-cable into CN6 the jumper-flag needs to be bend away.

Figure 9.6: OPC displacement of JP39 and CN6 solved new board revision

Figure 9.5: OPC displacement of JP39 and CN6

RH850/U2A 516pin 10. Mechanical Dimensions

R20UT4371ED0100 Rev.1.00 of 64 Feb 20, 2019

10. Mechanical Dimensions

Figure 10.1 Mechanical dimensions

RH850/U2A 516pin 11. Schematics

R20UT4371ED0100 Rev.1.00 of 64 Feb 20, 2019

11. Schematics

CAUTION

The schematics shown in this document are not intended to be used as a reference for mass production. Any usage in an application design is in sole responsibility of the customer.

The following components described in the schematics are not provided with the board upon delivery:

• Oscillators and resonators: OSC1, X3

• Capacitors: C97, C98, C113, C116,

• Resistors: R2 – R4, R6, R15 – R18, R21 – R23, R104 – R107, R127 – R129, R137, R138 – R141, R143,

The above components are indicated with "DNF/DNB" in the schematics.

The following components described in the schematics are provided with but not mounted on the board upon delivery:

• 3 Hirschmann 4 mm power lab sockets, red for CN9 – CN11

• 1 Hirschmann 4 mm power lab sockets, black for CN8

• three resonators HC49 (16/20/24 MHz)

• 49 jumpers, 2.54 mm, black

The above components are indicated with "DO NOT FIT / TO DELIVER WITH THE BOARD" in the schematics.


R20UT4371ED0100 Rev.1.00 of 64 Feb 20, 2019

11.1 Page 1

2.0

0

16 M

Hz

pro

vide a

dditi

onal

24 M

Hz

pro

vide a

dditi

onal

1.0

2

W.R

ause

r

F19

K21

W17

N22

M21

F23

K18J1

7

F22

T22

R21

M21

M22

M21

H30

K30

9m

Ohm

@ 1

MH

z5m

Ohm

@ 5

00kH

z

CA

UTIO

N!

G20

F24

TX

_C

LK

PT

X_C

LK

N

L21

resi

stors

clo

se to M

CU

pin

20 M

Hz

pro

vide a

dditi

onal

Each

capaci

tor

ES

R

16.0

8.2

018

22.0

8.2

018

F18

K22

G21

crys

tal

W.R

ause

r

W.R

ause

r

2.0

0

2.0

0

3.0

0

changed to v

ers

ion 2

for new

pro

duct

ion

changed P

ow

er IC

9

changed p

lace

TR

1/T

R2 a

dd D

1 &

R144

1.0

1

added R

145

changed w

irin

g o

f th

e A

UR

OR

ES

PDZ

28.0

9.2

018

04.0

9.2

018

W.R

ause

r

W.R

ause

r

W.R

ause

r04.1

0.2

018

18.1

0.2

018

changed fro

m D

NF

to p

lace

(R

127, R

128, R

129, R

137-R

141)

Thu O

ct 1

8 1

2:3

0:1

3 2

01

8P

AG

E 1

OF

6

CR

-1 : @

RH

850_U

2X

_516P

IN_P

B_T

1_V

1_LIB

.RH

850_U

2X

_516P

IN_P

B_T

1_V

1(S

CH

_1):

PA

GE

1

3.0

0

D016345_04

rh850_u2a_516pin

_pb_t1

_v1

Ele

ctro

nic

s E

uro

pe G

mbH

03.0

7.2

018

W.R

ause

r

3.3

V

100

40.0

00 M

Hz

+ s

ock

et

100n

100n

100n

100n

220n

DN

F/D

NB

0

1u

1K

0

100n

DN

F/D

NB

SG

8002C

E-2

0M

Hz

DN

F/D

NB

0

18pF

100n

100n

n0

01

n0

01

n0

01

100n

100n

100n

100n

100n

100n

100n

100n

100n

100n

100n

100n

100n

100n

100n

100n

100n

100n

220n

100n

100n

100n

100n

100n

100n

100n

100n

100n

100n

100n

100n

100n

100n

100n

100n

100n

100n

100n

100n

100n

100n

0

Test

poin

t_sm

all_

bl

ES

R<10m

Ohm

@ 0

.5&

1M

HZ

22u

22u

ES

R<10m

Ohm

@ 0

.5&

1M

HZ

22u

ES

R<10m

Ohm

@ 0

.5&

1M

HZ

22u

ES

R<10m

Ohm

@ 0

.5&

1M

HZ

22u

ES

R<10m

Ohm

@ 0

.5&

1M

HZ

22u

ES

R<10m

Ohm

@ 0

.5&

1M

HZ

22u

ES

R<10m

Ohm

@ 0

.5&

1M

HZ

ES

R<10m

Ohm

@ 0

.5&

1M

HZ

22u

Test

poin

t_sm

all_

rd

Test

poin

t_sm

all_

ye

16M

HzDN

F/D

NB

8pF

1uH

2.2

u

100n

15u

0

DN

F/D

NB

22pDNF/DNB

22pDNF/DNB

4.7

uH

RT

R030P

02H

ZG

TL

RT

R040N

03H

ZG

TL

1.1

2V

14

15

100

DN

F/D

NB

DN

F/D

NB

100

12

13 10

1.0

9V

3v3

or

5V

3.3

V o

r 5V

3v3

or

5V

3.3

V o

r 5V

3.3

V o

r 5V

100

3.3

V

3.3

V o

r 5V

3.3

V

3.3

V o

r 5V

3.3

V

3.3

or

5V

3.3

V o

r 5V

ren_rh

850_u2a_516_so

cket

3v3

or

5V

3.3

or

5V

3.3

or

5V

3.3

or

5V

3v3

or

5V

3v3

or

5V

3v3

or

5V

1.1

2V

1.1

2V

3.3

V o

r 5V

3.3

V

1.1

2V

3.3

V3.3

V3v3

or

5V

3.3

V o

r 5V

1.1

2V

3.3

V o

r 5V

3v3

or

5V

3v3

or

5V

3v3

or

5V

3.3

or

5V

3.3

V o

r 5V

3.3

V o

r 5V

3.3

V3.3

or

5V

3v3

or

5V

3.3

V

100

11

1.1

2V

3.3

V

1.1

2V

3.3

V

1.1

2V

3v3

or

5V

3.3

V o

r 5V

3.3

V o

r 5V

AW

OV

CL

E0V

CC

SV

R_O

UT

PU

T

E1V

CC

E0V

CC

SV

RA

VC

CG

ET

H0B

VC

CA

WO

VC

L

GE

TH

0R

VC

C

A0V

CC

ER

AM

VD

D

ER

AM

VC

C

SV

RD

RV

CC

SV

RA

VC

C

GE

TH

0P

VC

CE

MU

VC

CE

MU

VD

DE

RA

MV

DD

SY

SV

CC

EM

UV

DD

P3V

3

A2V

RE

FH

SY

SV

CC

VC

C

VD

D

ER

AM

VC

C

A0V

RE

FH

E2V

CC

A1V

RE

FH

LV

DV

CC

A0V

CC

A2V

CC

A1V

RE

FH

DV

DD

A2V

CC

A0V

RE

FH

EM

UV

CC

A2V

RE

FH

VC

C

LV

DV

CC

E1V

CC

GE

TH

0V

CL

GE

TH

0P

VC

C

E2V

CC

DV

DD

DV

CC

_f

VD

D

DV

CC

A1V

CC

A1V

CC

GE

TH

0B

VC

C

SV

RD

RV

CC

GE

TH

0V

CL

SV

RD

RV

CC

GE

TH

0R

VC

C

C2

C8

C5

C13

C15

C19

R3

C14

R1

C16

OS

C1

R2

X1

C10

C11

6C

7C

9C

C3

C4

C1

C35

C34

C33

C32

C29

C28

C27

C26

C25

C23

C22

C20

C18

C17

C36

C64

C63

C62

C37

C38

C39

C40

C41

C56

C43

C45

C48

C51

C50

C59

C42

C47

C44

C53

C55

C60

C61

R58

TP

9

C49

C133

C130

C78

C65

C24

C21

C46

TP

10

TP

4

X3

L2

C30

C31

C12

R4

C97

C98

L1

TR

2

TR

1

R143

R6

R7

R142

R109

IC1

6B

6

2B

6

4F

52D

2

2D

46B

46B

62B

42D

4

2D

84A

6

6B

16B

36B

7

4A

1

2C

3

2D

8

1B

72C

62D

22D

44D

34D

56B

36B

46B

6

5B

1

2D

62D

86B

16B

36C

16C

32A

72A

92A

72A

92B

62B

72B

9

5C

35B

15B

1

5C

3

5B

1

2D

3

2B

62B

72B

9

2D

24E

9

2B

62B

76B

96C

76C

92B

72B

9

2D

22D

34A

14A

62D

24B

6

2D

44C

7

2C

32C

42D

4

2D

64C

1

2B

62B

9

2B

75D

16D

4

2D

44C

2

2C

92D

96B

46B

6

2B

72B

92D

82D

96B

16B

36C

16C

36C

76C

9

2C

9

2A

22A

32A

46B

46B

66C

46C

62A

32B

62B

72B

9

2D

62D

86B

36C

3

1C

92C

62D

24D

34D

56B

36B

4

2A

62D

62D

94D

66C

76C

9

2D

22D

34B

64C

84C

96B

16B

36B

46B

76C

16C

3

2D

26B

32D

46C

1

2D

32D

44C

56B

36B

66B

9

2C

82D

32D

42D

44A

44A

64B

9

2A

62D

96A

76B

16B

36C

16C

3

4A

6

2A

62B

62B

72B

96B

16B

96C

46C

6

2B

22B

32B

46A

36A

46A

66B

16B

46B

66B

9

2A

32B

22B

42C

32C

42D

22D

32D

45E

86A

46B

16B

66C

46C

6

2A

42B

22B

32B

46B

96C

46C

6

2C

8

2C

9

4B

7

4A

6

2C

22D

22D

46C

16C

36D

16D

3

2D

43E

54A

14A

64E

16A

1

2D

96C

46C

66D

46D

62D

66A

96B

36C

16C

32D

62D

96D

6

2D

34A

14A

64E

2

2D

34C

3

2D

2

2D

2

2D

2

2D

22D

36C

46C

6

4A

44A

4

4F

32B

72B

92D

34A

64F

8

2D

3

6B

72B

9

AU

RO

RE

S2Z

AU

RO

RE

S1Z

AU

DS

YN

CZ

ER

AM

RE

SP

DZ

ER

AM

RE

S2Z

AP

3<3..0>

AP

2<15..0>

AP

1<3..0>

AU

DA

TA

<3..0>

P3<15..0>

VM

ON

OU

TZ

RX

_D

AT

AN

TO

DN

<3..0>

TO

DP

<3..0>

P2<15..0>

TX

_D

AT

AP

P20<10..0>

P19<5..0>

P18<15..0>

RX

_C

LK

P

RX

_D

AT

AP

RX

_C

LK

N

TX

_D

AT

AN

MS

YN

Z

JP0<3..0>

JP0<5>

FLM

D0

SVRDRVSS

ER

RO

RO

UT

Z

P12<5..0>

P9<8..0>

P8<10..0>

P10<14..0>

P1<15..0>

AP

0<15..0>

P20<15..12>

P2<15..0>

P11<15..0>

P6<15..2>

P5<6>

P6<0>

P5<4..2>

EV

TO

Z

P21<7..0>

CIC

RE

FN

P17<6..0>

P4<15..0>

P24<13..4>

EV

TIZ

CIC

RE

FP

RE

SE

TZ

P23<13..0>

P22<4..0>

P21<13..12>

DC

DC

_N

DC

DC

_P

NC

NC

TR

ST

Z

PW

RC

TL

X2

X1

AU

RO

RE

SP

DZ

X1_C

X2_C

P0<12..0>

AU

DR

ST

ZA

UD

CK

AP

4<15..0>

AP

5<3..0>

K24

B24

3

2

1

4

1

1

1

G24

3

P21

L25

K25

L22

P18

R18

N24

L21

F19

G20

F22

G21

P22

R22

P19

R19

M25

V22

A25

J17

R25

K22

N22M22R21

L24

A24

F8

AJ7

AK

8A

K9

K30H30

AA17

F20

F21

AA

30

G30

J30

J29

B21

A21

A20

AC24AC6AE8

N21

AA

29

1

2

1

32

ININ IN IN ININ ININ IN INB

I

IN

D S

G

S D

G

BI

BI

OU

TO

UT

IN

IN

INO

UT

OU

TB

I

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OU

T

BI

BI

ININOU

TO

UT

ININ

OE

VC

CG

ND

CLK

INBI

BI

ININININ

DVDD[3..0]

JP0[3

..0]

E2VCC

GETH0RVCCGETH0PVCC

P21[1

3..12]

P21[7

..0]

P20[1

5..12]

P20[1

0..0]

P6[1

5..2]

P5[4

..2]

AP

5[3

..0]

P23[1

3..0]

AU

DA

TA

[3..0]

TO

DN

[3..0]

TO

DP

[3..0]

A0VSS[6..0]A0VCC[2..0]A1VCC[2..0]A2VCC[2..0]

DVCC[1..0]

VDD[14..0]

P10[1

4..0]

AP

2[1

5..0]

P18[1

5..0]

AP

1[3

..0]

P2[1

5..0]

P24[1

3..4]

P8[1

0..0]

P9[8

..0]

AWOVCL[1..0]

P4[1

5..0]

VCC[2..0]

P0[1

2..0]

E0VCC[4..0]E1VCC[3..0]

P3[1

5..0]

VSS[87..0]

P11[1

5..0]

P17[6

..0]

AP

0[1

5..0]

P1[1

5..0]

P19[5

..0]

A1VSS[4..0]A2VSS[13..5]

AP

4[1

5..0]

ERAMVDD[1..0]

AP

3[3

..0]

P12[5

..0]

P22[4

..0]

SYSVCC

SVRDRVCCSVRAVCC

LVDVCC

GETH0VCL

GETH0BVCC

ERAMVCC

EMUVDDEMUVCC

A2VREFHA1VREFHA0VREFH

X2

TX

_D

AT

AP

TX

_D

AT

AN

TX

_C

LK

PT

X_C

LK

N

EV

TO

Z

ER

RO

RO

UT

Z

X1

VM

ON

OU

TZ

TR

ST

Z

RX

_D

AT

AP

RX

_D

AT

AN

RX

_C

LK

PR

X_C

LK

N

RE

SE

TZ

PW

RC

TL

MS

YN

Z

FLM

D0

EV

TIZ

ER

AM

RE

SP

DZ

ER

AM

RE

S2Z

DC

DC

_P

DC

DC

_N

CIC

RE

FP

CIC

RE

FN

AU

RO

RE

SP

DZ

AU

RO

RE

S2Z

AU

RO

RE

S1Z

AU

DS

YN

CZ

AU

DR

ST

ZA

UD

CK

SVRDRVSSSVRAVSS

P6[0

]P

5[6

]

JP0[5

]

INININ

CO

MM

EN

TR

EV

1.0

0R

ele

as

e

DR

AW

N B

YD

AT

E

Th

ese

in

tan

gib

le g

oo

ds a

re n

ot

su

bje

ct

to A

nn

ex I

of

co

mm

on

Du

al-

Use

lis

t (4

28

/20

09

) in

its

cu

rre

nt

ve

rsio

n.

Siz

eD

ocu

me

nt

Nu

mb

er

A2

Title

Da

te:

98

76

54

32

1

98

76

54

32

1

A B C D E F

A B C D E F


R20UT4371ED0100 Rev.1.00 of 64 Feb 20, 2019

11.2 Page 2

CO

NN

EC

TO

R_15

CO

NN

EC

TO

R_14

CO

NN

EC

TO

R_13

CO

NN

EC

TO

R_16

Tue J

un 2

6 1

1:4

9:2

3 2

01

8P

AG

E 2

OF

6

CR

-2 : @

RH

850_U

2X

_516P

IN_P

B_T

1_V

1_LIB

.RH

850_U

2X

_516P

IN_P

B_T

1_V

1(S

CH

_1):

PA

GE

2

3.0

0

D016345_04

rh850_u2a_516pin

_pb_t1

_v1

Ele

ctro

nic

s E

uro

pe G

mbH

3X

20X

2_54

3X

30X

2_54

GE

TH

0V

CL

3X

30X

2_54

3X

30X

2_54

3X

30X

2_54

3X

30X

2_54

3X

30X

2_54

3X

30X

2_54

3X

30X

2_54

3X

30X

2_54

3X

20X

2_54

3X

20X

2_54

AW

OV

CL

CN

16

CN

15

CN

15

CN

14

CN

13

CN

13

CN

15

CN

16

CN

16

CN

14

CN

14

CN

13

1C

76B

96C

61C

76B

16B

96C

4

1C

76B

46B

6

1B

76C

4

1B

76C

6

1C

7

1C

76C

4

4D

24D

5

4D

24D

54D

5

4D

24D

5

4D

24D

5

1B

71C

94D

34D

56B

4

1B

71C

94D

34D

56B

3

1C

76C

11C

76B

1

1C

76A

96B

36C

1

1C

76B

3

1C

76B

16B

41C

76B

36C

11C

76B

36C

31C

71C

76B

61C

36D

1

1C

76B

46B

7

1D

34C

3

1B

71B

71C

34A

64B

7

1B

34E

9

1C

74A

64C

86B

16B

7

1D

31E

3

1C

34A

14A

61C

34A

14A

61C

34A

14B

6

1C

76C

71C

76C

71C

76C

71C

76C

71C

74D

61C

74D

61C

74D

61C

74D

61C

71B

74C

11C

76C

31C

76B

31C

76B

31C

76B

36C

31C

76B

16B

3

1C

76C

11C

76A

96C

31C

76A

96B

31C

76B

36C

34D

5

1C

76B

36C

16C

71C

76C

11C

76B

11C

76B

11C

76B

11C

76B

11C

76C

11C

76C

31C

71C

76C

41C

76C

41C

76C

41C

76D

61C

76C

61C

76C

61C

76B

31C

76B

31C

76B

16C

11C

76B

31C

76B

11C

76C

31C

76B

61C

71C

71C

71C

74D

5

1B

31B

7

1C

76C

91C

76C

91C

76C

91C

74D

61C

74D

61C

74D

61C

74D

61C

76C

11C

76D

61C

76C

41C

76D

41C

76C

41C

76C

41C

76C

61C

76C

61C

76C

61C

76C

61C

76A

76C

11C

76C

31C

76C

11C

76B

11C

76B

31C

76B

41C

76B

41C

76B

61C

71C

71C

71B

31B

3

1C

76C

6

1C

76C

4

1B

31B

31B

31B

31B

31C

71C

71C

71C

31B

36B

71C

71C

71C

71C

71B

36B

71B

36B

71B

36C

71C

71C

71C

71C

71C

76B

16C

41C

76C

61C

76B

16C

61C

76C

41C

76B

91C

76A

76B

16C

31C

76A

76C

11C

76A

76C

31C

76C

9

1C

34F

31B

31B

31B

31B

31B

31C

31C

31B

31B

31C

75D

16D

41C

71C

71C

71B

31B

31C

76C

41C

71C

76B

16C

11C

76C

11C

71C

71C

71C

71C

71C

71C

71C

71C

71C

7

1B

31B

31C

34F

81B

31B

31B

31C

71C

71C

71C

31B

36B

91B

36B

91B

36B

91B

36C

91B

31B

31B

31C

76C

61C

76C

31C

76C

31C

76C

36C

91C

71C

71C

71C

71C

71C

71C

71C

71C

7

1B

71C

94D

34D

56B

31B

71C

94D

34D

56B

61B

71C

94D

34D

56B

61B

71C

94D

34D

56B

41C

76B

31B

76B

41B

76B

61B

71C

94D

34D

56B

41B

31B

34F

5

1C

71C

76B

3

1C

31C

31C

3

1B

76B

4

1B

76C

6

1C

76B

3

1D

34A

14A

64E

21C

34A

14A

61C

34A

14A

61C

74C

96B

16B

71C

74B

61C

76B

4

1C

76B

1

1C

76B

61C

36C

3

1C

3

1B

71B

74A

44A

64B

91B

71C

94D

34D

56B

41B

71C

94D

34D

56B

31B

76B

41B

76B

61B

76B

61B

76C

41B

76C

41B

71C

34C

71C

74C

56B

66B

91B

74C

21C

76B

16B

61C

73E

54A

14A

64E

16A

11C

75E

86B

16B

66C

41C

75E

86B

16C

61C

76C

11C

36C

31C

36C

11C

36C

31C

36C

11C

36C

11C

31C

31C

31C

31C

31C

31C

76C

6

1C

71C

76B

46B

61C

76C

61C

76C

41C

76A

36A

41C

76C

41C

76B

76C

6

1C

76B

41B

31C

76A

41B

31B

31B

31B

31B

31B

76B

4

1C

76C

6

1C

76A

61C

76B

11C

7

1C

76A

61C

76B

41B

76C

61C

76B

36B

96C

6

1B

76B

61B

76B

41B

76B

61B

76B

41B

76B

6

1C

76C

61C

76C

41C

76C

61C

76A

61C

71C

71C

76B

16B

91C

76B

96C

41C

76A

41C

76A

61C

76A

41C

76B

76C

41B

76C

41B

76B

61B

76B

41B

76B

61B

76B

41B

76B

61B

76B

4

1C

3

1B

76B

4

1B

76B

6

1B

76C

6

1C

76B

66B

9

1C

76B

3

1C

76B

4

1C

36D

3

1C

31C

31C

76C

4

NC

NC

P24<5>

P24<6>

P4<15>

P1<13>

P1<15>

P3<15>

P3<1>

CN

_P

2<11>

CN

_P

2<10>

CN

_P

2<9>

CN

_P

2<12>

CN

_P

2<13>

P2<7>

P2<8>

P20<0>

P20<2>

P22<0>

P20<4>

P6<5>

P6<3>

P6<2>

P6<11>

P3<5>

AP

4<6>

P6<15>

PW

RC

TL

AU

DA

TA

<2>

AU

DA

TA

<0>

EV

TIZ

AU

RO

RE

S1Z

P6<13>

X1_C

X2_C

JP0<0>

JP0<2>

JP0<5>

P11<14>

P11<12>

P11<10>

P11<8>

P11<6>

P11<4>

P11<2>

P11<0>

P21<12>

ER

RO

RO

UT

ZP

20<14>

P20<13>

P20<10>

P20<8>

P20<6>

P22<2>

P22<1>

P22<4>

P22<3>

CN

_P

2<15>

P10<8>

P10<7>

P10<6>

P10<5>

P10<4>

P10<3>

P10<2>

P10<1>

P20<15>

P23<2>

P23<4>

P23<6>

P23<8>

P23<10>

P23<12>

P20<12>

P20<9>

P20<7>

P20<5>

P20<3>

P20<1>

P8<2>

P8<4>

P8<6>

P8<8>

P8<10>

CN

_P

2<14>

AU

DS

YN

CZ

AU

DA

TA

<3>

P11<13>

P11<11>

P11<9>

P11<7>

P11<5>

P11<3>

P11<1>

P10<0>

P21<13>

P23<0>

P23<1>

P23<3>

P23<5>

P23<7>

P23<9>

P23<11>

P23<13>

P21<4>

P21<3>

P21<2>

P21<1>

P21<0>

P8<0>

P8<1>

P8<3>

P8<5>

P8<7>

P8<9>

AU

DC

KA

UD

RS

TZ

P24<11>

P3<11>

AP

0<8>

AP

0<5>

AP

0<4>

AP

0<2>

AP

0<0>

P12<0>

P12<2>

P12<4>

AP

3<0>

AP

2<0>

P9<1>

P9<3>

P9<5>

P9<7>

AP

2<2>

AP

2<4>

AP

2<6>

P9<8>

P18<0>

P18<1>

P18<2>

P17<3>

P17<4>

P17<2>

P17<5>

P17<6>

P21<7>

P21<6>

P21<5>

P11<15>

ER

AM

RE

S2Z

AP

0<6>

AP

1<0>

AP

1<2>

AP

1<3>

AP

2<12>

AP

3<1>

AP

3<3>

AP

2<15>

AP

2<14>

P9<0>

P9<2>

P9<4>

P9<6>

AP

2<8>

AP

2<10>

P17<1>

P10<14>

P10<12>

P10<10>

P18<3>

P18<4>

P18<6>

P18<8>

P18<10>

P18<12>

P18<14>

P19<5>

P19<3>

P19<1>

AP

0<14>

AP

0<15>

ER

AM

RE

SP

DZ

AP

0<3>

AP

1<1>

AP

0<1>

P12<1>

P12<3>

P12<5>

AP

3<2>

AP

2<1>

AP

2<3>

AP

2<5>

AP

2<7>

AP

2<9>

AP

2<11>

AP

2<13>

P17<0>

P10<13>

P10<11>

P10<9>

P18<5>

P18<7>

P18<9>

P18<11>

P18<13>

P18<15>

P19<4>

P19<2>

P19<0>

P2<5>

P2<3>

P2<2>

P2<0>

P5<6>

P0<3>

P0<4>

P2<1>

AU

RO

RE

SP

DZ

AU

RO

RE

S2Z

P6<9>

P6<7>

AP

4<8>

AP

4<10>

AP

4<12>

P0<5>

P0<9>

P5<4>

TR

ST

ZJP

0<1>

JP0<3>

P6<14>

P6<10>

P6<12>

P6<6>

P3<4>

AP

4<5>

AP

4<9>

AU

DA

TA

<1>

EV

TO

ZP

2<6>

P2<4>

P0<0>

P0<2>

P0<6>

P0<8>

P0<10>

P0<12>

FLM

D0

P5<3>

VM

ON

OU

TZ

P3<8>

RE

SE

TZ

P3<7>

P3<6>

P6<0>

AP

4<1>

AP

4<2>

AP

4<3>

AP

4<0>

AP

4<4>

AP

4<13>

AP

4<14>

AP

4<15>

AP

5<0>

AP

5<1>

AP

5<2>

P3<9>

P4<13>

P4<14>

P24<13>

P24<12>

P4<7>

P24<10>

P24<9>

P4<0>

AP

0<11>

P3<2>

AP

0<9>

AP

0<10>

AP

0<12>

AP

0<13>

AP

0<7>

P1<0>

P3<13>

P4<11>

P4<9>

P4<3>

P4<5>

P4<1>

P1<14>

P24<7>

P1<11>

P1<9>

P1<7>

P1<5>

P1<3>

P3<10>

P3<12>

P3<14>

P4<12>

P4<10>

P4<2>

P4<8>

P24<8>

P4<6>

P4<4>

P3<3>

P24<4>

P1<12>

P1<10>

P1<8>

P1<6>

P1<4>

P1<2>

P1<1>

MS

YN

Z

P0<1>

P0<7>

P0<11>

P5<2>

P6<8>

P6<4>

AP

4<7>

AP

4<11>

AP

5<3>

P3<0>

A30

A29

A28

A27

A26

A25

A24

A23

A22

A21

A20

A19

A18

A17

A16

A15

A14

A13

A12

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

B30

B29

B28

B27

B26

B25

B24

B23

B22

B21

B20

B19

B18

B17

B16

B15

B14

B13

B12

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

C30

C29

C28

C27

C26

C25

C24

C23

C22

C21

C20

C19

C18

C17

C16

C15

C14

C13

C12

C11

C10

C9

C8

C7

C6

C5

C4

C3

C2

C1

A30

A29

A28

A27

A26

A25

A24

A23

A22

A21

A20

A19

A18

A17

A16

A15

A14

A13

A12

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

B20

B19

B18

B17

B16

B15

B14

B13

B12

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

C20

C19

C18

C17

C16

C15

C14

C13

C12

C11

C10

C9

C8

C7

C6

C5

C4

C3

C2

C1

A30

A29

A28

A27

A26

A25

A24

A23

A22

A21

A20

A19

A18

A17

A16

A15

A14

A13

A12

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

B30

B29

B28

B27

B26

B25

B24

B23

B22

B21

B20

B19

B18

B17

B16

B15

B14

B13

B12

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

C30

C29

C28

C27

C26

C25

C24

C23

C22

C21

C20

C19

C18

C17

C16

C15

C14

C13

C12

C11

C10

C9

C8

C7

C6

C5

C4

C3

C2

C1

C30

C29

C28

C27

C26

C25

C24

C23

C22

C21

C20

C19

C18

C17

C16

C15

C14

C13

C12

C11

C10

C9

C8

C7

C6

C5

C4

C3

C2

C1

B30

B29

B28

B27

B26

B25

B24

B23

B22

B21

B20

B19

B18

B17

B16

B15

B14

B13

B12

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

A20

A19

A18

A17

A16

A15

A14

A13

A12

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

BI

A30

A29

A28

A27

A26

A25

A24

A23

A22

A21

A20

A19

A18

A17

A16

A15

A14

A13

A12

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

B20

B19

B18

B17

B16

B15

B14

B13

B12

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

BI

BI

BI

BI

BI

BI

BI

C20

C19

C18

C17

C16

C15

C14

C13

C12

C11

C10

C9

C8

C7

C6

C5

C4

C3

C2

C1

BI

BI

BI

BI

BI

BI

A30

A29

A28

A27

A26

A25

A24

A23

A22

A21

A20

A19

A18

A17

A16

A15

A14

A13

A12

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

BI

BI

BI

BI

ININININININININ

BI

INININBI

ININININININ ININININ

BI

INININININININ BI

BI

BI

BI

BI

BI

BI

ININ

OU

T

BI

BI

BI

IN

B30

B29

B28

B27

B26

B25

B24

B23

B22

B21

B20

B19

B18

B17

B16

B15

B14

B13

B12

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

IN BI

BI

BI

ININININ

BI

BI

BI

BI

BI

BI

BI

BI

OU

TININ

BI

IN BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN IN IN

INININ BI

BI

BI

BI

BI

BI

BI

IN BI

BI

BI

IN

BI

IN

INININININBI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

ININ

BI

C30

C29

C28

C27

C26

C25

C24

C23

C22

C21

C20

C19

C18

C17

C16

C15

C14

C13

C12

C11

C10

C9

C8

C7

C6

C5

C4

C3

C2

C1

BI

BI

BI

BI

ININININININININ

ININ

IN IN IN ININ

ININB

I

IN

ININ ININ

BI

IN INININ INININ INININ

BI

IN

ININ

INININ

BI

C30

C29

C28

C27

C26

C25

C24

C23

C22

C21

C20

C19

C18

C17

C16

C15

C14

C13

C12

C11

C10

C9

C8

C7

C6

C5

C4

C3

C2

C1

INININININININININININ

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

B30

B29

B28

B27

B26

B25

B24

B23

B22

B21

B20

B19

B18

B17

B16

B15

B14

B13

B12

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN BI

BI

BI

BI

BI

A30

A29

A28

A27

A26

A25

A24

A23

A22

A21

A20

A19

A18

A17

A16

A15

A14

A13

A12

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

B30

B29

B28

B27

B26

B25

B24

B23

B22

B21

B20

B19

B18

B17

B16

B15

B14

B13

B12

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

BI

BI

BI

BI

BI

BI

BI

BI

C30

C29

C28

C27

C26

C25

C24

C23

C22

C21

C20

C19

C18

C17

C16

C15

C14

C13

C12

C11

C10

C9

C8

C7

C6

C5

C4

C3

C2

C1

A20

A19

A18

A17

A16

A15

A14

A13

A12

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

Th

ese

in

tan

gib

le g

oo

ds a

re n

ot

su

bje

ct

to A

nn

ex I

of

co

mm

on

Du

al-

Use

lis

t (4

28

/20

09

) in

its

cu

rre

nt

ve

rsio

n.

Siz

eD

ocu

me

nt

Nu

mb

er

A2

Title

Da

te:

98

76

54

32

1

98

76

54

32

1

A B C D E F

A B C D E F


R20UT4371ED0100 Rev.1.00 of 64 Feb 20, 2019

11.3 Page 3

TO

BE

PR

INTE

D O

N P

CB

Min

3m

s fr

om

VC

C u

p to r

ese

tz u

p

VO

LTA

GE

RE

GU

LA

TO

R

PO

WE

R S

UP

PLY

adju

stable

set

T

O B

E P

RIN

TE

D O

N P

CB

5.0

V

3

.3V

TO

BE

PR

INTE

D O

N P

CB

GN

D

1.1

2V

Connect

or

PU

LL_D

ow

nP

ULL_U

P

PU

LL U

P P

ULL D

OW

N

T

O B

E P

RIN

TE

D O

N P

CB

VO

LTA

GE

DIS

TR

IBU

TIO

N

PU

SH

BU

TTO

N F

OR

RE

SE

T

Mon O

ct 0

1 0

7:2

7:5

8 2

01

8P

AG

E 3

OF

6

CR

-3 : @

RH

850_U

2X

_516P

IN_P

B_T

1_V

1_LIB

.RH

850_U

2X

_516P

IN_P

B_T

1_V

1(S

CH

_1):

PA

GE

3

3.0

0

D016345_04

rh850_u2a_516pin

_pb_t1

_v1

Ele

ctro

nic

s E

uro

pe G

mbH

P3V

3

VD

D

VD

D

P3V

3

P3V

3

ER

AM

VD

D

3V

35V

0

reg_vc

c_V

DD

VD

DIO

F

SV

RA

VC

C

IN_1v1

2

reg_vc

c_V

DD

SV

R_O

UT

PU

T

VD

D

P3V

3

E2V

CC

P3V

3

IN_1v1

2

P3V

3

P5V

0

0V

53

V3

P5V

0

SY

SV

CC

SY

SV

CC

A3V

3A

5V

0P

5V

0

A0V

CC

A0V

RE

FH

A1V

CC

A1V

RE

FH

A2V

CC

A2V

RE

FH

SV

RD

RV

CC

VD

Ds

P3V

3

E0V

CC

EM

UV

CC

EM

UV

DD

DV

DD

P3V

3

DV

CC

ER

AM

VC

C

GE

TH

0B

VC

C

GE

TH

0P

VC

C

E1V

CC

LV

DV

CC

GE

TH

0R

VC

C

VC

C

Std

Pow

er

Lab s

ock

et 4m

m r

ed

DO

NO

T F

IT / T

O D

ELIV

ER

WIT

H T

HE

BO

AR

D

Std

Pow

er

Lab s

ock

et 4m

m r

ed

DO

NO

T F

IT / T

O D

ELIV

ER

WIT

H T

HE

BO

AR

D

Std

Pow

er

Lab s

ock

et 4m

m r

ed

DO

NO

T F

IT / T

O D

ELIV

ER

WIT

H T

HE

BO

AR

D

DO

NO

T F

IT / T

O D

ELIV

ER

WIT

H T

HE

BO

AR

D

Std

Pow

er

Lab s

ock

et 4m

m b

lack

10K

56K

470p

133K

15n

22u

22u

10K

22u

22u

1K6

1u

1u

1u

1u

1u

1u

1u

1K

0

1K

01K

0

1K

0

1K

01K

0

1K

01K

0

1K

0

header

20w

ay

1K

01K

01K

0

1K

01K

0

1K

0

1K

01K

01K

01K

01K

0

NX

P_B

C847C

10K

10K

10K

NX

P_B

C847C1

00n

BT

1H

-2M

4-Z

10K

TLC

7701ID

10K

SN

74LV

1T

125D

CK

R

2K2

1u

1u

1S

MA

5914B

T3G

_3.6

V 100U

100U

100U

10K

56K

NX

P_B

C847C

1S

MA

5919B

T3G

_5.6

V

220n

115K

750

750

750

1.1

2V

3.3

V o

r 5V

3.3

V o

r 5V

3.3

V o

r 5V

3.3

V o

r 5V

3.3

V

3.3

V o

r 5V

3.3

V

3.3

V

3.3

V

3.3

V o

r 5V

BS

S84

ISL8202M

3.3

V

1.1

2V

1.1

2V

1.1

2V

3.3

V

3.3

V

3.3

V

1.1

2V

3.3

V o

r 5V

5.0

V

3.3

or

5V

3v3

or

5V

3.3

or

5V

3.3

V

3v3

or

5V

3.3

or

5V

3v3

or

5V

5.0

V5.0

V3.3

V

5.0

V3.3

V

3.3

V o

r 5V

5.0

V

5.0

V

1.1

2V

1.1

2V

3.3

V o

r 5V

3.3

V

1.1

2V

gre

en

gre

en

3.3

V

1.0

9V

3.3

V o

r 5V

gre

en

1.1

2V

10

3.3

V o

r 5V

red3.3

V

3.3

V

3.3

V

CN

10 C

N11

CN

9

CN

8

R50

R49

JP22

C156

R54

C155

C91

C93

R46

C89

C88

R44

JP24

JP28

JP29

JP21

JP19

JP20

JP18

JP17

C94

JP37

JP36

JP35

JP34

C109

C108

C107

C106

JP33

JP32

JP31

JP30

C105

C104

JP15

JP25

R69

R67

R68

R66

R64

R65

R62

R63

R61

CN

12

R79

R78

R77

R75

R74

R76

R73

R72

R71

R60

R70

TR

7R

53

R51

R52

TR

8

C92

SW

1

R10

IC8

R56

IC9

R57

JP14

JP13

JP12

JP11

JP10

JP9

JP8

C96

JP7

JP6

JP5

JP4

C95

D4

C85

C87

C86

R41

R42

TR

6

D3

JP23

JP16

C81

R55

R45

R59

R43

LE

D12

LE

D11

LE

D10

LE

D13

IC16

TR

9

3E

3

6A

14E

1

4A

64A

12D

41C

73F

4

RE

SE

T_IN

RE

SE

TZ

NC

RE

G_F

B<0..1>

RE

SE

T_IN

1 2

1 2

1 2

21

321

21

21

21

21

21

21

21

21

321321321321321321

21

21

321321

20

19

18

17

16

15

14

13

12

11

10

98

76

54

32

1

23

1

23

1

32

1

8

7256

4

315 4

1 32

321321321321321321321321321

21

21

23

1

321

321

18

15

20

16

12

22

17

13

11

6

3

1

2

20

18

16

14

12

108642

19

17

15

13

11

97531

321

D

S

G

VS

EN

SE

[1..0]

PG

ND

[1..0]

SW

[1..0]

FB

[1..0]

NC[3..0]

VO

UT

VIN

SY

NC

SS

SG

ND

PG

FS

EP

AD

EN

CO

MP

21

21

321

21

21

21

B

EC

321

21

321

32132132132132132121

21

21

21

32132132132132132132132132121

21

OU

T

OE

ZV

CC Y

GN

D

A

RE

SE

T_Z

*R

ES

ET

GNDVCC

SE

NS

ER

ES

IN*

CT

CO

NT

RO

L

OU

T

B

EC

B

EC

IN

321

Th

ese

in

tan

gib

le g

oo

ds a

re n

ot

su

bje

ct

to A

nn

ex I

of

co

mm

on

Du

al-

Use

lis

t (4

28

/20

09

) in

its

cu

rre

nt

ve

rsio

n.

Siz

eD

ocu

me

nt

Nu

mb

er

A2

Title

Da

te:

98

76

54

32

1

98

76

54

32

1

A B C D E F

A B C D E F


R20UT4371ED0100 Rev.1.00 of 64 Feb 20, 2019

11.4 Page 4

RX

DN

RE

SE

TO

UT

Z

Sig

nalli

ng L

ED

s

pla

ce S

ilksc

reen:

Auro

ra I/F

MO

DE

0 J

um

per

RH

SIF

TX

DN

RX

DN

RX

DP

TX

DP

RX

DP

TX

DN

TX

DP

MS

PI0

_S

CK

N

FLM

D2

pla

ce S

ilksc

reen:

FLM

D2 J

um

per

FLM

D2

FLM

D1

pla

ce S

ilksc

reen:

FLM

D1

MO

DE

0

MO

DE

0

TM

S

WD

TD

IS

ET

K-B

GN

T

FLM

D1

TM

S

TD

O/L

PD

O

EV

TIZ

pla

ce S

ilksc

reen:

EV

TO

Zpla

ce S

ilksc

reen:

RD

YZ

/LP

DC

LK

O

FLM

D0 C

ircu

it

EV

TI Ju

mper

EV

TO

Jum

per

Sig

nalli

ng for V

MO

NO

UT

FLM

D1 J

um

per

TD

I/LP

DI

TC

K/L

PD

CLK

Only

fit

if th

e s

ignal i

s to

go to the co

nnect

or

DE

BU

G A

ND

PR

OG

RA

MM

ING

IN

TE

RFA

CE

TD

CK

/LP

DC

LK

/FP

CK

TD

O/L

PD

O/F

PD

TT

DI/LP

DIO

/FP

DR

RD

Y/L

PD

CLK

OU

T

Sig

nalli

ng for E

RR

OR

OU

T

MS

PI0

_S

CK

P

HS

IF0_R

EF

CLK

FLM

D0

ET

K-B

RE

Q

Sig

nalli

ng for P

WR

CTL

RH

SIF

& M

SP

I I/F

pla

ce S

ilksc

reen:

Thu O

ct 0

4 1

5:1

0:4

6 2

01

8P

AG

E 4

OF

6

CR

-4 : @

RH

850_U

2X

_516P

IN_P

B_T

1_V

1_LIB

.RH

850_U

2X

_516P

IN_P

B_T

1_V

1(S

CH

_1):

PA

GE

4

3.0

0

D016345_04

rh850_u2a_516pin

_pb_t1

_v1

Ele

ctro

nic

s E

uro

pe G

mbH

SN

74LV

1T

32D

CK

R

SN

74LV

1T

08

BA

T54C

LT

1G

SN

74LV

1T

126D

CK

R

yello

w

SN

74LV

1T

126D

CK

R

3.3

V

SN

74LV

1T

126D

CK

R

3v3

or

5V

3v3

or

5V

3.3

V o

r 5V

1.1

2V

3.3

V o

r 5V

3.3

V o

r 5V

3.3

V o

r 5V

3.3

V o

r 5V

10

11

12

13

3.3

V o

r 5V

3.3

V

BS

S84

red

3.3

V

BS

S84

red

3.3

V

SN

74LV

1T

126D

CK

R

10K

15

14 9

15

14 9

3 2 1 0

13

12

11

10

11

13

12

10

10

13

12

3.3

V

3 2 1 0

1k8

2ye

llow

1k8

2

1k8

2

1k8

2

yello

w

yello

w

1k8

2

1k8

2

1k8

2

yello

w

yello

w

21 3 4 5 76

3.3

V

0

3v3

or

5V

3.3

V

3.3

V

AS

P-1

37973-0

1

100K

yello

w

1k8

2

yello

w

3.3

V

3.3

V3.3

V

3.3

VS

N74LV

1T

08

CB

TL02043A

1.1

2V

BS

S84

red

11

3v3

or

5V

3v3

or

5V

100n

100n

100n

100n

56K

10K

68K

750

1K0

1K0

750

1K0

1K0

1K0

1K0

750

100n

100n

100n

100n

100n

100n

100n

100n

100n

100n

0

10K

HE

AD

ER

14W

AY

SH

RO

UD

ED

10K

10K

10K

10K

10K

100n

10K

10K

DN

F/D

NB 0

DN

F/D

NB 0

DN

F/D

NB 0

100n

ER

F8-0

05-0

5.0

-L-D

V-L

-TR

0D

NF

/DN

B

0D

NF

/DN

BD

NF

/DN

B0 0

DN

F/D

NB

100n

100n

220p

header

16w

ay

TLC

7701ID

10K

100n

150p

NX

P_B

C847C

10K

10K

NX

P_B

C847C

220p

68K

TLC

7701ID

150p

NX

P_B

C847C

10K

10K

100n

10K

NX

P_B

C847C

56K

100n

E0V

CC

P3V

3

EM

UV

DD

E0V

CC

EM

UV

CC

P3V

3

P3V

3

P3V

3

ER

AM

VC

C

EM

UV

CC

E0V

CC

3V

3

SY

SV

CC

P3V

3P

3V

3P

3V

3E

0V

CC

E0V

CC

E0V

CC

E0V

CC

E0V

CC

E0V

CC

E1V

CC

EM

UV

CC

ER

AM

VD

D10K

10K

R145

IC4

IC18

IC19

LE

D7

LE

D6

LE

D5

IC10

LE

D15

TR

11

R19

IC17

LE

D14

TR

3

LE

D9

R32

R31

R30

LE

D4

R28

LE

D3

R27

LE

D2

R26

IC3

LE

D1

CN

6

R144

D1

IC11

R29

LE

D8

R33

IC6

TR

10

C111

C57

C58

C100

R36

R37

R34

R48

R130

R122

R119

R120

R123

R25

R24

R13

JP3

JP2

C76

C77

C69

C68

C71

C70

C73

C72

C74

C75

R11

R14

CN

4

R8

R9

R47

R12

JP38

R121

C83

JP41

JP39

R5

JP40

R124

R21

R22

R23

C67

CN

5

R15

R16

R17

R18

C66

JP1

C110

C79

JP42

CN

7

IC5

R39

C84

C82

TR

5R

40

R38

TR

4

C80

R35

IC2

C52

TR

15

R135

R133

C54

R134

C99

R131TR

14

R132

2B

91C

3

1C

3

1C

72D

24C

86B

16B

71C

72D

43E

54A

16A

1

1C

7

2C

84D

5

1B

72D

44A

44A

6

1C

32D

34A

6

1C

7

1C

32D

24A

11C

32D

34A

11C

32D

24A

11C

32D

34A

11D

32D

34A

14E

24C

61C

32D

34B

71B

72D

44B

9

1C

32D

24A

1

1D

7

1D

7

1D

7

1D

71D

74A

64C

6

1B

72D

44A

64B

91C

32D

34A

61C

32D

24A

6

1C

32D

24A

6

1C

32D

34A

6

2D

24B

61C

72D

43E

54A

64E

16A

1

1B

72D

61D

32D

31B

72D

4

1C

72D

46B

66B

9

1C

34A

44A

61C

72D

24A

66B

16B

7

1C

72D

36B

16B

7

1D

32D

34A

64E

2

1D

7

1D

7

4E

24E

84F

7

2C

62C

82D

62D

84D

2 2D

44D

36B

36B

6

2D

6

1C

72D

3

4E

24E

8

4F

1

1B

32D

2

1C

72D

43E

54A

14A

66A

1

2D

9

2D

4

4E

1

4A

4

4A

4

2B

7

4F

14E

84F

7

1C

7

1C

3

6B

41B

72D

22C

61C

9

4F

7

4F

14E

2

2D

34A

14A

61D

3

1D

7

2D

6

AU

RO

RE

SP

DZ

ER

AM

RE

SP

DZ

JP0<3>

ER

AM

RE

S2Z

RE

SE

TZ_E

VA

CIC

RE

FP

CN

_P

2<13..10>

CO

N<3..0>

EV

TO

Z

EV

TIZ

CIC

RE

FN

TO

DN

<0>

TO

DP

<0>

TO

DN

<1>

TO

DP

<2>

FLM

D0_T

OO

LN

C

EV

TO

ZJP

0<0>

JP0<2>

JP0<1>

JP0<5>

RE

SE

TZ

ER

RO

RO

UT

ZP

WR

CT

LV

MO

NO

UT

Z

P5<3>

FLM

D0

FLM

D0_T

OO

LP

6<13>

P6<14>

TR

ST

Z

TO

DP

<1>

TO

DN

<2>

RE

SE

TZ

_E

VA

CN

_P

2<15..0>

P2<15..0>

RE

SE

TZ

_E

VA

AU

RO

RE

S2Z

RE

SE

TZ

NC

NC

JP0<2>

JP0<3>

JP0<1>

TR

ST

ZF

LM

D0_T

OO

LE

VT

IZE

VT

OZ

P6<13>

RE

SE

TZ

JP0<5>

P6<10>

JP0<0>

CO

N<3..0>

OE

_IC

11

TR

ST

Z

P11<7..0>

P2<15..0>

NC

NC

TO

DN

<3>

TO

DP

<3>

RE

SE

TZ

_E

VA

TR

ST

ZA

UR

OR

ES

1Z

5 4321

15 4

32

32 1

2

5

4

5 3

214

1 32

2

1

3

451 32

2

1

3

2

1

3

2 9

21

13

12

14

17

19

18

7 83 4

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

98

76

54

32

1

45

321

1

35

16

15

4

12

12

21 3

45

67

89

10

11

12

13

14

1 2 3

12

12

1 2 3

12

34

56

78

910

11

12

123

12

12

34

56

78

910

11

12

13

14

15

16

1

4

52 7

8

63

1

3 2

1

3 2

8

7256

4

31

23

1

23

1

IN

VC

C YG

ND

BA

IN

OU

T

OE

VC

C YG

ND

A

OU

T

IN

OU

T

VCC

YBA

GND

RE

SE

T_Z

*R

ES

ET

GNDVCC

SE

NS

ER

ES

IN*

CT

CO

NT

RO

L

IN

VCC

YBA

GND

IN

RE

SE

T_Z

*R

ES

ET

GNDVCC

SE

NS

ER

ES

IN*

CT

CO

NT

RO

L

B

EC

B

EC

B

EC

B

EC

OU

T

OE

VC

C YG

ND

A

BI

OU

T

OU

T

OE

VC

C YG

ND

AIN

21

IN

BI

OU

T

IN

D

S

G

OU

T

OE

VC

C YG

ND

A

2 1

INO

UT

OU

T

IN

D

S

G

D

S

G

321

321

2 1

BI

31

41

11

21

90

18

76

54

32

1

INO

UT

2 1

BI

BI

BI

BI

BI

BI

2 1

IN

BI

OU

T

OU

TO

UT

OU

T

IN

OU

TIN

OU

TIN O

UT

BI

BI

3 2 1

BI

B0_N

B1_N

C0_N

C1_N

A1_N

A0_N

EX

P_G

ND

GND[3..1]VDD[3..1]

XS

D

SE

LC

1_P

C0_P

B1_P

B0_P

A1_P

A0_P

OU

TO

UT

OU

T

OU

TIN

OU

T

OU

TO

UT

BI

GND[1..0]

34

32

30

28

26

24

22

20

18

16

14

12

108642

33

31

29

27

25

23

21

19

17

15

13

11

97531B

I

BI

BI

12

108642

11

97531

51

61

31

41

11

21

90

18

76

54

32

1

Th

ese

in

tan

gib

le g

oo

ds a

re n

ot

su

bje

ct

to A

nn

ex I

of

co

mm

on

Du

al-

Use

lis

t (4

28

/20

09

) in

its

cu

rre

nt

ve

rsio

n.

Siz

eD

ocu

me

nt

Nu

mb

er

A2

Title

Da

te:

98

76

54

32

1

98

76

54

32

1

A B C D E F

A B C D E F


R20UT4371ED0100 Rev.1.00 of 64 Feb 20, 2019

11.5 Page 5

G-P

hy

350m

A

Pdis

= 0

.8W

340m

A

Pdis

= 0

.3W

Thu O

ct 1

8 1

2:3

3:1

1 2

01

8P

AG

E 5

OF

6

CR

-5 : @

RH

850_U

2X

_516P

IN_P

B_T

1_V

1_LIB

.RH

850_U

2X

_516P

IN_P

B_T

1_V

1(S

CH

_1):

PA

GE

5

3.0

0

D016345_04

rh850_u2a_516pin

_pb_t1

_v1

Ele

ctro

nic

s E

uro

pe G

mbH

4K

7D

NF

/DN

B

DNF/DNBDNF/DNB4K74K7

DNF/DNB 4K7

49.9

0

0000

00

0

0

23

1.2

V

4

1

2.5

VCB

TL02043A

3.3

V

10K

2.5

V

1.2

V

100K

1k40 1K0

ISL78310A

RA

JZ3.3

V

100K

2.5

V 1K2

10K

300

ISL78310A

RA

JZ3.3

V

10K

0

4K7

4K7

J0G

-0001N

L

2.5

V

0 000

0 0

49.949.90

3.3

V

1k821k82

2.5

V

100

100

100

49.90

49.949.90

49.949.9

MA

X14591

1k821k82

2.5

V

1K

0

4k9

9

5

88E

1112-X

X-N

NC

-I000

10n

10n

10n

10n

10n

10n

100n100n

100n100n

100n

22p

22p

SM

D-T

est

poin

tS

MD

-Test

poin

tS

MD

-Test

poin

t

100n

100n

100n

25.0

00 M

Hz

100n100n

100n100n100n

100n

100n

10u

10u

22p

DN

F/D

NB

10u

DN

F/D

NB

22p

10u

470p

100n

100n

100n

100n

100n

100n

100n

100n

100n

100n

GE

TH

0P

HY

VA

NP

3V

3

gro

und_P

OW

ER

_E

TH

GE

TH

0P

HY

VA

N

3V

3G

ET

H0P

HY

VAN

3V

3G

ET

H0P

HY

VC

C

GE

TH

0P

HY

VA

N

3V

3

GE

TH

0P

HY

VA

N

GE

TH

0P

HY

VA

N

GE

TH

0P

HY

VC

C

R107

R126R125

R114

R127

R128

R129

R137

R141

R140

R139

R138

R20

IC7

R136

R113R112R111R110

R105 R106R104R103

R102

R108

R118R117

R116R115

R91

IC15

R99R98

R97R96

R95R94

R93R92

R101

R100

R90

R89

R88

CN

17

R84

IC13

R86R85

R87

R82R81

R80

R83

IC12

IC14

C128

C127

C126

C125

C124

C123

C141C140

C139C138

C137

C153

C154

TP

1T

P2

TP

3

C136

C132

C131

X2

C121C122

C120C119C118

C90

C129

JP26

C117

C114

C116

C115

C113

C112

C148

C149

C150

C151

C152

C146

C145

C143

C142

C147

C144

1C

31C

3

1C

31C

31C

31C

3

6D

42B

71C

7

6C

46B

66B

12D

41C

76C

66B

12D

41C

7

CLK

NR

X_C

LK

N

OU

TN

S_O

UT

NO

UT

PS

_O

UT

P

CLK

PR

X_C

LK

P

INN

S_IN

NIN

PS

_IN

P

NC

NC

GE

TH

0_P

HY

_M

DC

ET

H0P

HY

CO

NF

<5..0>

GE

TH

0_P

HY

_M

DI_

0_P

GE

TH

0_P

HY

_M

DI_

3_N

GE

TH

0_P

HY

_M

DIO

GE

TH

0_P

HY

_M

DI_

1_N

NC

NCN

C

NC

NC

NC

TX

_D

AT

AP

TX

_D

AT

AN

RX

_D

AT

AP

RX

_D

AT

AN

NC

RE

SE

T_M

AR

VE

L

NC

NC

P9<0>

GE

TH

0_P

HY

_M

DI_

0_N

GE

TH

0_P

HY

_M

DI_

1_P

GE

TH

0_P

HY

_M

DI_

2_N

GE

TH

0_P

HY

_M

DI_

2_P

GE

TH

0_P

HY

_M

DI_

3_P

P3<7>

P3<6>

SIG

DE

T

2 9

21

13

12

15

14

17

16

19

18

7 83 4

18

42 37 6 5

14

1358 9 3 2 4

11

107 1 6

12

15

17

1918

16

21109 6

3 4

8

5

11

7

21109 6

3 4

8

5

11

7

35

36

34

38

40

60

53

54

3

2 19 8 5 4

17

52

50

51

49

30

27

21

18

58

31

28

22

19

57

59

61

25

26

12

11

10

16

15

65

1 1 1

123

4

1 2

L/S

1.6

5V

..

5.5

V0

.9V

..

5.5

V

GN

DIO

VC

C[1

]IO

VC

C[2

]V

CC

TS

#IO

VL[1

]IO

VL[2

]V

L

TR

P2_M

INU

S

TR

D2_P

LU

S

TR

D3_P

LU

S

TR

D3_M

INU

ST

RC

T3

GND[2]GND[1]

GR

N_M

INU

SC

OM

_P

LU

SO

RN

_M

INU

SY

EL_P

LU

SY

EL_M

INU

S

TR

CT

1T

RD

1_P

LU

S

TR

D1_M

INU

S

TR

D4_M

INU

S

TR

D4_P

LU

ST

RC

T4

TR

CT

2

OU

TO

UT

ININ

VO

UT

[1]

VO

UT

[0]

VIN

[1]

VIN

[0]

EPAD

EN

AB

LE

SS

GND

SE

NS

E/A

DJ

NC

PG

VO

UT

[1]

VO

UT

[0]

VIN

[1]

VIN

[0]

EPAD

EN

AB

LE

SS

GND

SE

NS

E/A

DJ

NC

PG

21

B0_N

B1_N

C0_N

C1_N

A1_N

A0_N

EX

P_G

NDGND[3..1]VDD[3..1]

XS

D

SE

LC

1_P

C0_P

B1_P

B0_P

A1_P

A0_P

OU

TO

UT

IN

BI

IN

3.3

V D

igIO

& T

ran

sc.

1.2

V C

ore

&P

ll

ST

AT

US

[1]

ST

AT

US

[0]

MD

IN[3

]

MD

IN[2

]

MD

IN[1

]

MD

IN[0

]

MD

IP[3

]

MD

IP[2

]

MD

IP[1

]

MD

IP[0

]

VDDO[1..0]

CO

NF

IG[5

..0]

VDDAH[1..0]

VSS[1..0]

DVDD[4..0]

VDDA[4..0]

VDDAL[1..0]

EP

AD

S_VTTF_VTT

RS

ET

TS

TP

TH

SD

AC

NH

SD

AC

P

NO

RM

AL

PW

RD

N

PO

L_R

ST

RE

SE

T

XT

AL2

XT

AL1

INIT

/IN

T

SD

AS

CL

MD

IO/S

SD

AM

DC

/SS

CL

LO

S

S_O

UT

NS

_O

UT

P

S_C

LK

NS

_C

LK

P

S_IN

NS

_IN

P

F_O

UT

NF

_O

UT

P

SIG

DE

T

F_IN

NF

_IN

P

Th

ese

in

tan

gib

le g

oo

ds a

re n

ot

su

bje

ct

to A

nn

ex I

of

co

mm

on

Du

al-

Use

lis

t (4

28

/20

09

) in

its

cu

rre

nt

ve

rsio

n.

Siz

eD

ocu

me

nt

Nu

mb

er

A2

Title

Da

te:

98

76

54

32

1

98

76

54

32

1

A B C D E F

A B C D E F


R20UT4371ED0100 Rev.1.00 of 64 Feb 20, 2019

11.6 Page 6

PS

I5S

TX

0

SE

NT

0S

PC

OP

SI5

SR

X0

ET

H0T

XD

3E

TH

0T

XD

2E

TH

0T

XD

1E

TH

0T

XD

0

PS

I5T

X0

FLX

ST

PW

TF

LX

1E

N

ET

H0M

DC

PS

I5S

CLK

0

ET

H0R

XC

LK

ETH

0LIN

K

UA

RT

1R

XLIN

1T

X

FLX

CLK

ET

H0R

XD

0E

TH

0R

XD

1

CO

NN

EC

TO

R1

SE

NT

0R

X

CA

N0T

X

RE

SE

T

VD

DA

RU

BB

ER

FE

ET

TO

P

FU

DU

CIA

LS

BO

TTO

M

GN

D T

ES

T P

OIN

T

ET

H1R

ES

ET

--E

TH

1LIN

K

ET

H1R

XE

RE

TH

1R

XC

LK

ET

H1R

XD

1E

TH

1R

XD

0E

TH

1M

DIO

- ET

H1R

XD

V

ET

H1R

XD

3E

TH

1R

XD

2

ET

H1C

RS

DV

MM

CA

0D

AT

6

SF

MA

0C

LK

SF

MA

0IO

0

MM

CA

0D

AT

4M

MC

A0D

AT2

MM

CA

0D

AT

0M

MC

A0C

LK

SF

MA

0IO

2--LIN

22R

XLIN

22T

X

LIN

20TX

LIN

18R

XLIN

18T

XLIN

16R

XLIN

16T

X

CA

N10R

X- LIN

20R

X

CA

N14R

XC

AN

14T

XC

AN

12R

X

CA

N10T

X

CA

N6T

X

CA

N8R

XC

AN

8T

XC

AN

6R

X

- CA

N12TX

LIN

12R

XLIN

12T

XLIN

10R

XLIN

10T

X

LIN

6T

XLIN

6R

XLIN

8T

XLIN

8R

X

LIN

14R

XLIN

14T

X

LIN

4R

X

CA

N2T

XC

AN

2R

XC

AN

4T

XC

AN

4R

XLIN

2T

XLIN

2R

XLIN

4T

X

CO

NN

EC

TO

R2

- ET

H1T

XE

NE

TH

1T

XE

R

ET

H1T

XD

2

ET

H1T

XD

0E

TH

1M

DC

ET

H1C

OL

ET

H1T

XD

1

ET

H1T

XD

3E

TH

1T

XC

LK

MM

CA

0D

AT

7

-- MM

CA

0C

MD

MM

CA

0D

AT

1

MM

CA

0D

AT

5M

MC

A0D

AT3

SF

MA

0IO

3S

FM

A0IO

1S

FM

A0S

SL

LIN

23R

X

- LIN

21R

XLIN

21TX

LIN

19R

XLIN

19T

XLIN

17R

XLIN

17T

X

CA

N11R

X

LIN

23T

X

- CA

N9R

XC

AN

9T

XC

AN

7R

X

CA

N15T

xC

AN

13R

x

CA

N11T

X

CA

N13Tx

CA

N7T

XC

AN

15R

x

LIN

11T

XLIN

9R

XLIN

9T

XLIN

7R

XLIN

7T

X

LIN

15R

X

LIN

11R

XLIN

13T

XLIN

13R

XLIN

15T

X

LIN

5R

X

LIN

3T

XLIN

3R

X

CA

N5R

XC

AN

5T

XC

AN

3R

XC

AN

3T

X

LIN

5T

X

--

------ - - - ---- ---- - -EN

C0

DIG

IO22

DIG

IO20

PW

M6

PW

M4

PW

M2

PW

M0

AD

1_6

AD

1_4

DIG

IO16

DIG

IO18

------ -

-------- - ---------EN

C1

-DIG

IO23

DIG

IO17

PW

M7

PW

M3

PW

M1

AD

1_5

DIG

IO21

DIG

IO19

AD

1_3

AD

1_1

--------

-- --- -- -CS

I1C

S2

CS

I1S

CLK

PS

I5S

CLK

1

-- PS

I5S

TX

1P

SI5

SR

X1

CS

I0C

S3

CS

I0C

S2

CS

I0C

S1

CS

I0C

S0CO

NN

EC

TO

R3 ---C

SI1

SI

CS

I1S

OD

IGIO

_24

CS

I1C

S0

- -CS

I1C

S3

-PS

I5T

X1

PS

I5R

X1

-CS

I1C

S1

-CS

I0S

OC

SI0

SI

CS

I0C

LK

ET

H0R

XE

R

AD

C4

AD

C2

DIG

IO_5

DIG

IO_1

-US

B0U

DP

HU

SB

0U

DM

H

ET

H0T

XE

RE

TH

0C

RS

DV

ETH

0R

ES

ET

FLX

0E

N

PS

I5R

X0

SE

NT

1S

PC

O

IIC

1S

DL

UA

RT

1T

X

ET

H0M

DIO

DIG

IO_15

DIG

IO_13

VD

DB

SE

NT

1R

X

LIN

1R

X

CA

N1T

XIIC

1S

DA

CA

N1R

X

VD

DB

VD

DB

VD

DIO

FA

DC

7A

DC

5A

DC

3A

DC

1-M

UX

1-D

IGIO

_11

DIG

IO_9

DIG

IO_7

DIG

IO_3

----ET

H0C

OL

ET

H0T

XE

N

---INT

3IN

T1

-NM

IV

DD

AV

DD

A

ET

H0R

XD

2

DIG

IO_6

DIG

IO_4

DIG

IO_2

VD

DB

- MU

X0

MU

X2

AD

C0

AD

C6

DIG

IO_12

DIG

IO_14

VD

DIO

F

DIG

IO_10

- - - - DIG

IO_0

DIG

IO_8

US

B0U

DP

F

- US

B0U

DM

F

ET

H0R

XD

3

-FLX

1R

X

CA

N0R

X

VD

DA

WA

KE

INT

0

- ET

H0R

XD

V

ET

H0T

XC

LK

IIC

0S

DA

IIC

0S

DL

LIN

0R

X

INT

2

FLX

1T

XF

LX

0R

XF

LX

0T

X

LIN

0T

XU

AR

T0R

XU

AR

T0T

X

AD

1_7

AD

1_2

AD

1_0

PW

M5

-

CO

NN

EC

T T

O M

AIN

BO

AR

D

Mon O

ct 0

1 0

7:2

8:0

3 2

01

8P

AG

E 6

OF

6

CR

-6 : @

RH

850_U

2X

_516P

IN_P

B_T

1_V

1_LIB

.RH

850_U

2X

_516P

IN_P

B_T

1_V

1(S

CH

_1):

PA

GE

6

3.0

0

D016345_04

rh850_u2a_516pin

_pb_t1

_v1

Ele

ctro

nic

s E

uro

pe G

mbH

VD

DIO

F

P5V

0P

5V

0

P3V

3P

3V

3V

DD

IOF

BLA

CK

BLA

CK

BLA

CK

BLA

CK

BLA

CK

BLA

CK

FID

UC

IAL_1M

M

FID

UC

IAL_1M

M

FID

UC

IAL_1M

M

FID

UC

IAL_1M

M

GN

D-T

ES

TP

OIN

T

GN

D-T

ES

TP

OIN

T

GN

D-T

ES

TP

OIN

T

GN

D-T

ES

TP

OIN

T

QT

H-0

60-0

1-F

-D-A

QS

H-0

60-0

1-F

-D-A

QS

H-0

60-0

1-F

-D-A

3.3

V o

r 5V

3.3

V

5.0

V5.0

V

3.3

V o

r 5V

3.3

V

MP

5

MP

3

MP

6

MP

4

MP

1M

P2

TP

15

TP

14

TP

12

TP

11

TP

7

TP

8

TP

6

TP

5

CN

2C

N3

CN

1

1C

72B

75D

11C

72D

9

1C

72D

91C

72D

81C

72D

81C

72D

91C

72D

81C

72D

91C

72D

45E

86B

16B

6

1C

72B

31C

72B

31C

72B

26B

91C

72B

36B

16B

91C

72B

26B

7

1C

72B

71C

72B

66B

11C

72A

6

1C

72B

41C

72B

21C

72C

31C

72B

41B

72A

21B

72A

41B

72D

41B

72D

4

1B

72A

41B

72A

21B

72A

21B

72A

31C

72B

36B

61C

72B

36B

61C

72D

91C

72D

91B

72A

41B

72A

2

1B

72D

21B

72D

31B

72D

41B

72D

31C

72D

31C

72D

26B

11C

72B

41C

72B

31B

71C

92D

44D

34D

51B

71C

92C

64D

34D

51C

72D

26B

71C

72D

31B

71C

92D

24D

34D

51B

71C

92D

24D

34D

51C

72B

36A

31C

72B

21C

72B

21C

72A

3

1B

71C

92D

24D

34D

51B

71C

92D

44D

34D

51C

72D

66A

91C

72D

66C

31C

72D

31C

72D

2

1C

72A

66A

71C

72A

66A

76B

1

1C

32D

21C

32D

41C

32D

41C

32D

41C

72D

26B

31C

72D

4

1C

72B

76B

11C

72B

71C

72D

86B

36C

71C

72D

61C

72D

66A

96B

31C

72A

66A

71C

72D

96A

71C

72D

9

1C

72D

61C

72D

81C

72D

86B

11C

72D

91C

72D

8

1C

72D

81C

72D

8

1C

72D

81C

72D

8

1C

72D

86B

1

1C

72B

26B

9

1C

72D

86B

11C

72D

66B

31C

72D

61C

72D

86C

11C

72D

46B

61C

72D

45E

86B

66C

4

1C

72D

45E

86C

61C

72B

36B

96C

41C

72D

91C

72D

24A

64C

86B

7

1C

72D

34C

96B

71C

72A

66C

61C

72B

66C

41C

72B

4

1C

72D

26B

41C

72D

3

1C

72A

66A

76C

31C

72B

76C

1

1C

72D

43E

54A

14A

64E

1

1C

72B

96C

31C

72D

86B

36C

1

1C

72D

9

1C

72A

61C

72D

9

1C

72D

9

1C

72D

61C

72D

61C

72D

61C

72D

6

1C

72A

66B

16C

3

1C

72A

66C

31C

72D

96C

1

1B

32B

6

1C

72B

2

1C

72D

9

1C

72D

81C

72D

91C

72D

91C

72D

91C

72D

81C

72D

91C

72D

81C

72D

45E

86B

1

1C

72B

31C

72B

41C

72B

36B

71C

72A

46B

36B

91C

72B

36B

9

1C

72B

91C

72A

66B

11C

72B

6

1C

72B

41C

72B

21C

72C

41C

72B

21B

72B

41B

72B

41B

72D

31B

72D

3

1B

72A

41B

72A

21B

72A

41B

72A

21C

72D

26B

61C

72D

36B

61C

72D

91C

72D

81B

72A

41B

72A

2

1B

72D

41B

72D

31B

72D

41B

72D

21C

72D

45E

86B

16C

41C

72D

46B

11C

72D

36B

91C

72D

44C

56B

91C

72D

36B

61C

72D

26B

61B

71C

92D

24D

34D

51B

71C

92D

24D

34D

51C

72B

36B

41C

72B

36B

41C

72B

21C

72B

41C

72B

4

1B

32B

6

1B

32B

61B

32B

61C

72D

26B

4

1C

72B

26C

4

1C

72B

36C

6

1C

72D

24A

64C

86B

11C

72D

34C

96B

1

1C

72A

66C

1

1B

32B

9

1B

32B

91B

32B

91B

32B

9

1C

72B

36C

61C

72B

36B

16C

41C

72A

61C

72A

46B

36C

61C

72B

26B

1

1C

72D

44C

56B

61C

72D

36B

6

1C

72B

26C

4

1C

72D

66B

36C

11C

72D

66C

31C

72D

66B

3

1B

71C

92C

64D

34D

5

1C

72A

46B

96C

6

1C

72D

8

1C

72D

26B

3

1C

72B

36A

4

1C

72D

66A

96C

1

1C

72D

31C

72D

2

1C

72D

81C

72D

6

1C

72D

61C

72D

81C

72D

6

1C

72D

81C

72D

66B

31C

72D

6

1C

72D

66A

91C

72D

66B

31C

72B

96C

91C

72B

91C

72B

9

1C

32D

41C

32D

41C

32D

31C

32D

3

1C

72D

26C

11C

72D

26C

3

1C

72D

9

1C

72D

9

1C

72D

81C

72D

66B

1

1C

72D

66C

31C

72D

86C

16C

7

P9<0>

P23<1>

P23<0>

P23<2>

P23<6>

P23<5>

P23<4>

P23<3>

P3<7>

P24<12>

P24<10>

P24<8>

P24<6>

P24<4>

P17<1>

P17<3>

P17<5>

P3<11>

P3<12>

P3<0>

P3<1>

P1<12>

P1<13>

P0<8>

P0<10>

P1<5>

P1<4>

P1<1>

P1<0>

P4<15>

P4<14>

P8<1>

P8<0>

P1<9>

P1<8>

P0<3>

P0<5>

P0<0>

P0<1>

P6<4>

P6<5>

P4<1>

P4<0>

P2<6>

P2<7>

P6<15>

P6<12>

P2<1>

P2<0>

P4<7>

P4<6>

P3<3>

P3<2>

P2<5>

P2<4>

P22<4>

P22<3>

P6<8>

P6<7>

P21<5>

P21<7>

AP

4<6>

AP

4<4>

AP

4<2>

AP

4<0>

P6<3>

P6<0>

P10<12>

P10<10>

P10<8>

P22<2>

P22<0>

P21<6>

P21<4>

P21<2>

P20<0>

P10<7>

P20<7>

P10<0>

P10<2>

P10<6>

P10<5>

P10<3>

P10<4>

P20<3>

P4<8>

P20<3>

P20<6>

P20<2>

P20<7>

P3<8>

P3<7>

P3<6>

P24<6>

P21<1>

P6<13>

P6<14>

P17<2>

P17<3>

P4<9>

P6<5>

P6<6>

P21<7>

P10<12>

RE

SE

TZ

P10<9>

P10<8>

NC

P11<11>

P11<15>

NC

NC

P11<13>

P11<9>

P24<11>

P11<14>

P11<12>

P11<10>

P11<8>

P24<10>

P21<7>

P21<5>

P21<4>

NC

AP

2<0>

P4<4>

NC

NC

P21<13>

NC

P23<8>

NC

P23<7>

P23<9>

P23<13>

P23<12>

P23<11>

P23<10>

P3<6>

NC

P24<13>

P24<11>

P24<9>

P24<7>

P24<5>

NC

P17<0>

P17<2>

P17<4>

NC

P3<13>

P3<14>

P3<9>

P3<10>

P1<14>

P1<15>

P0<9>

P0<11>

NC

P1<7>

P1<6>

P1<3>

P1<2>

P3<5>

P3<4>

P8<3>

P8<2>

P1<11>

P1<10>

NC

P0<6>

P0<7>

P0<2>

P0<4>

P3<7>

P3<8>

P5<2>

P5<3>

P3<4>

P3<5>

P2<3>

P2<2>

P4<15>

P4<14>

P4<12>

P4<11>

P4<5>

NC

NC

NC

NC

NC

AP

2<6>

AP

2<4>

AP

2<2>

P6<15>

P24<4>

P24<9>

P6<13>

P6<14>

P21<6>

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

P24<9>

P24<7>

P24<5>

AP

2<7>

AP

2<5>

AP

2<3>

AP

2<1>

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

P24<5>

P24<6>

P17<6>

P24<7>

P4<8>

NC

NC

P5<3>

P5<2>

NC

P24<8>

NC

P22<0>

P22<1>

P22<4>

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

P24<8>

P24<6>

P24<4>

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

P2<8>

P24<7>

P20<1>

P6<2>

NC

NC

NC

NC

NC

NC

NC

NC

P4<7>

NC

P22<0>

NC

P5<4>

P5<6>

NC

P20<5>

P20<4>

P20<10>

P20<12>

P20<13>

P10<1>

P20<8>

P20<14>

NC

NC

NC

NC

NC

NC

NC

NC

P22<1>

P22<3>

P10<9>

P10<11>

P10<13>

NC

NC

NC

AP

4<1>

AP

4<3>

AP

4<5>

AP

4<7>

P6<3>

P6<2>

P21<0>

P21<3>

P20<9>

P20<6>

NC

P20<8>

P10<8>

1111

1 111

12

34

56

78

910

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

12

34

56

78

910

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

12

34

56

78

910

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

INO

UT

IN OU

TIN INO

UT

OU

T

OU

T

INO

UT

IN OU

T

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

10098

96

94

92

90

88

86

84

82

80

78

76

74

72

70

68

66

64

62

60

58

56

54

52

50

48

46

44

42

40

38

36

34

32

30

28

26

24

22

20

18

16

14

12

108642

99

97

95

93

91

89

87

85

83

81

79

77

75

73

71

69

67

65

63

61

59

57

55

53

51

49

47

45

43

41

39

37

35

33

31

29

27

25

23

21

19

17

15

13

11

97531

OU

T

OU

TO

UT

OU

T

IN

OU

TIN

OU

T

INO

UT

OU

T

ININ

OU

T

ININ IN INININ IN

BI

BI

BI

BI

BI

BI

IN

IN

BI

BI

BI

BI

BI

BI

OU

TINBI

OU

T

OU

TO

UT

OU

T

INININ

BI

BI

OU

T

OU

T

ININBI

BI

BI

BI

BI

OU

T

BI

OU

TO

UT

OU

T

BI

BI

OU

T

ININININ

BI

ININ

IN

OU

TO

UT

OU

T

INININO

UT

BI

INININ IN

IN

IN IN BI

BI

BI

BI

BI

BI

BI

OU

TIN

OU

TIN

OU

TIN

OU

TIN

OU

TIN

OU

TIN

OU

TININ

OU

TIN

OU

T

OU

TININ

OU

T

IN

IN

IN IN IN IN IN IN IN IN

OU

T

OU

T

OU

T

OU

TO

UT

OU

TO

UT

OU

TO

UT

OU

TB

I

BI

BI

OU

T

BI

BI

INBI

BI

INOU

TINO

UT

IN

IN

OU

TINO

UT

ININ OU

T

IN OU

T

IN OU

T

OU

T

OU

TINO

UT

INOU

TINO

UT

IN

OU

T

ININO

UT

OU

TO

UT

OU

T

OU

TO

UT

OU

T

OU

T

OU

T

OU

TINO

UT

OU

T

IN IN OU

T

OU

T

INO

UT

IN OU

T

OU

TIN

OU

TIN

OU

TIN

OU

TIN

OU

TIN

OU

T

BI

BI

BI

OU

TO

UT

OU

TO

UT

INOU

T

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

10098

96

94

92

90

88

86

84

82

80

78

76

74

72

70

68

66

64

62

60

58

56

54

52

50

48

46

44

42

40

38

36

34

32

30

28

26

24

22

20

18

16

14

12

108642

99

97

95

93

91

89

87

85

83

81

79

77

75

73

71

69

67

65

63

61

59

57

55

53

51

49

47

45

43

41

39

37

35

33

31

29

27

25

23

21

19

17

15

13

11

97531

BI

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

10098

96

94

92

90

88

86

84

82

80

78

76

74

72

70

68

66

64

62

60

58

56

54

52

50

48

46

44

42

40

38

36

34

32

30

28

26

24

22

20

18

16

14

12

108642

99

97

95

93

91

89

87

85

83

81

79

77

75

73

71

69

67

65

63

61

59

57

55

53

51

49

47

45

43

41

39

37

35

33

31

29

27

25

23

21

19

17

15

13

11

97531IN

OU

T

OU

T

Th

ese

in

tan

gib

le g

oo

ds a

re n

ot

su

bje

ct

to A

nn

ex I

of

co

mm

on

Du

al-

Use

lis

t (4

28

/20

09

) in

its

cu

rre

nt

ve

rsio

n.

Siz

eD

ocu

me

nt

Nu

mb

er

A2

Title

Da

te:

98

76

54

32

1

98

76

54

32

1

A B C D E F

A B C D E F

Revision History

Rev. Date

Description

Page Summary

V0.01 2018-08-31 ‒ Initial release

V1.00 2019-02-20 • Schematics update

• OPC Section added

Colophon

RH850/U2A 516pin PiggyBack Board V1 User's Manual: PiggyBack Board

Publication Date: Rev.1.00 Feb 20, 2019

Published by: Renesas Electronics Corporation

Address List

http://www.renesas.com

Refer to "http://www.renesas.com/" for the latest and detailed information.

Renesas Electronics America Inc.1001 Murphy Ranch Road, Milpitas, CA 95035, U.S.A.Tel: +1-408-432-8888, Fax: +1-408-434-5351

Renesas Electronics Canada Limited9251 Yonge Street, Suite 8309 Richmond Hill, Ontario Canada L4C 9T3Tel: +1-905-237-2004

Renesas Electronics Europe LimitedDukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.KTel: +44-1628-651-700, Fax: +44-1628-651-804

Renesas Electronics Europe GmbH

Arcadiastrasse 10, 40472 Düsseldorf, GermanyTel: +49-211-6503-0, Fax: +49-211-6503-1327

Renesas Electronics (China) Co., Ltd.Room 1709 Quantum Plaza, No.27 ZhichunLu, Haidian District, Beijing, 100191 P. R. ChinaTel: +86-10-8235-1155, Fax: +86-10-8235-7679

Renesas Electronics (Shanghai) Co., Ltd.Unit 301, Tower A, Central Towers, 555 Langao Road, Putuo District, Shanghai, 200333 P. R. ChinaTel: +86-21-2226-0888, Fax: +86-21-2226-0999

Renesas Electronics Hong Kong LimitedUnit 1601-1611, 16/F., Tower 2, Grand Century Place, 193 Prince Edward Road West, Mongkok, Kowloon, Hong KongTel: +852-2265-6688, Fax: +852 2886-9022

Renesas Electronics Taiwan Co., Ltd.13F, No. 363, Fu Shing North Road, Taipei 10543, TaiwanTel: +886-2-8175-9600, Fax: +886 2-8175-9670

Renesas Electronics Singapore Pte. Ltd.80 Bendemeer Road, Unit #06-02 Hyflux Innovation Centre, Singapore 339949Tel: +65-6213-0200, Fax: +65-6213-0300

Renesas Electronics Malaysia Sdn.Bhd.Unit 1207, Block B, Menara Amcorp, Amcorp Trade Centre, No. 18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, MalaysiaTel: +60-3-7955-9390, Fax: +60-3-7955-9510

Renesas Electronics India Pvt. Ltd.No.777C, 100 Feet Road, HAL 2nd Stage, Indiranagar, Bangalore 560 038, IndiaTel: +91-80-67208700, Fax: +91-80-67208777

Renesas Electronics Korea Co., Ltd.17F, KAMCO Yangjae Tower, 262, Gangnam-daero, Gangnam-gu, Seoul, 06265 KoreaTel: +82-2-558-3737, Fax: +82-2-558-5338

SALES OFFICES

ã 2018 Renesas Electronics Corporation. All rights reserved.

Colophon 5.0

Back Cover

RH850/U2A 516pin

R20UT4371ED0100

Manual RH850/U2A 516pin - renesas.com

Documents

Transcript of Manual RH850/U2A 516pin - renesas.com