Making the Most of your FPGA Design - NIaustralia.ni.com/sites/default/files/Making The Most Of...

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ni.com Making the Most of your FPGA Design Rejwan Ali Marketing Engineer

Transcript of Making the Most of your FPGA Design - NIaustralia.ni.com/sites/default/files/Making The Most Of...

Page 1: Making the Most of your FPGA Design - NIaustralia.ni.com/sites/default/files/Making The Most Of FPGA.pdf · Making the Most of your FPGA Design Rejwan Ali Marketing Engineer. ni.com

ni.com

Making the Most of your FPGA Design

Rejwan Ali

Marketing Engineer

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Overview

• Introduction to “Making the most”

• Maintainability through Simulation

• Creating Scalable LVFPGA

• Reactor Pattern in LVFPGA

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Making the Most of our FPGA

Maintainable – The code is easy to test and

changeScalable – Maximize FPGA capabilities

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LabVIEW FPGA

• Reconfigurable I/O

• Custom hardware algorithms

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LV FPGA Development Process

Requirements

Design

Implement

Test

Deploy

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LV FPGA Development Process

Implement

Compile

Test

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LV FPGA Development Process

Implement

Compile

Test

15 sec

544 sec

65 sec

87% spent compiling

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Reduce Development Time

• Buy a faster compilation machine

• Improve the compiler (Xilinx, NI)

• Simulation

ni.com/trycompilecloud

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Simulation

Simulation– The imitation of the operation of a real-world system over time.

LVFPGA Simulation Options

1. Simulation on Windows

2. Development Computer with Simulated I/O

3. Conditional Disable Structures

4. LVFPGA Desktop Execution Node

5. Testbench

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Simulation On Windows

Pre-FPGA

WindowsFPGA code Post-

FPGA

Windows

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Simulation On Windows

Quick

Good for inline algorithms

Allows Windows VIs

+No/incorrect timing

I/O does not work

Code snipetsonly

-

Use case: Quick functionality

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Development Computer with Simulated I/O

FPGA Target Press RunGenerate

VHDLCompile

BitfileRun on

Hardware

Development Computer w/

Sim I/OPress Run

Run Diagram on Windows (Simulation)

Debug Code

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Development Computer with Simulated I/O

1.

2.

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Development Computer with Simulated I/O

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Development Computer with Simulated I/O

Full simulation

Memory, FIFOs and I/O supported

Standard debug tool available

+Inputs are random data by default

Windows VIs unsupported on FPGA

-

Use case: Functional test

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Conditional Disable

Allows changing FPGA source easily by switching

between FPGA and Development Computer context

ConditionalDisable/ConditionalExample.lvproj
ConditionalDisable/ConditionalExample.lvproj
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Conditional Disable

Quick

Changes functionality automatically

+Branches code

Windows VIs unsupported

-

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LV FPGA Desktop Execution Node

LV FPGA

Host-side

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LV FPGA Desktop Execution Node

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LV FPGA Desktop Execution Node

Test Harness

Unit Test

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LV FPGA Desktop Execution Node

Iteration Accurate

Simulates I/O

Memory and FIFO supported

+Not Tick Accurate

-

Use case: Unit Testing &

Integration Testing

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Testbench

Embedded Testbench – An application which verifies functionality of software and hardware through simulation

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Testbench

I/O Simulation

Testbench

FPGA

Example

FPGA Interface

TestbenchDemo/Testbench.lvproj
TestbenchDemo/Testbench.lvproj
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Testbench

Full Simulation

Test FPGA Interface

UI available

Customizable I/O

Waveform Probes

+Ensure Simulation starts first

-

Use case: System testing

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Scalable LabVIEW FPGA

How difficult to scale this FPGA Code?

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Scalable LabVIEW FPGA

1. Copy/Paste

2. Change IO

3. Add more memory blocks to

the project

4. Add more DMA FIFOs

5. Change the names of

controls and indicators

DO NOT DO THIS:

• Unmaintainable

• Limited DMA FIFOs

• Huge Diagrams make it hard to debug/simulate

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Scalable SubVIs

1. Create SubVI

2. Copy SubVIs

3. …..

4. Profit???

Problems:

1. I/O is incorrect

2. Same memory blocks in each copy

3. Same DMA FIFO in each SubVI

4. How do we change the Delay?

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Purple Wires

VI-Defined

Local FIFOs

Memory

Registers

References

Inputs

Outputs

DMA FIFOs

Local FIFOs

Memory

Registers

Timing

Sources

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Single-cycle Timed Loops

Problems

• Some hardware MUST be run inside a SCTL

• SCTL is not compatible with some operations

Not allowed in

SCTL

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Single-cycle Timed Loops

Bonus

• SCTL code can be used in non-SCTL locations

• SCTL code is typically smaller than non-SCTL

• SCTL code is very deterministic

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Reactor Pattern

Reactor Pattern– A design pattern for handling information that is being sent concurrently. Very common is networking software.

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Reactor Pattern

Channel 0

Channel 1

Channel N

Channel 2

……..

Dispatcher Aggregator

Host Application

FPGA

Local FIFODMA FIFO

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Reactor Pattern

Advantages

• Very scalable

• Works on all NI Targets

• Concurrency

Disadvantages

• Difficult without simulation

• FIFO sizing can be tricky

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Maintainable Scalable

Questions


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