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IOG 20

Handout


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Handout - IOG 20

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Handout IOG 20

Table of Contents

Topic Page

IOG 20 HARDWARE STRUCTURE.......................................................1

INTRODUCTION ........................................................................................................... 1

HARDWARE CONFIGURATIONS.........................................................2

IOG 20B-P...................................................................................................................... 2

IOG 20B ......................................................................................................................... 3

IOG 20C......................................................................................................................... 4

IOG 20 SUBRACKS AND BOARDS .....................................................5

SPVM-P SUBRACK IOG 20B-P .................................................................................... 5

SPVM SUBRACK IOG 20B ........................................................................................... 5

SPVCM SUBRACK IOG 20C......................................................................................... 6

BOARDS........................................................................................................................ 6

LEDS AND BUTTONS, IOG 20..................................................................................... 9

SUMMARY, IOG 20 ..................................................................................................... 12


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Handout - IOG 20

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IOG 20 HARDWARE STRUCTURE

INTRODUCTION

This chapter will explain the differences between the hardware

configurations that exist in the SP-based IO systems IOG 20:

IOG 20B-P

IOG 20B

IOG 20C

All IOG 20 equipment is mounted in BYB 501 racks.

The IOG 20 rack contains one subrack:

SPVM-P in IOG 20B-P

SPVM in IOG 20B

SPVCM in IOG 20C


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HARDWARE CONFIGURATIONS

IOG 20B-P

Figure 1 IOG 20B-P

The IOG 20B-P interfaces towards the parallel RP-bus (this is

indicated by the P).

The IOG 20B-P has a maximum capacity of:

32 terminals or 32 data links or 16 duplicated data links or a

combination of this 3 hard disks per node (2 or 4 Gb)

1 flexible disk per node

1x5 1/4 inch opto disk per node

32 external alarm connections per node

4 alarm panel interfaces per node

1 SCAN alarm interface per node

The IOG 20B-P may be used as SPG>0 if the alarm interface

boards are removed.


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Handout - IOG 20

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IOG 20B

Figure 2 IOG 20B

The IOG 20B interfaces towards the serial RP-bus.

The IOG 20B has a maximum capacity of:

32 terminals or

32 data links or

16 duplicated data links or

a combination of this

3 hard disks per node (2 or 4 Gbyte)

1 flexible disk per node


32 external alarm connections per node

4 alarm panel interfaces per node

1 SCAN alarm interface per node

The IOG 20B may be used as SPG>0 if the alarm interface

boards are removed.


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IOG 20C

Figure 3 IOG 20C

The IOG 20C interfaces towards the serial RP-bus.

The IOG 20C has a maximum capacity of:

16 terminals or16 data links or

8 duplicated data links or

a combination of this

1 hard disk per node (2 or 4 Gbyte)


32 external alarm connections

4 alarm panel interfaces

1 SCAN alarm interface

The IOG 20C is never used as SPG>0, even though this is

technically possible.


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Handout - IOG 20

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IOG 20 SUBRACKS AND BOARDS

The SPVM, SPVM-P and SPVCM subracks are electro

magnetically shielded.

SPVM-P SUBRACK IOG 20B-P

An IOG 20B-P consists of two SPVM-P subracks.

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SPVM SUBRACK IOG 20B

An IOG 20B consists of two SPVM subracks.

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SPVCM SUBRACK IOG 20C

An IOG 20C consists of one SPVCM subrack.

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Figure 6 SPVCM subrack

BOARDS

Power - supplies power for all boards in the subracks via the

backplane. The power-feeding is connected to the front plane.

Input power is 48 volts and output power is +5 and +/-12 volts.

CPU60 - processor board with microprocessor M68060. The

primary memory on the board is 32 MB. The CPU60 interfaces

to the intercomputer bus (Ethernet) via the front plane and to the

SCSI-2 bus, power and VME bus in the back plane. The CPU60

has two RS232 ports on the front plane for connection of IO

terminal. The RS232 ports communicates with 4800 baud.

FD/HD drive - this board contains both 3 1/2 inch diskette drive

and hard disk drive. It interfaces to the SCSI-2 bus and power in

the backplane.

HD drive - this board contains one or two hard disks. It

interfaces to the SCSI-2 bus and powers in the backplane.

OD drive 3 1/2 inch - this board contains one opto disk drive. It

interfaces towards the VSA board via a separate SCSI-2 bus in

the back plane. It is also power-fed in the backplane.

OD drive 5 1/4 inch - this board contains one opto disk drive. It

interfaces towards the VSA board via a separate SCSI-2 bus in

the back plane. It is also power-fed in the backplane.


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96$this board converts VME bus to a separate SCSI-2 buswhich interfaces to the opto disk drive. It interfaces to VMEbus, SCSI-2 bus and power in the back plane.

DRPBU - this board interfaces to the parallel RP-bus in the

front plane. In the back plane it interfaces to the PROVME

board, via an internal interface, and to power.

35290(- this board interfaces to the DRPBU board via aninternal interface. It interfaces to the VME bus and its powersupply is in the back plane.

RPV2 - this board interfaces to the serial RP-bus in the front

plane. In the back plane it interfaces to the VME bus and to

power.

LUM - this board contains a microprocessor Motorola M68060.

It interfaces to the daughter boards V.24/V.35/V.36/X.21

INTERFACE, G.703 E0 INTERFACE and G.703 E1

INTERFACE via a connector on the board. It can hold four

daughter boards, of which each controls one physical port. The

boards are fitted on the LUM board with four screws.

The LUM mother board interfaces to the VME bus and power

in the back plane.

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V.24/V.35/V.36/X.21 INTERFACE daughter boards - these

boards implement one physical port towards a data link or

terminal. It is fitted to the LUM board with four screws and is

power-fed from the LUM board. It supplies the interfaces V.24,V.35, V.36 and X.21.

G.703 E0 INTERFACE daughter board - this board

implements one physical port towards a data link or terminal. It

is fitted to the LUM board with four screws and is power-fed

from the LUM board. It supplies the interface G.703 E0 with a

baudrate of 64 kbit/s.

G.703 E1 INTERFACE daughter board - this board

implements one physical port towards a data link or terminal. It

is fitted to the LUM board with four screws and is power-fedfrom the LUM board. It supplies the interface G.703 E1 with a

baudrate of 2 megabit/s.

T- Ethernet INTERFACE daughter board - this board is not

introduced as an orderable product at the first IOG 20 release.

$/&38 - Alarm interface board. This board has two V.24 portswhich interfaces to the LUM board and to the fan. The boardhas a SCAN input and input of an external alarm. The board isconnected to a VME bus and powered in the back plane.

$/(;3- This board has four outputs for control of alarmdisplays. The board is controlled by board ALCPU.

ESDCV - EMC shield and Daisy Chain VME bus circuit board.

The purpose of this board is to fill empty positions in the SPVM

subrack. This is to maintain the electro magnetic shield that the

subrack forms. The board also connections the VME bus in the

back plane of the SPVM subrack.

Empty positions may occur if the subrack is not fully equipped

with LUM boards or if the RP-bus interface is serial with oneRPV2 board instead of the DRPBU and PROVME boards.

Empty positions may also occur if only one hard disk is installed

in an IOG 20B-P or IOG 20B node.


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Handout - IOG 20

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LEDS AND BUTTONS, IOG 20

In the IOG hardware there are a number of lamps (LEDs)

indicating different states and faults that can occur in an IOG.

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Figure 9 LEDs on CPU60 board

There are also two flip buttons on the CPU60 board front. These

buttons should only be used in special situations. The upper

button is for debugging of SP programs. The lower (reset

button) is for restarting (flip once) or reloading (flip twice) of

the SP.


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A terminal can be connected straight into the SP on the front of

the CPU60 board. This is referred to as a local terminal. From

this terminal only SP commands can be sent. There are two

RS232 connections for this.

A local terminal is, for instance, used at initial start of IOG 20.

Normally no terminal is connected to the CPU port.

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SUMMARY, IOG 20

IOG 20 exists in three versions: IOG 20B, IOG 20B-P and

IOG 20C

All three versions are two-node SPGs

IOG 20B and IOG 20C interfaces to the serial RP-bus

IOG 20B-P interfaces to the parallel RP-bus

The subrack implementing IOG 20B-P is SPVM-P

The subrack implementing IOG 20B is SPVM

The subrack implementing IOG 20C is SPVCM

All IOG 20 subracks are built according to BYB501

All three IOG 20 versions are using the M68060

microprocessor with 32 MB primary memory

IOG 20C has only one HD per node

IOG 20C has only one 3 1/5 OD per node

IOG 20C can have a maximum of three LUM boards pernode

IOG 20B/-P can have a maximum of 3 HDs and one 3 1/5FD per node

IOG 20B/-P has a maximum of one 5 1/5 OD per node

IOG 20B/-P can have a maximum of four LUM boards per

node

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