M9 MLB DVT Resolved.bak
Transcript of M9 MLB DVT Resolved.bak
ANGLES
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
DATE
APPDENG
DATE
APPDCK
ECNZONEREV
DO NOT SCALE DRAWING
X.XXX
X.XX
XX
DIMENSIONS ARE IN MILLIMETERS
THIRD ANGLE PROJECTIOND
SIZE
APPLICABLENOTED AS
MATERIAL/FINISH
NONE
SCALE
DESIGNER
MFG APPD
DESIGN CK
RELEASE
QA APPD
ENG APPD
DRAFTER
METRIC
OFSHT
DRAWING NUMBER
TITLE
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PARTII NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
Apple Computer Inc.
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B
C
D
A
B
C
D
A
REV.
DESCRIPTION OF CHANGE
DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL
DRAWING
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(6.0.0)
DVT
3/3/2006
Schematic / PCB #’s
M9 MLBSully
ALIASES RESOLVEDFireWire Port Power
45(M1_MLB)43 (11/03/2005)
FW PHY Power Supply44
(MASTER)42 (MASTER)Yukon Power Control
43M1_MLB41 02/10/2006
Ethernet Connector42
M1_MLB40 02/10/2006ETHERNET CONTROLLER
41M1_MLB39 02/10/2006
FireWire PHY (TSB83AA22)40
(MASTER)38 (MASTER)FireWire Link (TSB83AA22)
39(MASTER)37 (MASTER)
PATA Connector38
M1_MLB36 02/10/2006Mobile Clocking
37M1_MLB35 02/10/2006
Clock Termination34
M1_MLB34 02/10/2006CLOCKS
33M1_MLB33 02/10/2006
DDR2 VRef32
M1_MLB32 12/19/2005Memory Vtt Supply
31M1_MLB31 02/10/2006
Memory Active Termination30
(M1_MLB)30 (11/07/2006)DDR2 SO-DIMM Connector B
29M1_MLB29 02/10/2006
DDR2 SO-DIMM Connector A28
M1_MLB28 02/10/2006M1 SMBus Connections
27M1_MLB27 01/04/2006
SB Misc26
M1_MLB26 02/10/2006SB Decoupling
25M1_MLB25 02/10/2006
SB: 4 OF 424
M1_MLB24 02/10/2006SB: 3 OF 4
23M1_MLB23 02/10/2006
SB: 2 of 422
M1_MLB22 02/10/2006SB: 1 OF 4
21M1_MLB21 02/10/2006
NB Config Straps20
M1_MLB20 02/10/2006NB (GM) Decoupling
19M1_MLB19 02/08/2006
NB Grounds18
M1_MLB18 02/10/2006NB Power 2
17M1_MLB17 02/10/2006
NB Power 116
M1_MLB16 02/10/2006NB DDR2 Interfaces
15M1_MLB15 02/10/2006
NB Misc Interfaces14
M1_MLB14 02/10/2006NB PEG / Video Interfaces
13M1_MLB13 02/10/2006
NB CPU Interface12
M1_MLB12 02/10/2006CPU ITP700FLEX DEBUG
11M1_MLB11 02/10/2006
CPU MISC1-TEMP SENSOR10
M1_MLB10 02/10/2006CPU Decoupling & VID
9M1_MLB9 02/08/2006
CPU 2 OF 2-PWR/GND8
M1_MLB8 02/10/2006CPU 1 OF 2-FSB
7M1_MLB7 02/10/2006
Signal Aliases6
(M1_MLB)6 (11/11/2005)Functional / ICT Test
5(MASTER)5 (MASTER)
BOM Configuration4
(MASTER)4 (MASTER)Power Block Diagram
3(MASTER)3 (MASTER)
System Block Diagram2
(MASTER)2 (MASTER)
86 104M1_MLB
02/10/2006M1 Net Properties
85 103M1_MLB
02/10/2006M1 Spacing & Physical Constraints
84 102M1_MLB
02/10/2006More System Constraints
83 101M1_MLB
02/10/2006Napa Platform Constraints
82 100(MASTER)
(MASTER)Revision History
81 99M1_MLB
12/19/2005LVDS Interface Pull-downs
80 98(MASTER)
(MASTER)M9 Specific Connectors
79 97M1_MLB
11/18/2005External Display Connector
78 94M1_MLB
01/09/2006Internal Display Connectors
77 93M1_MLB
02/10/2006ATI M56 Video Interfaces
76 91M1_MLB
02/10/2006ATI M56 GPIO/DVO/Misc
75 90M1_MLB
02/10/2006GDDR3 Frame Buffer B
74 89M1_MLB
02/10/2006GDDR3 Frame Buffer A
73 88M1_MLB
02/10/2006GPU Straps
72 87M1_MLB
02/10/2006ATI M56 Frame Buffer I/F
71 86M1_MLB
02/10/2006ATI M56 Core Power
70 85M1_MLB
02/10/2006GPU (M56) Core Supplies
69 84M1_MLB
02/10/2006ATI M56 PCI-E
68 83M1_LIO
12/19/2005PBus Supply & Batt. Charger
67 82(MASTER)
(MASTER)DC-In & Battery Connectors
66 81M1_MLB
12/19/2005Power Aliases
65 80M1_MLB
02/10/20063.3V G3Hot Supply & Power Control
64 79M1_MLB
02/10/20063.3V / 1.05V Power Supplies
63 78M1_MLB
02/10/20061.8V Supply
62 77M1_MLB
02/10/20062.5V & 1.2V Regulators
61 76M1_MLB
02/10/20065V / 1.5V Power Supply
60 75M1_MLB
02/08/2006IMVP6 CPU VCore Regulator
59 67M1_MLB
02/10/2006TPM
58 66M1_MLB
02/10/2006Sudden Motion Sensor (SMS)
57 65M1_MLB
02/10/2006Fan Connectors
56 64M1_MLB
02/10/2006ALS Support
55 63M1_MLB
02/10/2006SPI BOOTROM
54 62M1_MLB
01/05/2006Current & Voltage Sensing
53 61M1_MLB
02/10/2006Thermal Sensors
52 60M1_MLB
02/10/2006LPC+ Debug Connector
51 59M1_MLB
02/10/2006SMC Support
50 58M1_MLB
02/10/2006SMC
49 57M1_MLB
02/10/2006PCI-E Connections
48 56(MASTER)
(MASTER)Current & Thermal Sensors
47 55(MASTER)
(MASTER)Left I/O Board Connector
46 52M1_MLB
02/10/2006External USB Connector
45 49M1_MLB
02/10/2006Internal USB Connections
Page Contents(.csa) Date
SyncTable of Contents
1N/A1 N/A
ContentsDate(.csa)
SyncPage44 46
(MASTER)(MASTER)
FireWire Ports
TITLE=SULLYABBREV=DRAWINGLAST_MODIFIED=Fri Mar 3 17:59:45 2006
PCBF,SULLY,FINAL,M9820-2023 CRITICALPCB1
CRITICALSCH1051-7023 SCHEM,SULLY,M9
?? ?? ?
861
051-7023
SCHEM,SULLY,M9
06
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
P.82Connector
TemperatureSensors
P.48,53
P.39P.41
P.37-38Controller
TSB83AA22 FireWire
P.44Connectors
HDD/BT/IR
P.80
USB x2
w/TV-Out Support
SENSOR
& REGULATOR
DDR2 VTTUpper Connector
Lower ConnectorDDR2 SO-DIMM A
J2800
J2900
ConnectorAudio BoardLeft I/O &
DDR2 VREFBUFFER
Azalia (HD-Audio)
PCIe x1
Connector
ITP700FLEXCPU Debug
479 BGA
CH.A
CH.B
FSB
NB1466UFCBGA
945GM
Core Duo(Yonah)
CPUTHERMAL
ATI M56P
GDDR3
S-Video/Composite
Dual-Channel LVDS
Dual-Channel TMDS
PWM
USB
609 BGA
DebugLPC
Connector
Sensors
SMC
SPIBootROM
SMBus
USB
USB
SATA
USB
SB SMBus
PATA66MHZ16BITS
CK410 ClockController
TP ConnectorGeyser KB /
Connector ODD
Connector
LCD Panel
CONNECTORINVERTER
Yukon PowerYukon Gig-E
PCI
Controller
FW
SMS
FanConnectors
PWM/Tach
SMC SMBus
DDR2 SO-DIMM B
Battery SMBus
Analog
SMBus x5
H8S/2116
ConnectorRight USB 2.0
GPU
128MB/256MBFrame Buffer
ENET
DVI-I/DL Connector
P.78
P.78,81
P.79 P.69-73,76-77
P.74-75 P.10P.7-9
P.11
P.12-20
P.47
P.30-31P.29
P.28
P.32
P.46
P.45
P.45
P.36
P.33-34 P.27
P.27
PCIe x1
Connectors
P.50-51
P.52
P.55
P.56
P.57
P.58
P.59
Power
RT ALS
Camera
USB x2
P.40Connector
RJ45 (Ethernet)
Supplies
P.43Port Power
1394a/b (FireWire)
P.42PHY Power
TPM
LPC 33MHZ
P.21-26
SB
ICH7-M
P.54
P.68
PBUS SupplyBatt Chgr/
PCIe x1
DMI x4
PCIe x16
P.60-67,70
051-7023
862
06
System Block DiagramSYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
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B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
PPBUS_G3H_B
12.6V - 9V
PPBUS_G3H_A
18.5V - 9V
PP1V8_S3
1.8V
Q7615
U8000ENABLE
(LT3470)
SMC_PM_G2_ENABLE
U7900
3.3V
PPVCORE_S0_GPU
PP2V5_S3S3
PGOOD
IMVP_PWRGD_IN
PPDCIN_G3H
J5500
U7530
(ISL6262)
PP3V3_S5
PP1V05_S0
1.05V
PM_SLP_S3_L
PP3V42_G3H
Q7845
ENABLES
PPVCORE_S0_CPU
NC
U7750
Q7770
Q7720"IMVP6"
PGOOD
RSMRST_PWRGD
3.3V
PP3V3_S3
Q7610
LIO Power
J5500Inverter
Connector
PM_SLP_S3_LS5V
PPBUS_S5_FWPORT
12.6V - 9V
FWPWR_EN
5V/1.5V
U8500
PP3V3_S0
NC
1.5V
PGOOD
(ISL6269)
S5
3.3V
ENABLE
?V
PGOOD
1.05V
U7950
1.2V - 1.0VS0
(ISL6269)
GPU VCore
ENABLE
3.3V
NC
(LTC3412)
S3
PGOOD
1.2V
ENABLE
1.2V
PP1V2_S3
2.5V
PP2V5_S0
2.5V(LTC3411)
2.5V
PGOOD
ENABLEU7700
PP5V_S0
5.0V
PP5V_S3
PP1V5_S0
5.0V
PP5V_S5
NC
(LTC3728)
S5/S0
PGOOD
ENABLESU76005
V
1.5V
SMC_PM_G2_ENABLE
VR_PWRGOOD_DELAY
S0CPU VCore
IMVP_VR_ON
(ISL6269)
S0
PM_SLP_S3_L
PM_SLP_S4_LS5V
PM_SLP_S3_LS5V
PM_SLP_S3_LS5V_L
ENABLE
ENABLE
NC
1.8V
U7800
S3
ENABLE
(ISL6269)
PGOOD
PM_SLP_S3_L
U3100
0.9V (Vtt)
S0
(BD3533FVM)
PP0V9_S0
0.9V
Q4565
PP1V2_S0
1.2V
PM_SLP_S3_LS5V_L
PM_SLP_S3_LS5V_L
PP1V8_S0
1.8V
5.0V
3.425VG3Hot
3.425
J8200
LIO Flex
Connector
12.6V - 9V
Connector
PM_SLP_S4_L
IMVP_PWRGD_IN/ALL_SYS_PWRGD
PM_SLP_S3_L
PM_SLP_S4_LS5V
Q7945
Q7947
3 86
06051-7023
Power Block DiagramSYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
TABLE_ALT_ITEM
DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL
DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
PART NUMBERALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:
TABLE_ALT_HEAD
BOM OPTIONSBOM NAMEBOM NUMBERTABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
BOM OPTIONSBOM GROUPTABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL
DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL
TABLE_BOMGROUP_ITEM
BOM OPTIONSBOM GROUPTABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
Module Parts
Bar Code Labels / EEE #’s
M9 Specific Aliases
IS
GPU_MEM_256M,VRAM_256_SAMSUNGVRAM_256SAM
VRAM_256HY GPU_MEM_HYNIX,GPU_MEM_256M,VRAM_256_HYNIX
SMC_BLANK338S0274 1 CRITICALIC,SMC,HS8/2116 U5800
SMC_FINALIC,SMC,PRGRM,M9341S1876 U5800 CRITICAL1
338S0270 CRITICALU41011 IC,88E8053,GIGABIT ENET XCVR,64P QFN, NO
BOOTROM_BLANK335S0384 CRITICAL1 IC,16MBIT 8-PIN SPI SERIAL FLASH,SOIC8 U6301
ITP,ITPCONN,LPCPLUSM9_DEBUG
LIO_TEMP,BOOTROM_DEVEL,SMC_DEVELM9_COMMON4
LVDS_PD,M56_REV_B24_LP,FW_B_BILINGUAL,FW_A_DS_ONLY,FW_PORT_FAULT_PU,FW_PLTRST_UNGATEDM9_COMMON3
ENET_LOM_DISABLE,ENETPWR_S3AC,GPUTHM_A_GPU,GPU_BB_CTL,HSTHMSNS_HAS,INVERTER_BUF,ONEWIRE_PUM9_COMMON1
ALTERNATE,COMMON,M9_COMMON1,M9_COMMON2,M9_COMMON3,M9_COMMON4,M9_DEBUGM9_COMMON
VRAM_128_SAMSUNGVRAM_128SAM
1343S0385 IC,SB,652BGA CRITICALU2100
338S0269 IC,945GM,SOUTHBRIDGE U1200 CRITICAL1
CPU_2_16GHZU07001 CRITICALIC,CPU,479 BGA337S3268
CPU_2_0GHZ337S3267 IC,CPU,479 BGA CRITICAL1 U0700
337S3282 CPU_1_83GHZU07001 CRITICALIC,CPU,479 BGA
U6700 CRITICAL1 IC, TPM, 28-PIN TSSOP341S1789
IC,CY28445-5,CLOCK GEN,68PIN QFN U33011 CRITICAL359S0101
1 IC,CPU VOLTAGE REGULATOR,IMVP,TWO PHASE CRITICALU7530353S1235
BOOTROM_FINALIC,EFI,BOOTROM FINAL,M9341S1829 CRITICAL1 U6301
BOOTROM_DEVELIC,EFI,BOOTROM DEVELOPMENT,M9341S1828 U63011 CRITICAL
341S1797 U4102IC,EEPROM,SERIAL IIC,8KBIT,SO81 CRITICAL
SMC_DEVELIC,SMC,PRGRM,M9341S1876 1 CRITICALU5800
IC,SGRAM,GDDR3,16MX32,700MHZ,136 FBGA VRAM_256_HYNIXCRITICALU8900,U8950,U9000,U90504333S0351
VRAM_128_SAMSUNGCRITICALU8900,U8950,U9000,U9050IC,SGRAM,GDDR3,8MX32,700MHZ,136 FBGA4333S0354
KBDLED_HAS,MEMVREF_S3,MEMVTT_EN_PU,RTUSB_ESD,USB_C_OC_PU,USB_D_OC_PU,USB_E_OC_PUM9_COMMON2
GPU_MEM_HYNIX,VRAM_128_HYNIXVRAM_128HY
VRAM_256SAM,M9_COMMON,CPU_2_16GHZ,EEE_UP1630-7406 PCBA,SULLY,2.16GHz,M9
VRAM_256SAM,M9_COMMON,CPU_2_0GHZ,EEE_UNZPCBA,SULLY,2.0GHz,M9630-7404
IC,SGRAM,GDDR3,8MX32,700MHZ,136 FBGA VRAM_128_HYNIXCRITICALU8900,U8950,U9000,U9050333S0358 4
333S0350 4 VRAM_256_SAMSUNGU8900,U8950,U9000,U9050 CRITICALIC,SGRAM,GDDR3,16MX32,700MHZ,136 FBGA
M56_REV_B24_LL U8400338S0266 LP is alt to LL338S0309
1.86 max alt to 1.9 max128S0083 128S0073 C2516
376S0445376S0448 Vishay 2nd sourceALL
U8400338S0266 338S0309 M56_REV_B24_LP LL is alt to LP
B26_LP is alt to B24_LP338S0315 U8400338S0309 M56_REV_B24_LP
LBL,P/N LABEL,PCB,28MM X 6 MM CRITICAL826-4393 1 EEE_UNZ[EEE:UNZ]
LBL,P/N LABEL,PCB,28MM X 6 MM1 CRITICAL EEE_UP0[EEE:UP0]826-4393
LBL,P/N LABEL,PCB,28MM X 6 MM CRITICAL1 [EEE:UP1]826-4393 EEE_UP1
LBL,P/N LABEL,PCB,28MM X 6 MM CRITICAL[EEE:UYU] EEE_UYU1826-4393
LBL,P/N LABEL,PCB,28MM X 6 MM [EEE:UP2] CRITICAL826-4393 EEE_UP21
IC,ATI,M56P,GRPHSCTRL,880BGA,LF CRITICAL338S0302 M56_REV_B24_HLU84001
IC,ATI,M56P,GRPHSCTRL,880BGA,LF U84001 CRITICAL338S0266 M56_REV_B24_LL
CRITICALIC,ATI,M56P,GRPHSCTRL,880BGA,LF U8400338S0309 M56_REV_B24_LP1
CRITICALIC,ATI,M56P,GRPHSCTRL,880BGA,LF U84001338S0315 M56_REV_B26_LP
M56_REV_B26_P338S0316 CRITICALIC,ATI,M56P,GRPHSCTRL,880BGA,LF U84001
128S0093 128S0092 ALL Kemet is alt to Sanyo
BOM ConfigurationSYNC_DATE=(MASTER)SYNC_MASTER=(MASTER)
4 86
06051-7023
C2 package is alt to C3128S0061128S0081 ALL
Sanyo is alt to Panasonic128S0094128S0060 ALL
ALL128S0094128S0095 330uF,2V,6MOHM,D2
PP3V3_FWPHY
PPFW_PORTA_VP_UF
SMC_RSTGATE_L
MAKE_BASE=TRUEPPFW_PORTB_VP_UF
PP3V3_FWPHY
PP3V3_FWPHY
PP3V3_S0
PP1V8_S3
PP1V95_FWPHY
PCI_REQ3_L
PCI_GNT3_LMAKE_BASE=TRUE
LT2USB_OC_L
PP1V95_FWPHY
PPBUS_S5_FW_FET
MAKE_BASE=TRUEPCI_AD<19>
MAKE_BASE=TRUELT2USB_OC_L
SMBUS_SMC_B_S0_SCL
PP1V95_FWPHY
MAKE_BASE=TRUE
VOLTAGE=1.95VPP1V95_FWPHYMIN_LINE_WIDTH=0.38 mmMIN_NECK_WIDTH=0.25 mm
PP1V8_S3
PP5V_S0
MAKE_BASE=TRUESMC_RSTGATE_L
PP3V3_FWPHY
PPBUS_S5_FW_FET
PCI_GNT3_L
MIN_LINE_WIDTH=0.38 mmVOLTAGE=3.3VPP3V3_FWPHY
MAKE_BASE=TRUEMIN_NECK_WIDTH=0.25 mm
PPBUS_S5_FW_FET
SMBUS_SMC_B_S0_SDA
MAKE_BASE=TRUEPCI_REQ3_L
PP3V3_FWPHY
PP3V3_FWPHY
PPBUS_S5_FW_FET
SMBUS_SMC_B_S0_SCL
SMBUS_SMC_B_S0_SDA
PPDCIN_G3H
PPDCIN_G3H
PPBUS_G3H
PP3V3_S0
=FW_PCI_IDSEL
PP5V_S0
PP3V3_S0
PP3V3_S0
PPFW_PORTB_VP_UFMAKE_BASE=TRUEPPFW_PORTA_VP_UF
PPDCIN_G3H
PPBUS_G3H
79
79
79
79 78
78
78
78 70
70
70
70 66
66
66
66
65
65
65
65 64
64
64
64 60
60
60
60 59
59
59
59 57
57
57
57 56
56
56
56 53
53
53
53 51
51
51
51 48
48
48
48 43
43
43
43 37
80
37
80
37
37 36
79
36
79
36
36 34
78
34
78
34
34 33
70
33
70
33
33 29
67
29
67
29
29 28
66
28
66
28
28 27
65
78
27
65
27
27
78
26
66 66
61
70
26
61
26
26
70
25
63 63
60
68
25
60
25
25
68
24
54 54
57
66
24
57
24
24
66
23
37 37
56
64
23
56
23
23
64
22
32 32
54
63
22
54
22
22
63
21
31 31
52
61
21
52
21
21
61
20
29 29
47
44
60
20
47
20
20
60
44
44
44
19
28 28
42
44 43
44
44
54
19
42
19
19
54
43
43
43
17
19
66
50
42
19
36
43
66
42
66
50
43
43
66
50
50
68
68
47
17
36
17
17
68
47
42
42
42
14
16
42
37
47
42
43
47
48
42 38
16
31
42
43
38
43
48
37
42
42
43
48
48
67
67
43
14
31
14
14
67
43
38
44
50
44
38
38
10
14
38
26
37
22
38
42
22
27
38 5
14
25
50
38
42
37
5
42
27
26
38
38
42
27
27
66
66
41
10
25
10
10
44
44
66
41
5
43
37
43
5
5
5
5
5
22
22
5
5
38
37
5
10
5 4
5
5
37
5
38
22
4
38
10
22
5
5
38
10
10
65
65
5
5
5
5
5
43
43
65
5
4
4
4
4
4
4
4
4
4
4
4
4
4
4
22
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
37
4
4
4
4
4
4
4
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
Request for at least 2 GND TPs per resistor
Camera Connector
FUNC_TEST
Resistor Calibration
(=PP3V3_S0_CK410)
FUNC_TEST
Left I/O Data ConnectorFUNC_TEST
FUNC_TEST
Functional Test Points
CPU FSB NO_TESTsNO_TEST
NO_TEST
EXPOSED_VIA
EXPOSED_VIA
EXPOSED_VIABattery Connector
FUNC_TEST
FUNC_TEST
Fan ConnectorsFUNC_TEST
FUNC_TEST
Left I/O Power Connector
FUNC_TEST
SMC TPs
Power Nets
Request for at least 10 GND TPs
LPC+ Debug Connector
Request for at least 10 GND test points
Thermal Sensors
Misc EXPOSED_VIA Nets
opening for use as engineering probe point.should have a via with 10-mil soldermaskEXPOSED_VIA property indicates that the net
FUNC_TEST
MAC-1 TPs
Characterization TPs
FUNC_TEST
FUNC_TEST
Power Supply NO_TESTs
(=PP1V2_S3_ENET)(=PP3V3_S3_ENET)(=PP2V5_S3_ENET)
I134
I135
I138
I139
I140
I141
I142
I143
I164
I165
I166
I167
I168
I169
I170
I171
I172
I173
I174
I175
I176
I177
I178
I179
I182
I183
I184
I185
I186
I187
I188
I189
I190
I191
I192
I193
I194
I195
I197
I198
I199
I200
I201
I202
I203
I204
I205
I206
I207
I208
I209
I210
I211
I212
I213
I214
I215
I216
I217
I218
I219
I220
I221
I222
I223
I224
I225
I226I227
I228
I229
I230
I231
I232
I233
I234
I235
I236
I237
I238
I239
I240
I241
I242
I243
I244
I245
I246
I247
I248
I249
I250
I251
I252
I253
I254
I255
I256
I257
I258
I259
I260
I261
I262
I263
I264
Functional / ICT Test
5 86
06051-7023
SYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)
TRUE PP2V5_S3TRUE PP2V5_S3_ENET_AVDD
TRUE PM_SLP_S5_LTRUE P1V5P1V05S0_PGOOD
PP3V3_S0_CK410_VDDATRUE
TRUE PP3V3_S5
TRUE PP5V_S3
IMVP_VR_ONTRUE
TRUE PM_SLP_S3_LTRUE PM_SLP_S3BATT
P1V8S3_FSETTRUE
PP3V3_S0_CK410_VDD_CPU_SRCTRUE
PP3V3_S0_CK410_VDD_PCITRUEPP3V3_S0_CK410_VDD48TRUE
PP3V3_S0_CK410_VDD_REFTRUE
TRUE PP3V3_S0PP2V5_S0_GPU_LVDDRTRUEPP2V5_S0_GPU_LPVDDTRUEPP2V5_S0_GPU_A2VDDTRUEPP2V5_S0_GPU_AVDDTRUEPP2V5_S0_GPU_TXVDDRTRUEPP2V5_S0_GPU_TPVDDTRUE
CPU_PWRGDTRUE
NB_SB_SYNC_LTRUEFSB_DPWR_LTRUEFSB_SLPCPU_LTRUEFSB_CPURST_LTRUEVR_PWRGOOD_DELAYTRUEVR_PWRGD_CK410TRUEPM_STPPCI_LTRUEPM_STPCPU_LTRUESB_RTC_RST_LTRUE
PM_RSMRST_LTRUEPM_SB_PWROKTRUE
PCI_RST_LTRUEPM_LAN_ENABLETRUECPU_DPSLP_LTRUEPM_DPRSLPVRTRUETP_CPU_CPUSLP_LTRUE
TRUE FSB_ADSTB_L<1..0>TRUE
TRUE FSB_BREQ0_L
TP_SB_SUS_CLKTRUECPU_THERMTRIP_RTRUE
GNDTRUEGNDTRUE
GNDTRUEGNDTRUENB_CLK100M_GCLKIN_NTRUENB_CLK100M_GCLKIN_PTRUECLK_NB_OE_LTRUE
TRUE FSB_CLK_NB_NTRUE FSB_CLK_NB_PTRUE CPU_STPCLK_L
TPM_LRESET_LTRUETRUE SMC_LRESET_LTRUE PEG_RESET_LTRUE PLT_RST_LTRUE PLT_RST_L
TRUE FSB_CLK_CPU_NIMVP6_VID<6..0>TRUE
TRUE CPU_DPRSTP_L
TRUE PM_SLP_S4_L
TRUE IMVP_DPRSLPVR
DMI_N2S_P<1..0>TRUEDMI_N2S_N<1..0>TRUE
SB_CLK100M_SATA_NTRUE
SV_SET_UPTRUE
PCI_CLK_PORT80_LPCTRUELPC_AD<2>TRUELPC_AD<3>TRUE
FWH_INIT_LTRUESMC_TX_LTRUE
TRUE SMC_MD1
SMC_TRST_LTRUEDEBUG_RST_LTRUE
BOOT_LPC_SPI_LTRUEPM_CLKRUN_LTRUE
TRUE LPC_FRAME_L
TRUE FAN_RT_PWM
TRUE LPC_AD<0>TRUE LPC_AD<1>
SMC_TMSTRUE
SMC_TDOTRUE
INT_SERIRQTRUEPM_SUS_STAT_LTRUE
TRUE SMC_TDISMC_TCKTRUE
SMC_NMITRUESMC_RX_LTRUE
ISENSE_CAL_ENTRUE
USB2_CAMERA_NTRUEUSB2_CAMERA_PTRUE
TRUE HSTHMSNS_DX_P
TRUE PP3V3_S3TRUE PP3V3_S0
TRUE PP1V8_S3
TRUE PP1V5_S0
PP0V9_S0TRUEPP1V05_S0TRUE
SMC_BC_ACOKTRUETRUE PCIE_WAKE_L
TRUE PP18V5_DCINTRUE PP5V_S5TRUE PP5V_S0_AUDIO_PWR
GND_AUDIO_PWRTRUE
TRUE PP1V8_S0
TRUE PP2V5_S0
TRUE PP5V_S0
TRUE PP5V_S5
TRUE GND
TRUE PP2V5_S3
TRUE PPBUS_G3H
PP1V05_S0TRUE
PPVCORE_S0_GPUTRUE
GNDTRUE
RSFSTHMSNS_D_PTRUE
P2V5S3_MODETRUE
FSB_DSTBN_L<3..0>TRUE TRUE
PP5V_S0TRUE
TRUE PP5V_S0
TRUE PP5V_S3
RSFSTHMSNS_D_NTRUE
P1V5S0_RUNSSTRUETRUE PP1V2_S0
PP1V2_S3TRUE
GPUBBP_ADJTRUE
P1V05S0_COMPTRUE
TRUE IMVP6_RBIAS
TRUE P1V2S3_RUNSS
PP3V42_G3HTRUE
TRUE PM_SYSRST_LTRUE SMC_ONOFF_L
TRUE HSTHMSNS_DX_N
GND_AUDIOTRUETRUE PP5V_S0_AUDIOTRUE PP3V42_G3H
PPBUS_G3HTRUE
TRUE P1V8S3_COMP
SMBUS_SMC_BSA_SDATRUE
TRUE SMC_BS_ALRT_L
P2V5S3_SHDNRTTRUE
P5VS5_RUNSSTRUE
SB_CLK100M_SATA_PTRUE
TRUE TRUE FSB_DSTBP_L<3..0>
TRUE FSB_HITM_LFSB_LOCK_LTRUE
TRUE FSB_REQ_L<4..0>
FSB_BNR_LTRUE
TRUE FSB_D_L<63..0>
FSB_ADS_LTRUEFSB_A_L<31..3>TRUE
TRUE PP5V_S0
TRUE FAN_LT_TACH
TRUE FAN_RT_TACH
P3V3S5_FSETTRUEP3V3S5_COMPTRUE
P1V2S3_RTTRUE
FSB_DBSY_LTRUE
FSB_HIT_LTRUE
FSB_DRDY_LTRUETRUE TRUE FSB_DINV_L<3..0>
TRUE GPUVCORE_FSET
SMBUS_SMC_BSA_SCLTRUE
BATT_POSTRUEBATT_NEGTRUE
PP1V5_S0TRUE
FAN_LT_PWMTRUE
TRUE ALS_GAINTRUE LTALS_OUTTRUE ACZ_SDATAIN<0>TRUE ACZ_SDATAOUTTRUE ACZ_BITCLKTRUE ACZ_RST_LTRUE EXCARD_OC_LTRUE LTUSB_OC_LTRUE LT2USB_OC_L
PM_SLP_S4_LTRUETRUE PM_SLP_S3_LS5V
TRUE SYS_ONEWIRE
TRUE SMC_EXCARD_CPTRUE MINI_CLKREQ_L
TRUE SMC_EXCARD_PWR_ENTRUE EXCARD_CLKREQ_L
TRUE LIO_PLT_RESET_LTRUE ACZ_SYNCTRUE USB2_LT_NTRUE USB2_LT_PTRUE USB2_EXCARD_NTRUE USB2_EXCARD_P
PCIE_EXCARD_R2D_C_PTRUETRUE PCIE_EXCARD_R2D_C_N
PCIE_EXCARD_D2R_PTRUETRUE PCIE_EXCARD_D2R_N
TRUE PCIE_CLK100M_EXCARD_P
TRUE PCIE_MINI_R2D_C_PPCIE_MINI_R2D_C_NTRUE
TRUE PCIE_MINI_D2R_NTRUE PCIE_MINI_D2R_PTRUE PCIE_CLK100M_MINI_P
SMBUS_SB_SCLTRUETRUE PCIE_CLK100M_MINI_N
SMBUS_SB_SDATRUE
GNDTRUE
TRUE USB2_LT2_P
TRUE PCIE_CLK100M_EXCARD_NTRUE USB2_LT2_N
TRUE PP3V3_S3ACTRUE PP1V2_S3TRUE PP1V95_FWPHY_PLLVDDTRUE PP1V95_FWPHY
PP3V3_FWPHY_PLLVDDTRUETRUE PP3V3_FWPHY_AVDDTRUE PP3V3_FWPHY
PP1V8_S3TRUE
PPVCORE_S0_CPUTRUE
TRUE SMBUS_SMC_0_S0_SCLTRUE SMBUS_SMC_0_S0_SDA
SMC_RST_LTRUETRUE FSB_CLK_CPU_P
TRUE GPUVCORE_COMP
TRUE P3V42G3H_FB
P1V05S0_FSETTRUE
79
79
78
78
70
70
66
66
65
65
64
64
60
60
59
59
57
57
56
56
53
53
51
51
48
48
43
43
37
37
80 80
80
80
36
36
79 79
79
79
34
34
78 78
78
78
33
33
66
70
66
70
70
70
29
29
64
67
64
67
67
67
28
28
54
66
54
66
66
66
27
80
27
34
65
78
34
65
65
78
65
26
66
26
66
25
61
70
25
61
61
68
68
70
61
78
25
64
25
63
66
24
60
68
24
60
60
67
67
68
60
66 66
24
63
24
54
65
21
70
57
70
66
21
57
57
66
66
66
57
65 65
23
62
23
37
47
19
67
56
67
64
19
56
56
65
65
64
56
47 64
22
59
22
32
25
17
66
54
66
63
17
54
54
54
54
63
54
25 62
65
21
65
58
21
31
24
16
65
52
65
61
16
52
52
52
52
61
52
24
65
55
64
20
63
56
20
29
19
13
64
77
47
64
60
13
47
47
51
51
60
47
19
63
47
47
26
80
54
19
50
51
19
28
17
12
63
76
42
63
54
12
42
42
80
50
50
54
42
17
50
45
45
25
66
50
17
47
59
45
17
19
16
11
68
61
66
36
61
47
11
76
36
36
66
76
45
45
47
36
16
47
33
33
44
66
66
24
61
43
14
86
86
26
26
46 59
59
52
59
59
59
59
59
52
41
14
16
13
66
9
67
51
65
31
51
66
43
9
71
31
31
61
69
66
35
54
35
43
31
13
51
46
29
29
66
43
60
53
62
51
65
23
51
39
10
86
86
12
60
86
60
86
86
86
22
22
60
41 52
52
51
52
52
52
52
52
52
52
52
52
51
52
52
52
45
45
37
10
14
9
65
8
51
47
46
66
62
25
46
62
41
8
70
86
25
25
51
66
62
27
50
51
27
41
67
67
86
86
86
86
86
86
86
86
25
86
86
86
86
67
9
50
86
86
86
86
47
47
47
41
65
51
51
47
47
86
47
47
47
47
49
49
49
49
28
28
47
47
66
62
42
42
54
53
50
52
39
40
50
64
22
45
60
32
5
21
22
12
12
11
26
26
33
33
26
50
26
37
50
21
23
12
12
23
34
34
33
34
34
21
59
50
69
14
14
34
60
21
23
86
22
22
34
52
52
50
50
50
51
52
52
52
50
50
50
50
50
51
51
50
50
51
51
52
51
54
22
22
32
5
5
8
31
7
50
39
25
65
19
5
25
39
5
7
66
12
5
5
45
65 65
39
62
26
26
50
26
5
50
51
65
34
12
12
12
12
12
12
12
12
5
12
12
12
12
50
68
68
8
47
56
47
47
47
47
22
22
22
23
61
50
50
34
50
34
47
47
22
22
22
22
49
49
47
47
47
49
49
47
47
47
27
47
27
22
47
22
41
39
38
38
9
50
45
51 34
5
39
23
60
33
11
5
50
23
41
63
33
33
33
33
4
77
77
77
77
77
7
14
7
7
7
14
23
23
23
21
23
23
22
23
7
14
21
7
7
6
21
14
14
14
12
12
7
26
26
26
5
5
7
9
7
5
60
14
14
21
23
34
21
21
21
50
50
50
26
22
23
21
57
21
21
50
50
23
23
50
50
50
50
50
6
6
53
27
4
4
5
30
5
47
23
67
5
67
67
63
17
4
5
5
4
5
54
53
62
7
4
4
5
53
61 62
5
70
64
60
41
5
23
45
53
47
47
5
4
63
27
50
62
61
21
7
7
7
7
7
7
7
7
4
57
57
64
64
62
7
7
7
7
70
27
67
67
5
57
6
47
21
21
21
21
6
6
4
5
47
47
47
33
47
33
26
21
6
6
6
6
47
47
22
22
34
47
47
22
22
34
23
34
23
6
34
6
39
5
38
4
38
38
4
8
27
27
50 7
70
65
64
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
USB Port "D" = Camera
USB Port "F" = IR Receiver
USB Port "C" = Left USB 2.0 Port
USB Port "G" = Bluetooth (M13P)
USB Port "A" (Debug Port) = Right USB 2.0 Port
USB Port "E" = ExpressCard
USB Port "B" = Trackpad (Geyser)
USB Port "H" = 2nd Left USB 2.0 Port
Chassis connection to be made at the mounting hole southwest of the USB connector
NOTE: NB_CFG<13..12> require test access
Ethernet Powr Management Support
"ENET_LOM_DISABLE" are mutually-exclusive.NOTE: BOM options "USB_G_OC_PU" and
Chassis connection to be made on FW shell
Chassis connection to be made at the mounting hole northwest of the DVI connector
Chassis connection to be made at the fan cutout near the right ALS
Chassis connection to be made at the mounting hole east of the LVDS connector
ZT06001
HOLE-VIA-P5RP25
ZT06031
HOLE-VIA-P5RP25
ZT06021
HOLE-VIA-P5RP25
SH06001
2
3
OG-503040SHLD-SM-LF
ZT06011
HOLE-VIA-P5RP25
R06001 2
0
5%1/16WMF-LF402
R06901 2
ENET_LOM_DISABLE
0
5%
402MF-LF1/16W
R06011 2
5%1/16W
0
402MF-LF
SH06011EMI-SPRING
0G-502620R
6 86
06051-7023
Signal AliasesSYNC_MASTER=(M1_MLB) SYNC_DATE=(11/11/2005)
NC_CPU_A35_LNO_TEST=TRUEMAKE_BASE=TRUE
NC_CPU_APM0_LNC_CPU_APM0_LMAKE_BASE=TRUENO_TEST=TRUE
NC_CPU_SPARE0
NC_CPU_SPARE4
NC_CPU_A37_L
NC_CPU_A34_LNO_TEST=TRUEMAKE_BASE=TRUE
NC_CPU_A33_LMAKE_BASE=TRUENO_TEST=TRUE
NC_CPU_A32_LNC_CPU_A32_LNO_TEST=TRUEMAKE_BASE=TRUE
NC_CPU_A33_L
MIN_LINE_WIDTH=0.5 mm
VOLTAGE=0VMAKE_BASE=TRUE
GND_CHASSIS_DVI_TOPMIN_NECK_WIDTH=0.25 mm
GND_CHASSIS_INVERTERGND_CHASSIS_INVERTER
MIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mmVOLTAGE=0VMAKE_BASE=TRUE
ENET_LOM_DIS_LSB_GPIO30
NO_TEST=TRUEMAKE_BASE=TRUENC_ENET_CTRL25 NC_ENET_CTRL25NO_TEST=TRUEMAKE_BASE=TRUENC_ENET_CTRL12 NC_ENET_CTRL12
RTALS_GAINMAKE_BASE=TRUE
ALS_GAIN RTALS_GAIN
TP_SB_SUS_CLK
MAKE_BASE=TRUETP_NB_CFG<13..12> NB_CFG<13..12>
MAKE_BASE=TRUETP_NB_CFG<17> NB_CFG<17>
MAKE_BASE=TRUETP_NB_CFG<15..14> NB_CFG<15..14>
MAKE_BASE=TRUETP_NB_CFG<11..10> NB_CFG<11..10>
MAKE_BASE=TRUETP_NB_CFG<8> NB_CFG<8>
MAKE_BASE=TRUETP_NB_CFG<6> NB_CFG<6>
MAKE_BASE=TRUETP_NB_CFG<4..3>
NO_TEST=TRUEMAKE_BASE=TRUENC_MEM_A_A<15..14>
NC_CPU_A36_LNO_TEST=TRUEMAKE_BASE=TRUE
NC_CPU_A39_LNO_TEST=TRUEMAKE_BASE=TRUE
NC_CPU_A36_L
GNDGND_CHASSIS_DVI_TOPGND_CHASSIS_DVI_TOP
GND_CHASSIS_USBGND_CHASSIS_USB
GND_CHASSIS_USB
GND_CHASSIS_DVI_BOT
GND_CHASSIS_DVI_BOTGND_CHASSIS_DVI_BOT
GND_CHASSIS_DVI_BOTGND_CHASSIS_DVI_BOT
GND_CHASSIS_USBMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.5 mm
VOLTAGE=0VMAKE_BASE=TRUE
GND_CHASSIS_DVI_BOTMIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mmVOLTAGE=0VMAKE_BASE=TRUE
MAKE_BASE=TRUEUSB2_LT2_N
MAKE_BASE=TRUEUSB2_LT2_P
USB2_LT2_N
USB2_LT2_P
VOLTAGE=0VMAKE_BASE=TRUE
MIN_LINE_WIDTH=0.5 mmGND_CHASSIS_LVDS
MIN_NECK_WIDTH=0.25 mmGND_CHASSIS_LVDS
NC_CPU_HFPLL
NC_CPU_EXTBREFNO_TEST=TRUEMAKE_BASE=TRUE
MAKE_BASE=TRUEUSB2_LT_N
USB2_LT_PMAKE_BASE=TRUE
USB_TRACKPAD_P
USB2_CAMERA_P
USB_IR_NMAKE_BASE=TRUE
USB_IR_PMAKE_BASE=TRUE
USB_IR_N
USB_BT_P
USB_BT_N
USB_IR_N
MAKE_BASE=TRUEUNUSED_USB_D_OC_L
NC_CPU_SPARE1
NC_CPU_SPARE2
NC_CPU_APM1_L
NC_CPU_A39_L
NC_CPU_A38_L
NC_CPU_A35_L
NC_CPU_A34_L
NC_CPU_SPARE4NO_TEST=TRUEMAKE_BASE=TRUE
NC_CPU_SPARE1NO_TEST=TRUEMAKE_BASE=TRUE
NC_CPU_SPARE2NO_TEST=TRUEMAKE_BASE=TRUE
NC_CPU_HFPLLMAKE_BASE=TRUENO_TEST=TRUE
NC_CPU_A38_LNO_TEST=TRUEMAKE_BASE=TRUE
NC_CPU_A37_LNO_TEST=TRUEMAKE_BASE=TRUE
GND_CHASSIS_LVDSGND_CHASSIS_LVDS
GND_CHASSIS_LVDS
MAKE_BASE=TRUEUSB2_RT_N
USB2_RT_PMAKE_BASE=TRUE
USB2_RT_P
USB2_RT_N
USB2_RT_P
USB2_RT_N
RTUSB_OC_L
USB_TRACKPAD_P
USB_TRACKPAD_N
UNUSED_USB_B_OC_LMAKE_BASE=TRUEUNUSED_USB_B_OC_L
USB2_LT_P
LTUSB_OC_L
USB2_LT_N
RTUSB_OC_LMAKE_BASE=TRUE
RTUSB_OC_L
MAKE_BASE=TRUEUSB_TRACKPAD_P
MAKE_BASE=TRUEUSB_TRACKPAD_NUSB_TRACKPAD_N
USB2_LT_P
USB2_CAMERA_N
UNUSED_USB_D_OC_L
EXCARD_OC_LMAKE_BASE=TRUEEXCARD_OC_L
USB2_EXCARD_N
USB_BT_N
USB_BT_P
MAKE_BASE=TRUEUSB2_CAMERA_PUSB2_CAMERA_P
USB2_CAMERA_NMAKE_BASE=TRUE
USB2_CAMERA_N
USB2_EXCARD_PMAKE_BASE=TRUE
MAKE_BASE=TRUEUSB2_EXCARD_N
USB_BT_PMAKE_BASE=TRUE
MAKE_BASE=TRUEUSB_BT_N
USB2_EXCARD_N
USB2_EXCARD_P USB2_EXCARD_P
USB2_LT_N
USB_IR_PUSB_IR_P
USB2_LT2_N
USB2_LT2_P
MAKE_BASE=TRUELTUSB_OC_L
GND_CHASSIS_FANFRAMEMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.5 mm
VOLTAGE=0V
NB_CFG<4..3>
MEM_B_A<15..14>
MEM_A_A<15..14>
NO_TEST=TRUEMAKE_BASE=TRUENC_MEM_B_A<15..14>
MAKE_BASE=TRUETP_SB_SUS_CLK
NC_CPU_SPARE0NO_TEST=TRUEMAKE_BASE=TRUE
NC_CPU_EXTBREF
NC_CPU_APM1_LNO_TEST=TRUEMAKE_BASE=TRUE
47
47
47
47
51 51
45
45
47
47
79
79
79
79
79
79
22
22
47
47
22
22
45
80
80
46
46
47
47
47
46
45
45
47
45
47 47
47
22 45
22 45
22
22
80
80
47
47 47
47
47
47
47
50
23
46
46
46
44
44
44
44
44
46
44
6
6
22
22
6
6
45
22
22
22
80
80
80
80
22
22 46
46
46
46
46
45
45
22
22
22
22 46
22
22 45
22
22
22 22
22
80
80
6 22
6 22
6
6
22
22
22
22 22
22
80 80
22
22
22
23
7
7 7
7
7
7
7
7
7 7
7
79
78
78
39 39
39 39
47 56
6
7
7
7
79
79
44
44
44
40
40
40
40
40
44
40
5
5
6
6
78
78
7
7
5
5
22
6
6
6
22
22
22
22
22
7
7
7
7
7
7
7
7
7
7
7
7
7
78
78
78
6
6 22
22
22
22
22
22
22
22 22
6
6
6
6 22
6
6 22
6
6
22
6 6
6
22
22
5 6
5 6
5
5
6
6
6
6 6
6
22 22
6
6
6
6
7
7
7
6
6 6
6
6
6
6
6
6 6
6
6
6
6
39 22
6 6
6 6
5 6
5
14
14
14
14
14
14
28
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
5
5
6
6
6
6
6
5
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6 6
5
5
5
6
6
5
5
6
5 5
5
6
6
5
5
5
5 5
5
6 6
5
5
5
14
29
5
6
6
6
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
IN
IN
IN
IN
IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
IN
IN
IN
IN
IN
IN
IN
IN
OUT
A7*
RSVD14
RSVD15
BCLK1
BCLK0
RSVD20
RSVD17
RSVD18
RSVD19
RSVD16
RSVD13
RSVD12
THERMTRIP*
THERMDC
THERMDA
PROCHOT*
DBR*
TRST*
TMS
TDO
TDI
TCK
PREQ*
PRDY*
BPM3*
BPM1*
BPM2*
BPM0*
HITM*
HIT*
TRDY*
RS2*
RS1*
RS0*
RESET*
LOCK*
INIT*
IERR*
BR0*
DBSY*
DRDY*
DEFER*
BPRI*
BNR*
ADS*
RSVD11
RSVD6
RSVD7
RSVD8
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD9
RSVD10
SMI*
LINT0
LINT1
STPCLK*
IGNNE*
FERR*
A20M*
ADSTB1*
A30*
A31*
A27*
A28*
A29*
A26*
A25*
A24*
A22*
A23*
A21*
A20*
A19*
A18*
A17*
REQ4*
REQ3*
REQ1*
REQ0*
REQ2*
ADSTB0*
A14*
A15*
A16*
A13*
A12*
A11*
A10*
A9*
A8*
A6*
A5*
A4*
A3*
(1 OF 4)
THERM
HCLK
RESERVED
ADDR GROUP1
ADDR GROUP0
CONTROL
XDP/ITP SIGNALS
PSI*
SLP*
PWRGOOD
DPRSTP*
DPSLP*
DPWR*
COMP2
COMP3
COMP1
COMP0
DSTBP3*
DSTBN3*
DINV3*
D63*
D62*
D61*
D60*
D59*
D58*
D57*
D56*
D55*
D54*
D52*
D53*
D51*
D50*
D49*
D48*
DINV2*
DSTBN2*
D47*
DSTBP2*
D45*
D46*
D44*
D43*
D42*
D41*
D40*
D39*
D38*
D37*
D36*
D35*
D34*
D33*
D32*
BSEL2
DSTBN1*
BSEL0
BSEL1
TEST2
TEST1
DINV1*
DSTBP1*
D31*
D30*
D29*
D26*
D27*
D28*
D24*
D25*
D23*
D21*
D22*
D20*
D19*
D18*
D16*
D17*
DINV0*
DSTBP0*
DSTBN0*
D15*
D14*
D13*
D12*
D11*
D10*
D9*
D8*
D7*
D6*
D5*
D4*
D3*
D2*
D1*
D0*
GTLREF
NC
(2 OF 4)
MISC
DATA GRP0
DATA GRP2
DATA GRP1
DATA GRP3
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
CPU IS HOTAND CPU VR TO INFORM
WITHOUT T-ING (NO
CHANGE THE PULLS RESISTOR VALUE PER NAPA PLATFORM DG REV 0.9
WE THROUGH THE ITP700FLEX CONNECTOR CONNECT TO PDB XDP BUFFER BOARD--ECM*50 SO THE TDI PULL UP THROUGH 54.9 OHM,TMS PULL UP THROUGH 54.9 OHM TCK PULL DOWN THROUGH 54.9 OHM(FOLLOW UP XDP DESIGN REFERENCE)
PLACE GND VIA W/IN 1000 MILS
FSB_IERR_L WITH A GNDPLACE TESTPOINT ON
LAYOUT NOTE: 0.5" MAX LENGTH
ICH7-M AND GMCH
TRACE LENGTH SHORTER THAN 0.5".
TRACE LENGTH SHORTER THAN 0.5".COMP0,2 CONNECT WITH ZO=27.4OHM, MAKELAYOUT NOTE:
COMP1,3 CONNECT WITH ZO=55OHM, MAKE
CPU_PROCHOT_L TO SMC
SHOULD CONNECT TOPM_THRMTRIP#
STUB)
SPARE[7-0],HFPLL:ROUTE TO TP VIA AND
0.1" AWAY
R07021
2
1%54.9MF-LF4021/16W
R07041
2
681/16W5%
402MF-LF
R07051
2
1KMF-LF402
1%1/16W
R07061
2
2.0KMF-LF402
1%1/16W
R07191 2
1%402
54.9
R07181 227.4
R07171 2
1% 402
54.9
R07161 227.4402
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 21 60
5 21 86
5 12 86
5 12
60
5 21 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
34
34
34
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
12 86
12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
5 12 86
11 86
11 86
11 86
11 86
11 86
11 86
11
11 26
10
14 21 51
21 86
5 11 12 86
12 86
12 86
12 86
12 86
7 11
7 11
7 11
11
10
5 34
5 34
21 86
21 86
21 86
21 86
5 21 86
21 86
21
R07301 2
NOSTUFF
402
0
R07071
2
1/16W5%
402MF-LF
1K
NOSTUFFR07121
2
511/16W5%
402MF-LF
R07031
2402MF-LF1/16W1%54.9
R07201 2
1%402
54.9
R07211 254.9
4021%
R07221 2
1%402
54.9
U0700
N3P5P2L1P4P1R1
Y2U5R3W6
A6
U4Y5U2R4T5T3W3W5Y4
J4
W2Y1
L4M3K5M1N2J1
H1
L2
V4
A22A21
E2
AD4AD3AD1AC4
G5
F1
C20
E1
H5F21
A5
G6E4
D20
C4
B3
C6B4
H4
AC2AC1
D21
K3H2K2J3L5
B1F3F4G3
AA1
C3
B25
T22
D2F6D3C1AF1D22C23
AA4
C24
AB2AA3M4N5T2V3B2
A3
D5
AC5AA6AB3
A24A25
C7
AB5
G2
AB6
OMIT
CPUYONAH
BGA
U0700
B22B23C21
R26U26U1V1
E22F24
J24J23H26F26K22H25
N22K25P26R23
E26
L25L22L23M23P25P22P23T24R24L26
H22
T25N24
AA23AB24V24V26W25U23U25U22
F23
AB25W22Y23AA26Y26Y22AC26AA24
AC22AC23
G25
AB22AA21AB21AC25AD20AE22AF23AD24AE21AD21
E25
AE25AF25AF22AF26
E23K24G24
J26
M26
V23
AC20
E5B5D24
H23
M24
W24
AD23
G22
N25
Y25
AE24
AD26A2
AE6
D6D7
C26
D25
OMIT
BGA
YONAHCPU
CPU 1 OF 2-FSBSYNC_MASTER=M1_MLB
7
06051-7023
86
SYNC_DATE=02/10/2006
FSB_BPRI_LFSB_BNR_LFSB_ADS_L
CPU_PSI_LFSB_SLPCPU_LCPU_PWRGD
CPU_DPRSTP_LCPU_DPSLP_LFSB_DPWR_L
CPU_COMP<2>CPU_COMP<3>
CPU_COMP<1>CPU_COMP<0>
FSB_DSTBP_L<3>FSB_DSTBN_L<3>
FSB_DINV_L<3>
FSB_D_L<63>FSB_D_L<62>FSB_D_L<61>FSB_D_L<60>FSB_D_L<59>FSB_D_L<58>FSB_D_L<57>FSB_D_L<56>FSB_D_L<55>FSB_D_L<54>
FSB_D_L<52>FSB_D_L<53>
FSB_D_L<51>FSB_D_L<50>FSB_D_L<49>FSB_D_L<48>FSB_DINV_L<2>
FSB_DSTBN_L<2>FSB_D_L<47>
FSB_DSTBP_L<2>
FSB_D_L<45>FSB_D_L<46>
FSB_D_L<44>FSB_D_L<43>FSB_D_L<42>FSB_D_L<41>FSB_D_L<40>FSB_D_L<39>FSB_D_L<38>FSB_D_L<37>FSB_D_L<36>FSB_D_L<35>FSB_D_L<34>FSB_D_L<33>FSB_D_L<32>
CPU_BSEL<2>
FSB_DSTBN_L<1>
CPU_BSEL<0>CPU_BSEL<1>
CPU_TEST2CPU_TEST1
FSB_DINV_L<1>FSB_DSTBP_L<1>
FSB_D_L<31>FSB_D_L<30>FSB_D_L<29>
FSB_D_L<26>FSB_D_L<27>FSB_D_L<28>
FSB_D_L<24>FSB_D_L<25>
FSB_D_L<23>
FSB_D_L<21>FSB_D_L<22>
FSB_D_L<20>FSB_D_L<19>FSB_D_L<18>
FSB_D_L<16>FSB_D_L<17>
FSB_DINV_L<0>FSB_DSTBP_L<0>FSB_DSTBN_L<0>FSB_D_L<15>FSB_D_L<14>FSB_D_L<13>FSB_D_L<12>FSB_D_L<11>FSB_D_L<10>FSB_D_L<9>FSB_D_L<8>FSB_D_L<7>FSB_D_L<6>FSB_D_L<5>FSB_D_L<4>FSB_D_L<3>FSB_D_L<2>FSB_D_L<1>FSB_D_L<0>
CPU_GTLREF
FSB_A_L<7>
NC_CPU_SPARE1NC_CPU_SPARE2
FSB_CLK_CPU_NFSB_CLK_CPU_P
TP_CPU_SPARE7
NC_CPU_SPARE4TP_CPU_SPARE5TP_CPU_SPARE6
TP_CPU_SPARE3
NC_CPU_SPARE0
NC_CPU_EXTBREF
PM_THRMTRIP_LCPU_THERMD_NCPU_THERMD_PCPU_PROCHOT_L
XDP_DBRESET_LXDP_TRST_LXDP_TMSXDP_TDOXDP_TDIXDP_TCK
XDP_BPM_L<4>XDP_BPM_L<3>XDP_BPM_L<2>
XDP_BPM_L<0>
FSB_CPURST_LFSB_LOCK_LCPU_INIT_LFSB_IERR_LFSB_BREQ0_L
FSB_DRDY_LFSB_DEFER_L
NC_CPU_HFPLL
NC_CPU_A37_LNC_CPU_A38_LNC_CPU_A39_L
NC_CPU_A32_LNC_CPU_A33_LNC_CPU_A34_LNC_CPU_A35_LNC_CPU_A36_L
NC_CPU_APM0_LNC_CPU_APM1_L
CPU_SMI_L
CPU_INTRCPU_NMI
CPU_STPCLK_LCPU_IGNNE_LCPU_FERR_LCPU_A20M_LFSB_ADSTB_L<1>
FSB_A_L<30>FSB_A_L<31>
FSB_A_L<27>FSB_A_L<28>FSB_A_L<29>
FSB_A_L<26>FSB_A_L<25>FSB_A_L<24>
FSB_A_L<22>FSB_A_L<23>
FSB_A_L<21>FSB_A_L<20>FSB_A_L<19>FSB_A_L<18>FSB_A_L<17>FSB_REQ_L<4>FSB_REQ_L<3>
FSB_REQ_L<1>FSB_REQ_L<0>
FSB_REQ_L<2>
FSB_ADSTB_L<0>
FSB_A_L<14>FSB_A_L<15>FSB_A_L<16>
FSB_A_L<13>FSB_A_L<12>FSB_A_L<11>FSB_A_L<10>FSB_A_L<9>FSB_A_L<8>
FSB_A_L<6>FSB_A_L<5>FSB_A_L<4>FSB_A_L<3>
XDP_TCK
XDP_TDI
XDP_TMS
PP1V05_S0
PP1V05_S0
PP1V05_S0
FSB_DBSY_L
XDP_BPM_L<1>
PP1V05_S0FSB_TRDY_LFSB_RS_L<2>
FSB_HIT_LFSB_HITM_L
XDP_BPM_L<5>
FSB_RS_L<1>FSB_RS_L<0>
66
66
66
66
64
64
64
64
54
54
54
54
34
34
34
34
25
25
25
25
24
24
24
24
21
21
21
21
19
19
19
19
17
17
17
17
16
16
16
16
13
13
13
13
12
12
12
12
11
11
11
11
9
9
9
9
8
8
8
8
11
11
11
7
7
7
7
86
86
86
86 86
6
6
6
6
6
86
6
6
6
6
6
6
6
6
6
6
6
7
7
7
5
5
5
5
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
VSS_82
VSS_83
VSS_84
VSS_85
VSS_87
VSS_86
VSS_88
VSS_89
VSS_90
VSS_92
VSS_91
VSS_93
VSS_94
VSS_95
VSS_97
VSS_96
VSS_100
VSS_98
VSS_99
VSS_102
VSS_101
VSS_105
VSS_103
VSS_104
VSS_106
VSS_107
VSS_110
VSS_109
VSS_108
VSS_111
VSS_112
VSS_115
VSS_114
VSS_113
VSS_116
VSS_117
VSS_118
VSS_120
VSS_119
VSS_123
VSS_121
VSS_122
VSS_124
VSS_125
VSS_128
VSS_126
VSS_127
VSS_129
VSS_130
VSS_133
VSS_131
VSS_132
VSS_134
VSS_135
VSS_138
VSS_136
VSS_137
VSS_139
VSS_140
VSS_141
VSS_143
VSS_142
VSS_146
VSS_144
VSS_145
VSS_147
VSS_148
VSS_151
VSS_150
VSS_149
VSS_152
VSS_153
VSS_156
VSS_155
VSS_154
VSS_157
VSS_158
VSS_159
VSS_161
VSS_160
VSS_162
VSS_1
VSS_2
VSS_3
VSS_5
VSS_4
VSS_6
VSS_7
VSS_8
VSS_10
VSS_9
VSS_11
VSS_12
VSS_15
VSS_13
VSS_14
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_23
VSS_22
VSS_21
VSS_24
VSS_25
VSS_28
VSS_27
VSS_26
VSS_29
VSS_30
VSS_33
VSS_32
VSS_31
VSS_34
VSS_35
VSS_38
VSS_37
VSS_36
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_46
VSS_44
VSS_45
VSS_47
VSS_48
VSS_51
VSS_49
VSS_50
VSS_52
VSS_53
VSS_56
VSS_54
VSS_55
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_63
VSS_62
VSS_64
VSS_65
VSS_66
VSS_69
VSS_68
VSS_67
VSS_70
VSS_71
VSS_74
VSS_73
VSS_72
VSS_75
VSS_76
VSS_79
VSS_78
VSS_77
VSS_80
VSS_81
(4 OF 4)
VCC_67
VCC_64
VCC_66
VCC_65
VCC_63
VCC_62
VCC_61
VCC_59
VCC_60
VCC_58
VCC_57
VCC_56
VCC_54
VCC_55
VCC_53
VCC_51
VCC_52
VCC_49
VCC_50
VCC_48
VCC_47
VCC_46
VCC_44
VCC_45
VCC_43
VCC_41
VCC_42
VCC_40
VCC_39
VCC_38
VCC_36
VCC_37
VCC_33
VCC_35
VCC_34
VCC_31
VCC_32
VCC_29
VCC_30
VCC_28
VCC_26
VCC_27
VCC_23
VCC_25
VCC_24
VCC_22
VCC_21
VCC_20
VCC_18
VCC_19
VCC_17
VCC_16
VCC_15
VCC_13
VCC_14
VCC_12
VCC_10
VCC_11
VCC_8
VCC_9
VCC_7
VCC_6
VCC_5
VCC_3
VCC_4
VCC_2
VCC_1 VCC_68
VCC_69
VCC_71
VCC_70
VCC_72
VCC_74
VCC_76
VCC_75
VCC_78
VCC_77
VCC_79
VCC_81
VCC_80
VCC_84
VCC_82
VCC_83
VCC_86
VCC_85
VCC_87
VCC_89
VCC_88
VCC_90
VCC_91
VCC_92
VCC_94
VCC_93
VCC_95
VCC_96
VCC_97
VCC_99
VCC_98
VCC_100
VCCP_1
VCCP_2
VCCP_3
VCCP_4
VCCP_5
VCCP_6
VCCP_7
VCCP_9
VCCP_8
VCCP_11
VCCP_10
VCCP_12
VCCP_13
VCCP_14
VCCP_16
VCCP_15
VCCA
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VSSSENSE
VCCSENSE
VCC_73(3 OF 4)
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
CPU_VCCSENSE_P/CPU_VCCSENSE_N USEZO=27.4 OHM DIFFERNTIAL TRACE ROUTING.
(CPU INTERNAL PLL POWER 1.5V)
TO TP_VSSSENSE WITH NO
LAYOUT NOTE:
PROVIDE A TEST POINT (WITH NO STUB)TO CONNECT A DIFFERENCTIAL PROBEBETWEEN VCCSENSE AND VSSSENSE AT THELOCATION WHERE THE TWO 54.9 OHM
SHOULD BE OF EQUAL LENGTHVCCSENSE AND VSSSENSE LINESLAYOUT NOTE:
STUB.
(CPU IO POWER 1.05V)
(CPU CORE POWER)
LAYOUT NOTE:
RESISTORS TERMINATE THE 55 OHMTRANSMISSION LINE
VID FOR CPU POWER SUPPLYIF NO USE, NEED PULL-UP ORPULL-DOWN
LAYOUT NOTE: CONNECT R0803
VCCA=1.5 ONLY
9 86
9 86
9 86
9 86
9 86
9 86
R08031
2
1/16W1%
402MF-LF
100
9 86
60 86
60 86
R08021
2
100MF-LF402
1%1/16W
U0700A4
B8
V25W1W4W23W26Y3Y6Y21Y24AA2
B11
AA5AA8AA11AA14AA16AA19AA22AA25AB1AB4
B13
AB8AB11AB13AB16AB19AB23AB26AC3AC6AC8
B16
AC11AC14AC16AC19AC21AC24AD2AD5AD8AD11
B19
AD13AD16AD19AD22AD25AE1AE4AE8AE11AE14
B21
AE16AE19AE23AE26AF3AF6AF8AF11AF13AF16
B24
AF19AF21AF24
C5C8
C11
A8
C14C16C19C2
C22C25D1D4D8
D11
A11
D13D16D19D23D26E3E6E8
E11E14
A14
E16E19E21E24F5F8
F11F13F16F19
A16
F2F22F25G4G1
G23G26H3H6
H21
A19
H24J2J5
J22J25K1K4
K23K26L3
A23
L6L21L24M2M5
M22M25N1N4
N23
A26
N26P3
P6P21P24R2R5R22R25T1
B6 T4T23T26U3U6U21U24V2V5V22
OMIT
BGA
YONAHCPU
U0700A7
B7
AF20
B9B10B12B14B15B17B18B20C9
A9
C10C12C13C15C17C18D9
D10D12D14
A10
D15D17D18E7E9
E10E12E13E15E17
A12
E18E20F7F9
F10F12F14F15F17F18
A13
F20AA7AA9
AA10AA12AA13AA15AA17AA18AA20
A15
AB9AC10AB10AB12AB14AB15AB17AB18
AB20AB7
A17
AC7AC9AC12AC13AC15AC17AC18AD7AD9AD10
A18
AD12AD14AD15AD17AD18AE9AE10AE12AE13AE15
A20
AE17AE18AE20AF9AF10AF12AF14AF15AF17AF18
B26
V6
N6R21R6T21T6V21W21
G21J6K6M6J21K21M21N21
AF7
AD6AF5AE5AF4AE3AF2AE2
AE7
OMIT
BGA
YONAHCPU
CPU 2 OF 2-PWR/GNDSYNC_MASTER=M1_MLB
051-7023 06
8 86
SYNC_DATE=02/10/2006
PPVCORE_S0_CPU
PP1V05_S0
PP1V5_S0
CPU_VID<0>CPU_VID<1>CPU_VID<2>CPU_VID<3>CPU_VID<4>CPU_VID<5>CPU_VID<6>
CPU_VCCSENSE_N
CPU_VCCSENSE_P
PPVCORE_S0_CPU
66 64 54 34 25 24 21 19 17 16
66
13
66
60
12
60
54
11
54
9
9
9
8
7
8
5
5
5
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
NOTE: This cap is shared
CPU VCORE HF AND BULK DECOUPLING
VCCP (CPU I/O) Decoupling
Will probably be removed before productionResistors to allow for override of CPU VID
CPU VCORE VID Connections4x 470uF. 20x 22uF 0805
1x 10uF, 1x 0.01uF
between CPU and NB
1x 470uF, 6x 0.1uF 0402
VCCA (CPU AVdd) Decoupling
C09061
2 6.3V20%
CERM805
22UFC09041
2 6.3V20%
CERM
22UF
805
C09161
2 6.3V20%
CERM
22UF
805
C09141
2 6.3V20%
CERM
22UF
805
C09081
2 6.3V20%
CERM
22UF
805
C09031
2 6.3V20%
CERM
22UF
805
C09071
2 6.3V20%
CERM
22UF
805
C09021
2 6.3V20%
CERM
22UF
805
C09011
2 6.3V20%
CERM805
22UF
C09131
2 6.3V20%
CERM805
22UFC09121
2 6.3V20%
CERM
22UF
805
C09111
2805
6.3V20%
CERM
22UFC09191
2 6.3V20%
CERM
22UF
805
C09001
2 6.3V20%
CERM
22UF
805
C09101
2
22UF6.3V20%
CERM805
C09361
2
0.1UF
CERM402
20%10V
C0935 1
2 3
D2TSPOLY
470uF-9MOHM20%
2.5V
CRITICAL
C09051
2 6.3V20%
CERM
22UF
805
C09091
2 6.3V20%
CERM
22UF
805
C09151
220%
CERM
22UF6.3V
805
C09171
2 6.3V20%
CERM
22UF
805
C09371
2
0.1UF
CERM402
20%10V
C09381
2
0.1UF
CERM402
20%10V
C09391
2
0.1UF
CERM402
20%10V
C09401
2
0.1UF
CERM402
20%10V
C09411
2
0.1UF
CERM402
20%10V
C09181
2
22UF
CERM
20%6.3V
805
C09501
23
D2TS
CRITICAL
470uF-8MOHM
POLY
20%2.5V
C09521
23
D2TS
CRITICAL
470uF-8MOHM
POLY
20%2.5V
C09531
23
D2TS
CRITICAL
470uF-8MOHM
POLY
20%2.5V
C09541
23
D2TS
CRITICAL
470uF-8MOHM
POLY
20%2.5V
C09811
2 16V
0.01UF
CERM402
20%
C0980 1
2X5R
10uF20%
6.3V
603
R09961 2
0
5%1/16WMF-LF402
R09951 2
0
5%1/16WMF-LF402
R09931 2
402MF-LF1/16W5%
0
R09941 2
402
1/16W5%
0
MF-LF
R09911 2
402MF-LF1/16W5%
0
R09921 2
402MF-LF1/16W5%
0
R09901 2
402MF-LF1/16W5%
0
CPU Decoupling & VID
051-7023
SYNC_DATE=02/08/2006SYNC_MASTER=M1_MLB
06
9 86
PP1V5_S0
PP1V05_S0
IMVP6_VID<1>
CPU_VID<6>
IMVP6_VID<4>CPU_VID<4>
IMVP6_VID<2>CPU_VID<2>
IMVP6_VID<0>CPU_VID<0>
IMVP6_VID<5>CPU_VID<5>
IMVP6_VID<3>CPU_VID<3>
CPU_VID<1>
IMVP6_VID<6>
PPVCORE_S0_CPU
66 64 54 34 25
66
24
65
21
47
19
25
17
24
16
19
13
17
12
66
16
11
60
13
8
54
8
7
60
86
60 86
60 86
60 86
60 86
60 86
86
60
8
5
5
5
8
5 8
5 8
5 8
5 8
5 8
8
5
5
D+
D-
ALERT*/
THM*
SCLK
SDATA
VDD
GND
THM2*
BI
BI
IN
OUT
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
PLACE U1001 NEAR THE U1200
ADD GND GUARD TRACE
CPU_THERMD_N ON SAMEFOR CPU_THERMD_P AND
10 MIL SPACING
LAYER.
10 MIL TRACE
ROUTE CPU_THERMD_P AND
CPU ZONE THERMAL SENSOR
LAYOUT NOTE:
CPU_THERMD_N
(TO CPU INTERNAL THERMAL DIODE)
LAYOUT NOTE:
PLACEHOLDER ADT7461A
U10016
2
3
5
8
7
4
1CRITICAL
MSOP
ADT7461
R10011 2
MF-LF
499
1/16W
402
1%
C10011
2 CERM50V
0.001uF10%
402
4 27 48 50
4 27 48 50
C10021
2 X5R
0.1UF16V10%
402
7
7
R10021 2499
1%
MF-LF402
1/16W
R10051
2
1/16W5%
402
10K
MF-LF
R10061
2
10K1/16W
402MF-LF
5%
051-7023 06
10 86
SYNC_MASTER=M1_MLB SYNC_DATE=02/10/2006
CPU MISC1-TEMP SENSOR
SMBUS_SMC_B_S0_SDASMBUS_SMC_B_S0_SCL
THRM_ALERT
THRM_ALERT_L
PP3V3_S0
CPU_THERMD_N
CPU_THERMD_PTHRM_CPU_DX_NTHRM_CPU_DX_P
79 78 70 66 65 64 60 59 57 56 53 51 48 43 37 36 34 33 29 28 27 26 25 24 23 22 21 20 19 17 14 5 4
53
53
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
BI
BI
BI
BI
BI
BI
OUT
IN
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
ITP TCK SIGNAL LAYOUT NOTE:
CONNECTOR’S FBO PIN.
518S0320
(TCK)
(FBO)
CPU ITP700FLEX DEBUG SUPPORT
(DEBUG PORT ACTIVE)(DBR#)
(DBA#)
NC
NC
NCTO ICH7M SYS_RST*, AND WITH SYSTEM RESET LOGIC(AND WITH RESET BUTTON)
(DEBUG PORT RESET)
(FROM CK410M HOST 133/167MHZ)
INDICATE THAT ITP IS USING TAP I/F, NC IN 945GM CHIPSET SYSTEM.
TCK PIN AND THEN FORK BACK FROM CPU TCK PIN AND ROUTE BACK TO ITP700FLEXROUTE THE TCK SIGNAL FROM ITP700FLEX CONNECTOR’S TCK PIN TO CPU’S
R11001 2
MF-LF
22.61%
1/16W402
ITP
R11021 2
ITP
402
1%
22.6
1/16WMF-LF
R11031
2
54.91/16W1%
402MF-LF
ITP
C11001
2402X5R16V10%0.1UF
R11041
2
1/16W240
402MF-LF5%
J1101
1
10111213141516171819
2
202122232425262728
29
3
30
456789
F-RT-SM52435-2872
CRITICALITPCONN
R11011
2
1/16W402
54.91%MF-LF
R11061
2
680
402
5%1/16WMF-LF
7
7
7
7 11
7 11
7
34 86
7 86
7 86
7 86
7 86
7 86
7 86
5 7 12 86
CPU ITP700FLEX DEBUGSYNC_DATE=02/10/2006
051-7023 06
11 86
SYNC_MASTER=M1_MLB
ITPRESET_L
XDP_DBRESET_L
ITP_TDO
CPU_XDP_CLK_PXDP_TCKXDP_BPM_L<5>XDP_BPM_L<4>XDP_BPM_L<3>XDP_BPM_L<2>XDP_BPM_L<1>
XDP_TRST_L
CPU_XDP_CLK_N
XDP_TMS
PP1V05_S0
PP3V3_S5
XDP_TDO
XDP_TDI
XDP_TCK
XDP_BPM_L<0>
FSB_CPURST_L
PP1V05_S0
66
66
64
64
54
54
34
34
25
25
24
78
24
21
66
21
19
65
19
17
64
17
16
62
16
13
55
13
12
26
12
11
25
11
9
24
9
8
23
8
7
22
7
86
5
5
5
BI
BI
BI
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
BI
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
IN
BI
IN
BI
BI
HD4*
HD6*
HD16*
HTRDY*
HSLPCPU*
HRS1*
HRS0*
HHITM*
HLOCK*
HHIT*
HDSTBP2*
HDTSBP3*
HDSTBP1*
HDSTBP0*
HDSTBN3*
HDSTBN1*
HDSTBN2*
HDSTBN0*
HDINV2*
HDINV3*
HDINV1*
HDINV0*
HDVREF
HDRDY*
HDPWR*
HDEFER*
HDBSY*
HCPURST*
HBREQ0*
HBPRI*
HBNR*
HAVREF
HCLKIN*
HCLKIN
HYSWING
HYRCOMP
HYSCOMP
HXSWING
HXSCOMP
HXRCOMP
HA13*
HADS*
HADSTB0*
HD3*
HD2*
HD1*
HD0*
HD63*
HD62*
HD61*
HD60*
HD59*
HD58*
HD57*
HD56*
HD55*
HD54*
HD53*
HD52*
HD51*
HD50*
HD49*
HD48*
HD47*
HD46*
HD45*
HD44*
HD43*
HD42*
HD41*
HD40*
HD39*
HD38*
HD37*
HD36*
HD35*
HD34*
HD33*
HD32*
HD31*
HD29*
HD28*
HD27*
HD26*
HD25*
HD24*
HD23*
HD22*
HD21*
HD20*
HD19*
HD18*
HD17*
HD15*
HD10*
HD11*
HD12*
HD13*
HD14*
HD5*
HD7*
HD8*
HD9*
HA30*
HA29*
HA28*
HA27*
HA26*
HA25*
HA24*
HA23*
HA31*
HA20*
HA19*
HA18*
HA16*
HA15*
HA14*
HA21*
HA22*
HA17*
HA9*
HA8*
HA7*
HA6*
HA5*
HA4*
HA3*
HA10*
HA11*
HA12*
HADSTB1*
HREQ0*
HREQ1*
HREQ2*
HREQ3*
HD30*
HREQ4*
HRS2*
(1 OF 10)
HOST
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
5 7 86
5 7 86
5 7 86
5 7 11 86
7 86
7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
C1211 1
2402X5R16V10%
0.1uFR12111
2
2001%1/16WMF-LF402
R12101
2
1001%1/16WMF-LF402
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
7 86
5 7 86
5 7
7 86
7 86
7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 34
5 7 86
5 34
R12201
2
54.91%
1/16WMF-LF
402
R12211
2402MF-LF1/16W
1%24.9
R12251
2
2211%1/16WMF-LF402
R12261
2
1%1/16WMF-LF402
100 C12261
2
0.1uF
402X5R16V10%
C12361
2402X5R16V10%0.1uF
R12351
2
2211%1/16WMF-LF402
R12301
2
54.91%
1/16WMF-LF
402
5 7 86
R12361
2
1%1/16WMF-LF402
100R12311
2402MF-LF1/16W
1%24.9
5 7 86
U1200
H11
J12
G14
D9
J14
H13
J15
F14
D12
A11
C11
A12
A13
E13
G13
F12
B12
B14
C12
A14
H9
C14
D14
C9
E11
G11
F11
G12
F9
E8
B9
C13
J13
C6
F6
C7
AG2
AG1
B7
F1
J1
K7
J8
H4
J3
K11
G4
T10
W11
T3
U7
H1
U9
U11
T11
W9
T1
T8
T4
W7
U5
T9
J6
W6
T5
AB7
AA9
W4
W3
Y3
Y7
W5
Y10
H3
AB8
W2
AA4
AA7
AA2
AA6
AA10
Y8
AA1
AB4
K2
AC9
AB11
AC11
AB3
AC2
AD1
AD9
AC1
AD7
AC6
G1
AB5
AD10
AD4
AC8
G2
K9
K1
A7
C3
J7
W8
U3
AB10
J9
H8
K4
T7
Y5
AC4
K3
T6
AA5
AC5
K13
D3
D4
B3
D8
G8
B8
F8
A8
B4
E6
D6
E3
E7
E1
E2
E4
Y1
U1
W1
BGA
NB945GM
OMIT
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
5 7 86
SYNC_MASTER=M1_MLB SYNC_DATE=02/10/2006
NB CPU Interface
06
12 86
051-7023
NB_FSB_XRCOMP
PP1V05_S0
PP1V05_S0
PP1V05_S0
FSB_RS_L<2>
FSB_REQ_L<4>
FSB_D_L<30>
FSB_REQ_L<3>FSB_REQ_L<2>FSB_REQ_L<1>FSB_REQ_L<0>
FSB_ADSTB_L<1>
FSB_A_L<12>FSB_A_L<11>FSB_A_L<10>
FSB_A_L<3>FSB_A_L<4>FSB_A_L<5>FSB_A_L<6>FSB_A_L<7>FSB_A_L<8>FSB_A_L<9>
FSB_A_L<17>
FSB_A_L<22>FSB_A_L<21>
FSB_A_L<14>FSB_A_L<15>FSB_A_L<16>
FSB_A_L<18>FSB_A_L<19>FSB_A_L<20>
FSB_A_L<31>
FSB_A_L<23>FSB_A_L<24>FSB_A_L<25>FSB_A_L<26>FSB_A_L<27>FSB_A_L<28>FSB_A_L<29>FSB_A_L<30>
FSB_D_L<14>FSB_D_L<13>FSB_D_L<12>FSB_D_L<11>
FSB_D_L<15>
FSB_D_L<18>FSB_D_L<19>FSB_D_L<20>FSB_D_L<21>FSB_D_L<22>FSB_D_L<23>FSB_D_L<24>FSB_D_L<25>FSB_D_L<26>FSB_D_L<27>FSB_D_L<28>FSB_D_L<29>
FSB_D_L<31>FSB_D_L<32>FSB_D_L<33>FSB_D_L<34>FSB_D_L<35>FSB_D_L<36>FSB_D_L<37>FSB_D_L<38>FSB_D_L<39>FSB_D_L<40>FSB_D_L<41>FSB_D_L<42>FSB_D_L<43>FSB_D_L<44>FSB_D_L<45>FSB_D_L<46>FSB_D_L<47>FSB_D_L<48>FSB_D_L<49>FSB_D_L<50>FSB_D_L<51>FSB_D_L<52>FSB_D_L<53>FSB_D_L<54>FSB_D_L<55>FSB_D_L<56>FSB_D_L<57>FSB_D_L<58>FSB_D_L<59>FSB_D_L<60>FSB_D_L<61>FSB_D_L<62>FSB_D_L<63>
FSB_ADSTB_L<0>FSB_ADS_L
FSB_A_L<13>
NB_FSB_XSCOMPNB_FSB_XSWING
NB_FSB_YSCOMPNB_FSB_YRCOMP
NB_FSB_YSWING
FSB_CLK_NB_PFSB_CLK_NB_N
FSB_BNR_LFSB_BPRI_LFSB_BREQ0_LFSB_CPURST_LFSB_DBSY_LFSB_DEFER_LFSB_DPWR_LFSB_DRDY_L
FSB_DINV_L<3>
FSB_DSTBN_L<1>
FSB_DSTBP_L<0>
FSB_HIT_L
FSB_LOCK_LFSB_HITM_L
FSB_RS_L<0>FSB_RS_L<1>
FSB_SLPCPU_LFSB_TRDY_L
FSB_D_L<16>
FSB_D_L<0>
FSB_D_L<3>
FSB_D_L<7>FSB_D_L<8>FSB_D_L<9>FSB_D_L<10>
FSB_D_L<6>FSB_D_L<5>FSB_D_L<4>
FSB_D_L<2>FSB_D_L<1>
NB_FSB_VREF
FSB_DINV_L<2>FSB_DINV_L<1>
FSB_DSTBN_L<0>
FSB_DINV_L<0>
FSB_DSTBP_L<3>FSB_DSTBP_L<2>FSB_DSTBP_L<1>
FSB_DSTBN_L<3>FSB_DSTBN_L<2>
FSB_D_L<17>
66
66
66
64
64
64
54
54
54
34
34
34
25
25
25
24
24
24
21
21
21
19
19
19
17
17
17
16
16
16
13
13
13
12
12
12
11
11
11
9
9
9
8
8
8
7
7
7
5
5
5
CRT_BLUE*
CRT_BLUE
CRT_GREEN*
CRT_GREEN
CRT_RED
CRT_DDC_CLK
CRT_RED*
HSYNC
CRT_DDC_DATA
CRT_VSYNC
CRT_IREF
TV_IRTNC
TV_IRTNB
TV_IREF
TV_IRTNA
TV_DACB_OUT
TV_DACC_OUT
TV_DACA_OUT
LB_DATA2
LB_DATA1
LB_DATA0
LB_DATA2*
LB_DATA1*
LB_DATA0*
LA_DATA2
LA_DATA1
LA_DATA0
LA_DATA2*
LA_DATA1*
LA_DATA0*
LB_CLK
LB_CLK*
LA_CLK
LA_CLK*
L_VDDEN
L_VREFL
L_VREFH
L_VBG
L_IBG
L_DDC_CLK
L_DDC_DATA
EXP_A_COMPI
EXP_A_COMPO
EXP_A_RXN0
EXP_A_RXN1
EXP_A_RXN2
EXP_A_RXN3
EXP_A_RXN4
EXP_A_RXN5
EXP_A_RXN6
EXP_A_RXN7
EXP_A_RXN8
EXP_A_RXN9
EXP_A_RXN10
EXP_A_RXN11
EXP_A_RXN12
EXP_A_RXN13
EXP_A_RXN15
EXP_A_RXN14
EXP_A_RXP0
EXP_A_RXP1
EXP_A_RXP2
EXP_A_RXP4
EXP_A_RXP3
EXP_A_RXP5
EXP_A_RXP6
EXP_A_RXP7
EXP_A_RXP10
EXP_A_RXP9
EXP_A_RXP8
EXP_A_RXP11
EXP_A_RXP12
EXP_A_RXP14
EXP_A_RXP13
EXP_A_RXP15
EXP_A_TXN1
EXP_A_TXN0
EXP_A_TXN3
EXP_A_TXN2
EXP_A_TXN6
EXP_A_TXN5
EXP_A_TXN4
EXP_A_TXN7
EXP_A_TXN8
EXP_A_TXN9
EXP_A_TXN10
EXP_A_TXN11
EXP_A_TXN12
EXP_A_TXN14
EXP_A_TXN13
EXP_A_TXN15
EXP_A_TXP0
EXP_A_TXP2
EXP_A_TXP1
EXP_A_TXP3
EXP_A_TXP4
EXP_A_TXP5
EXP_A_TXP7
EXP_A_TXP6
EXP_A_TXP8
EXP_A_TXP9
EXP_A_TXP10
EXP_A_TXP12
EXP_A_TXP11
EXP_A_TXP13
EXP_A_TXP14
EXP_A_TXP15
L_CLKCTLB
L_BKLTEN
L_CLKCTLA
L_BKLTCTL
(3 OF 10)
LVDS
TV
VGA
PCI-EXPRESS GRAPHICS
IN
IN
OUT
IN
OUT
OUT
OUT
OUT
IN
IN
OUT
OUT
OUT
OUT
IN
OUT
OUT
BI
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
BI
BI
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
Tie VCC_TXLVDS and VCCA_LVDS to GND. If SDVO is usedCan leave all signals NC if LVDS is not implemented
CRT Disable
TV-Out Disable
Composite: DACA only
TV-Out Signal Usage:
HSYNC and VSYNC to GND. Tie VCCA_CRTDAC to VCC Core
Unused DAC outputs must remain powered, but can omit
S-Video: DACB & DACC only
connect to GND through 75-ohm resistors.
Tie VCCD_TVDAC, VCCD_QTVDAC, VCCA_TVDACx, and
Component: DACA, DACB & DACC
rail, and tie VSSA_CRTDAC and VCC_SYNC to GND.
VCCA_TVBG to 1.5V power rail. Tie VSSA_TVBG to GND.
Tie DACx_OUT, IRTNx, and IREF to 1.5V power rail.
filtering components. Unused DAC outputs should
Tie R/R#/G/G#/B/B# and IREF to VCC Core rail, tie
VCCD_LVDS must remain powered with proper decoupling.
LVDS Disable
Otherwise, tie VCCD_LVDS to GND also.
SDVOC_CLKPSDVOC_BLUESDVOC_GREENSDVOC_RED
SDVOB_BLUESDVOB_CLKP
SDVOB_RED#SDVOB_GREEN#SDVOB_BLUE#SDVOB_CLKNSDVOC_RED#SDVOC_GREEN#SDVOC_BLUE#SDVOC_CLKN
SDVOB_REDSDVOB_GREEN
SDVO_FLDSTALLSDVO_INTSDVO_TVCLKIN
SDVO_INT#SDVO_TVCLKIN#
SDVO Alternate Function
SDVO_FLDSTALL#
U1200
E23
D23
C26
C25
C22
B22
J22
A21
B21
H23
D40
D38
F34
G38
V34
W38
Y34
AA38
AB34
AC38
H34
J38
L34
M38
N34
P38
R34
T38
D34
F38
T34
V38
W34
Y38
AA34
AB38
G34
H38
J34
L38
M34
N38
P34
R38
F36
G40
V36
W40
Y36
AA40
AB36
AC40
H36
J40
L36
M40
N36
P40
R36
T40
D36
F40
T36
V40
W36
Y40
AA36
AB40
G36
H40
J36
L40
M36
N40
P36
R40
G23
D32
J30
H30
H29
G26
G25
B38
C35
F32
C33
C32
A32
A33
B37
C37
B34
B35
A36
A37
E26
E27
F30
G30
D29
D30
F28
F29
A16
C18
A19
J20
B16
B18
B19
OMIT
945GMNBBGA
69
69
R13101
2
24.91%1/16WMF-LF402
19
69
5 8 9 13 16 17 19 24 25 47 65 66
5 8 9 13 16 17 19 24 25 47 65 66
5 8 9 13 16 17 19 24 25 47 65 66
5 8 9 13 16 17 19 24 25 47 65 66
19
19
5 7 8 9 11 12 13 16 17 19 21 24 25 34 54 64 66
5 7 8 9 11 12 13 16 17 19 21 24 25 34 54 64 66
69
5 7 8 9 11 12 13 16 17 19 21 24 25 34 54 64 66
5 7 8 9 11 12 13 16 17 19 21 24 25 34 54 64 66
19
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
19
19
19
19
69
19
19
19
19
19
19
19
19
69
19
19
19
19
19
19
19
19
19
19
69
5 8 9 13 16 17 19 24 25 47 65 66
5 8 9 13 16 17 19 24 25 47 65 66
5 8 9 13 16 17 19 24 25 47 65 66
5 7 8 9 11 12 13 16 17 19 21 24 25 34 54 64 66
5 7 8 9 11 12 13 16 17 19 21 24 25 34 54 64 66
5 7 8 9 11 12 13 16 17 19 21 24 25 34 54 64 66
19
19
NB PEG / Video InterfacesSYNC_DATE=02/10/2006SYNC_MASTER=M1_MLB
13 86
06051-7023
GND
GND
TP_LVDS_CLKCTLB
PP1V5_S0
TP_LVDS_BKLTCTL
TP_LVDS_CLKCTLATP_LVDS_BKLTEN
PEG_R2D_C_P<15>PEG_R2D_C_P<14>PEG_R2D_C_P<13>
PEG_R2D_C_P<11>PEG_R2D_C_P<12>
PEG_R2D_C_P<10>PEG_R2D_C_P<9>PEG_R2D_C_P<8>
PEG_R2D_C_P<6>PEG_R2D_C_P<7>
PEG_R2D_C_P<5>PEG_R2D_C_P<4>PEG_R2D_C_P<3>
PEG_R2D_C_P<1>PEG_R2D_C_P<2>
PEG_R2D_C_P<0>
PEG_R2D_C_N<15>
PEG_R2D_C_N<13>PEG_R2D_C_N<14>
PEG_R2D_C_N<12>PEG_R2D_C_N<11>PEG_R2D_C_N<10>PEG_R2D_C_N<9>PEG_R2D_C_N<8>PEG_R2D_C_N<7>
PEG_R2D_C_N<4>PEG_R2D_C_N<5>PEG_R2D_C_N<6>
PEG_R2D_C_N<2>PEG_R2D_C_N<3>
PEG_R2D_C_N<0>PEG_R2D_C_N<1>
PEG_D2R_P<15>
PEG_D2R_P<13>PEG_D2R_P<14>
PEG_D2R_P<12>PEG_D2R_P<11>
PEG_D2R_P<8>PEG_D2R_P<9>PEG_D2R_P<10>
PEG_D2R_P<7>PEG_D2R_P<6>PEG_D2R_P<5>
PEG_D2R_P<3>PEG_D2R_P<4>
PEG_D2R_P<2>PEG_D2R_P<1>PEG_D2R_P<0>
PEG_D2R_N<14>PEG_D2R_N<13>PEG_D2R_N<12>PEG_D2R_N<11>PEG_D2R_N<10>
PEG_D2R_N<8>
PEG_D2R_N<6>PEG_D2R_N<5>PEG_D2R_N<4>PEG_D2R_N<3>PEG_D2R_N<2>PEG_D2R_N<1>PEG_D2R_N<0>
PEG_COMP
TP_LVDS_DDC_DATATP_LVDS_DDC_CLK
NC_LVDS_IBGTP_LVDS_VBG
NC_LVDS_VREFHTP_LVDS_VREFL
TP_LVDS_VDDEN
NC_LVDS_A_CLKNNC_LVDS_A_CLKPNC_LVDS_B_CLKNNC_LVDS_B_CLKP
NC_LVDS_A_DATAN<0>NC_LVDS_A_DATAN<1>NC_LVDS_A_DATAN<2>
NC_LVDS_A_DATAP<0>NC_LVDS_A_DATAP<1>NC_LVDS_A_DATAP<2>
NC_LVDS_B_DATAN<0>NC_LVDS_B_DATAN<1>NC_LVDS_B_DATAN<2>
NC_LVDS_B_DATAP<0>NC_LVDS_B_DATAP<1>NC_LVDS_B_DATAP<2>
PP1V05_S0
TP_CRT_DDC_DATA
PP1V05_S0
TP_CRT_DDC_CLK
PP1V05_S0
PP1V05_S0PP1V05_S0
PP1V05_S0PP1V05_S0
PEG_D2R_N<15>
PEG_D2R_N<9>
PEG_D2R_N<7>
PP1V5_S0PP1V5_S0PP1V5_S0PP1V5_S0
PP1V5_S0PP1V5_S0PP1V5_S0
66 65 47 25 24 19 17 16 13 9 8 5
SM_CS0*RSVD15
RSVD14
SM_CKE2
RSVD2
RSVD3
RSVD6
RSVD4
RSVD5
RSVD8
RSVD7
RSVD9
RSVD1
RSVD10
RSVD11
RSVD12
RSVD13
CFG1
CFG0
CFG2
CFG3
CFG4
CFG6
CFG5
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG17
CFG16
CFG15
CFG18
CFG19
CFG20
PM_BM_BUSY*
PM_EXTTS0*
PM_EXTTS1*
PW_THRMTRIP*
PWROK
RSTIN*
SDVO_CTRLCLK
SDVO_CTRLDATA
ICH_SYNC*
CLK_REQ*
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC0
NC1
NC13
NC12
NC11
NC10
NC18
NC17
NC16
NC15
NC14
SM_CK0
SM_CK1
SM_CK2
SM_CK0*
SM_CK3
SM_CK1*
SM_CK2*
SM_CK3*
SM_CKE0
SM_CKE1
SM_CKE3
SM_CS1*
SM_CS2*
SM_CS3*
SMOCDCOMP0
SMOCDCOMP1
SM_ODT1
SM_ODT0
SM_ODT2
SMRCOMP*
SM_ODT3
SMRCOMP
SMVREF0
SMVREF1
G_CLKIN*
G_CLKIN
D_REFCLKIN*
D_REFCLKIN
D_REFSSCLKIN*
D_REFSSCLKIN
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI_TXP0
DMI_TXP2
DMI_TXP1
DMI_TXP3
DDR MUXING
CFG
NC
PM
CLK
DMI
MISC
(2 OF 10)
RSVD
IN
IN
IN
IN
IN
OUT
OUT
IN
IN
IN
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
NC
NC
NC
IPU
IPU
NCNC
IPUIPUIPUIPU
IPUIPUIPU
IPU
IPUIPU
IPU
IPU
IPD
IPU
NCNCNCNCNC
NC
NCNCNCNCNCNCNCNCNC
NCNC
NC
NCNCNC(D_PLLMON1#)
(VSS_MCHDETECT)
(H_PCREQ#)(H_PLLMON1#)(H_PLLMON1)
(TV_DCONSEL1)(TV_DCONSEL0)
(TESTIN#)(H_PROCHOT#)
(D_PLLMON1)(H_EDRDY#)
(LB_DATAP3)(LB_DATAN3)(LA_DATAP3)(LA_DATAN3)
IPD
IPD
NCNC
U1200
K16
K18
E16
D15
G15
K15
C15
H16
G18
H15
J25
K27
J18
J26
F18
E15
F15
E18
D19
D16
G16
H32
A26
A27
D41
C40
AE35
AF39
AG35
AH39
AC35
AE39
AF35
AG39
AE37
AF41
AG37
AH41
AC37
AE41
AF37
AG41
AG33
AF33
K28
D1
C41
B2
AY41
AY1
AW41
AW1
A40
A4
A39
A3
C1
BA41
BA40
BA39
BA3
BA2
BA1
B41
G28
F25
H26
G6
AH33
AH34
T32
J29
A41
A35
A34
D28
D27
R32
F3
F7
AG11
AF11
H7
J19
K30
H28
H27
AY35
AW35
AR1
AT1
AW7
AY7
AW40
AY40
AU20
AT20
BA29
AY29
AW13
AW12
AY21
AW21
BA13
BA12
AY20
AU21
AL20
AF10
AT9
AV9
AK1
AK41
BGANB
945GM
OMIT
6
6
20
R14301 2
402MF-LF1/16W5%
1005 22 26
R14411
2
10K
402
5%
MF-LF1/16W
R14401
2
10K
402
5%1/16WMF-LF
14 28 29 32
C14161
2
0.1uF
402CERM10V20%
C1415 1
2
0.1uF
402CERM10V20%
23
7 21 51
28 29 50 51
5 23 60 86
5 26 60
19
19
5 22
5 33
28
29
29
28
28
29
29
28
28 30
28 30
29 30
28 30
29 30
28 30
29 30
29 30
28 30
28 30
29 30
29 30
R14101
2
1/16W1%
402MF-LF
80.6
R14111
2
1/16W1%
402MF-LF
80.6
14 28 29 32
5 34
5 34
22
22
22
22
22
22
22
22
5 22
22
22
5 22
5 22
5 22
22
22
R14201
2
1/16W5%
402MF-LF
10K
34
34
34
20
20
6
20
6
6
6
6
6
6
20
6
20
6
20
NB Misc InterfacesSYNC_DATE=02/10/2006SYNC_MASTER=M1_MLB
051-7023 06
8614
PM_EXTTS_L
NB_RST_IN_L_R
CLK_NB_OE_L
GNDGNDGNDGND
PP3V3_S0
NB_TV_DCONSEL1NB_TV_DCONSEL0
NC_NB_XOR_LVDS_A35
TP_NB_TESTIN_L
PM_DPRSLPVR
PP3V3_S0
NB_CFG<18>
NB_CFG<13>
NB_CFG<11>
NB_CFG<8>
PLT_RST_L
DMI_N2S_P<3>
DMI_N2S_P<1>DMI_N2S_P<2>
DMI_N2S_P<0>
DMI_N2S_N<3>DMI_N2S_N<2>DMI_N2S_N<1>DMI_N2S_N<0>
DMI_S2N_P<3>DMI_S2N_P<2>DMI_S2N_P<1>DMI_S2N_P<0>
DMI_S2N_N<3>DMI_S2N_N<2>DMI_S2N_N<1>DMI_S2N_N<0>
NB_CLK100M_GCLKIN_PNB_CLK100M_GCLKIN_N
MEM_ODT<3>
MEM_ODT<0>
MEM_CKE<3>
MEM_CKE<1>MEM_CKE<0>
MEM_CLK_N<3>MEM_CLK_N<2>MEM_CLK_N<1>
MEM_CLK_P<3>
MEM_CLK_N<0>
MEM_CLK_P<2>MEM_CLK_P<1>MEM_CLK_P<0>
NB_SB_SYNC_LTP_SDVO_CTRLDATATP_SDVO_CTRLCLK
VR_PWRGOOD_DELAYPM_THRMTRIP_L
PM_BMBUSY_L
NB_CFG<20>NB_CFG<19>
TP_NB_CFG<15>NB_CFG<16>NB_CFG<17>
TP_NB_CFG<14>
NB_CFG<10>NB_CFG<9>
NB_CFG<7>
NB_CFG<5>NB_CFG<6>
NB_CFG<4>NB_CFG<3>NB_BSEL<2>
NB_BSEL<0>NB_BSEL<1>
MEM_CS_L<0>
NB_CFG<12>
MEM_ODT<2>MEM_ODT<1>
MEM_CS_L<3>MEM_CS_L<2>MEM_CS_L<1>
MEM_CKE<2>
PP1V8_S3
MEM_RCOMP_LMEM_RCOMP
MEMORY_VREFMEMORY_VREF
NC_NB_XOR_LVDS_A34NC_NB_XOR_LVDS_D28NC_NB_XOR_LVDS_D27
TP_NB_XOR_FSB2_H7
79
79
78
78
70
70
66
66
65
65
64
64
60
60
59
59
57
57
56
56
53
53
51
51
48
48
43
43
37
37
36
36
34
34
33
33
29
29
28
28
27
27
26
26
25
25
66
24
24
63
23
23
54
22
22
37
21
21
32
20
20
31
19
19
29
17
17
28
14
14
19
10
10
16
5
5
5
4
19
4
4
19
19
19
SA_DQ1
SA_DQ0
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ12
SA_DQ11
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ29
SA_DQ28
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ35
SA_DQ34
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ46
SA_DQ45
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63
SA_BS1
SA_BS0
SA_BS2
SA_CAS*
SA_DM0
SA_DM1
SA_DM2
SA_DM3
SA_DM5
SA_DM4
SA_DM7
SA_DM6
SA_DQS0
SA_DQS2
SA_DQS1
SA_DQS3
SA_DQS5
SA_DQS4
SA_DQS6
SA_DQS7
SA_DQS3*
SA_DQS2*
SA_DQS4*
SA_DQS5*
SA_DQS6*
SA_DQS7*
SA_MA1
SA_MA0
SA_MA2
SA_MA3
SA_MA5
SA_MA4
SA_MA6
SA_MA7
SA_MA9
SA_MA8
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_RAS*
SA_RCVENIN*
SA_RCVENOUT*
SA_WE*
SA_DQS1*
SA_DQS0*
(4 OF 10)
DDR SYSTEM MEMORY A
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
BI
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
SB_DQ1
SB_DQ0
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ12
SB_DQ11
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ29
SB_DQ28
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ35
SB_DQ34
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ46
SB_DQ45
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63
SB_BS1
SB_BS0
SB_BS2
SB_CAS*
SB_DM0
SB_DM1
SB_DM2
SB_DM3
SB_DM5
SB_DM4
SB_DM7
SB_DM6
SB_DQS0
SB_DQS2
SB_DQS1
SB_DQS3
SB_DQS5
SB_DQS4
SB_DQS6
SB_DQS7
SB_DQS3*
SB_DQS2*
SB_DQS4*
SB_DQS5*
SB_DQS6*
SB_DQS7*
SB_MA1
SB_MA0
SB_MA2
SB_MA3
SB_MA5
SB_MA4
SB_MA6
SB_MA7
SB_MA9
SB_MA8
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_RAS*
SB_RCVENIN*
SB_RCVENOUT*
SB_WE*
SB_DQS1*
SB_DQS0*
(5 OF 10)
DDR SYSTEM MEMORY B
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
NCNC
NCNC
U1200AU12
AV14
BA20
AY13
AJ33
AM35
AL26
AN22
AM14
AL9
AR3
AH4
AJ35
AJ34
AR31
AP31
AN38
AM36
AM34
AN33
AK26
AL27
AM26
AN24
AM31
AK28
AL28
AM24
AP26
AP23
AL22
AP21
AN20
AL23
AP24
AM33
AP20
AT21
AR12
AR14
AP13
AP12
AT13
AT12
AL14
AL12
AJ36
AK9
AN7
AK8
AK7
AP9
AN9
AT5
AL5
AY2
AW2
AK35
AP1
AN2
AV2
AT3
AN1
AL2
AG7
AF9
AG4
AF6
AJ32
AG9
AH6
AF4
AF8
AH31
AN35
AP33
AK33
AK32
AT33
AU33
AN28
AN27
AM22
AM21
AN12
AM12
AN8
AL8
AP3
AN3
AG5
AH5
AY16
AU14
AU13
AT17
AV20
AV12
AW16
BA16
BA17
AU16
AV17
AU17
AW17
AT16
AW14
AK23
AK24
AY14
OMIT
NB945GM
BGA
28
28
28
28
28
28
28
28
28
28
28
28
28
28
29
29
29
29
29
29
29
29
28 29
29
29
29
29
29
29
29
29
29
28
29
29
29
29
29
29
29
29
29
29
28
29
29
29
29
29
29
29
29
29
29
28
29
29
29
29
29
29
29
29
29
29
28
29
29
U1200AT24
AV23
AY28
AR24
AK36
AR38
AT36
BA31
AL17
AH8
BA5
AN4
AK39
AJ37
AU38
AV38
AP38
AR40
AW38
AY38
BA38
AV36
AR36
AP36
AP39
BA36
AU36
AP35
AP34
AY33
BA33
AT31
AU29
AU31
AW31
AR41
AV29
AW29
AM19
AL19
AP14
AN14
AN17
AM16
AP15
AL15
AJ38
AJ11
AH10
AJ9
AN10
AK13
AH11
AK10
AJ8
BA10
AW10
AK38
BA4
AW4
AY10
AY9
AW5
AY5
AV4
AR5
AK4
AK3
AN41
AT4
AK5
AJ5
AJ3
AP41
AT40
AV41
AM39
AM40
AT39
AU39
AU35
AT35
AR29
AP29
AR16
AP16
AR10
AT10
AR7
AT7
AN5
AP5
AY23
AW24
AV24
BA27
AY27
AR23
AY24
AR28
AT27
AT28
AU27
AV28
AV27
AW27
AU23
AK16
AK18
AR27
OMIT
NB945GM
BGA
29
29
29
29
29
29
29
28
29
29
29
29
29
29
29
29 30
29 30
29 30
28
29 30
29 30
29 30
29 30
29 30
29 30
29 30
29 30
29 30
29 30
28
29 30
29 30
29 30
29
29
29
29
29
29
29
28
29
29
29
29
29
29
29
29
29
29
28
29
29
29
29
29
29
29
29 30
29 30
29 30
28
29 30
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28 30
28 30
28 30
28
28 30
28
28 30
28 30
28 30
28 30
28 30
28 30
28 30
28
28 30
28 30
28 30
28 30
28 30
28 30
28 30
28 30
28 30
28
28
28
28
28
28
28
28
28
28
28
28
15 86
06051-7023
NB DDR2 InterfacesSYNC_MASTER=M1_MLB SYNC_DATE=02/10/2006
MEM_A_DQ<5>
MEM_A_DQS_N<0>MEM_A_DQS_N<1>
MEM_A_WE_L
MEM_A_RAS_L
MEM_A_A<13>MEM_A_A<12>MEM_A_A<11>MEM_A_A<10>
MEM_A_A<8>MEM_A_A<9>
MEM_A_A<7>MEM_A_A<6>
MEM_A_A<4>MEM_A_A<5>
MEM_A_A<3>MEM_A_A<2>
MEM_A_A<0>MEM_A_A<1>
MEM_A_DQS_N<7>MEM_A_DQS_N<6>MEM_A_DQS_N<5>MEM_A_DQS_N<4>
MEM_A_DQS_N<2>MEM_A_DQS_N<3>
MEM_A_DQS_P<7>MEM_A_DQS_P<6>
MEM_A_DQS_P<4>MEM_A_DQS_P<5>
MEM_A_DQS_P<3>
MEM_A_DQS_P<1>MEM_A_DQS_P<2>
MEM_A_DQS_P<0>
MEM_A_DM<6>MEM_A_DM<7>
MEM_A_DM<4>MEM_A_DM<5>
MEM_A_DM<3>MEM_A_DM<2>MEM_A_DM<1>MEM_A_DM<0>MEM_A_CAS_L
MEM_A_BS<2>
MEM_A_BS<0>MEM_A_BS<1>
MEM_A_DQ<63>MEM_A_DQ<62>MEM_A_DQ<61>MEM_A_DQ<60>MEM_A_DQ<59>MEM_A_DQ<58>MEM_A_DQ<57>MEM_A_DQ<56>MEM_A_DQ<55>MEM_A_DQ<54>MEM_A_DQ<53>MEM_A_DQ<52>MEM_A_DQ<51>MEM_A_DQ<50>MEM_A_DQ<49>MEM_A_DQ<48>MEM_A_DQ<47>
MEM_A_DQ<45>MEM_A_DQ<46>
MEM_A_DQ<44>MEM_A_DQ<43>MEM_A_DQ<42>MEM_A_DQ<41>MEM_A_DQ<40>MEM_A_DQ<39>MEM_A_DQ<38>MEM_A_DQ<37>MEM_A_DQ<36>
MEM_A_DQ<34>MEM_A_DQ<35>
MEM_A_DQ<33>MEM_A_DQ<32>MEM_A_DQ<31>MEM_A_DQ<30>
MEM_A_DQ<28>MEM_A_DQ<29>
MEM_A_DQ<27>MEM_A_DQ<26>MEM_A_DQ<25>MEM_A_DQ<24>MEM_A_DQ<23>MEM_A_DQ<22>MEM_A_DQ<21>MEM_A_DQ<20>MEM_A_DQ<19>MEM_A_DQ<18>MEM_A_DQ<17>MEM_A_DQ<16>MEM_A_DQ<15>MEM_A_DQ<14>MEM_A_DQ<13>
MEM_A_DQ<11>MEM_A_DQ<12>
MEM_A_DQ<10>MEM_A_DQ<9>MEM_A_DQ<8>MEM_A_DQ<7>MEM_A_DQ<6>
MEM_A_DQ<4>MEM_A_DQ<3>MEM_A_DQ<2>
MEM_A_DQ<0>MEM_A_DQ<1>
MEM_B_DQS_N<0>MEM_B_DQS_N<1>
MEM_B_WE_L
MEM_B_RAS_L
MEM_B_A<13>MEM_B_A<12>MEM_B_A<11>MEM_B_A<10>
MEM_B_A<8>MEM_B_A<9>
MEM_B_A<7>MEM_B_A<6>
MEM_B_A<4>MEM_B_A<5>
MEM_B_A<3>MEM_B_A<2>
MEM_B_A<0>MEM_B_A<1>
MEM_B_DQS_N<7>MEM_B_DQS_N<6>MEM_B_DQS_N<5>MEM_B_DQS_N<4>
MEM_B_DQS_N<2>MEM_B_DQS_N<3>
MEM_B_DQS_P<7>MEM_B_DQS_P<6>
MEM_B_DQS_P<4>MEM_B_DQS_P<5>
MEM_B_DQS_P<3>
MEM_B_DQS_P<1>MEM_B_DQS_P<2>
MEM_B_DQS_P<0>
MEM_B_DM<6>MEM_B_DM<7>
MEM_B_DM<4>MEM_B_DM<5>
MEM_B_DM<3>MEM_B_DM<2>MEM_B_DM<1>MEM_B_DM<0>MEM_B_CAS_L
MEM_B_BS<2>
MEM_B_BS<0>MEM_B_BS<1>
MEM_B_DQ<63>MEM_B_DQ<62>MEM_B_DQ<61>MEM_B_DQ<60>MEM_B_DQ<59>MEM_B_DQ<58>MEM_B_DQ<57>MEM_B_DQ<56>MEM_B_DQ<55>MEM_B_DQ<54>MEM_B_DQ<53>MEM_B_DQ<52>MEM_B_DQ<51>MEM_B_DQ<50>MEM_B_DQ<49>MEM_B_DQ<48>MEM_B_DQ<47>
MEM_B_DQ<45>MEM_B_DQ<46>
MEM_B_DQ<44>MEM_B_DQ<43>MEM_B_DQ<42>MEM_B_DQ<41>MEM_B_DQ<40>MEM_B_DQ<39>MEM_B_DQ<38>MEM_B_DQ<37>MEM_B_DQ<36>
MEM_B_DQ<34>MEM_B_DQ<35>
MEM_B_DQ<33>MEM_B_DQ<32>MEM_B_DQ<31>MEM_B_DQ<30>
MEM_B_DQ<28>MEM_B_DQ<29>
MEM_B_DQ<27>MEM_B_DQ<26>MEM_B_DQ<25>MEM_B_DQ<24>MEM_B_DQ<23>MEM_B_DQ<22>MEM_B_DQ<21>MEM_B_DQ<20>MEM_B_DQ<19>MEM_B_DQ<18>MEM_B_DQ<17>MEM_B_DQ<16>MEM_B_DQ<15>MEM_B_DQ<14>MEM_B_DQ<13>
MEM_B_DQ<11>MEM_B_DQ<12>
MEM_B_DQ<10>MEM_B_DQ<9>MEM_B_DQ<8>MEM_B_DQ<7>MEM_B_DQ<6>MEM_B_DQ<5>MEM_B_DQ<4>MEM_B_DQ<3>MEM_B_DQ<2>
MEM_B_DQ<0>MEM_B_DQ<1>
VCC_SM19
VCC_SM107
VCC_SM105
VCC_SM106
VCC_SM102
VCC_SM104
VCC_SM103
VCC_SM100
VCC_SM101
VCC_SM98
VCC_SM99
VCC_SM97
VCC_SM95
VCC_SM96
VCC_SM93
VCC_SM94
VCC_SM92
VCC_SM91
VCC_SM90
VCC_SM89
VCC_SM88
VCC_SM86
VCC_SM87
VCC_SM85
VCC_SM84
VCC_SM83
VCC_SM81
VCC_SM80
VCC_SM82
VCC_SM79
VCC_SM78
VCC_SM77
VCC_SM74
VCC_SM75
VCC_SM76
VCC_SM73
VCC_SM72
VCC_SM70
VCC_SM71
VCC_SM68
VCC_SM67
VCC_SM69
VCC_SM65
VCC_SM66
VCC_SM64
VCC_SM63
VCC_SM62
VCC_SM61
VCC_SM60
VCC_SM59
VCC_SM58
VCC_SM56
VCC_SM57
VCC_SM55
VCC_SM53
VCC_SM54
VCC_SM52
VCC_SM50
VCC_SM51
VCC_SM49
VCC_SM48
VCC_SM46
VCC_SM47
VCC_SM44
VCC_SM45
VCC_SM43
VCC_SM41
VCC_SM42
VCC_SM40
VCC_SM39
VCC_SM37
VCC_SM38
VCC_SM36
VCC_SM34
VCC_SM35
VCC_SM32
VCC_SM33
VCC_SM30
VCC_SM31
VCC_SM28
VCC_SM29
VCC_SM27
VCC_SM26
VCC_SM25
VCC_SM23
VCC_SM24
VCC_SM22
VCC_SM21
VCC_SM20
VCC_SM18
VCC_SM16
VCC_SM17
VCC_SM15
VCC_SM13
VCC_SM14
VCC_SM11
VCC_SM12
VCC_SM10
VCC_SM9
VCC_SM8
VCC_SM7
VCC_SM6
VCC_SM5
VCC_SM4
VCC_SM3
VCC_SM0
VCC_SM1
VCC_SM2
VCC_110
VCC_109
VCC_108
VCC_105
VCC_106
VCC_107
VCC_104
VCC_103
VCC_101
VCC_100
VCC_102
VCC_98
VCC_99
VCC_96
VCC_97
VCC_95
VCC_94
VCC_93
VCC_92
VCC_91
VCC_90
VCC_88
VCC_89
VCC_87
VCC_86
VCC_85
VCC_83
VCC_84
VCC_82
VCC_80
VCC_81
VCC_79
VCC_78
VCC_76
VCC_77
VCC_74
VCC_73
VCC_75
VCC_72
VCC_71
VCC_70
VCC_69
VCC_68
VCC_67
VCC_66
VCC_65
VCC_64
VCC_62
VCC_63
VCC_61
VCC_60
VCC_59
VCC_57
VCC_58
VCC_55
VCC_56
VCC_53
VCC_54
VCC_52
VCC_50
VCC_51
VCC_49
VCC_46
VCC_47
VCC_48
VCC_44
VCC_45
VCC_43
VCC_42
VCC_41
VCC_40
VCC_39
VCC_38
VCC_37
VCC_36
VCC_34
VCC_35
VCC_33
VCC_32
VCC_31
VCC_30
VCC_28
VCC_29
VCC_25
VCC_26
VCC_27
VCC_24
VCC_23
VCC_21
VCC_20
VCC_22
VCC_13
VCC_14
VCC_12
VCC_16
VCC_15
VCC_17
VCC_18
VCC_19
VCC_11
VCC_10
VCC_9
VCC_8
VCC_7
VCC_4
VCC_5
VCC_6
VCC_2
VCC_3
VCC_0
VCC_1
(6 OF 10)
VCC
VCCAUX_NCTF57
VCCAUX_NCTF56
VCCAUX_NCTF55
VCCAUX_NCTF54
VCCAUX_NCTF53
VCCAUX_NCTF52
VCCAUX_NCTF51
VCCAUX_NCTF50
VCCAUX_NCTF49
VCCAUX_NCTF47
VCCAUX_NCTF48
VCCAUX_NCTF45
VCCAUX_NCTF44
VCCAUX_NCTF46
VCCAUX_NCTF40
VCCAUX_NCTF39
VCCAUX_NCTF37
VCCAUX_NCTF38
VCCAUX_NCTF36
VCCAUX_NCTF34
VCCAUX_NCTF35
VCCAUX_NCTF32
VCCAUX_NCTF33
VCCAUX_NCTF31
VCCAUX_NCTF30
VCCAUX_NCTF29
VCCAUX_NCTF27
VCCAUX_NCTF28
VCCAUX_NCTF26
VCCAUX_NCTF24
VCCAUX_NCTF25
VCCAUX_NCTF22
VCCAUX_NCTF21
VCCAUX_NCTF23
VCCAUX_NCTF42
VCCAUX_NCTF43
VCCAUX_NCTF41
VCCAUX_NCTF19
VCCAUX_NCTF20
VCCAUX_NCTF18
VCCAUX_NCTF17
VCCAUX_NCTF16
VCCAUX_NCTF14
VCCAUX_NCTF15
VCCAUX_NCTF13
VCCAUX_NCTF12
VCCAUX_NCTF11
VCCAUX_NCTF9
VCCAUX_NCTF10
VCCAUX_NCTF8
VCCAUX_NCTF7
VCCAUX_NCTF6
VCCAUX_NCTF5
VCCAUX_NCTF4
VCCAUX_NCTF3
VCCAUX_NCTF1
VCCAUX_NCTF0
VCCAUX_NCTF2
VSS_NCTF12
VSS_NCTF11
VSS_NCTF10
VSS_NCTF9
VSS_NCTF7
VSS_NCTF8
VSS_NCTF5
VSS_NCTF6
VSS_NCTF4
VSS_NCTF2
VSS_NCTF3
VSS_NCTF0
VSS_NCTF1
VCC_NCTF72
VCC_NCTF71
VCC_NCTF70
VCC_NCTF69
VCC_NCTF68
VCC_NCTF67
VCC_NCTF66
VCC_NCTF65
VCC_NCTF64
VCC_NCTF61
VCC_NCTF62
VCC_NCTF63
VCC_NCTF60
VCC_NCTF57
VCC_NCTF58
VCC_NCTF59
VCC_NCTF56
VCC_NCTF55
VCC_NCTF53
VCC_NCTF54
VCC_NCTF52
VCC_NCTF50
VCC_NCTF51
VCC_NCTF49
VCC_NCTF48
VCC_NCTF46
VCC_NCTF47
VCC_NCTF45
VCC_NCTF44
VCC_NCTF43
VCC_NCTF41
VCC_NCTF40
VCC_NCTF42
VCC_NCTF38
VCC_NCTF39
VCC_NCTF36
VCC_NCTF37
VCC_NCTF34
VCC_NCTF35
VCC_NCTF33
VCC_NCTF31
VCC_NCTF32
VCC_NCTF30
VCC_NCTF29
VCC_NCTF28
VCC_NCTF27
VCC_NCTF26
VCC_NCTF25
VCC_NCTF24
VCC_NCTF23
VCC_NCTF22
VCC_NCTF21
VCC_NCTF20
VCC_NCTF18
VCC_NCTF19
VCC_NCTF17
VCC_NCTF16
VCC_NCTF15
VCC_NCTF13
VCC_NCTF14
VCC_NCTF11
VCC_NCTF12
VCC_NCTF10
VCC_NCTF8
VCC_NCTF9
VCC_NCTF7
VCC_NCTF6
VCC_NCTF5
VCC_NCTF4
VCC_NCTF3
VCC_NCTF2
VCC_NCTF0
VCC_NCTF1
(7 OF 10)
NCTF
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
1.8V Max CurrentSpeed 1 Channel 2 Channel400MTs 1300mA 2400mA533MTs 1500mA 2800mA667MTs 1700mA 3200mA
1.05V, Internal Graphics: 3500mA Max
1.5V, Internal Graphics: 5500mA Max1.05V, External Graphics: 1500mA Max
1.05V or 1.5V
Place in cavityLayout Note:
Layout Note:Place near pin BA15
Place near pin BA23Layout Note:
impacting part performance.These connections can break without
NCTF balls are Not Critical To Function
U1200
AA33
W33
P32
M19
L19
N18
M18
L18
P17
N17
M17
N16
M16
N32
L16
M32
L32
J32
AA31
W31
V31
T31
R31
P33
P31
N31
M31
AA30
Y30
W30
V30
U30
T30
R30
N33
P30
N30
M30
L30
AA29
Y29
W29
V29
U29
R29
L33
P29
M29
L29
AB28
AA28
Y28
V28
U28
T28
R28
J33
P28
N28
M28
L28
P27
N27
M27
L27
P26
N26
AA32
L26
N25
M25
L25
P24
N24
M24
AB23
AA23
Y23
Y32
P23
N23
M23
L23
AC22
AB22
Y22
W22
P22
N22
W32
M22
L22
AC21
AA21
W21
N21
M21
L21
AC20
AB20
V32
Y20
W20
P20
N20
M20
L20
AB19
AA19
Y19
N19
AU41
AT41
AR34
AR6
AP6
AN6
AL6
AK6
AJ6
AV1
AJ1
BA30
AY30
AW30
AV30
AU30
AT30
AR30
AP30
AN30
AM41
AM30
AM29
AL29
AK29
AJ29
AH29
AJ28
AH28
AJ27
AH27
AU40
BA26
AY26
AW26
AV26
AU26
AT26
AR26
AJ26
AH26
AJ25
BA34
AH25
AJ24
AH24
BA23
AJ23
BA22
AY22
AW22
AV22
AU22
AY34
AT22
AR22
AP22
AK22
AJ22
AK21
AK20
BA19
AY19
AW19
AW34
AV19
AU19
AT19
AR19
AP19
AK19
AJ19
AJ18
AJ17
AH17
AV34
AJ16
AH16
BA15
AY15
AW15
AV15
AU15
AT15
AR15
AJ15
AU34
AJ14
AJ13
AH13
AK12
AJ12
AH12
AG12
AK11
BA8
AY8
AT34
AW8
AV8
AT8
AR8
AP8
BA6
AY6
AW6
AV6
AT6
BGA
NB
945GM
OMIT
C16101
2402
6.3VCERM-X5R
0.47uF20%
C16211
2603
20%
X5R6.3V
10uFC1620 1
2
10uF6.3VX5R
20%
603
U1200AD27
AC27
AD26
AC26
AB26
AA26
Y26
W26
V26
U26
T26
R26
AB27
AD25
AC25
AB25
AA25
Y25
W25
V25
U25
T25
R25
AA27
AD24
AC24
AB24
AA24
Y24
W24
V24
U24
T24
R24
Y27
AD23
V23
U23
T23
R23
AD22
V22
U22
T22
R22
W27
AD21
V21
U21
T21
R21
AD20
V20
U20
T20
R20
V27
AD19
V19
U19
T19
AD18
AC18
AB18
AA18
Y18
W18
U27
V18
U18
T18
T27
R27
AG27
AF27
AG22
AF22
AG21
AF21
AG20
AF20
AG19
AF19
R19
AG18
AG26
AF18
R18
AG17
AF17
AE17
AD17
AB17
AA17
W17
V17
AF26
T17
R17
AG16
AF16
AE16
AD16
AC16
AB16
AA16
Y16
AG25
W16
V16
U16
T16
R16
AG15
AF15
AE15
AD15
AC15
AF25
AB15
AA15
Y15
W15
V15
U15
T15
R15
AG24
AF24
AG23
AF23
AE27
AE26
AC17
Y17
U17
AE25
AE24
AE23
AE22
AE21
AE20
AE19
AE18
945GMNBBGA
OMIT
C16111
2402
6.3VCERM-X5R
0.47uF20%
C1612 1
2402
6.3VCERM-X5R
0.47uF20%
C16131
2402
6.3VCERM-X5R
20%0.47uF
C1614 1
2402
6.3VCERM-X5R
20%0.47uF
C16151
2402
6.3VCERM-X5R
20%0.47uF
NB Power 1SYNC_DATE=02/10/2006SYNC_MASTER=M1_MLB
051-7023 06
8616
PP1V5_S0
PP1V05_S0
PP1V05_S0
NB_VCCSM_LF4NB_VCCSM_LF5
NB_VCCSM_LF2NB_VCCSM_LF1
PP1V8_S3
66
66
64
64
54
54
34
34
25
25
24
24
66
66
21
21
63
65
19
19
54
47
17
17
37
25
16
16
32
24
13
13
31
19
12
12
29
17
11
11
28
13
9
9
19
9
8
8
14
8
7
7
5
5
5
5
4
VTT0
VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8
VTT9
VTT10
VTT11
VTT12
VTT13
VTT15
VTT14
VTT16
VTT18
VTT17
VTT19
VTT20
VTT21
VTT22
VTT23
VTT24
VTT25
VTT27
VTT26
VTT28
VTT29
VTT31
VTT30
VTT32
VTT34
VTT33
VTT35
VTT36
VTT37
VTT39
VTT38
VTT40
VTT41
VTT42
VTT43
VTT44
VTT45
VTT48
VTT46
VTT47
VTT49
VTT50
VTT52
VTT51
VTT53
VTT55
VTT54
VTT57
VTT56
VTT58
VTT59
VTT60
VTT61
VTT62
VTT64
VTT63
VTT65
VTT66
VTT67
VTT69
VTT68
VTT70
VTT71
VTT73
VTT72
VTT74
VTT76
VTT75
VCCSYNC
VCC_TXLVDS0
VCC_TXLVDS1
VCC_TXLVDS2
VCC3G0
VCC3G1
VCC3G3
VCC3G2
VCC3G4
VCC3G6
VCC3G5
VCCA_3GPLL
VCCA_3GBG
VSSA_3GBG
VCCA_CRTDAC0
VCCA_CRTDAC1
VSSA_CRTDAC
VCCA_DPLLB
VCCA_DPLLA
VCCA_HPLL
VSSA_LVDS
VCCA_LVDS
VCCA_MPLL
VCCA_TVBG
VSSA_TVBG
VCCA_TVDACC0
VCCA_TVDACC1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACA0
VCCA_TVDACA1
VCCD_HMPLL0
VCCD_HMPLL1
VCCD_LVDS2
VCCD_LVDS0
VCCD_LVDS1
VCCD_TVDAC
VCC_HV1
VCC_HV2
VCC_HV0
VCCD_QTVDAC
VCCAUX19
VCCAUX18
VCCAUX17
VCCAUX16
VCCAUX14
VCCAUX15
VCCAUX13
VCCAUX12
VCCAUX11
VCCAUX10
VCCAUX0
VCCAUX1
VCCAUX2
VCCAUX3
VCCAUX4
VCCAUX6
VCCAUX5
VCCAUX9
VCCAUX8
VCCAUX7
VCCAUX21
VCCAUX20
VCCAUX23
VCCAUX24
VCCAUX22
VCCAUX25
VCCAUX26
VCCAUX29
VCCAUX28
VCCAUX27
VCCAUX30
VCCAUX31
VCCAUX33
VCCAUX32
VCCAUX34
VCCAUX35
VCCAUX36
VCCAUX38
VCCAUX37
VCCAUX39
VCCAUX40
POWER
(8 OF 10)
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
1500mA Max VCC3G/3GPLL
800mA Max
2mA Max
60mA Max
70mA Max VCCA_CRTDAC/VCCSYNC
20mA Max
24mA Max
10mA Max
50mA Max50mA Max45mA Max
45mA Max
120mA Max
150mA Max
See VCCSYNC
40mA Max
1900mA Max
U1200
AJ41
AB41
Y41
V41
R41
N41
L41
A23
B23
B25
C30
B30
A30
G41
AC33
F21
E21
B26
C39
AF1
A38
AF2
H20
E19
F19
C20
D20
E20
F20
AK31
AF31
AE30
AD30
AC30
AG29
AF29
AE29
AD29
AC29
AG28
AF28
AE31
AE28
AH22
AJ21
AH21
AJ20
AH20
AH19
P19
P16
AH15
AC31
P15
AH14
AG14
AF14
AE14
Y14
AF13
AE13
AF12
AE12
AL30
AD12
AK30
AJ30
AH30
AG30
AF30
AH1
AH2
A28
B28
C28
H19
D21
H22
H41
G21
B39
G20
AC14
AB14
AD13
AC13
AB13
AA13
Y13
W13
V13
U13
T13
R13
W14
N13
M13
L13
AB12
AA12
Y12
W12
V12
U12
T12
V14
R12
P12
N12
M12
L12
R11
P11
N11
M11
R10
T14
P10
N10
M10
P9
N9
M9
R8
P8
N8
M8
R14
P7
N7
M7
R6
P6
M6
A6
R5
P5
N5
P14
M5
P4
N4
M4
R3
P3
N3
M3
R2
P2
N14
M2
D2
AB1
R1
P1
N1
M1
M14
L14
OMIT
BGANB
945GM
C1711 1
2402
CERM-X5R6.3V
0.47uF20%
C17121
220%0.22uF6.3V
402X5R
C1713 1
2402
6.3VCERM-X5R
20%0.47uF
SYNC_DATE=02/10/2006SYNC_MASTER=M1_MLB
NB Power 2
051-7023 06
8617
GND
PP1V5_S0
PP1V05_S0
NB_VTTLF_CAP3
NB_VTTLF_CAP2NB_VTTLF_CAP1
GND
GND
PP1V5_S0_NB_VCC3G
PP1V5_S0_NB_VCCA_3GPLLPP2V5_S0GND
GND
TP_NB_VCCA_DPLLBTP_NB_VCCA_DPLLA
PP1V5_S0_NB_VCCA_HPLL
NC_GND_NB_VSSA_LVDSGND
PP1V5_S0_NB_VCCA_MPLL
PP1V5_S0GND
PP1V5_S0
PP1V5_S0
PP1V5_S0
PP1V5_S0
PP3V3_S0
PP1V5_S0
PP1V5_S0
PP1V05_S0
79 78 70
66 65 64 60 59 57 56 53 51 48
43 37 36
66
34
66
64
33
64
54
29
54
34
28
34
25
27
25
66
24
66
66
66
66
66
26
66
66
24
65
21
65
65
65
65
65
25
65
65
21
47
19
47
47
47
47
47
24
47
47
19
25
17
25
25
25
25
25
23
25
25
17
24
16
24
24
24
24
24
22
24
24
16
19
13
77
19
19
19
19
19
21
19
19
13
17
12
76
17
17
17
17
17
20
17
17
12
16
11
66
16
16
16
16
16
19
16
16
11
13
9
65
13
13
13
13
13
14
13
13
9
9
8
62
9
9
9
9
9
10
9
9
8
8
7
19
8
8
8
8
8
5
8
8
7
5
5
19
19
5
19
19
19
19
19
5
5
5
5
5
4
5
5
5
VSS_1
VSS_0
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_9
VSS_8
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_19
VSS_18
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_28
VSS_27
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_37
VSS_36
VSS_39
VSS_38
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_49
VSS_48
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_57
VSS_56
VSS_59
VSS_58
VSS_61
VSS_60
VSS_64
VSS_63
VSS_62
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_73
VSS_72
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_82
VSS_80
VSS_81
VSS_84
VSS_83
VSS_85
VSS_87
VSS_86
VSS_89
VSS_88
VSS_91
VSS_90
VSS_92
VSS_93
VSS_94
VSS_96
VSS_95
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_114
VSS_113
VSS_115
VSS_117
VSS_116
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_127
VSS_126
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_137
VSS_136
VSS_138
VSS_139
VSS_140
VSS_141
VSS_143
VSS_142
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_158
VSS_157
VSS_159
VSS_160
VSS_161
VSS_162
VSS_164
VSS_163
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_172
VSS_171
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS
(9 OF 10)
VSS_272
VSS_271
VSS_269
VSS_270
VSS_268
VSS_266
VSS_267
VSS_265
VSS_264
VSS_263
VSS_261
VSS_262
VSS_260
VSS_259
VSS_258
VSS_256
VSS_257
VSS_255
VSS_254
VSS_253
VSS_251
VSS_252
VSS_250
VSS_248
VSS_249
VSS_247
VSS_246
VSS_245
VSS_243
VSS_244
VSS_242
VSS_241
VSS_240
VSS_238
VSS_239
VSS_237
VSS_236
VSS_235
VSS_233
VSS_234
VSS_232
VSS_231
VSS_230
VSS_228
VSS_229
VSS_227
VSS_225
VSS_226
VSS_224
VSS_223
VSS_222
VSS_220
VSS_221
VSS_219
VSS_218
VSS_217
VSS_215
VSS_216
VSS_214
VSS_213
VSS_212
VSS_210
VSS_211
VSS_209
VSS_207
VSS_208
VSS_205
VSS_206
VSS_204
VSS_202
VSS_203
VSS_201
VSS_200
VSS_199
VSS_197
VSS_198
VSS_196
VSS_195
VSS_194
VSS_192
VSS_193
VSS_191
VSS_190
VSS_189
VSS_187
VSS_188
VSS_186
VSS_184
VSS_185
VSS_183
VSS_182
VSS_180
VSS_181
VSS_273
VSS_274
VSS_276
VSS_275
VSS_277
VSS_279
VSS_278
VSS_281
VSS_280
VSS_282
VSS_283
VSS_284
VSS_286
VSS_285
VSS_287
VSS_288
VSS_289
VSS_291
VSS_290
VSS_293
VSS_292
VSS_294
VSS_296
VSS_295
VSS_297
VSS_299
VSS_298
VSS_301
VSS_302
VSS_300
VSS_304
VSS_303
VSS_305
VSS_306
VSS_307
VSS_309
VSS_308
VSS_311
VSS_310
VSS_312
VSS_313
VSS_314
VSS_315
VSS_317
VSS_316
VSS_318
VSS_319
VSS_320
VSS_322
VSS_321
VSS_323
VSS_324
VSS_325
VSS_327
VSS_326
VSS_328
VSS_329
VSS_330
VSS_332
VSS_331
VSS_334
VSS_333
VSS_335
VSS_337
VSS_336
VSS_338
VSS_339
VSS_340
VSS_342
VSS_343
VSS_341
VSS_345
VSS_344
VSS_346
VSS_347
VSS_348
VSS_350
VSS_349
VSS_352
VSS_351
VSS_353
VSS_354
VSS_355
VSS_356
VSS_357
VSS_358
VSS_359
VSS_360
VSS
(10 OF 10)
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
U1200AC41
AA41
AN40
AE34
AC34
C34
AW33
AV33
AR33
AE33
AB33
Y33
V33
AK40
T33
R33
M33
H33
G33
F33
D33
B33
AH32
AG32
AJ40
AF32
AE32
AC32
AB32
G32
B32
AY31
AV31
AN31
AJ31
AH40
AG31
AB31
Y31
AB30
E30
AT29
AN29
AB29
T29
N29
AG40
K29
G29
E29
C29
B29
A29
BA28
AW28
AU28
AP28
AF40
AM28
AD28
AC28
W28
J28
E28
AP27
AM27
AK27
J27
AE40
G27
F27
C27
B27
AN26
M26
K26
F26
D26
AK25
B40
P25
K25
H25
E25
D25
A25
BA24
AU24
AL24
AW23
AY39
AW39
W41
AV39
AR39
AN39
AJ39
AC39
AB39
AA39
Y39
W39
V39
T41
T39
R39
P39
N39
M39
L39
J39
H39
G39
F39
P41
D39
AT38
AM38
AH38
AG38
AF38
AE38
C38
AK37
AH37
M41
AB37
AA37
Y37
W37
V37
T37
R37
P37
N37
M37
J41
L37
J37
H37
G37
F37
D37
AY36
AW36
AN36
AH36
F41
AG36
AF36
AE36
AC36
C36
B36
BA35
AV35
AR35
AH35
AV40
AB35
AA35
Y35
W35
V35
T35
R35
P35
N35
M35
AP40
L35
J35
H35
G35
F35
D35
AN34
AK34
AG34
AF34
NB945GM
BGA
OMIT
U1200AT23
AN23
AM23
AH23
AC23
W23
K23
J23
F23
C23
AA22
K22
G22
F22
E22
D22
A22
BA21
AV21
AR21
AN21
AL21
AB21
Y21
P21
K21
J21
H21
C21
AW20
AR20
AM20
AA20
K20
B20
A20
AN19
AC19
W19
K19
G19
C19
AH18
P18
H18
D18
A18
AY17
AR17
AP17
AM17
AK17
AV16
AN16
AL16
J16
F16
C16
AN15
AM15
AK15
N15
M15
L15
B15
A15
BA14
AT14
AK14
AD14
AA14
U14
K14
H14
E14
AV13
AR13
AN13
AM13
AL13
AG13
P13
F13
D13
B13
AY12
AC12
K12
H12
E12
AD11
AA11
Y11
J11
D11
B11
AV10
AP10
AL10
AJ10
AG10
AC10
W10
U10
BA9
AW9
AR9
AH9
AB9
Y9
R9
G9
E9
A9
AG8
AD8
AA8
U8
K8
C8
BA7
AV7
AP7
AL7
AJ7
AH7
AF7
AC7
R7
G7
D7
AG6
AD6
AB6
Y6
U6
N6
K6
H6
B6
AV5
AF5
AD5
AY4
AR4
AP4
AL4
AJ4
Y4
U4
R4
J4
F4
C4
AY3
AW3
AV3
AL3
AH3
AG3
AF3
AD3
AC3
AA3
G3
AT2
AR2
AP2
AK2
AJ2
AD2
AB2
Y2
U2
T2
N2
J2
H2
F2
C2
AL1
NB945GM
BGA
OMIT
SYNC_DATE=02/10/2006SYNC_MASTER=M1_MLB
NB Grounds
051-7023 06
8618
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
Rail Totals:
2310mA Max?
3674mA Max
40mA Max?
Power InterfaceThese are the power signals that leave the NB "block"
(MCH DDR DLL&IO, FSB HSIO&IO PWR 1.5V)
GMCH CORE PWR 1.05V BYPASS1500mA Max
1500mA Max 10mA Max?
?mA Max
?mA Max
60mA Max 70mA Max
3200mA Max
24mA Max 100mA Max
?mA Max 800mA Max
?mA Max 40mA Max
1500mA Max
2mA Max
1900mA Max 150mA Max
132mA Max
3200mA Max
(MCH TVDAC DEDICATED PWR 1.5V)
(MCH TVDAC DIGITAL QUIET 1.5V PWR)
(MCH TV OUT CHANNEL A 3.3V PWR)
(MCH TV OUT CHANNEL B 3.3V PWR)
(MCH TV DAC BAND GAP 3.3V PWR)
(MCH TV OUT CHANNEL C 3.3V PWR)
(MCH LVDS DATA/CLK TX 2.5V PWR)
(MCH LVDS DIGITAL 1.5V PWR)
(MCH LVDS ANALOG 2.5V PWR)
(MCH CRTDAC ANALOG 2.5V PWR)
(MCH H/V SYNC 2.5V PWR)
(MCH DISPLAY A PLL 1.5V PWR)
(MCH DISPLAY B PLL 1.5V PWR)
1500mA Maxbe close to MCHon opposite side.
GMCH VCCA_3GPLL FILTER
(PCI-E/DMI ANALOG 1.5V PWR)
10uF caps should
Layout Note: Route to caps, then GND
(3GIO PLL 1.5V PWR)
GMCH VCC3G FILTER
Layout Note:
be placed in cavity3GPLL 10uF cap shouldLayout Note:
Place L and Cclose to MCH
Layout Note:
1500mA Max
GMCH VCCA_HPLL FILTER
45mA Max
(HOST PLL 1.5V PWR)
(MCH MEMORY PLL 1.5V PWR)GMCH VCCA_MPLL FILTER
45mA Max
100mA Max
GMCH VCCAUX FILTER
1900mA Max
(MCH PCIE/DMI BAND GAP 2.5V PWR)MCH VCCA_3GBG BYPASS
2mA Max
MCH VCC_HV BYPASS(MCH HV BUFFER 3.3V PWR)
40mA Max
Place on the edgeLayout Note:
(SHARE C0940 470UF)
MCH VTT BYPASS(MCH FSB 1.05V PWR)
Layout Note:Place in cavity
800mA Max
C19071
2402
20%6.3VX5R
0.22uF
C19721
2
10uF6.3V20%
603X5R
C19701
2
220UF20%2.5V
SMB2POLY
C19671
2
0.22uF
X5R402
20%6.3V
C19661
2 CERM1
20%2.2uF
603
6.3V
C19651
2
4.7uF
CERM603
20%6.3V
5 7 8 9 11 12 13 16 17 19 21 24 25 34 54 64 66
5 7 8 9 11 12 13 16 17 19 21 24 25 34 54 64 66
5 8 9 13 16 17 19 24 25 47 65 66
5 8 9 13 16 17 19 24 25 47 65 66
5 8 9 13 16 17 19 24 25 47 65 66
5 8 9 13 16 17 19 24 25 47 65 66
5 8 9 13 16 17 19 24 25 47 65 66
5 17 19 62 65 66 76 77
5 7 8 9 11 12 13 16 17 19 21 24 25 34 54 64 66
4 5 10 14 17 19 20 21 22 23 24 25 26 27 28 29 33 34 36
37
43 48 51 53 56 57 59 60 64
65
66 70 78 79
C19001
23D2TS
CRITICAL
2.5V20%470uF-9MOHM
POLY
5 8 9 13 16 17 19 24 25 47 65 66
5 8 9 13 16 17 19 24 25 47 65 66
L1970
1 2
1210
91nH
C1916 1
2CERM10V20%
402
0.1uF
C19061
2402
0.22uF
X5R
20%6.3V
C19151
2
0.1uF
CERM402
20%10V
C1914 1
2
10uF
X5R603
20%6.3V
C19051
2
0.22uF
X5R
20%
402
6.3V
C19351
2
0.1uF
CERM402
10V20%
L1934
1 2
0603
FERR-120-OHM-0.2A
C19371
2402
10V20%
CERM
0.1uF
C19041
210%
CERM
1uF6.3V
402
L1936
1 2
0603
FERR-120-OHM-0.2A
C1934 1
26.3V20%
805CERM
22UF
C1936 1
26.3V20%
805CERM
22UF
C19031
2
10uF
603
20%
X5R6.3V
C19021
2
10uF
X5R603
20%6.3V
C1918 1
2CERM402
20%10V
0.1uF
C19761
2
0.1uF
CERM402
20%10V
L1975
1 2
0805
1.0UH-220MA-0.12-OHM
C1975 1
2
10uF
X5R603
20%6.3V
R19751 2
1%1/16W
0.51
402MF-LF
C19711
2 6.3V20%
603X5R
10uF
19 86
06051-7023
SYNC_MASTER=M1_MLB SYNC_DATE=02/08/2006
NB (GM) Decoupling
PP1V05_S0 PP3V3_S0PP2V5_S0 PP1V5_S0
PP1V5_S0
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.38 mm
VOLTAGE=1.5V
PP1V5_S0_NB_VCCA_MPLL
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.38 mm
VOLTAGE=1.5V
PP1V5_S0_NB_VCCA_HPLL
MIN_NECK_WIDTH=0.4 mmMIN_LINE_WIDTH=0.6 mm
VOLTAGE=1.5V
PP1V5_S0_NB_3GPLL_F
GND
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.5 mm
VOLTAGE=1.5V
PP1V5_S0_NB_VCCA_3GPLLPP1V5_S0
PP1V5_S0
GND
GND
GND
GND
MAKE_BASE=TRUETP_NB_VCCA_DPLLB TP_NB_VCCA_DPLLB
TP_NB_VCCA_DPLLAMAKE_BASE=TRUE
TP_NB_VCCA_DPLLA
GND
PP1V5_S0
PP1V5_S0
PP1V5_S0
PP1V5_S0
PP1V5_S0
PP1V5_S0
PP1V05_S0
GND
MAKE_BASE=TRUENC_GND_NB_VSSA_LVDS
NO_TEST=TRUENC_GND_NB_VSSA_LVDS
GND
GND
GND
PP1V5_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V5_S0
PP1V5_S0
PP1V05_S0
PP3V3_S0PP3V3_S0
PP2V5_S0
PP1V5_S0PP1V5_S0
PP1V5_S0PP1V5_S0
PP1V05_S0
PP1V05_S0
MAKE_BASE=TRUETP_CRT_DDC_CLK
TP_CRT_DDC_DATAMAKE_BASE=TRUETP_CRT_DDC_DATA
TP_CRT_DDC_CLK
PP1V05_S0PP1V05_S0PP1V05_S0PP1V05_S0PP1V05_S0PP1V05_S0PP1V05_S0
PP1V05_S0
PP1V5_S0PP1V5_S0
PP1V5_S0
PP1V5_S0PP1V5_S0
PP1V5_S0PP1V5_S0
TP_LVDS_BKLTENMAKE_BASE=TRUETP_LVDS_BKLTEN
TP_LVDS_BKLTCTLMAKE_BASE=TRUETP_LVDS_BKLTCTL
TP_LVDS_CLKCTLAMAKE_BASE=TRUETP_LVDS_CLKCTLA
TP_LVDS_CLKCTLBMAKE_BASE=TRUETP_LVDS_CLKCTLB
TP_LVDS_DDC_CLKMAKE_BASE=TRUETP_LVDS_DDC_CLK
NC_LVDS_IBGNO_TEST=TRUEMAKE_BASE=TRUE
NC_LVDS_IBG
TP_LVDS_DDC_DATAMAKE_BASE=TRUETP_LVDS_DDC_DATA
TP_LVDS_VREFLMAKE_BASE=TRUETP_LVDS_VREFL
TP_LVDS_VDDENMAKE_BASE=TRUETP_LVDS_VDDEN
NC_LVDS_VREFHNO_TEST=TRUEMAKE_BASE=TRUE
NC_LVDS_VREFH
NC_LVDS_A_CLKPMAKE_BASE=TRUE NO_TEST=TRUENC_LVDS_A_CLKP
NC_LVDS_A_CLKNMAKE_BASE=TRUE NO_TEST=TRUENC_LVDS_A_CLKN
LVDS_A_DATA_P<2..0>MAKE_BASE=TRUE NO_TEST=TRUENC_LVDS_A_DATAP<2..0>
LVDS_A_DATA_N<2..0>MAKE_BASE=TRUE NO_TEST=TRUENC_LVDS_A_DATAN<2..0>
NC_LVDS_B_CLKNNO_TEST=TRUEMAKE_BASE=TRUE
NC_LVDS_B_CLKN
LVDS_B_DATA_P<2..0>NO_TEST=TRUEMAKE_BASE=TRUE
NC_LVDS_B_DATAP<2..0>
NC_LVDS_B_CLKPNO_TEST=TRUEMAKE_BASE=TRUE
NC_LVDS_B_CLKP
MAKE_BASE=TRUE NO_TEST=TRUENC_NB_XOR_LVDS_A35
MAKE_BASE=TRUE NO_TEST=TRUENC_NB_XOR_LVDS_D27
NC_NB_XOR_LVDS_D28MAKE_BASE=TRUE NO_TEST=TRUENC_NB_XOR_LVDS_D28
NC_NB_XOR_LVDS_A35MAKE_BASE=TRUE NO_TEST=TRUENC_NB_XOR_LVDS_A34
TP_SDVO_CTRLDATAMAKE_BASE=TRUETP_SDVO_CTRLDATA
TP_SDVO_CTRLCLKMAKE_BASE=TRUETP_SDVO_CTRLCLK
NC_NB_XOR_LVDS_A34MAKE_BASE=TRUE NO_TEST=TRUENC_LVDS_B_DATAN<2..0>
PP1V5_S0
GNDGND
GND
LVDS_B_DATA_N<2..0>
NC_NB_XOR_LVDS_D27
GND
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.5 mmPP1V5_S0_NB_VCC3G
VOLTAGE=1.5V
PP1V5_S0
PP1V5_S0
PP1V8_S3
GND
79 78 70 66 65 64
60 59 57 56
53 51 48 43 37 36 34 66 33
66
66
66
66
66
66
66
66
66
66
66
64 29
64
64
64
64
64
64
64
64
64
64
64
54 28
54
54
54
54
54
54
54
54
54
54
54
34
27
34
34
34
34
34
34
34
34
34
34
34
25 26
25
25
25
25
25
25
25
25
25
25
25
24 25
66
66
66
66
66
66
66
66
66
66
24
66
24
24
24
24
24
24
24
24
24
24
66
66
66
66
66
66
66
66
21 24
65
65
65
65
65
65
65
65
65
65
21
65
21
21
21
21
21
21
21
21
21
21
65
65
65
65
65
65
65
65
19 23
47
47
47
47
47
47
47
47
47
47
19
47
19
19
19
19
19
19
19
19
19
19
47
47
47
47
47
47
47
47
17 22
25
25
25
25
25
25
25
25
25
25
17
25
17
17
17
17
17
17
17
17
17
17
25
25
25
25
25
25
25
25
16 21
77 24
24
24
24
24
24
24
24
24
24
16
24
16
16
16
16
16
16
16
16
16
16
24
24
24
24
24
24
24
24
13 20
76 19
19
19
19
19
19
19
19
19
19
13
19
13
13
13
13
13
13
13
13
13
13
19
19
19
19
19
19
19
19
12 19
66 17
17
17
17
17
17
17
17
17
17
12
17
12
12
12
12
12
12
12
12
12
12
17
17
17
17
17
17
17
17
11 17
65 16
16
16
16
16
16
16
16
16
16
11
16
11
11
11
11
11
11
11
11
11
11
16
16
16
16
16
16
16
16
9 14
62 13
13
13
13
13
13
13
13
13
13
9
13
9
9
9
9
9
9
9
9
9
9
13
13
13
13
13
13
13
13
8 10
19 9
9
9
9
9
9
9
9
9
9
8
9
8
8
8
8
8
8
8
8
8
8
9
9
9
9
9
9
9
9
7 5
17 8
8
8
8
19 19
19 19
8
8
8
8
8
8
7
19 19
8
7
7
19
19 19
19
7
7
7
7
7
7
7
7
8
8
8
8
8
8
8
19 19
19 19
19 19
19 19
19 19
19 19
19 19
19 19
19 19
19 19
19 19
19 19
19 19
19 19
19
19
19 19
19
19
19 19
19 19
19
8
19
5 4
5 5
5
17
17
17 5
5
17 17
17 17
5
5
5
5
5
5
5
17 17
5
5
5
13
13 13
13
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
13 13
13 13
13 13
13 13
13 13
13 13
13 13
13 13
13 13
13 13
13 13
13 13
13
13
13 13
13
13 13
14
14
14 14
14
14
14 14
14 14
14
13
5
14
17
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
Internal pull-ups
Internal pull-up
RESERVED
RESERVED
NB_CFG<11>
NB_CFG<10>
High = Mobile CPUNB_CFG<7>
RESERVED
Internal pull-up
DMI x2 Select
PROBABLY NOT NEEDED
PROBABLY NOT NEEDED
Lane Reversal
NB_CFG<4>
NB_CFG<3>
RESERVED
NB_CFG<13:12>
NB_CFG<14>
NB_CFG<5>NB_CFG<15>
NB_CFG<16>NB_CFG<6>
NB_CFG<17>
NB_CFG<18>NB_CFG<8>
NB_CFG<9> NB_CFG<19>
NB_CFG<20>
Low = DMIx2
High = DMIx4
Low = RESERVED
High = NormalPCIE Graphics
RESERVED
CPU Strap
RESERVED
Low = Reversed
Internal pull-up
11 = Normal Operation10 = All-Z Mode Enabled01 = XOR Mode Enabled00 = Partial Clock Gating Disable
RESERVED
Internal pull-up
RESERVED
High = Enabled
Low = Disabled
RESERVED
FSB DynamicODT
or PCIe x1Low = Only SDVO
High = Both active
945 External Design Spec says reserved
Internal pull-down
Internal pull-down
Internal pull-down
Low = 1.05V
High = 1.5V
Low = Normal
High = ReversedDMI LaneReversal
VCC Select
Interop. ModePCIe Backward
R20751
2402
5%2.2K1/16WMF-LF
NBCFG_DMI_X2
R20851
2
5%2.2K1/16WMF-LF402
NBCFG_DYN_ODT_DISABLE
R20581
2 402
1/16W5%2.2K
NBCFG_VCC_1V5
MF-LF
R20591
2 402MF-LF1/16W5%2.2K
NBCFG_DMI_REVERSE
R20601
2
NBCFG_SDVO_AND_PCIE
402MF-LF1/16W5%2.2K
R20771
2
NO STUFF
2.2K5%1/16WMF-LF402
R20791
2402MF-LF1/16W5%2.2K
NBCFG_PEG_REVERSE
20 86
06051-7023
NB Config StrapsSYNC_MASTER=M1_MLB SYNC_DATE=02/10/2006
PP3V3_S0
PP3V3_S0
PP3V3_S0
NB_CFG<18>
NB_CFG<19>
NB_CFG<20>
NB_CFG<16>
NB_CFG<5>
NB_CFG<9>
NB_CFG<7>
79
79
79
78
78
78
70
70
70
66
66
66
65
65
65
64
64
64
60
60
60
59
59
59
57
57
57
56
56
56
53
53
53
51
51
51
48
48
48
43
43
43
37
37
37
36
36
36
34
34
34
33
33
33
29
29
29
28
28
28
27
27
27
26
26
26
25
25
25
24
24
24
23
23
23
22
22
22
21
21
21
20
20
20
19
19
19
17
17
17
14
14
14
10
10
10
5
5
5
4
4
4
14
14
14
14
14
14
14
BI
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
BI
BI
BI
BI
IN
BI
DDACK*
SATARBIASN
SATARBIASP
SATA_CLKN
SATA_CLKP
SATA_2TXP
SATA_2TXN
SATA_2RXN
SATA_2RXP
SATA_0TXP
SATA_0TXN
SATA_0RXP
SATA_0RXN
SATALED*
ACZ_SDOUT
ACZ_SDIN1
ACZ_SDIN2
ACZ_SDIN0
ACZ_SYNC
ACZ_BIT_CLK
LAN_TXD2
LAN_TXD0
LAN_TXD1
LAN_RXD1
LAN_RXD2
LAN_RSTSYNC
LAN_RXD0
LAN_CLK
EE_SHCLK
EE_CS
INTVRMEN
INTRUDER*
RTCRST*
RTCX2
RTCX1
THRMTRIP*
STPCLK*
NMI
SMI*
RCIN*
INTR
INIT*
INIT3_3V*
IGNNE*
GPIO49/CPUPWRGD
FERR*
TP1/DPRSTP*
TP2/DPSLP*
A20M*
CPUSPL*
A20GATE
LFRAME*
LDRQ1*/GPIO23
LDRQ0*
LAD3
LAD2
LAD0
LAD1
EE_DOUT
EE_DIN
ACZ_RST*
DIOR*
IDEIRQ
DIOW*
IORDY
DDREQ
DD0
DD1
DD3
DD2
DD5
DD4
DD6
DD7
DD8
DD11
DD9
DD10
DD12
DD13
DD14
DD15
DA0
DA1
DA2
DCS3*
DCS1*
AC-97/
AZALIA
RTC
LPC
LAN
CPU
IDE
SATA
(1 OF 6)
OUT
OUT
OUT
IN
OUT
IN
IN
IN
IN
OUT
OUT
OUT
OUT
IN
IN
OUT
OUT
OUT
IN
IN
IN OUT
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
NOTE: EE_CS HAS INTERNAL PD, ONLY ENABLED WHEN LAN_RST#=L
(INT PU)
(INT PU)
(WEAK INT PD)
NOTE: R2108=56 IN CV.
BOM CONSOLIDATIONCHANGED TO 54.9 FORNOTE: R2110=56 IN CV.
NOTE: PULLED UP PER INTEL
NOTE: LDRQ<0-1># HAVE INTERNAL 20K PU
INTEL CONFIRMS OK TO LEAVE PINS AS NC
- BOTH FUNCTION 2 & 3 OF DEVICE 30 ARE DISABLED
INTO RESET STATE TO SAVE PWR.
NOTE:POR IS SMC WILL PUT LAN INT’F
NOTE: KEYBOARD CONTROLLER RESET CPU
NOTE: RISING-EDGE TRIGGERED AT CPUBOM CONSOLIDATION
< 2 IN OF SBLAYOUT NOTE: R2107 TO BE
CHANGED TO 54.9 FOR
LAYOUT NOTE: R2108 TO BE< 2 IN OF R2107 W/O STUB
(DSTROBE)
20K PD
20K PD
20K PD
(STOP)(HSTROBE)
NOTE: DD<7> HAS INTERNAL 11.5K PD
NOTE: ENABLE INTERNAL 1.05V SUSPEND REG
INTERNAL 20K PD ONLY ENABLED IN S3COLD
INTERNAL 20K PD
NONE
- LSO BIT IN AC’97 GLOBAL CONTROL REG = 1; OR
INTERNAL 20K PD ENABLED WHEN
INTERNAL 20K PD
INTERNAL 20K PD ENABLED DURING RESET AND WHEN
- BOTH FUNCTION 2 & 3 OF DEVICE 30 ARE DISABLED
- LSO BIT IN AC’97 GLOBAL CONTROL REG = 1; OR
- BOTH FUNCTION 2 & 3 OF DEVICE 30 ARE DISABLED
- LSO BIT IN AC’97 GLOBAL CONTROL REG = 1; OR
AC ’07
INTERNAL 20K PD
INTERNAL 20K PD ENABLED WHEN
ACZ_SDIN[0-2]
ACZ_RST#
ACZ_BIT_CLK
ACZ_SYNC
ACZ_SDOUT
INTEL HIGH DEFINITION AUDIO
NOTE: LAD<0-3> HAVE INTERNAL 20K PU
NOTE: DDREQ HAS INTERNAL 11.5K PD
LAYOUT NOTE: PLACE R2101 & R2194 WHERE ACCESSIBLE
NOTE: ALL IDE PINS HAVE INTERNAL 33-OHM SERIES R’S
(WEAK INT PU)
36
7 14 51
5 7 86
7 86
7 86
7 86
5 50 51 52
7 86
5 7 86
7
5 7 86
5 7 60
5 50 52 59
7 86
26
26
5 26
26
21 36
21 36
5 50 52 59
5 50 52 59
5 50 52 59
R21001 2
NOSTUFF
1/16WMF-LF
0
5%402
50
R21011 2
NOSTUFF
402
2.2K5%
1/16WMF-LF
R2195 1 2MF-LF5%
394021/16W
R2198 1 2 39R2197 1 2 39
R2196 1 2 39
R21991
2402
10K5%1/16WMF-LF
U2100
AE22AH28
U1
R5T2T3T1
T4
R6
AG27
AH17AE17AF17
AE16AD16
AB15AE14
AB13AC14AF14AH13AH14AC15
AG13AF13AD14AC13AD12AC12AE12AF12
AF16
AE15
AF15AH15
W1
W3Y2Y1
AG26
AG24
AH16
AG22
AF22AG21
AF25
Y5W4
AG16
AA6AB5AC4Y6
V3
U3
U5V4T5
U7V6V7
AC3AA5
AB3
AH24
AG23
AA3
AB1AB2
AF3AE3AG2AH2
AF7AE7AG6AH6
AF1AE1
AF18
AH10AG10
AF23
AH22
AF26
AF24AH25
BGASB
ICH7-M
OMIT
R21941
2402
10K5%1/16WMF-LF
R2105
1
2
332K402
1%1/16WMF-LF
R21071 224.9MF-LF1/16W1%
402
R2108
1
2
402MF-LF1/16W1%54.9
R2110
12
MF-LF1/16W
40254.9
1%
5 47 86
5 47 86
5 47 86
5 47 86
5 47 86
36
36
80
80
36
36
80
80
5 34
5 34
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
06
21 86
051-7023
SYNC_MASTER=M1_MLB SYNC_DATE=02/10/2006
SB: 1 OF 4
IDE_PDD<3>IDE_PDD<2>
TP_SB_XOR_V3
TP_SB_XOR_W3
TP_SB_XOR_T5TP_SB_XOR_V4TP_SB_XOR_U5
TP_SB_XOR_U3
PP3V3_G3C_SB_RTC_D
ACZ_RST_L
ACZ_BITCLK
SB_RTC_RST_L
SB_RTC_X2
LPC_FRAME_L
TP_SB_GPIO23TP_SB_DRQ0_L
LPC_AD<3>LPC_AD<2>LPC_AD<1>LPC_AD<0>
PP3V3_S0
PP3V3_S0
IDE_PDD<6>
ACZ_SDATAOUTPM_THRMTRIP_L
PP1V05_S0
SMC_RCIN_LACZ_SYNC
IDE_PDCS1_LIDE_PDCS3_L
IDE_PDA<2>IDE_PDA<1>IDE_PDA<0>
IDE_PDD<15>IDE_PDD<14>IDE_PDD<13>IDE_PDD<12>
IDE_PDD<10>IDE_PDD<9>
IDE_PDD<11>
IDE_PDD<8>IDE_PDD<7>
IDE_PDD<4>IDE_PDD<5>
IDE_PDD<1>IDE_PDD<0>
IDE_PDDREQIDE_PDIORDY
IDE_PDIOW_L
IDE_IRQ14
IDE_PDIOR_L
SB_ACZ_RST_L
TP_CPU_CPUSLP_L
CPU_A20M_L
CPU_DPSLP_LCPU_DPRSTP_L
CPU_PWRGD
CPU_IGNNE_LFWH_INIT_LCPU_INIT_LCPU_INTR
CPU_SMI_LCPU_NMI
CPU_STPCLK_L
CPU_THERMTRIP_R
SB_RTC_X1
SB_SM_INTRUDER_L
SB_ACZ_BITCLKSB_ACZ_SYNC
ACZ_SDATAIN<0>
TP_SB_ACZ_SDIN2TP_SB_ACZ_SDIN1
SB_ACZ_SDATAOUT
TP_SB_SATALED_L
TP_SATA_A_D2RNTP_SATA_A_D2RPTP_SATA_A_R2DNTP_SATA_A_R2DP
SATA_C_D2R_N
SATA_C_R2D_C_NSATA_C_R2D_C_P
SB_CLK100M_SATA_PSB_CLK100M_SATA_N
SATA_RBIASSATA_RBIAS
IDE_PDDACK_L
SATA_C_D2R_P
CPU_RCIN_L
SB_A20GATE
CPU_FERR_L
PP1V05_S0
SB_INTVRMEN
TP_SB_XOR_W1TP_SB_XOR_Y1TP_SB_XOR_Y2
TP_SB_XOR_U7TP_SB_XOR_V6TP_SB_XOR_V7
79
79
78
78
70
70
66
66
65
65
64
64
60
60
59
59
57
57
56
56
53
53
51
51
48
48
43
43
37
37
36
36
34
34
33
33 66
66
29
29 64
64
28
28 54
54
27
27 34
34
26
26 25
25
25
25 24
24
24
24 21
21
23
23 19
19
22
22 17
17
21
21 16
16
20
20 13
13
19
19 12
12
17
17 11
11
14
14 9
9
26
10
10 8
8
25
5
5 7
7
24
4
4 5
86
5
5
86
86
86
5
IN
BI
BI
BI
BI
BI
BI
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
BI
BI
BI
IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
DMI_ZCOMP
DMI_CLKP
DMI_IRCOMP
USBRBIAS*
USBRBIAS
DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP
DMI2TXN
DMI2TXP
DMI3RXN
DMI3TXP
DMI3TXN
DMI3RXP
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP4N
OC0*
OC1*
OC2*
OC3*
OC4*
OC6*/GPIO30
OC5*/GPIO29
SPI_CLK
SPI_CS*
SPI_MOSI
SPI_MISO
SPI_ARB
DMI_CLKN
DMI2RXP
DMI2RXN
DMI1TXP
DMI1TXN
DMI1RXN
DMI1RXP
PERN1
PERP1
PETN1
PETP1
PERN2
PERP2
PETN2
PETP2
PERN3
PERP3
PETN3
PETP3
PERN4
PERP4
PETN4
PETP4
PERN5
PERP5
PETN5
PETP5
PERN6
PERP6
PETN6
PETP6
OC7*/GPIO31
PCI-EXP
(3 OF 6)
DMI
SPI
USB
REQ4*/GPIO22
REQ0*
MCH_SYNC*
RSVD8
RSVD7
RSVD6
RSVD5
RSVD4
GPIO5/PIRQH*
GPIO4/PIRQG*
GPIO3/PIRQF*
GPIO2/PIRQE*
GPIO17/GNT5*
GPIO1/REQ5*
GNT4*/GPIO48
C/BE0*
C/BE1*
DEVSEL*
PERR*
STOP*
PCIRST*
PME*
PLTRST*
TRDY*
FRAME*
IRDY*
PCICLK
PAR
PLOCK*
SERR*
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
C/BE2*
C/BE3*
GNT0*
REQ1*
GNT1*
REQ2*
GNT2*
REQ3*
GNT3*
PIRQA*
PIRQB*
PIRQC*
PIRQD*
RSVD0
RSVD1
RSVD2
RSVD3
MISC
INT I/F
PCI
(2 OF 6)
BI
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
BI
BI
BI
BI
OUT
BI
BI
BI
BI
BI
BI
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
NO STUFF - DEFAULT
GNT[0-3]# HAVE INT 20K PU
(INT 20K PU)
(AKA TP3, INTERNAL 20K PU)
SB: 2 OF 4
ENABLED ONLY WHEN PCIRST#=0
R2211
NOTE: FWH_WP_L NOT USED
NOTE: USBP[0-7]P/N HAVE INTERNAL 15K PD
GNT5# HAS INT PU (NOMINAL=20K, SIMULATION=15K-35K)
(INT PD)
(INT PD)
GNT4# HAS INT PU; ENABLED ONLY WHEN PCIRST#=0 AND PWROK=H
PLACE R2204 < 1/2 IN FROM SBLAYOUT NOTE:
PLACE R2203 < 1/2 IN FROM SBLAYOUT NOTE:
NOTE:
LPC (DEFAULT)
PCI
SPI UNSTUFF
STUFF
UNSTUFFUNSTUFF
UNSTUFF
STUFF01
10
11
STRAP R2210
NOTE: CHANGE SYMBOL TO RSVD[1-9]
GNT5# GNT4#
SB BOOT BIOS SELECT
TARGETING FWH BIOS SPACE)IE SB INVERTS A16 FOR ALL CYCLES(STRAPPED TO TOP-BLOCK SWAP MODE
STUFF - A16 SWAP OVERRIDE
NOTE:
EXTERNAL 0
EXTERNAL 1
EXTERNAL 2
AIRPORT (MINI-PCIE)
CAMERA
CF/SD
BT
IR
BOM NOTE FOR PD ON PCI_GNT3_L:
NOTE: R2210 WAS PD ON PIN A14 = FWH_TBL_L
AND PWROK=H
34
37
26 37
37
37
37
37
37
4 26 37
26
26
26
5 50 52
39
39
5 47 49
5 47 49
5 47 49
5 47 49
R22031 2
1/16W 402
24.9MF-LF1%
49
49
49
49
49
49
39
39
49
49
49
49
49
49
49
49
49
49
50 55
50 55
50 55
50 55
6 22 46
6 46
6 45
5 6 47
5 6 45
5 6 45
5 6 47
6 80
6 80
6 80
6 80
5 6 47
5 6 47
34
14
34
14
14
14
14
5 14
5 14
5 14
5 14
14
14
14
14
14
14
14
R22221
2
10K1/16WMF-LF5%
402
USB_G_OC_PU
R22041 2
402
22.61%
1/16WMF-LF
R22231
2
1/16W5%10KMF-LF402
R22251
2
10K5%1/16WMF-LF402
R22261
2402MF-LF1/16W10K5%
5 37
R22991
2
10K5%1/16WMF-LF402
U2100V26V25U28U27
Y26Y25W28W27
AB26AB25AA28AA27
AD25AD24AC28AC27
AE28AE27
D25C25
D3C4D5D4E5C3A2B3
F26
H26
K26
M26
P26
T25
F25
H25
K25
M25
P25
T24
E28
G28
J28
L28
N28
R28
E27
G27
J27
L27
N27
R27
P1
R2P6
P2P5
F1F2G4G3H1H2J4J3K1K2L4L5M1M2N4N3
D1D2
OMIT
BGASB
ICH7-M
U2100E18C18
E14D14B12C13G15G13E12C11D11A11
A16
A10F11F10E9D9B9A8A6C7B6
F18
E6D6
E16A18E17A17A15C14
B15C12D12C15
A12
F16
E7
D16
D17
F13
A14C8D8
G8F7F8G7
A7
AH20
E10A9
B18
C9
A3B4C5B5
E11
C26
B19
D7
C16
C17
E13
A13
AE5AD5AG4AH4AD9
AE9AG8AH8F21
B10F15F14
SBBGA
ICH7-M
OMIT
50
R22001
2MF-LF1/16W5%10K
402
R22501
2402MF-LF1/16W5%10K
USB_C_OC_PU
R22511
2
10K5%1/16WMF-LF402
USB_E_OC_PU
R22551
2
USB_D_OC_PU
MF-LF1/16W5%10K
402
R22981
2MF-LF4021/16W5%10K
4 37
R2205
1
2
MF-LF402 5%
10K1/16W
R2206
1
2
402
10KMF-LF
5%1/16W
NOSTUFF
R2207
1
2
MF-LF1/16W10K
402 5%
VOLTAGE=0V
R22111
2
1/16WMF-LF5%1K
402
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
37
4 37
37
37
37
37
37
37
37
37
37
37
37
37
26 37
26
26
26
26 37
5 14
36
26
26
26
5 14 26
26 37
26 37
26 37
26
26 37
26 37
051-7023
8622
06
TP_PCI_GNT4_L
PCI_GNT3_L
TP_PCI_GNT2_L
TP_PCI_GNT0_L
TP_PCI_GNT1_L
PP3V3_S5
UNUSED_USB_D_OC_L
UNUSED_USB_B_OC_L
EXCARD_OC_L
RTUSB_OC_L
LT2USB_OC_L
NB_SB_SYNC_LTP_SB_RSVD9
ODD_PWR_EN_LSB_GPIO4SB_GPIO3SB_GPIO2
PCI_C_BE_L<0>PCI_C_BE_L<1>
PCI_DEVSEL_LPCI_PERR_L
PCI_RST_LTP_PCI_PME_L
PLT_RST_L
PCI_TRDY_L
PCI_FRAME_L
PCI_IRDY_L
PCI_CLK_SBPCI_PAR
PCI_LOCK_LPCI_SERR_L
PCI_AD<0>
PCI_AD<2>PCI_AD<3>PCI_AD<4>PCI_AD<5>
PCI_AD<7>PCI_AD<8>PCI_AD<9>PCI_AD<10>PCI_AD<11>PCI_AD<12>PCI_AD<13>PCI_AD<14>PCI_AD<15>PCI_AD<16>PCI_AD<17>PCI_AD<18>PCI_AD<19>PCI_AD<20>PCI_AD<21>PCI_AD<22>PCI_AD<23>PCI_AD<24>PCI_AD<25>PCI_AD<26>PCI_AD<27>PCI_AD<28>PCI_AD<29>PCI_AD<30>PCI_AD<31>
PCI_C_BE_L<3>
INT_PIRQA_LINT_PIRQB_LINT_PIRQC_L
DMI_IRCOMP_R
SB_CLK100M_DMI_P
USB_RBIAS_PN
DMI_N2S_N<0>DMI_N2S_P<0>DMI_S2N_N<0>DMI_S2N_P<0>
DMI_S2N_N<2>DMI_S2N_P<2>
DMI_N2S_N<3>
DMI_S2N_P<3>DMI_S2N_N<3>DMI_N2S_P<3>
USB2_RT_NUSB2_RT_PUSB_TRACKPAD_NUSB_TRACKPAD_PUSB2_LT_NUSB2_LT_PUSB2_CAMERA_NUSB2_CAMERA_P
USB2_EXCARD_PUSB_IR_NUSB_IR_PUSB_BT_NUSB_BT_PUSB2_LT2_N
USB2_EXCARD_N
SB_GPIO30SB_GPIO29
SB_CLK100M_DMI_N
DMI_N2S_P<2>DMI_N2S_N<2>
DMI_S2N_P<1>DMI_S2N_N<1>
DMI_N2S_N<1>DMI_N2S_P<1>
PCIE_A_D2R_NPCIE_A_D2R_PPCIE_A_R2D_C_NPCIE_A_R2D_C_P
PCIE_MINI_D2R_NPCIE_MINI_D2R_PPCIE_B_R2D_C_NPCIE_B_R2D_C_P
PCIE_EXCARD_D2R_NPCIE_EXCARD_D2R_PPCIE_C_R2D_C_NPCIE_C_R2D_C_P
TP_PCIE_D_D2RNTP_PCIE_D_D2RPTP_PCIE_D_R2DNTP_PCIE_D_R2DP
TP_PCIE_E_D2RNTP_PCIE_E_D2RPTP_PCIE_E_R2DNTP_PCIE_E_R2DP
TP_PCIE_F_D2RNTP_PCIE_F_D2RPTP_PCIE_F_R2DNTP_PCIE_F_R2DP
LT2USB_OC_L
PP1V5_S0_SB_VCC1_5_BPP3V3_S5
LTUSB_OC_L
RTUSB_OC_LUNUSED_USB_B_OC_L
UNUSED_USB_D_OC_LLTUSB_OC_L
SPI_ARB
SPI_SO
USB2_LT2_P
INT_PIRQD_L
TP_SB_XOR_AD5TP_SB_XOR_AG4TP_SB_XOR_AH4TP_SB_XOR_AD9
TP_SB_XOR_AE5
TP_SB_XOR_AH8
SB_CRT_TVOUT_MUX
TP_SB_XOR_AG8TP_SB_XOR_AE9
SB_GPIO29
EXCARD_OC_L
PCI_AD<6>
PCI_AD<1>PCI_REQ0_L
PCI_REQ1_L
PCI_REQ3_L
PCI_STOP_L
SPI_SCLK
PCI_C_BE_L<2>
BOOT_LPC_SPI_L
PCI_REQ2_L
SB_GPIO30
SPI_CE_L
SPI_SI
PP3V3_S0
PCI_PME_FW_L
79 78
70 66 65 64 60 59 57 56 53 51
48 43 37 36 34 33 29 28
78
78
27
66
66
26
65
65
25
64
64
24
62
62
23
55
55
21
26
26
20
25
25
19
24
51
24
51
17
23
47
47
47
23
47
47
47
14
22
22
22
22
22
22
46
22
22
10
11
22
22
6
5
22
5
25 11
6
22
22
22
6
6
22
5
5
6
6
5
4
6
22
4
24 5
5
6
6
6
5
22
5
6
4
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
IN
IN
BI
BI
OUT
OUT
OUT
IN
IN
BI
IN
IN
BI
IN
IN
IN
IN
OUT
BI
BI
IN
OUT
IN
OUT
IN
OUT
GPIO19/SATA1GP
GPIO21/SATA0GP
GPIO36/SATA2GP
CLK48
GPIO37/SATA3GP
CLK14
SUSCLK
SLP_S3*
SLP_S4*
SLP_S5*
PWROK
TP0/BATLOW*
GPIO16/DPRSLPVR
PWRBTN*
LAN_RST*
RSMRST*
GPIO10
GPIO9
GPIO12
GPIO14
GPIO13
GPIO24
GPIO15
GPIO25
GPIO35
GPIO38
GPIO39
SMBCLK
SMBDATA
LINKALERT*
SMLINK1
SMLINK0
RI*
SYS_RST*
SPKR
SUS_STAT*
GPIO0/BM_BUSY*
GPIO18/STPPCI*
GPIO11/SMBALERT*
GPIO20/STPCPU*
GPIO26
GPIO28
GPIO27
GPIO32/CLKRUN*
GPIO33/AZ_DOCK_EN*
WAKE*
GPIO34/AZ_DOCK_RST*
SERIRQ
THRM*
GPIO7
GPIO6
VRMPWRGD
GPIO8
(4 OF 6)
SMB
GPIO
PWR MNGT
SYS GPIO
CLKS
SATA GPIO
IN
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
- HAS INTERNAL 20K PU, ENABLED DURING RSMRST# AND DISABLED WITHIN 100MS AFTER RSMRST# DEASSERTS- CAN NOT BE LOW FOR 35US AFTER RSMRST# ON BOOT (DMI AC COUPLING MODE STRAP)
AZALIA DOCKING INT’FRESERVED FOR MOBILE
SYSTEM REBOOT FEATURE
STRAPPING @ PWROK RISING:SB WILL DISABLE TCO TIMER
NOTE FOR R2323 (DEF=NOSTUFF)
NOT USED
NOTE: RESERVED FOR FUTURE
(INT WEAK PD)
LAYOUT NOTE:PLACE R2306-14 WHERE PHYSICALLY ACCESSIBLE
NOTE: DPRSLPVR HAS INT 20K PD, ENABLED AT BOOT/RESET FOR STRAPPING FCN
NOTE FOR GPIO25:
(INT 20K PU)
OD
DEF=GPI
DEF=GPI
DEF=GPI
IN RESET STATE TO SAVE PWRSMC WILL DRIVE 0-1-0 TO KEEP LAN INT’FNOTE:
NOTE: SV_SET_UP IS LINDACARD DETECT
LO = NOT PRESENTHI = PRESENT
5 50
50
50
5 14 60 86
5 32 39 43 50 54 64 65
5 41 46 47 50 63 65
5 50 51
5 6
34
34
5 27 28 29 33 45 47
5 27 28 29 33 45 47
5 33
5 33
5 50 51 52 59
5 26 50
14
5 50 52 59
5 39 47
50
5 50 52 59
5 26
50
50
5 26
23
R23021 2100 R23031 2100
R23051 210036
36
50 51
23
50
R23061
2
NOSTUFF
4025%MF-LF1/16W10K
R23071
2
10K4025%MF-LF1/16W
R23081
24021/16WMF-LF5%
10K
R23091
25%MF-LF1/16W0402
NOSTUFF
R23101
24025%MF-LF1/16W10K
R23111
21/16WMF-LF5%
NOSTUFF
40210K
R23131
2
10K1/16WMF-LF5%402
R23141
2402
NOSTUFF
01/16WMF-LF5%
33
R23161
240210K1/16WMF-LF5%
R23171
240210K1/16WMF-LF5%
R23181
2
10K4021/16WMF-LF5% R2319
1
2
10K1/16WMF-LF5%402
R23201
24025%MF-LF1/16W10K
RP2300
1 2 3 4
8 7 6 5
1/16W5%10KSM-LF
R23991 25%402MF-LF
1/16W
100K
R23981
21/16WMF-LF5%4021K
R23971
25%MF-LF1/16W8.2K402
R23961
2MF-LF5%
1/16W10K402
R23951
2
8.2K1/16WMF-LF4025%
U2100
AC1B2
AB18
A20
B23
F19E19R4E22
AC22AC20
AH18
AF21
AF19
R3D20
A21
B21E23
AG18
AC19U2
AD21
AH19AE19
AD20AE20
AC21AC18E21
E20
C19
A26
C23
AA4
A28
Y4
AH21
B24D23F22
C22B22
B25A25
A19A27
C20
A22
AF20
C21
AD22
F20
OMIT
BGASB
ICH7-M
R23901
2402
10K5%1/16WMF-LF
R23881
24021/16WMF-LF5%10K
R23231
2MF-LF4025%
1K1/16W
NO_REBOOT_MODER23261
2
NOSTUFF
10K1/16WMF-LF4025%
R23271
2
NOSTUFF
5%MF-LF1/16W40210K
R23431
25%
402
8.2K1/16WMF-LF
50
SB: 3 OF 4SYNC_DATE=02/10/2006SYNC_MASTER=M1_MLB
051-7023
8623
06
SV_SET_UP
PM_RSMRST_L
SMBUS_SB_SCL
SATA_C_DET_LSB_GPIO19SB_GPIO21
SB_CLK48M_USBCTLR
SB_GPIO37
SB_CLK14P3M_TIMER
TP_SB_SUS_CLK
PM_SLP_S3_LPM_SLP_S4_LPM_SLP_S5_L
PM_SB_PWROK
PM_BATLOW_L
PM_DPRSLPVR
PM_PWRBTN_L
PM_LAN_ENABLE
SV_SET_UP
TP_SB_GPIO25_DO_NOT_USESB_CLK100M_SATA_OE_L
SATA_C_PWR_EN_L
SMB_LINK_ALERT_L
SMLINK<1>SMLINK<0>
PM_RI_L
PM_SYSRST_LPM_SUS_STAT_L
BIOS_REC
TP_AZ_DOCK_EN_L
VR_PWRGD_CK410
PP3V3_S5
PP3V3_S5
PP3V3_S5
IDE_RESET_L
TP_SB_GPIO6TP_SB_GPIO38
CRB_SV_DET
PP3V3_S5
FWH_MFG_MODEBIOS_REC
PP3V3_S0
SMC_SB_NMIPATA_PWR_EN_L
SMS_INT_L
SMC_WAKE_SCI_L
CRB_SV_DET
PP3V3_S0
SATA_C_PWR_EN_L
PP3V3_S5
PATA_PWR_EN_L
PM_STPPCI_L
TP_AZ_DOCK_RST_L
FWH_MFG_MODE
PM_STPCPU_L
PM_BMBUSY_L
SB_SPKR
SMBUS_SB_SDA
PP3V3_S5
INT_SERIRQPCIE_WAKE_L
PM_CLKRUN_L
SMB_ALERT_L
SB_GPIO26
PM_THRM_L
SMC_EXTSMI_LSMC_RUNTIME_SCI_L
79
79
78
78
70
70
66
66
65
65
64
64
60
60
59
59
57
57
56
56
53
53
51
51
48
48
43
43
37
37
36
36
34
34
33
33
29
29
28
28
27
27
78
78
78
78
26
26
78
78
66
66
66
66
25
25
66
66
65
65
65
65
24
24
65
65
64
64
64
64
23
23
64
64
62
62
62
62
22
22
62
62
55
55
55
55
21
21
55
55
26
26
26
26
20
20
26
26
25
25
25
25
19
19
25
25
24
24
24
24
17
17
24
24
23
23
23
23
14
14
23
23
52
52
22
22
22
22
10
10
22
22
23
23
11
11
11
11
5
5
11
11
5
5
23
5
5
5
23
5
23
23
4
23
4
23
5
23
23
5
(6 OF 6)
VSS
V5REF_SUS
VCC3_3
VCCDMIPLL
VCCSATAPLL
VCC3_3
VCCRTC
VCCUSBPLL
VCCSAUS1_5
VCC PAUX
USB COREVCC1_5_A
ARX
USB
PCI
IDE
VCCA3GP
CORE
ATX
VCC1_5_A
VCC3_3
VCC3_3
VCCSUS3_3
VCC1_5_A
VCCSUS3_3
VCCSUS3_3
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCCLAN1_5
V_CPU_IO
VCC3_3/VCCHDA
VCCSUS3_3/VCCSUSHDA
VCCLAN_3_3
VCC1_05
V5REF
VCC1_5_B
(5 OF 6)
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
NOTE FOR VCCLAN_3_3:S3 IF INTERNAL LAN IS USEDS0 OR S3 IF NOT
CHANGE SYMBOL TO 1.05
CHANGE SYMBOL TO 1.05
SO NO CONNECT HEREVOLTAGE GENERATED INTERNALLY
SO NO CONNECT HEREVOLTAGE GENERATED INTERNALLY
NOTE:VCCHDA AND VCCSUSHDA CAN BE 1.5V OR 3.3VDEPENDING ON VIO OF AZALIA INTERFACECODEC IC’S CONSIDERED SO FAR ARE 3.3V
0 0
U2100A4
A23
B1
B8B11B14B17B20B26B28C2C6C27
D10
D13D18D21D24E1E2E4E8E15F3
F4
F5F12F27F28G1G2G5G6G9G14
G18
G21G24G25G26H3H4H5H24H27H28
J1
J2J5J24J25J26K24K27K28L13L15
L24
L25L26M3M4M5M12M13M14M15M16
M17
M24M27M28N1N2N5N6N11N12N13
N14
N15N16
AE24AE25AF2AF4AF8
AF11AF27AF28
N17
AG1AG3AG7
AG11AG14AG17AG20AG25AH1AH3
N18
AH7AH12AH23AH27
N24
N25N26P3P4
P12P13P14P15P16P17
P24
P27P28R1
R11R12R13R14R15R16R17
R18
T6T12T13T14T15T16T17U4
U12U13
U14
U15U16U17U24U25U26V2
V13V15V24
V27
V28W6
W24W25W26Y3
Y24Y27Y28AA1
AA24
AA25AA26AB4AB6
AB11AB14AB16AB19AB21AB24
AB27
AB28AC2AC5AC9
AC11AD1
AD3AD4AD7AD8
AD11
AD15AD19AD23AE2AE4AE8AE11AE13AE18AE21
OMIT
BGA
ICH7-MSB
U2100G10
AD17
F6
AE23AE26AH26
L11
P18T11T18U11U18V11V12V14V16V17
L12
V18
L14L16L17L18M11M18P11
AB7AC6
AB9AC10AD10AE10AF10AF9AG9AH9
AB17AC17
AC7
T7F17G17
AB8AC8
A1H6H7J6J7
AD6AE6AF5AF6AG5AH5
AB10
AA22AA23
AD28D26D27D28E24E25E26F23F24G22
AB22
G23H22H23J22J23K22K23L22L23M22
AB23
M23N22N23P22P23R22R23R24R25R26
AC23
T22T23T26T27T28U22U23V22V23W22
AC24
W23Y22Y23
AC25AC26AD26AD27
U6
B27
AH11
AG19
A5B13B16B7C10D15F9G11G12
AA7
G16
AB12AB20AC16AD13AD18AG12AG15
AG28
AA2Y7
V5V1W2W7
W5
AD2
K7
C28G20
R7
P7
A24
L1L2L3L6L7M6M7N7
E3
C24D19D22G19
K3K4K5K6
C1
OMIT
BGASB
ICH7-M
SB: 4 OF 4SYNC_DATE=02/10/2006SYNC_MASTER=M1_MLB
06
24 86
051-7023
PP1V5_S0_SB_VCC1_5_B
PP5V_S0_SB_V5REF
PP5V_S5_SB_V5REF_SUS
PP1V05_S0
PP3V3_S0
PP3V3_S0PP3V3_S5
PP1V05_S0
PP3V3_S0
PP1V5_S0_SB_VCCDMIPLL
PP1V5_S0
PP1V5_S0
PP3V3_S0
PP1V5_S0
PP3V3_S5
PP3V3_S0
PP3V3_S0
PP3V3_G3C_SB_RTC_D
PP3V3_S5
PP3V3_S5
PP1V5_S0
PP1V5_S0
PP1V5_S0
79
79
79
79
79
79
78
78
78
78
78
78
70
70
70
70
70
70
66
66
66
66
66
66
65
65
65
65
65
65
64
64
64
64
64
64
60
60
60
60
60
60
59
59
59
59
59
59
57
57
57
57
57
57
56
56
56
56
56
56
53
53
53
53
53
53
51
51
51
51
51
51
48
48
48
48
48
48
43
43
43
43
43
43
37
37
37
37
37
37
36
36
36
36
36
36
34
34
34
34
34
34
66
33
33
66
33
33
33
33
64
29
29
64
29
29
29
29
54
28
28
54
28
28
28
28
34
27
27
34
27
27
27
27
25
26
26
25
26
26
78
26
26
78
78
24
25
25
24
25
66
66
25
66
66
25
25
66
66
66
66
66
21
24
24
21
24
65
65
24
65
65
24
24
65
65
65
65
65
19
23
23
19
23
47
47
23
47
64
23
23
64
64
47
47
47
17
22
22
17
22
25
25
22
25
62
22
22
62
62
25
25
25
16
21
21
16
21
24
24
21
24
55
21
21
55
55
24
24
24
13
20
20
13
20
19
19
20
19
26
20
20
26
26
19
19
19
12
19
19
12
19
17
17
19
17
25
19
19
25
25
17
17
17
11
17
17
11
17
16
16
17
16
24
17
17
24
24
16
16
16
9
14
14
9
14
13
13
14
13
23
14
14
23
23
13
13
13
8
10
10
8
10
9
9
10
9
22
10
10
26
22
22
9
9
9
25
7
5
5
7
5
8
8
5
8
11
5
5
25
11
11
8
8
8
22
25
25
5
4
4
5
4
25
5
5
4
5
5
4
4
21
5
5
5
5
5
NC
NC
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
(ICH IO,LOGIC 1.5V PWR)ICH VCCA3GP(VCC1_5_B BYPASS
PLACE < 2.54MM OF SB ON
PLACE < 2.54MM OF SB ON SECONDARY OR
PLACEMENT NOTE:PLACE CAPS AT EDGE OF SB
ICH VCC3_3/VCCHDA BYPASS(ICH INTEL HDA CORE 3.3V PWR)
PLACE NEAR PINS AE23, AE26 & AH26 OF SB
PLACE C2500 & C2505-07 < 2.54MM OF SBON SECONDARY SIDE OR 3.56MM ON PRIMARY
ICH VCCUSBPLL BYPASS(ICH USB PLL 1.5V PWR)
(ICH DMI PLL 1.5V PWR)
ICH PCI/VCC3_3 BYPASS
(ICH IDE I/O 3.3V PWR)
PLACEMENT NOTE:PLACE < 2.54MM OF SB ON SECONDARY OR
PLACEMENT NOTE:PLACE < 2.54MM OF SB ON SECONDARY OR3.56MM ON PRIMARY NEAR PIN AH11
PLACEMENT NOTE:
PLACEMENT NOTE:
PLACEMENT NOTE:
ICH USB CORE/VCC1_5_A BYPASS
PLACE < 2.54MM OF SB ON SECONDARY OR3.56MM ON PRIMARY NEAR PINS A1 ... J7
(ICH USB CORE 1.5V PWR)
(ICH LOGIC&IO 1.5V PWR)ICH VCC1_5A BYPASS
PLACEMENT NOTE:
PLACEMENT NOTE:
ICH VCCSUS3_3 BYPASS(ICH SUSPEND 3.3V PWR)
PLACEMENT NOTE:
PLACEMENT NOTE:
PLACEMENT NOTE:
3.56MM ON PRIMARY NEAR PIN U6
PLACE CAP UNDER SB NEAR PINS V1,PLACEMENT NOTE:
(ICH CORE 1.05V PWR)ICH CORE/VCC1_05 BYPASS
PLACEMENT NOTE:
ICH V5REF BYPASS
PLACE < 2.54MM OF SB ON SECONDARY OR
SB: 4 OF 4
PLACEMENT NOTE:
PLACEMENT NOTE:
PLACE CAPS NEAR PIN W5 OF SB
PLACEMENT NOTE:PLACE CAPS NEAR PINS
FOR 270UFPLACEHOLDER
PLACEMENT NOTE:
3.56MM ON PRIMARY NEAR PIN AG5
3.56MM ON PRIMARY NEAR PIN AG9
(ICH IO BUFFER 3.3V PWR)
NEAR PINS A5 ... G16 DISTRIBUTE IN PCI SECTION OF SB
A24 ... G19 AND P7 OF SB
(ICH PCI I/O 3.3V PWR)
PLACE < 2.54MM OF SB ON SECONDARY OR
ICH IDE/VCC3_3 BYPASS
(ICH CPU I/O 1.05V PWR)ICH V_CPU_IO BYPASS
PLACE < 2.54MM OF SB ON SECONDARY OR
(ICH SATA PLL 1.5V PWR)ICH VCCSATAPLL BYPASS
(ICH REFERENCE FOR 5V TOLERANCE ON CORE WELL INPUT)
(ICH IO BUFFER 3.3V PWR)
ICH VCC1_5_A/ATX BYPASS
PLACEMENT NOTE:
NEAR PINS D28, T28, AD28
PLACE C2520 NEAR PIN C1 OF SB
K3 ... N7 OF SBPLACE CAPS NEAR PINS
(ICH SUSPEND USB 3.3V PWR)ICH USB/VCCSUS3_3 BYPASS
AB8 AND AC8 OF SBPLACE CAPS NEAR PINSPLACEMENT NOTE:
(ICH LAN I/F BUFFER 3.3V PWR)ICH VCC_PAUX/VCCLAN3_3 BYPASS
3.56MM ON PRIMARY NEAR PIN AD2
3.56MM ON PRIMARY NEAR PINS AA7 ... AG19
V5, W2, OR W7
ICH VCCRTC BYPASS(ICH RTC 3.3V PWR)
ICH VCC3_3 BYPASS
PLACEMENT NOTE:PLACE C2509 NEAR PIN B27 OF SB
ICH VCC3_3 BYPASS
ICH VCC1_5_A/ARX BYPASS(ICH LOGIC&IO[ARX] 1.5V PWR)
(ICH LOGIC&IO[ATX] 1.5V PWR)
ICH VCCSUS3_3 BYPASS(ICH SUSPEND 3.3V PWR)
ICH V5REF_SUS BYPASS(ICH REFERENCE FOR 5V TOLERANCE ON RESUME WELL LOGIC)
PLACEMENT NOTE:PLACE C2504 < 2.54MM OF PIN F6 OF SBON SECONDARY SIDE OR 3.56MM ON PRIMARY
ON SECONDARY SIDE OR 3.56MM ON PRIMARYPLACE C2503 < 2.54MM OF PIN AD17 OF SBPLACEMENT NOTE:
PLACE C2520 NEAR PIN E3 OF SB
ICH VCCDMIPLL BYPASS
SECONDARY SIDE OR 3.56MM ON PRIMARY
C25001
220%220UFPOLY2.5VSMB2
C25101
2 X5R16V10%0.1UF
402
0
C25121
2402
0.1UF10%16VX5R
0
R25001 21
5%1/10WMF-LF603
C25241
2
4.7UF20%6.3VCERM603
C25221
2
0.1UF10%16VX5R402
D25021
6
5 BAT54DWSOT-363
D25024
3
2BAT54DWSOT-363
L25071 2
1206
0.28-OHM
C25031
2
0.1UF
402
10%16VX5R
0
C25041
2 X5R16V10%0.1UF
402
0
R2501
12
5%MF-LF1/16W402
10
L2500
1 2
100-OHM-EMISM-3
0
C25051
2
0.1UF10%16VX5R402
C25061
2 X5R16V10%0.1UF
402
C25071
2
0.1UF16V10%X5R402
C25011
2
0.01UF10%16VCERM402
C25081
2603
10UF20%6.3VX5R
0
C25091
210%16VX5R402
0.1UF
0
C25111
2 X5R40216V10%0.1UF
0
C25171
2
0.1UF
402X5R16V10%
0
C25131
2
0.1UF10%16VX5R402
0
0
C25141
24026.3VCERM10%1UF
0
C25201
2
0.1UF10%16VX5R402
C25151
2402X5R16V10%0.1UF
0
0
C25161
2CASE-C2POLY20%2.5V330UF
R2502
1
2
5%
1/16W402MF-LF100 C25021
2
1UF10%6.3VCERM402
C25181
2402
0.1UF10%16VX5R
0
C25191
2 X5R16V10%0.1UF
402
0
C25211
2
0.1UF10%16V402X5R
0
C25231
2 X5R16V10%0.1UF
402
0
C25251
2
0.1UFX5R16V10%
402
0
C25261
2 X5R16V10%0.1UF
402
C25271
2 X5R16V10%0.1UF
402
C25281
2 X5R16V10%0.1UF
402
C25291
2402
0.1UF10%16VX5R
0
C25301
2402
0.1UF10%16VX5R
C25341
2402
0.1UF10%16VX5R
0
C25311
2402
0.1UF10%16VX5R
C25321
2402
0.1UF10%16VX5R
0
C25331
2402
0.1UF10%16VX5R
051-7023
8625
06
PP5V_S0_SB_V5REFVOLTAGE=5V
MIN_LINE_WIDTH=0.3MMMIN_NECK_WIDTH=0.25MM
PP5V_S5_SB_V5REF_SUS
MIN_NECK_WIDTH=0.25MM
VOLTAGE=5VMIN_LINE_WIDTH=0.3MM
PP5V_S0
PP3V3_S5
PP3V3_S0
PP5V_S5
PP3V3_G3C_SB_RTC_D
PP3V3_S0
PP1V5_S0
PP3V3_S5
PP1V5_S0
PP3V3_S0
PP3V3_S0
PP1V5_S0
PP3V3_S0
PP3V3_S5
PP1V5_S0
PP3V3_S5
PP1V5_S0
PP3V3_S0
PP1V5_S0_SB_VCCDMIPLL_FVOLTAGE=1.5V
MIN_LINE_WIDTH=0.5MMMIN_NECK_WIDTH=0.25MM MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.5MMVOLTAGE=1.5V
PP1V5_S0_SB_VCCDMIPLL
PP1V5_S0
PP1V05_S0
PP3V3_S0
PP1V05_S0
PP1V5_S0
PP1V5_S0
VOLTAGE=1.5VMIN_LINE_WIDTH=0.5MMMIN_NECK_WIDTH=0.25MM
PP1V5_S0_SB_VCC1_5_B
79
79
79
79
79
79
79
78
78
78
78
78
78
78
70
70
70
70
70
70
70
66
66
66
66
66
66
66
65
65
65
65
65
65
65
64
64
64
64
64
64
64
60
60
60
60
60
60
60
59
59
59
59
59
59
59
57
57
57
57
57
57
57
56
56
56
56
56
56
56
53
53
53
53
53
53
53
51
51
51
51
51
51
51
48
48
48
48
48
48
48
43
43
43
43
43
43
43
37
37
37
37
37
37
37
80
36
36
36
36
36
36
36
79
34
34
34
34
34
34
34
78
33
33
33
33
33
33
66
33
66 70
29
29
29
29
29
29
64
29
64 67
28
28
28
28
28
28
54
28
54 66
27
27
27
27
27
27
34
27
34
65
78
26
26
78
26
26
26
78
78
26
25
26
25
61
66
25
25
66
66
66
25
25
66
25
66
66
66
66
25
66
24
25
24
66
66
60
65
24
24
65
65
65
24
24
65
24
65
65
65
65
24
65
21
24
21
65
65
57
64
23
70
23
47
64
47
23
23
47
23
64
47
64
47
23
47
19
23
19
47
47
56
62
22
67
22
25
62
25
22
22
25
22
62
25
62
25
22
25
17
22
17
25
25
54
55
21
66
21
24
55
24
21
21
24
21
55
24
55
24
21
24
16
21
16
24
24
52
26
20
65
20
19
26
19
20
20
19
20
26
19
26
19
20
19
13
20
13
19
19
47
25
19
64
19
17
25
17
19
19
17
19
25
17
25
17
19
17
12
19
12
17
17
42
24
17
63
17
16
24
16
17
17
16
17
24
16
24
16
17
16
11
17
11
16
16
36
23
14
61
14
13
23
13
14
14
13
14
23
13
23
13
14
13
9
14
9
13
13
31
22
10
51
26
10
9
22
9
10
10
9
10
22
9
22
9
10
9
8
10
8
9
9
5
11
5
46
24
5
8
11
8
5
5
8
5
11
8
11
8
5
8
7
5
7
8
8
24
24
24
4
5
4
5
21
4
5
5
5
4
4
5
4
5
5
5
5
4
24
5
5
4
5
5
5
22
BI
BI
IN
IN
IN
IN
BI
BI
BI
BI
BI
BI
BI
OUT
OUT IN
IN
OUT
IN OUT
IN
SYM_1
NCNC
IN
OUT
OUT
BI
BI
BI
BI
BI
BI
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
fault protection for RTC battery.NOTE: R2607 and D2600 form the double-
NCNC
Silk: "SYS RST"
Unbuffered
518S0226
NC
NC
RTC Battery Connector
SB RTC Crystal Circuit
it provides a set of padson the board to short orto solder a reset button.
1G00 used as small & cheap inverter
100-ohm on NB page
Linda Card represents 3 loads
Buffered
LIO represents X loads (2?)
This part is never stuffed,
NCNC
Initial resistor values are based on CRB,but may change after characterization.
Platform Reset Connections
22
22 37
22
22
22
4 22 37
22
22
22
R26001 2
MF-LF
5%
402
1/16W
20K
22
22 37
22
22
21
C2611 1
2
0.1UF
402CERM10V20%
5 23
C26051
2402CERM6.3V10%1UF
5 14 60
26 33 60
26 33 60
R26981
2
100K
MF-LF402
5%1/16W
OMIT7 11
R26061
2
1M
402MF-LF1/16W5%
5 23 50
R26971
2
10K
MF-LF402
5%1/16W
R26072 1
402
5%
MF-LF1/16W
1K
C26081 212pF
CERM402
5%50V
C26091 212pF
50V5%
402CERM
Y2600
24
13
SM-2
CRITICAL
32.768K
R26101 2
0
402MF-LF1/16W5%
R26091
2
10M
402MF-LF1/16W
5%
C26801
2 CERM
0.1UF20%10V
402
R26801
2
100K5%1/16WMF-LF402
R26811 2
402
0
MF-LF1/16W5%
R26831 2100
402MF-LF1/16W5%
R26841 2
0
1/16W5%
MF-LF402
R26851 2
0
402MF-LF1/16W5%
R26871 2
0
5%1/16WMF-LF402
R26821 2
0
402MF-LF1/16W5%
5 14 22 26
J2600
3
4
1
2
CRITICAL
F-RT-SM88460-0201
R26961 2
402
ITP
5%1/16WMF-LF
1K
U2603
3
2
1
4
5MC74VHC1G00SC70-5
U2680
3
2
1
4
5 MC74VHC1G08SC70
U2601
3
2
1
4
5SC70
MC74VHC1G08
D2600
1
4
6
3
5 2
BAT54DWSOT-363
50 65
R26111
2402MF-LF1/16W5%1.8K
C2607 1
2
0.1UF
402CERM10V20%
5 23
R26121
2402MF-LF1/16W
5%10K R26221
2
10K5%1/16WMF-LF402
R2623 1 2 8.2KR2624 1 2 8.2KR2625 1 2 8.2KR2626 1 2 8.2KR2627 1 2 8.2KR2628 1 2 8.2K
R2629 1 2 8.2KR2630 1 2 8.2K
R2631 1 2 8.2K
R2632 1 2 8.2K
R2633 1 2 8.2KR2634 1 2 8.2K
R2636 1 2 8.2K
5 21
R2637 1 2 8.2K
R2638 1 2 8.2KR2639 1 2 8.2KR2640 1 2 8.2K
R2641 1 2 8.2KR2642 1 2 8.2K
C26101
2402
6.3V10%
CERM
1UF
22 37
22 37
22 37
22 37
22 37
22 37
SYNC_MASTER=M1_MLB SYNC_DATE=02/10/2006
26
051-7023 06
86
SB Misc
PLT_RST_BUF_L
TPM_LRESET_L
ENET_RST_L
MAKE_BASE=TRUEPLT_RST_L
MAKE_BASE=TRUEVOLTAGE=3.3V
PP3V3_G3C_SB_RTC_D
SB_GPIO4
SB_GPIO2SB_GPIO3
INT_PIRQD_L
INT_PIRQB_LINT_PIRQC_L
PCI_REQ3_L
INT_PIRQA_L
PCI_REQ2_LPCI_REQ1_LPCI_REQ0_L
PCI_LOCK_LPCI_PERR_LPCI_DEVSEL_LPCI_SERR_LPCI_STOP_LPCI_TRDY_LPCI_IRDY_LPCI_FRAME_L
PP3V3_S0PP3V3_G3C_SB_RTC_D
PP3V42_G3H
PPVBATT_G3C_RTC_RVOLTAGE=3.3V
PP3V3_S0
VR_PWRGOOD_DELAY
ALL_SYS_PWRGDPM_SB_PWROK
PP3V3_S0
VR_PWRGD_CK410_LMAKE_BASE=TRUE
PP3V3_S0
MAKE_BASE=TRUEPM_SYSRST_LXDP_DBRESET_L
SB_SM_INTRUDER_L
LIO_PLT_RESET_LSB_RTC_X1
DEBUG_RST_L
SMC_LRESET_L
PEG_RESET_L
PLT_RST_L
PP3V3_S5
VR_PWRGD_CK410
VR_PWRGD_CK410_L
SB_RTC_RST_L
PPVBATT_G3C_RTCVOLTAGE=3.3V
SB_RTC_X1_R
SB_RTC_X2
79
79
79
79
78
78
78
78
70
70
70
70
66
66
66
66
65
65
65
65
64
64
64
64
60
60
60
60
59
59
59
59
57
57
57
57
56
56
56
56
53
53
53
53
51
51
51
51
48
48
48
48
43
43
43
43
37
37
37
37
36
36
36
36
34
34
34
34
33
33
33
33
29
29
29
29
28
28
28
28
27
27
27
27
26
26
26
26
25
68
25
25
25
78
24
67
24
24
24
66
23
66
23
23
23
65
22
65
22
22
22
64
21
54
21
21
21
62
20
52
20
20
20
55
19
51
19
19
19
25
17
50
17
17
17
24
26
14
26
45
14
14
14
26
23
25
10
25
35
10
10
10
22
22
59
24
5
24
27
5
5
5
47
52
50
69
14
11
37
5
39
21
4
21
5
4
4
4
5 21
5
5
5
5
5
21
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
(MASTER)U5800
ICH7-M SMBus Connections
(Write: 0xD2 Read: 0xD3)CY28445-5: U3301Clock Chip
SO-DIMM "A"
Right Temp - TMP105
(Write: 0x52 Read: 0x53)
ICH7-M(MASTER)
Left I/O SMBus Connections:
LIO - TMP105(Write: 0x90 Read: 0x91)
SMC "Battery A" SMBus Connections
Left I/O Board
NOTE: SMC RMT bus remains powered and may be active in S3 stateSMC "A" SMBus Connections
(Write: 0x16 Read: 0x17)
Top-CaseTop-Case SMBus Connections:
(Write: 0x90 Read: 0x91)
Battery
U5800(MASTER)
J4900Trackpad
J2900(Write: 0xA4 Read: 0xA5)
(See Table)J5500
Left Temp - TMP105 (See Table)
(Write: 0x98 Read: 0x99)
CPU TempADT7461: U1001
J5400(See Table)
SMC "B" SMBus Connections
U5800SMC
(MASTER)
SMC
(Write: 0x92 Read: 0x93)
Left ALS - TSL2561
(Write: 0x90 Read: 0x91)
J4900
(Write: 0x30 Read: 0x31)
(Write: 0x98 Read: 0x99)
MAX6695: U6100
U2100
J2800
TMP105: J4930
GPU Temp
ADT7461: U6150Right-Side Temp
Ambient Thermal
(MASTER)U5800
J8250
SMC "Battery B" SMBus Connections
SMCU5800
(MASTER)
SMC "0" SMBus Connections
(See Table)
Left I/O Board
ExpressCard Slot(Address determined by ARP)
(Write: 0x92 Read: 0x93)
(Write: 0x70 Read: 0x71)
M35 - TMP105
Trackpad I2C Connections:
U1 - Trackpad Controller
SMC
SMC
(Write: 0xA0 Read: 0xA1)
SO-DIMM "B"
Left I/O SMBus Connections:
(Write: 0x72 Read: 0x73)U2 - Keyboard Controller
R27001
2MF-LF
402
1/16W5%
4.7KR27011
2
4.7K1/16WMF-LF402
5%
R27801
2
1/16W5%
402MF-LF
4.7KR27811
2
1/16W5%
402MF-LF
4.7K
R27911
2
100K5%1/16W
402MF-LF
R27901
2
100K1/16W
5%
402MF-LF
R27611
2402MF-LF1/16W5%4.7K
R27601
2
5%1/16W
402MF-LF
4.7K
R27711
2
1/16WMF-LF402
5%4.7K
R27701
2
1/16W
402MF-LF
5%4.7K
R27511
2
4.7K5%1/16WMF-LF402
R27501
2MF-LF
402
5%1/16W
4.7K
C27011
2402
50V5%100pF
NO STUFF
CERM
C27611
2402CERM50V5%100pFC27511
2402CERM50V5%100pF
R27521
2
47
402MF-LF1/16W5%
M1 SMBus ConnectionsSYNC_MASTER=M1_MLB SYNC_DATE=01/04/2006
8627
06051-7023
MAKE_BASE=TRUESMBUS_SB_SDA
SMBUS_SB_SDA
SMBUS_SMC_B_S0_SDASMBUS_SB_SDA
SMBUS_SB_SCLMAKE_BASE=TRUESMBUS_SB_SCL
PP3V3_S3
SMBUS_SMC_A_S3_SDAMAKE_BASE=TRUE
MAKE_BASE=TRUESMBUS_SMC_A_S3_SCL
PP3V3_S0
PP3V42_G3H
SMBUS_SMC_BSA_SDAMAKE_BASE=TRUE
MAKE_BASE=TRUESMBUS_SMC_BSA_SCL
PP3V3_S0
SMBUS_SMC_0_S0_SCL_R
SMBUS_SB_SDA
PP3V3_S0
MAKE_BASE=TRUESMBUS_SMC_BSB_SCL
SMBUS_SMC_BSB_SDAMAKE_BASE=TRUE
SMBUS_SMC_BSA_SCL
SMBUS_SMC_BSB_SCL
SMBUS_SMC_0_S0_SCL
SMBUS_SMC_0_S0_SDA
SMBUS_SMC_0_S0_SCL
SMBUS_SMC_0_S0_SDA
SMBUS_SB_SDA
SMBUS_SB_SCL
SMBUS_SMC_0_S0_SDA
SMBUS_SMC_BSB_SDA
SMBUS_SMC_A_S3_SDA
SMBUS_SMC_A_S3_SCL
SMBUS_SMC_B_S0_SDA
SMBUS_SMC_B_S0_SCL
SMBUS_SMC_A_S3_SCL
SMBUS_SMC_B_S0_SCL
SMBUS_SB_SCL
SMBUS_SB_SDA
SMBUS_SB_SCL
SMBUS_SB_SCL
SMBUS_SB_SDA
SMBUS_SMC_BSA_SDASMBUS_SMC_BSA_SDA
SMBUS_SMC_BSA_SCL
PP3V3_S0
SMBUS_SMC_B_S0_SDA
SMBUS_SMC_B_S0_SCLMAKE_BASE=TRUESMBUS_SMC_B_S0_SDA
MAKE_BASE=TRUE
SMBUS_SMC_B_S0_SCL
SMBUS_SMC_A_S3_SDA
SMBUS_SB_SCL
MAKE_BASE=TRUESMBUS_SMC_0_S0_SDA
SMBUS_SMC_0_S0_SCL
SMBUS_SMC_0_S0_SDA
SMBUS_SMC_0_S0_SCLMAKE_BASE=TRUE
MAKE_BASE=TRUESMBUS_SMC_0_S0_SCL_R
79 79
79
79 78 78
78
78 70 70
70
70 66 66
66
66 65 65
65
65
64 64
64
64 60 60
60
60 59 59
59
59 57 57
57
57 56 56
56
56 53 53
53
53 51 51
51
51 48 48
48
48 43 43
43
43
37 37
37
37 36 36
36
36 34 34
34
34 33 33
33
33 29 29
29
29 28 28
28
28
80
27 27
27
27
66
26 26
26
26
64
25
68
25
25
25
63
24
67
24
24
24
62
23
66
23
23
23
59
22
65
22
22
22
47
47
47
58
21
54
21
47
21
47
47
47
47
47
47
47
21
47
45
45
45
56
20
52
20
45
20
45
45
45
45
45
45
45
20
45
33
33
33
51
19
51
19
33
19
33
33
33
33
33
33
33
19
33
29
50 29
29
45
17
50
17
29
17
53
53
29
29
53
50
50
50
29
29
29
29
29
17
50
50 29
53
28
48 28
28
41
14
45
14
28
14
67
53
50
53
50
28
28
50
48
48
48
28
28
28
28
28
67 67
14
48
48 28 53
50
27
27 27
27
37
50
50
10
35
10
27
10
50
50
45
50
45
27
27
45
50
50
27
27
50
27
27
27
27
27
27
50 50
10
27
27
50
27 50
45
23
10 23
23
32
45
45
5
26
5
45
23
5
50
50
27
50
27
27
27
27
23
23
27
50
45
45
10
10
45
10
23
23
23
23
23
27 27
5
10
10
45
23 27
27
45
5
4 5
5
5
27
27
4
5
4
27
5
4
27
27
5
27
5
5
5
5
5
5
5
27
27
27
4
4
27
4
5
5
5
5
5
5 5
4
4
4
27
5 5
5
27
VSS2
DQS0*
DQ5
VSS0
DQ4
VSS5
DQ6
VSS29
DM0
VSS7
DM1
DQ7
VDD1
DQ30
DQ23
VSS22
NC/ODT1
RAS*
SA1
SA0
VSS58
DQ63
DQ62
VSS56
DQS7
DQS7*
VSS54
DQ60
VSS52
DQ54
VSS50
VSS48
CK1*
CK1
VSS46
DQ53
DQ52
VSS44
VSS42
DQS5
DQS5*
VSS39
DQ45
DQ44
VSS37
DQ39
DQ38
VSS35
DM4
VSS34
DQ37
DQ36
VSS32
NC3
VDD11
NC/A13
ODT0
VDD9
S0*
BA1
VDD7
A0
A2
A4
VDD5
A6
A7
A11
VDD3
NC/A14
NC/A15
NC/CKE1
VSS30
DQ31
DQS3
DQ29
DQ28
VSS24
DQ22
DM2
NC0
VSS19
DQ21
DQ20
VSS17
VSS15
DQ15
DQ14
VSS13
CK0*
CK0
VSS11
DQ13
DQ12
DQ47
DQ46
DQ61
DQ55
DM6
VDDSPD
SCL
SDA
VSS57
DQ59
DQ58
VSS55
DM7
VSS53
DQ56
VSS51
DQ50
VSS49
DQS6*
VSS47
NC_TEST
VSS45
DQ49
DQ48
VSS43
VSS41
DM5
VSS40
DQ41
VSS38
DQ35
VSS36
DQS4
DQS4*
VSS33
DQ33
DQ32
VSS31
VDD10
NC/S1*
CAS*
VDD8
WE*
BA0
A10/AP
VDD6
A1
A3
A5
VDD4
A8
A9
A12
VDD2
BA2
NC2
VDD0
CKE0
DQ27
DQ26
VSS27
NC1
DM3
DQ25
DQ24
VSS23
DQ19
DQ18
VSS21
DQS2
DQS2*
VSS18
DQ17
DQ16
VSS16
VSS14
DQ11
DQ10
VSS12
DQS1
DQS1*
DQ9
DQ8
VSS8
DQ3
DQ2
VSS6
DQS0
VREF
DQ34
DQ40
DQ42
DQ43
DQS6
DQ51
DQ57
KEY
VSS9
DQ1
VSS4
DQ0
VSS1
DQS3*
VSS26
VSS28
VSS25
VSS10
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
NC
DDR2 Bypass Caps(For return current)
ADDR=0xA0(WR)/0xA1(RD)
NC
NC
NC
NC
516S0382
- =PPSPD_S0_MEM (2.5V - 3.3V)- =PP1V8_S3_MEM
Signal aliases required by this page:
BOM options provided by this page:(NONE)
Power aliases required by this page:
NC
- =I2C_SODIMMA_SCL- =I2C_SODIMMA_SDA
Page Notes
NOTE: This page does not supply VREF.The reference voltage must be providedby another page.
"Lower" (surface-mount) slot
C28131
2
0.1uF
CERM402
20%10V
C28121
2
0.1uF
CERM402
20%10V
C28091
2
10UF
X5R603
20%6.3V
C28111
2
0.1uF
CERM402
20%10V
C28081
2
10UF
X5R603
20%6.3V
C28101
2
0.1uF
CERM402
20%10V
C28191
2
0.1uF
CERM402
20%10V
C28181
2
0.1uF
CERM402
20%10V
C28171
2
0.1uF
CERM402
20%10V
C28161
2
0.1uF
CERM402
20%10V
C28211
2
0.1uF
CERM402
20%10V
C28201
2
0.1uF
CERM402
20%10V
C28151
2
0.1uF
CERM402
20%10V
C28141
2
0.1uF
CERM402
20%10V
C28001
2
0.1uF
CERM402
20%10V
J2800
102A
105A
90A89A
101A
100A99A
98A97A
94A
92A
93A
91A
107A
106A
85A
113A
30A
32A
164A
166A
79A
10A
26A
52A
67A
130A
147A
170A
185A
5A
35A
37A
20A
22A
36A
38A
43A
45A
55A
57A
7A
44A
46A
56A
58A
61A
63A
73A
75A
62A
64A
17A
74A
76A
123A
125A
135A
137A
124A
126A
134A
136A
19A
141A
143A
151A
153A
140A
142A
152A
154A
157A
159A
4A
173A
175A
158A
160A
174A
176A
179A
181A
189A
191A
6A
180A
182A
192A
194A
14A
16A
23A
25A
13A
11A
31A
29A
51A
49A
70A
68A
131A
129A
148A
146A
169A
167A
188A
186A
201
202
203
204
116A
86A
84A
80A
119A
115A
50A
69A
83A
120A
163A
114A
108A
110A
198A
200A
197A
195A
81A
117A 118A
82A
87A 88A
95A 96A
103A 104A
111A 112A
199A
1A 2A
27A 28A
33A 34A
39A 40A
41A 42A
47A 48A
3A
53A 54A
59A 60A
65A 66A
71A 72A
77A
8A
78A
121A 122A
127A 128A
132A
133A
138A
139A
144A
145A
149A 150A
155A 156A
161A 162A
165A
168A
171A
9A
172A
177A 178A
183A 184A
187A
190A
193A
196A
12A
15A
18A
21A
24A
109A
DDR2-SODIMM-DUAL
F-RT-SM
CRITICAL
C2801 1
2
2.2uF20%
603CERM16.3V
SYNC_DATE=02/10/2006SYNC_MASTER=M1_MLB
DDR2 SO-DIMM Connector A
051-7023 06
8628
MEM_A_DQ<56>
MEM_A_DQS_N<7>
MEM_A_DQ<63>
MEM_A_DQS_P<7>
MEM_A_DQ<62>
MEM_A_DQ<57>MEM_A_DQ<60>
MEM_A_DQ<55>
MEM_A_DQ<45>MEM_A_DQ<43>
MEM_A_DQ<61>
MEM_A_DQ<59>
MEM_A_DQS_N<1>MEM_A_DQS_P<1>
MEM_A_DQ<10>
MEM_A_DM<1>
MEM_A_DQ<15>MEM_A_DQ<9>
MEM_A_DQ<3>
MEM_A_DQ<28>
MEM_A_DQ<26>
MEM_A_DQS_P<3>
MEM_A_DQ<44>
PM_EXTTS_L
MEM_A_DQ<49>MEM_A_DQ<52>
MEM_A_DQS_P<6>MEM_A_DQS_N<6>
MEM_A_DQ<54>
MEM_A_DQ<47>
MEM_A_DM<5>
MEM_CLK_N<1>
MEM_A_DQ<42>MEM_A_DQ<40>
MEM_A_DQ<36>MEM_A_DQ<32>
MEM_A_DM<4>
MEM_A_DQ<34>MEM_A_DQ<38>
MEM_A_A<13>
MEM_CS_L<0>
MEM_A_A<2>MEM_A_A<4>
MEM_A_A<6>MEM_A_A<7>
NC_MEM_A_A<14>NC_MEM_A_A<15>
MEM_A_DQ<21>
MEM_A_DQ<0>
MEM_CLK_N<0>MEM_CLK_P<0>
MEM_A_DQ<8>
SMBUS_SB_SCLSMBUS_SB_SDA
MEM_A_DQ<48>MEM_A_DQ<53>
MEM_A_DM<6>
MEM_A_DQ<50>MEM_A_DQ<51>
MEM_A_DQ<46>MEM_A_DQ<41>
MEM_A_DQS_P<5>MEM_A_DQS_N<5>
MEM_A_DQ<58>
MEM_A_DM<7>
MEM_A_DQ<33>MEM_A_DQ<37>
MEM_A_DQS_P<4>MEM_A_DQS_N<4>
MEM_A_DQ<39>MEM_A_DQ<35>
MEM_ODT<1>
MEM_A_DQ<7>
MEM_A_WE_LMEM_A_BS<0>MEM_A_A<10>
MEM_A_A<1>MEM_A_A<3>MEM_A_A<5>
MEM_A_A<8>MEM_A_A<9>MEM_A_A<12>
MEM_A_BS<2>
MEM_CKE<0>
MEM_A_DQ<30>MEM_A_DQ<27>
MEM_A_DM<3>
MEM_A_DQ<25>
MEM_A_DQ<16>MEM_A_DQ<20>
MEM_A_DQS_P<2>MEM_A_DQS_N<2>
MEM_A_DQ<18>MEM_A_DQ<19>
MEM_A_DQ<6>
MEM_A_DQS_P<0>MEM_A_DQS_N<0>
MEM_A_DQ<4>MEM_A_DQ<5>
MEM_A_DQ<11>
MEM_A_DQ<14>
MEM_CKE<1>
MEM_A_BS<1>
MEM_A_DQ<1>
MEM_A_DQ<22>
MEM_A_DM<2>
MEM_A_DQ<17>
MEM_A_DQ<29>MEM_A_DQ<24>
MEM_A_DQ<31>
MEM_A_A<11>
MEM_A_A<0>
MEM_A_RAS_L
MEM_ODT<0>MEM_CS_L<1>MEM_A_CAS_L
MEM_A_DQ<23>
MEM_A_DQS_N<3>
MEM_A_DQ<12>MEM_A_DQ<13>
MEM_A_DQ<2>
PP1V8_S3
PP1V8_S3
PP3V3_S0
PP1V8_S3
MEM_CLK_P<1>
MEM_A_DM<0>
MEMORY_VREF
79
78 70 66
65 64 60 59 57 56 53 51 48
43 37 36 34 33 29 27
66
66
26
66 63
63
25
63 54
54
24
54 37
37
23
37 32
32
22
32 31
31
21
31
47
47
29
29
20
29
45
45
28
28
19
28
33
33
19
19
17
19
51
29
29
16
16
14
16
50
27
27
14
14
10
14
32
29
30
30
30
30
30
30
23
23
30
30
30
30
30
30
30
30
30
30
30
30 30
30
30
30
30
30
30
30
5
5
5
5
29
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
14
15
15
15
15
15
15
15
14
15
15
15
15
15
15
15
15
14
15
15
15
15
6
6
15
15
14
14
15
5
5
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
14
15
15
15
15
15
15
15
15
15
15
15
14
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
14
15
15
15
15
15
15
15
15
15
15
15
14
14
15
15
15
15
15
15
4
4
4
4
14
15
14
VSS7
VSS12
VSS9
KEY
DQ57
DQ51
DQS6
DQ43
DQ42
DQ40
DQ34
DQ1
DQ0
VSS1
DQS0*
DQS0
VSS6
DQ2
DQ3
DQ8
DQ9
VSS10
DQS1*
DQS1
DQ10
DQ11
VSS14
VSS16
DQ16
DQ17
VSS18
DQS2*
DQS2
VSS21
DQ18
DQ19
VSS23
DQ24
DQ25
VSS25
DM3
NC1
VSS27
DQ26
DQ27
VSS29
CKE0
VDD0
NC2
BA2
VDD2
A12
A9
A8
VDD4
A5
A3
A1
VDD6
A10/AP
BA0
WE*
VDD8
CAS*
NC/S1*
VDD10
NC/ODT1
VSS31
DQ32
DQ33
VSS33
DQS4*
DQS4
VSS36
DQ35
VSS38
DQ41
VSS40
DM5
VSS41
VSS43
DQ48
DQ49
VSS45
NC_TEST
VSS47
DQS6*
VSS49
DQ50
VSS51
DQ56
VSS53
DM7
VSS55
DQ58
DQ59
VSS57
SDA
SCL
VDDSPD
DM6
DQ55
DQ61
DQ46
DQ47
DQ12
DM1
DM0
DQ7
DQ13
VSS11
CK0
CK0*
VSS13
DQ14
DQ15
VSS15
VSS17
DQ20
DQ21
VSS19
NC0
DM2
VSS22
DQ22
DQ23
VSS24
DQ28
DQ29
VSS26
DQS3*
DQS3
VSS28
DQ30
DQ31
VSS30
NC/CKE1
VDD1
NC/A15
NC/A14
VDD3
A11
A7
A6
VDD5
A4
A2
A0
VDD7
BA1
RAS*
S0*
VDD9
ODT0
NC/A13
VDD11
NC3
VSS32
DQ36
DQ37
VSS34
DM4
VSS35
DQ38
DQ39
VSS37
DQ44
DQ45
VSS39
DQS5*
DQS5
VSS42
VSS44
DQ52
DQ53
VSS46
CK1
CK1*
VSS48
VSS50
DQ54
VSS52
DQ60
VSS54
DQS7*
DQS7
VSS56
DQ62
DQ63
VSS58
SA0
SA1
DQ5
VSS2
VREF
VSS4
VSS8
VSS0
DQ4
VSS5
DQ6
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONEADDR=0xA4(WR)/0xA5(RD)
Resistor prevents pwr-gnd short
(For return current)DDR2 Bypass Caps
NC
NC
NC
NC
NC
BOM options provided by this page:
- =PPSPD_S0_MEM (2.5V - 3.3V)- =PP1V8_S3_MEMPower aliases required by this page:
(NONE)
Signal aliases required by this page:
NC
Page Notes
- =I2C_SODIMMB_SCL- =I2C_SODIMMB_SDA
by another page.The reference voltage must be providedNOTE: This page does not supply VREF.
516-0140
"Upper" (thru-hole) slot
C29131
2 10V0.1uF
CERM402
20%
C29121
2 10V0.1uF
CERM402
20%
C29091
2 6.3V20%
603X5R
10UF
C29111
2 10V0.1uF
CERM402
20%
C29081
2 6.3V20%
603X5R
10UF
C29101
2 10V0.1uF
CERM402
20%
C29191
2 10V0.1uF
CERM402
20%
C29181
2 10V0.1uF
CERM402
20%
C29171
2
0.1uF
CERM402
20%10V
C29161
2 10V0.1uF
CERM402
20%
C29211
2 10V0.1uF
CERM402
20%
C29201
2
0.1uF10VCERM402
20%
C29151
2 10V0.1uF
CERM402
20%
C29141
2 10V0.1uF
CERM402
20%
R29001
2 402MF-LF1/16W5%10K
J2900
102B
105B
90B89B
101B
100B99B
98B97B
94B
92B
93B
91B
107B
106B
85B
113B
30B
32B
164B
166B
79B
10B
26B
52B
67B
130B
147B
170B
185B
5B
35B
37B
20B
22B
36B
38B
43B
45B
55B
57B
7B
44B
46B
56B
58B
61B
63B
73B
75B
62B
64B
17B
74B
76B
123B
125B
135B
137B
124B
126B
134B
136B
19B
141B
143B
151B
153B
140B
142B
152B
154B
157B
159B
4B
173B
175B
158B
160B
174B
176B
179B
181B
189B
191B
6B
180B
182B
192B
194B
14B
16B
23B
25B
13B
11B
31B
29B
51B
49B
70B
68B
131B
129B
148B
146B
169B
167B
188B
186B
201
202
116B
86B
84B
80B
119B
115B
50B
69B
83B
120B
163B
114B
108B
110B
198B
200B
197B
195B
81B
117B 118B
82B
87B 88B
95B 96B
103B 104B
111B 112B
199B
1B 2B
27B 28B
33B 34B
39B 40B
41B 42B
47B 48B
3B
53B 54B
59B 60B
65B 66B
71B 72B
77B
8B
78B
121B 122B
127B 128B
132B
133B
138B
139B
144B
145B
149B 150B
155B 156B
161B 162B
165B
168B
171B
9B
172B
177B 178B
183B 184B
187B
190B
193B
196B
12B
15B
18B
21B
24B
109B
CRITICAL
DDR2-SODIMM-DUAL
F-RT-TH1C29001
2
0.1uF
CERM402
20%10V
C2901 1
2
2.2uF20%
603CERM16.3V
8629
051-7023 06
SYNC_MASTER=M1_MLB SYNC_DATE=02/10/2006
DDR2 SO-DIMM Connector B
MEM_B_DQ<1>
MEM_CLK_N<3>
MEM_B_DQ<0>
PP1V8_S3
PP1V8_S3
MEM_B_DQ<20>
PP1V8_S3
MEM_B_DQ<27>
NC_MEM_B_A<15>
MEM_B_DQ<31>MEM_B_DQ<30>
MEM_B_DQ<26>
MEM_B_DQ<7>
MEM_B_DQ<5>
MEM_B_DQ<2>
MEM_B_DQ<3>MEM_B_DQ<6>
MEM_B_DQ<4>
MEM_CLK_P<3>
MEM_B_DM<0>
MEM_B_DQ<10>MEM_B_DQ<13>
MEM_B_DQS_P<1>MEM_B_DQS_N<1>
MEM_B_DQ<18>MEM_B_DQ<22>
PM_EXTTS_L
MEM_B_DQS_P<0>
MEM_B_DQ<8>
MEM_B_DQ<59>MEM_B_DQ<58>MEM_B_DQ<63>
MEM_B_DQ<62>
MEM_CLK_P<2>
MEM_B_DM<7>
MEM_B_DQ<56>MEM_B_DQ<60>MEM_B_DQ<57>MEM_B_DQ<61>
MEM_B_DQ<47>
MEM_B_DQS_N<7>
MEM_B_DQS_N<6>MEM_B_DQS_P<6>
MEM_B_DQS_P<7>
MEM_B_A<5>
MEM_CKE<3>
NC_MEM_B_A<14>
MEM_B_DM<3>
MEM_B_DQ<19>
MEM_B_DQ<11>MEM_B_DQ<9>
MEM_B_BS<1>
MEM_B_A<0>MEM_B_A<2>MEM_B_A<4>
MEM_B_A<6>MEM_B_A<7>MEM_B_A<11>
MEM_B_DQS_P<3>MEM_B_DQS_N<3>
MEM_B_DQ<28>
MEM_B_DQ<16>MEM_B_DQ<17>
MEM_B_DM<2>
MEM_B_DQ<12>
MEM_B_DQ<32>
MEM_B_DQ<55>
MEM_CLK_N<2>
MEM_B_DQ<46>
MEM_B_DQS_P<5>MEM_B_DQS_N<5>
MEM_B_DQ<45>MEM_B_DQ<44>
MEM_B_DQ<39>MEM_B_DQ<38>
MEM_B_DM<4>
MEM_B_DQ<37>
MEM_B_A<13>MEM_ODT<2>
MEM_CS_L<2>MEM_B_RAS_L
MEM_B_DQ<42>
MEM_B_DQ<49>MEM_B_DQ<52>
MEM_B_DM<6>
MEM_B_DQ<51>MEM_B_DQ<54>
MEM_B_DQ<43>
MEM_B_DM<5>
MEM_B_DQ<41>MEM_B_DQ<40>
MEM_B_DQ<35>MEM_B_DQ<34>
MEM_B_DQS_P<4>MEM_B_DQS_N<4>
MEM_B_DQ<33>MEM_B_DQ<36>
MEM_ODT<3>
MEM_CS_L<3>MEM_B_CAS_L
MEM_B_WE_LMEM_B_BS<0>MEM_B_A<10>
MEM_B_A<1>MEM_B_A<3>
MEM_B_A<8>MEM_B_A<9>MEM_B_A<12>
MEM_B_BS<2>
MEM_CKE<2>
MEM_B_DQ<25>
MEM_B_DQ<24>MEM_B_DQ<29>
MEM_B_DQ<23>
MEM_B_DQS_P<2>MEM_B_DQS_N<2>
MEM_B_DQ<21>
MEM_B_DQS_N<0>
MEM_B_DQ<14>MEM_B_DM<1>
MEM_B_DQ<15>
PP3V3_S0
SMBUS_SB_SCLSMBUS_SB_SDA
MEM_B_DQ<48>MEM_B_DQ<53>
MEM_B_DQ<50>
SODIMM_A_SA1
PP3V3_S0
MEMORY_VREF
79
79
78
78
70
70
66
66
65
65
64
64
60
60
59
59
57
57
56
56
53
53
51
51
48
48
43
43
37
37
36
36
34
34
33
33
29
29
28
28
27
27
66
66 66
26
26
63
63 63
25
25
54
54 54
24
24
37
37 37
23
23
32
32 32
22
22
31
31 31
21
21
29
29 29
20
47
20
28
28 28
19
45
19
19
19 19
17
33
17
16
16 16
51
14
28
14
14
14 14
50
10
27
10
32
5
5 5
28
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
5
23
5
28
15
14
15
4
4
15
4
15
6
15
15
15
15
15
15
15
15
15
14
15
15
15
15
15
15
15
14
15
15
15
15
15
15
14
15
15 15
15 15
15
15
15
15
15
15
14
6
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
14
15
15
15
15
15
15
15
15
15
15
14
14
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
14
14
15
15
15
15
15
15
15
15
15
15
14
15
15
15
15
15
15
15
15
15
15
15
4
5
15
15
15
4
14
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
One cap for each side of every RPAK, one cap for every two discrete resistorsEnsure CS_L and ODT resistors are close to SO-DIMM connector
C30511
2402
10V20%
CERM
0.1uF
C30531
2
0.1uF
402CERM10V20%
C30521
2
0.1uF
CERM10V
402
20%
C30501
2 CERM
0.1uF20%10V
402
C30551
220%10VCERM402
0.1uF
C30571
2
0.1uF
402CERM10V20%
C30591
220%10VCERM402
0.1uFC30581
2 CERM402
0.1uF20%10V
C30561
2402CERM10V20%0.1uF
C30541
2402
0.1uF
CERM10V20%
0
1
2
3
5
4
6
7
8
9
10
11
12
13
0
2
1
15 29
15 29
15 29
15 29
15 29
RP3004 2 7SM-LF5% 1/16W
56
RP3001 3 6SM-LF
561/16W5%
RP3010 2 7561/16W5% SM-LF
RP3012 4 5SM-LF1/16W5%
56
RP3012 3 6SM-LF1/16W5%
56
RP3003 4 55% 1/16W
56SM-LF
RP3012 2 7565% 1/16W SM-LF
RP3001 1 85%
56SM-LF1/16W
RP3004 1 8SM-LF
561/16W5%
RP3002 2 7SM-LF5% 1/16W
56
RP3006 1 8SM-LF1/16W5%
56
RP3007 1 8SM-LF5% 1/16W
56
RP3002 4 5SM-LF5% 1/16W
56
RP3010 1 85% SM-LF1/16W
56
RP3003 1 8561/16W SM-LF5%
RP3006 4 5SM-LF1/16W5%
56
RP3005 3 6SM-LF
561/16W5%
RP3005 4 5SM-LF5% 1/16W
56
RP3003 2 7SM-LF
561/16W5%
RP3006 3 656SM-LF1/16W5%
RP3005 2 756SM-LF1/16W5%
RP3006 2 75% 1/16W SM-LF
56
RP3002 3 6SM-LF5%
561/16W
RP3003 3 6SM-LF
561/16W5%
RP3001 2 7SM-LF1/16W5%
56RP3004 4 5
5% 1/16W SM-LF56
RP3012 1 8561/16W SM-LF5%
RP3001 4 5565% 1/16W SM-LF
RP3005 1 8565% 1/16W SM-LF
RP3004 3 65% 1/16W
56SM-LF
RP3008 2 7561/16W5% SM-LF
RP3002 1 8561/16W5% SM-LF
RP3013 4 5SM-LF5% 1/16W
56
RP3008 3 6SM-LF1/16W5%
56RP3008 4 5
SM-LF5% 1/16W56
RP3009 1 8SM-LF1/16W5%
56
RP3011 2 7561/16W5% SM-LF
RP3011 1 85% 1/16W
56SM-LF
RP3009 2 75%
561/16W SM-LF
RP3011 3 65% 1/16W
56SM-LF
RP3008 1 8561/16W SM-LF5%
RP3009 3 6565% SM-LF1/16W
RP3007 4 5SM-LF1/16W5%
56
RP3013 2 7SM-LF
565% 1/16W
RP3011 4 55% 1/16W
56SM-LF
RP3010 4 5SM-LF
565% 1/16W
RP3009 4 5SM-LF
561/16W5%
RP3007 2 7561/16W5% SM-LF
RP3010 3 6561/16W5% SM-LF
RP3013 1 8SM-LF
561/16W5%
RP3007 3 6SM-LF5% 1/16W
56
RP3013 3 6561/16W5% SM-LF
0
1
0
1
1
0
2
0
1
2
3
4
5
6
7
10
11
9
8
13
12
14 28 29
14 28 29
15 28
15 28
15 28
15 28
15 28
2
3
2
3
C30391
220%10VCERM402
0.1uFC30381
2
0.1uF20%
CERM402
10V
C30331
220%10VCERM402
0.1uFC30321
2402
20%10VCERM
0.1uF
C30311
2402CERM10V20%0.1uF
C30301
2 CERM
0.1uF20%10V
402
C30111
2402
0.1uF10V20%
CERM
C30101
2
0.1uF
402
20%10VCERM
C30071
220%
CERM402
0.1uF10V
C30051
2402CERM10V20%0.1uF
C30021
220%10VCERM402
0.1uFC30001
2402CERM10V20%0.1uF
C30371
2
0.1uF
402CERM10V20%
C30361
2402CERM10V20%0.1uF
C30351
220%10VCERM402
0.1uFC30341
2402CERM10V20%0.1uF
0
1
2
3
14 28 29
SYNC_MASTER=(M1_MLB)
Memory Active TerminationSYNC_DATE=(11/07/2006)
30 86
06051-7023
MEM_B_BS<2..0>
MEM_B_A<13..0>
MEM_ODT<3..0>
MEM_CKE<3..0>
MEM_CS_L<3..0>
MEM_A_BS<2..0>
MEM_A_A<13..0>
PP0V9_S0
MEM_A_WE_L
MEM_B_RAS_L
MEM_A_CAS_LMEM_A_RAS_L
MEM_B_WE_LMEM_B_CAS_L
66 65 31 5
VREF
VTT
GND
VTT_IN
ENVTTS
VDDQ VCC
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
disable MEMVTT in sleep.MEMVTT_EN can be used toIf power inputs are not S0,
DDR2 Vtt Regulator
leave 1.8V powered in S3.Okay to turn off 5V and
Page Notes
- =PP0V9_S0_MEMVTT_LDO- =PP1V8_S0_MEMVTT- =PP5V_S0_MEMVTT
BOM options provided by this page:
Signal aliases required by this page:
Power aliases required by this page:
(NONE)
(NONE)
C3101 1
26.3V20%
X5R603
10uF
U3100
2
1
65
4
8
7
3CRITICAL
MSOP-8BD3533FVM
R31001
2
MEMVTT_EN_PU
1K
402MF-LF1/16W5%
C3105
6.3V
SMC-LFPOLY
20%150UF
C31021
2603X5R
20%10uF6.3V
C3104 1
2CERM1
20%6.3V
2.2uF
603
R310412
220
5%1/16WMF-LF402
C31031
210%16VX5R
0.1uF
402
C31001
2 6.3V10%1uF
CERM402
SYNC_DATE=02/10/2006SYNC_MASTER=M1_MLB
Memory Vtt Supply
051-7023 06
8631
PP0V9_S0
VOLTAGE=1.8VMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.2 mmPP1V8_S0_MEMVTT_VDDQ
PP5V_S0
MEMVTT_VREF
MEMVTT_EN
PP1V8_S380 79 78 70 67 66 65 61
66
60
63
57
54
56
37
54
32
52
29
47
28
42
19
66
36
16
65
25
14
30
5
5
5
4
32
4
V+
V-
IN
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
U3200
3
4
1
5
6
2
CRITICAL
MAX4236EUTTSOT23-6-LF
5 23 39 43 50 54 64 65
R329012
NO STUFF
5%1/16WMF-LF402
0
R329112
5%1/16WMF-LF402
0
C3200 1
2402
20%0.1UF
10VCERM
C3205 1
2CERM402
220pF25V5%
R32061
2
10K1/16W
1%
402MF-LF
R32051
2
10K
MF-LF402
1%1/16W
R32021
2
100K
MEMVREF_S3
MF-LF402
5%1/16W
R320312
MEMVREF_S0
0
402MF-LF1/16W5%
32 86
06051-7023
DDR2 VRefSYNC_MASTER=M1_MLB SYNC_DATE=12/19/2005
PP1V8_S3
MEMVREF_UNBUFMIN_LINE_WIDTH=0.2 mmMIN_NECK_WIDTH=0.2 mmVOLTAGE=0.9V
PP3V3_S3
PM_SLP_S3_LMEMVREF_SHDN_L
MAKE_BASE=TRUEVOLTAGE=0.9VMIN_NECK_WIDTH=0.15 mmMIN_LINE_WIDTH=0.2 mmMEMVREF_OUT
VOLTAGE=0.9VMIN_NECK_WIDTH=0.15 mmMIN_LINE_WIDTH=0.2 mmMEMORY_VREF
MAKE_BASE=TRUE
MEMORY_VREFMEMORY_VREF
MEMORY_VREF
MEMVREF_OUT
VOLTAGE=0.9VMIN_NECK_WIDTH=0.15 mmMIN_LINE_WIDTH=0.2 mmMEMVTT_VREF
80 66
66
64
63
63
54
62
37
59
31
58
29
56
28
51
19
45
16
41
32
32
32
32
14
37
29
29
29
29
5
27
28
28
28
28
4
5
32
14
14
14
14
32
31
VTT_PWRGD*/PD
DOT96T/27MHZ_NON-SPREAD
SRCT_0/LCD100MT
CPUC2_ITP/SRCC_10
VDD48
XIN
VDD_PCI1
VDD_SRC0
VDD_REF
VDD_SRC1
VDD_SRC2
VDD_SRC3
REF1/FCTSEL0
REF0/FSC
FSA/48M
DOT96C/27MHZ_SPREAD
CLKREQ_8*
SRCT_8
SRCC_8
SRCT_7
SRCC_7
CLKREQ_6*
CPUT2_ITP/SRCT_10
IREF
SDATA
SCLK
VSS_REF
VSS_PCI1
VSS_PCI0
VSS_CPU
VSS48
VSS_SRC
PCIF1
PCI1
SRCT_5
THRML_PAD
PCI4
PCI2
FSB
CLKREQ_4*
SRCC_5
SRCC_4
SRCT_4
SRCT_3
CLKREQ_3*
SRCC_3
SRCC_2
SRCT_2
SRCC_1
CLKREQ_1*
SRCT_1
SRCC_0/LCD100MC
CPUC1
CPUT1
CPUC0
CPUT0
PCI_STP*
CPU_STP*
SRCC_6
CLKREQ_5*
SRCT_6
PCIF0/ITP_SEL
PCI5/FCTSEL1
PCI3
XOUT
VDDA
VSSA
VDD_PCI0
VDD_CPU
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
IN
BI
OUT
IN
BI
BI
OUT
OUT
IN
IN
IN
IN
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
IN
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
(FW PCI 33MHZ)
(FOR PCI-E CARD)
NEED TO CHECK CAP VALUE
(ICH7M USB 48MHZ)(FROM CPU VCORE PWR GOOD)
(GMCH D_REFCLKIN DISPLAY PLL A 96MHZ)
(GIGA LAN PCI-E 100 MHZ )
(WIRELESS PCI-E 100 MHZ )
(FROM GMCH CLK_REQ*)
(FROM ICH7 GPIO35)
(ICH7M DMI 100 MHZ )NEED TO DECIDE THE CLKREQ CONNECTION,TO GPIO?
(GPU PCI-E 100 MHZ )
(INT PU)(INT PU)
(EACH POWER PIN PLACED ONE 0.1UF)(PLACED 0.1UF NEAR THE RELATIVE POWER PIN)
(SMC LPC 33MHZ)(TPM LPC 33MHZ)
(ICH SATA 100 MHZ)
(INT PU)
FCTSEL0
SRCC0SRCC0SRCC0
SRCT0100MT_SSTDOT96C
TBDSPREAD27M
SPREAD27M NON
OFF LOW111
100 0
FCTSEL1100MC_SSTPIN 11PIN 10PIN 7
DOT96TDOT96T DOT96C
SRCT0SRCT0
* FOR INT. GRAPHIC SYSTEM
* FOR EXT. GRAPHIC SYSTEM
PIN 6
(INT PU)
(INT PU)
(INT PD)
(INT PU)
(INT PD)
(NOT USED )
(CPU HOST 133/167MHZ)
(INT PU) (SIGNAL NAME WILL BE CHANGED POSTPROTO TO REMOVE 100M FROM SIGNAL NAME)
(GMCH D_REFSSCLKIN DISPLAY PLL B 100MHZ)
(ITP HOST 133/167MHZ)
(GMCH HOST 133/167MHZ)
(FROM ICH7 GPIO20 STPCPU* )(FROM ICH7 GPIO18 STPPCI* )
(GMCH G_CLKIN 100 MHZ )
(INT PD)
(ICH7M,SIO,LPC REF. 14.318MHZ)
(INT PU)
0
(PORT80 LPC 33MHZ)
(ICH7M PCI 33MHZ)
(ICH SM BUS)(PULL UP PIN 68 TO ENABLE ITP HOST CLK)
(NO USED)
C33091
2603X5R
10UF20%6.3V
L33021 2
FERR-120-OHM-1.5A
0402
C33051
2
0.1UF10%X5R16V402
C33061
2 16VX5R402
10%0.1UF
C33071
2 16VX5R
0.1UF10%
402
C33081
2
0.1UF10%
40216VX5R
U3301
9
59
20
60
25
34
55
44
41
36
45
42
37
76
4
8
40
5758636465
56
681
5453
4748
11
14
16
19
22
24
27
30
32
10
13
15
18
21
23
26
29
33
69
3 43
61
67
49
12
17
28
35
38
5
46
6266
52
31
39
2
5150
CY284455
CRITICAL
QFN
OMIT
5 23
5 23
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
26 60
34
C33901
2 50V402CERM5%18pF
C33891
2 50V5%CERM402
18pF
34
5 23 27 28 29 45 47
R33001
2MF-LF1%475
4021/16W
C33121
220%10UF6.3VX5R603
C33111
2 16V0.1UF
402X5R10%
34
34
34
34
C33041
2402
10%16VX5R
0.1UFC33031
2 X5R16V402
0.1UF10%
C33021
2
0.1UF10%16VX5R402
C33011
2402X5R16V0.1UF10%
C33101
2
1UF6.3VCERM10%
402
C33161
2
10UF
6036.3V20%X5R
C33151
210%X5R16V402
0.1UF
L33011 2
FERR-120-OHM-1.5A
0402C33141
2
1UF10%CERM6.3V402
R33021 2
402MF-LF1/16W5%
2.2
R33031 2
4021/16W5%
MF-LF
1
C33171
26036.3V20%10UFX5R
R33041 2
MF-LF402
2.25%
1/16W
34
34
34
5 34 47
5 34 47
34
R33011
2
10K5%MF-LF4021/16W
34
34
34
34
34
34
34
5 14
Y33011 2
CRITICAL
5X3.2-SM
14.31818
06051-7023
33 86
SYNC_DATE=02/10/2006CLOCKS
SYNC_MASTER=M1_MLB
CK410_PCIF0_CLK
CK410_PCI1_CLK
CK410_FSB_TEST_MODE
CK410_SRC1_N
PP3V3_S0
CK410_SRC2_P
CK410_SRC3_N
CK410_PCI3_CLK
CK410_SRC6_PCK410_SRC6_N
TP_CK410_SRC7NTP_CK410_SRC7PCK410_SRC8_N
PP3V3_S0
CK410_SRC4_NCK410_SRC4_P
CK410_SRC5_NSB_CLK100M_SATA_OE_L
EXCARD_CLKREQ_L
SMBUS_SB_SCL
CK410_CPU2_ITP_SRC10_N
TP_CK410_LVDSNTP_CK410_LVDSP
CK410_CPU1_N
CK410_SRC3_P
CK410_SRC2_NCK410_SRC_CLKREQ1_L
CK410_PCI2_CLK
CK410_REF1_FCTSEL0CK410_CLK14P3M_TIMER
PP3V3_S0
CK410_CPU0_P
MINI_CLKREQ_L
CLK_NB_OE_LCK410_SRC5_P
SMBUS_SB_SDACK410_IREF
CK410_PCIF1_CLK
CK410_PCI5_FCTSEL1
PP3V3_S0_CK410_VDD_CPU_SRCVOLTAGE=3.3V
MIN_LINE_WIDTH=0.5mmMIN_NECK_WIDTH=0.2mm
PP3V3_S0_CK410_VDD_REFVOLTAGE=3.3V
MIN_LINE_WIDTH=0.5mmMIN_NECK_WIDTH=0.2mm
MIN_LINE_WIDTH=0.5mmMIN_NECK_WIDTH=0.2mm
VOLTAGE=3.3VPP3V3_S0_CK410_VDD_PCI
CK410_CPU1_P
PM_STPPCI_LPM_STPCPU_L
CK410_CPU0_N
CK410_CPU2_ITP_SRC10_P
CK410_USB48_FSAVR_PWRGD_CK410_L
CK410_27M_NONSPREADCK410_27M_SPREAD
CK410_SRC_CLKREQ8_LCK410_SRC8_P
TP_CK410_PCI4_CLK
PP3V3_S0_CK410_VDDAMIN_LINE_WIDTH=0.5mmMIN_NECK_WIDTH=0.2mm
VOLTAGE=3.3V
CK410_SRC1_P
CK410_XTAL_INCK410_XTAL_OUT
MIN_NECK_WIDTH=0.2mmMIN_LINE_WIDTH=0.5mm
PP3V3_S0_CK410_VDD48VOLTAGE=3.3V
79
79
79
78
78
78
70
70
70
66
66
66
65
65
65
64
64
64
60
60
60
59
59
59
57
57
57
56
56
56
53
53
53
51
51
51
48
48
48
43
43
43
37
37
37
36
36
36
34
34
34
33
33
33
29
29
29
28
28
28
27
27
27
26
26
26
25
25
25
24
24
24
23
23
23
22
22
22
21
21
21
20
20
20
19
19
19
17
17
17
14
14
14
10
10
10
5
5
5
4
4
4
5
5
5
5
5
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
IN
IN
IN
IN OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUTIN
IN
OUTIN
OUT
OUT
OUTOUT
OUT
BI
BI
OUT
IN
OUT
OUT
IN
IN
IN
IN
IN
OUT
OUT
IN
OUT
IN
IN
IN
OUT
OUT
OUT
IN
IN
IN
OUT
OUT
OUT
OUT
OUTIN
IN
IN
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
(GPU 27MHz Spread / Non-Spread)
# NAPA PLATFORM ONLY SUPPORT 133M/166M CPU SPEED
Yukon CLK OE*
(Yukon PCI-E 100MHZ)
(GPU PCI-E Graphics 100MHz)
(TO MCH FS_B)
(FROM CPU FS_B)
(FROM CPU FS_C)
0FS_B
166M
CPUFS_C00 0
00
0 00
0
11 1
11 11 11 1 1
100M333M
0
01#
#
400M
133M
200M
266MFS_A
(CPU HOST 133/167MHZ)
(GMCH HOST 133/167MHZ)
(GMCH G_CLKIN 100MHZ)
(ICH7M DMI 100MHZ)
NOSTUFF R3450,R3451,R3453 FOR MANUAL CPU FREQUENCY
(ICH7M 14.318MHZ)
(TO MCH FS_C)
RESERVED
(FROM CPU FS_A)
(ICH7M SATA 100MHZ)
(PORT80 LPC 33MHZ)
(TO ICH7M PCI 33MHZ)
(TO ICH7M USB 48MHZ)
NEED TO CHECK THE BSEL PULLS
(TO MCH FS_A)
(WIRELESS PCI-E MINI 100MHZ)
GPU CLK OE*
(ITP HOST 133/167MHZ)(TO SMC PCI 33MHZ)
(TO TPM PCI 33MHZ)
(TO FIREWIRE PCI 33MHZ)
(ExpressCard Slot)
R34411 249.9
MF-LF402
1%1/16W
ITP
R34021 2
NO STUFF
402
1/16W1%
MF-LF
71.5
33
33
33
33
R34181 2
MF-LF
1%
402
1/16W
121
R34191 2
5%
33
402MF-LF1/16W
33 34
33 34
33 34
33 34
34 73 76
34 73 76
R34221 2
402MF-LF1/16W5%
33
R34231 2
33
5%1/16WMF-LF402
5 14 34
5 14 34
33
33
R34651 2
33
MF-LF402
5%1/16W R3426
1 2
MF-LF402
1/16W
33
5%
33
33 34 39
34 39
22 34
R34281 2
33
MF-LF
5%1/16W
402
R34271 2
5%1/16W
33
MF-LF402
33
33
R34291 2
1/16W5%
402
33
MF-LF R34301 2
33
MF-LF402
5%1/16WR3433
1 2
1/16W5%
402MF-LF
33
R34321 2
MF-LF
5%
402
1/16W
33
33
33
33
33
37
59
50
22
5 34 47
5 34 47
R34351 2
5%
MF-LF402
1/16W
33
R34341 2
5%
402MF-LF1/16W
3333
R34081 249.9
MF-LF402
1%1/16W
33
R34361 249.9
MF-LF402
1%1/16W R3437
1 249.9
MF-LF402
1%1/16W
5 52
R34631 2
1/16W5%
MF-LF
33
402
33
22 34
R34671
2
10K
MF-LF402
5%1/16W
R34661
2
10K
MF-LF402
5%1/16W
R34311 249.9
MF-LF402
1%1/16W
R34691
2
1/16W5%
402MF-LF
1K
R34681 2
1/16W5%
402MF-LF
1K
R34721 2
1/16W5%
402MF-LF
1K
R34701
2
1/16W5%
402MF-LF
1K
R34711 2
1/16W5%
402MF-LF
1K33
R34731
2
1/16W5%
402MF-LF
1K
R34751 2
1/16W5%
402MF-LF
1KR34741 2
1/16W5%
402MF-LF
1K
33
33
23
R34061 249.9
MF-LF402
1%1/16W
5 21 34
5 21 34
R34781 2
33
MF-LF402
5%1/16W
R34771 2
MF-LF402
5%1/16W
3333
R34391 2
1/16W1%
402MF-LF
49.9
33
R34801
2
1/16W5%
402MF-LF
1K
NOSTUFF
R34811 2
1/16W1%
402MF-LF
49.9
R34821 2
1/16W1%
402MF-LF
49.9
R34761 2
1/16W5%
402MF-LF
33
R34501 2
1/16W5%
402MF-LF
07
7
R34531 2
1/16W5%
402MF-LF
0
R34541
2
1/16W5%
402MF-LF
1K
NOSTUFF
R34071 249.9
MF-LF402
1%1/16W
7
R34511 2
1/16W5%
402MF-LF
0
R34521
2
1/16W5%
402
1K
NOSTUFF
MF-LF
5 34 47
5 34 47
R34991 2
5%1/16WMF-LF402
33
R34981 2
1/16W5%
402
33
MF-LF
33
5 12 34
33
R34951 249.9
MF-LF402
1%1/16W R3496
1 249.9
MF-LF402
1%1/16W
33
33
R34931 2
MF-LF402
1/16W
33
5% R34941 2
5%
33
402
1/16WMF-LF
34 69
34 69
R34901 249.9
MF-LF
1%1/16W
402
5 12 34
R34911 249.9
MF-LF402
1%1/16W
33 34
33 34
33 34
5 7 34
R34861 2
5%
1K
1/16W
402MF-LF
R34851 2
5%
1K
MF-LF1/16W
402
5 7 34
11 34 86
11 34 86
R34111 2
402
33
MF-LF1/16W5%
R34401 249.9
MF-LF402
1%1/16W
ITP
R34131 2
33
MF-LF402
5%1/16W
R34151 2
402MF-LF1/16W5%
33
ITP
R34381 2
1/16W1%
402MF-LF
49.9
R34041 249.9
MF-LF402
1%1/16W
R34421 249.9
MF-LF402
1%1/16W
R34121 2
33
402
5%1/16WMF-LF
R34141 2
1/16W5%
402MF-LF
33
R34031 249.9
MF-LF402
1%1/16W
R34051 2
1/16W1%
402MF-LF
71.5
R34001 2
1/16W1%
402MF-LF
49.9
R34161 2
1/16W
402MF-LF
5%
33
ITP
R34171 2
1/16W5%
402MF-LF
33
R34011 2
1/16W5%
402MF-LF
2.2K
33
33
33
Clock TerminationSYNC_DATE=02/10/2006SYNC_MASTER=M1_MLB
34 86
06051-7023
CK410_27M_NONSPREAD
CK410_27M_SPREADCK410_27M_SPREAD
MAKE_BASE=TRUE
CK410_27M_NONSPREADMAKE_BASE=TRUE
MAKE_BASE=TRUETP_CK410_SRC7N
PCI_CLK_PORT80_LPC
CK410_SRC6_P
CK410_CPU2_ITP_SRC10_N
EXCARD_CLKREQ_L
CK410_SRC2_P
SB_CLK100M_DMI_N
PCIE_CLK100M_MINI_P
CK410_SRC5_P
CK410_SRC6_N
NB_CLK100M_GCLKIN_P
ENET_CLK100M_PCIE_P
PEG_CLK100M_GPU_P
TP_CK410_SRC7P
PP3V3_S0
PP1V05_S0
CK410_PCI5_FCTSEL1
SB_CLK14P3M_TIMER
CK410_REF1_FCTSEL0
CPU_BSEL_R<2>MAKE_BASE=TRUETP_CK410_LVDSN
PCIE_CLK100M_EXCARD_N
PCIE_CLK100M_EXCARD_PPCIE_CLK100M_EXCARD_P
CK410_SRC4_P
CK410_SRC8_P
CK410_SRC8_N
SB_CLK100M_DMI_P
SB_CLK100M_SATA_N
CPU_BSEL<2>
ENET_CLK100M_PCIE_N
CPU_BSEL<1>
NB_BSEL<1>
CPU_BSEL_R<1>
CK410_CLK14P3M_TIMER
CPU_BSEL<0>CPU_BSEL_R<0>
NB_BSEL<2>
CK410_USB48_FSA
CK410_FSB_TEST_MODE
NB_BSEL<0>
PP1V05_S0
PP1V05_S0
FSB_CLK_CPU_PCK410_CPU0_P
FSB_CLK_CPU_NCK410_CPU0_N
CK410_CPU1_P FSB_CLK_NB_P
FSB_CLK_NB_N
CK410_CPU2_ITP_SRC10_P
CPU_XDP_CLK_N
PCIE_CLK100M_MINI_N
NB_CLK100M_GCLKIN_N
SB_CLK100M_DMI_N
SB_CLK100M_DMI_P
CPU_XDP_CLK_N
CPU_XDP_CLK_P
FSB_CLK_NB_P
FSB_CLK_NB_N
FSB_CLK_CPU_P
FSB_CLK_CPU_N
ENET_CLK100M_PCIE_P
ENET_CLK100M_PCIE_N
PCIE_CLK100M_MINI_P
PCIE_CLK100M_MINI_N
NB_CLK100M_GCLKIN_P
NB_CLK100M_GCLKIN_N
SB_CLK100M_SATA_P
SB_CLK100M_SATA_N
PCIE_CLK100M_EXCARD_N
PEG_CLK100M_GPU_N
MAKE_BASE=TRUETP_CK410_LVDSPTP_CK410_LVDSP
MAKE_BASE=TRUETP_CK410_SRC7P
MAKE_BASE=TRUETP_CK410_PCI4_CLKTP_CK410_PCI4_CLK
PCI_CLK_SB
CK410_PCIF0_CLK
CK410_PCI1_CLK PCI_CLK_FW
CK410_PCI2_CLK PCI_CLK_TPM
CK410_PCI3_CLK
SB_CLK48M_USBCTLR
PEG_CLK100M_GPU_N
PEG_CLK100M_GPU_P
TP_CK410_LVDSN
CK410_SRC_CLKREQ8_L
CK410_SRC_CLKREQ1_L
TP_CK410_SRC7N
MINI_CLKREQ_LMAKE_BASE=TRUE
EXCARD_CLKREQ_LMAKE_BASE=TRUE
MINI_CLKREQ_L
CK410_SRC5_N
PCI_CLK_SMC
CK410_PCIF1_CLK
CK410_SRC4_N
CK410_SRC2_N
CK410_CPU1_N
CPU_XDP_CLK_P
SB_CLK100M_SATA_P
GPU_CLK27MSS_IN
GPU_CLK27M
GPU_CLK27MSS_IN
GPU_CLK27M
CK410_SRC3_N
CK410_SRC3_P
CK410_SRC1_N
CK410_SRC1_P
79 78 70
66 65 64 60 59 57 56 53 51 48
43 37 36 33
66
66
66
29
64
64
64
28
54
54
54
27
34
34
34
26
25
25
25
25
24
24
24
24
21
21
21
23
19
19
19
22
17
17
17
21
16
16
16
20
13
13
13
19
12
12
12
17
11
11
11
47
14
9
9
9
47
47
47
34
10
8
47
47
8
8
86
86
34
34
34
34
47
47
34
34
34
34
34
34
34
76
76
34
34
34
33
5
7
34
34
34
7
7
34
34
34
34
12
12
7
7
39
39
34
34
14
14
21
21
34
34
34
69
69
33
33
33
73
73
33
33
33
5
4
5
33
5
5
5
5
22
22
11
11
5
5
5
5
34
34
5
5
5
5
5
5
33
33
33
34
34
33
33
5
5
5
34
34
NC7
NC6
NC5
NC4
NC2
NC3
OUT
VDD
NC0
NC1
VIO
GND
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
NCNC
TPM Crystal Circuit
SMC G3Hot Oscillator
NCNC
NC
NC
NCNC
NC
NC
Y3720
24
13
SM-2
CRITICAL
32.768K
R37211 2
5%
402
0
1/16WMF-LFR37201
2
1/16W5%
402MF-LF
NO STUFF
10M
U3750
6
2
3
4
5
8
9
10
11
7
12
1
SG-3040LC-SM
CRITICAL
32.768KHZ-9-3.6V
C3751 1
210VCERM402
20%0.1uF
L3750
1 2
SM
FERR-EMI-100-OHM
C37501
2
4.7uF20%
CERM603
6.3V
R37501 2
5%1/16WMF-LF
22
402
C37201 215pF
50VCERM402
5%
C37211 215pF
CERM402
5%50V
Mobile ClockingSYNC_DATE=02/10/2006SYNC_MASTER=M1_MLB
051-7023 06
8635
SMC_CLK32K_SUSCLKSMC_CLK32K_SUSCLKMAKE_BASE=TRUE
VOLTAGE=3.425V
PP3V42_G3H_SMC_CLK_FMIN_LINE_WIDTH=0.2 mmMIN_NECK_WIDTH=0.2 mm
TPM_XTALO
PP3V42_G3H
SMC_CLK32K_SUSCLK_R
TPM_XTALO_R
TPM_XTALI
68 67 66 65 54 52 51 50 45 27
50 50
26
35 35
59
5
59
IN
BI
BI
BI
BI
BI
IN
BI
BI
BI
IN
IN
IN
IN
OUT
G
DS
IN
BI
BI
BI
BI
BI
BI
BI
BI
IN
OUT
OUT
INOUT
IN
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
ODD to keep SB GPIO <= 3.3VCounters 10K pull-up to 5V in
(UATA_CS0*)
(UATA_HSTROBE)(UATA_DSTROBE)
NC
(UATA_CS1*)
from ball of SBPlace within 12.7mmPlacement note
(UATA_STOP)
IDE (ODD) Connector
516S0335
Indicates disk presence
21
21
21
21
21
21
23
R38501
2
1/16W
100
402MF-LF
5%
J3800
1
10
11
12
13
14
15
16
17
18
19
2
20
21
22
23
24
25 26
27
28
29
3
30
31
32
33
34
35
36
37
38
39
4
40
41
42
43
44
45
46
47
48
49
5
50
6
7
8
9
M-ST-SM1-LF
CRITICAL
R38601
2
1%24.91/16WMF-LF402
21
21
21
21
21
21
21
R38011
2
1/16W
402MF-LF
NO STUFF
4.7K5%
R38021
2402
4.7K
MF-LF
5%1/16W
R38031
2
6.2K
MF-LF402
5%1/16W
50
R38101
2
33K
MF-LF402
5%1/16W
Q3820
C1
C2
C3
A1
A2
A3
B1
B2
B3 BGA
CRITICAL
FDZ293P
R38201
2
1/16W5%
402MF-LF
10K
22
21
21
21
21
21
21
21
21
21
21
21
21 21
21
C38211 2
0.22uF
402X5R6.3V20%
R38211
2
10K
MF-LF402
5%1/16W
R38111
2
1/16WMF-LF
402
5%15K
SYNC_MASTER=M1_MLB
8636
06051-7023
PATA ConnectorSYNC_DATE=02/10/2006
PP3V3_S0
IDE_PDIOW_L
SMC_ODD_DETECT
MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.4 mmVOLTAGE=5V
PP5V_S0_IDE_ODD
IDE_PDDREQIDE_PDIOR_LIDE_PDIORDY
IDE_PDD<3>
IDE_IRQ14
ODD_PWR_EN_L_RC
IDE_PDD<0>
PP5V_S0
IDE_PDD<13>
ODD_PWR_EN_L
SATA_RBIASMAKE_BASE=TRUE
TP_SATA_A_R2DNMAKE_BASE=TRUE
TP_SATA_A_D2RNMAKE_BASE=TRUE
TP_SATA_A_D2RN
TP_SATA_A_D2RPMAKE_BASE=TRUE
TP_SATA_A_D2RP
TP_SATA_A_R2DPMAKE_BASE=TRUE
TP_SATA_A_R2DP
SATA_C_DET_L
TP_SATA_A_R2DN
IDE_PDD<4>
IDE_PDCS3_L
IDE_PDA<1>
IDE_PDDACK_L
IDE_PDD<15>IDE_PDD<14>
IDE_PDD<11>IDE_PDD<10>IDE_PDD<9>IDE_PDD<8>
IDE_PDD<1>IDE_PDD<2>
IDE_PDD<5>IDE_PDD<6>IDE_PDD<7>
IDE_PDA<0>IDE_PDCS1_LIDE_PDA<2>
SATA_RBIASSATA_RBIAS
IDE_PDD<12>
IDE_RESET_L
79 78 70 66
65 64 60 59 57 56 53 51 48
43 37
80
34
79
33
78
29
70
28
67
27
66
26
65
25
61
24
60
23
57
22
56
21
54
20
52
19
47
17
42
14
31
10
25
5
5
36
36
36 36
36 36
36 36
36
36
36
4
4
21
21
21 21
21 21
21 21
23
21
21
21
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
IN
IN
IN
IN
OUT
BI
BI
BI
BI
BI
BI
OUT
IN
IN
BI
BI
OUT
OUT
G
D
S
G
D
S
G
D
S
IN
SDA
SCL
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD31
PCI_AD30
PCI_AD28
PCI_AD29
PCI_AD27
PCI_AD25
PCI_AD26
PCI_AD24
PCI_AD23
PCI_AD21
PCI_AD20
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_PAR
PCI_CLK
PCI_IDSEL
GND
PCI_AD1
PCI_AD0
VCC
MFUNC
G_RST_L
REG18_1
REG18_0
REG_EN_L
PHY_PINT
PHY_PCLK
PHY_LREQ
PHY_LPS
PHY_LINKON
PHY_LCLK
PHY_D7
PHY_D6
PHY_D5
PHY_D4
PHY_D3
PHY_D1-D1
PHY_D2
PHY_D0-D0
PHY_CTL1-CTL1
PHY_CTL0-CTL0
PCI_ACK64_L
PCI_TRDY_L
PCI_STOP_L
PCI_SERR_L
PCI_RST_L
PCI_REQ64_L
PCI_REQ_L
PCI_PME_L
PCI_PERR_L
PCI_IRDY_L
PCI_INTA_L
PCI_GNT_L
PCI_FRAME_L
PCI_DEVSEL_L
VCCP
PCI_AD22
PCI_C_BE2_L
PCI_C_BE0_L
PCI_C_BE3_L
PCI_C_BE1_L
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
Gated Platform Reset
from design after evaluation
THIS IS FROM ICH-7M
G_RST* assertion min 2ms
(OK if VCCP and VCC are
It must not be taken high
Resistor can probably be removed
aliased to the same rail)
G_RST* is clamped to VCCP
when there’s no power on VCCP
Might useMFUNC as aGPIO
From PCI clock generator via 33 Ohms
Ungated Platform Reset
22
22
22
22
22
4 22
22
22 26
22 26
22 26
22 26
22 26
22 26
22 26
22
34
4 22
5 22
37
C39081
2402
10%1uF10VX5R
C39091
2 10V
402X5R
1uF10%
C39041
210%1uF
X5R402
10V
C39031
2 10V
402X5R
10%1uF
C39021
2 10V
1uF10%
X5R402
C39011
210%1uF10VX5R402
C39001
210%
X5R10V
402
1uF
R39021
2402MF-LF1/16W5%4.7K
R39011
2
4.7K5%
402MF-LF1/16W
22 26
38
38
38
38
R39111
2
NO STUFF
1/16W
1K
MF-LF402
5%
R39901
2
5%1/16WMF-LF402
220R39801
2
5%1/16WMF-LF402
1KR39911
2 402MF-LF1/16W5%220
38
38
38
38
38
38 R39101
2402MF-LF1/16W5%10K
R39781 2
FW_PLTRST_UNGATED
5%1/16WMF-LF402
100
R39771
2
10K5%1/16W
402MF-LF
FW_PLTRST_GATED
37
C39771
2
NO STUFF
CERM402
0.001uF10%50VQ3970
6
2
1
FW_PLTRST_GATED
SOT-3632N7002DW-X-F
Q39713
5
4
FW_PLTRST_GATED
SOT-3632N7002DW-X-F
Q39716
2
1
FW_PLTRST_GATED
2N7002DW-X-FSOT-363
4 50
R39711
2
FW_PLTRST_GATED
100K1/16W
402MF-LF
5%
U3900
E4
C7C8
F7F8F9
F10G6G7G8G9
G10H6
D6
H7H8H9
H10J8J9
J10
K10
D7E6E7E8E9
E10F6
A1
N12
L12N11
N6M6M7K9K8M5K3N1L4M2
M11
M1L1J4H3H4J3H2G3H1F1
N10
F2G4
M10K12M9N9L8M8
N8M3K5K2
D3
N2L3E3
L2
B3K4
N3
L6F4
J13F3
D1L7L5J5
F13F12
E13E12
C13B9B10C11B12A11B7B4A2D4B6A3
G11G12
C2
C3C4
D5
D8
D9
E5
F5H11
J6
J7J11
E11
F11
TSB83AA22
CRITICAL
BGA(2 OF 2)
R39201 2
0
MF-LF1/16W5%
402
R39001 2
22
MF-LF402
5%1/16W
C39101
2
0.1uF
X5R402
10%16V
C39111
2
0.1uF10%16VX5R402
R39031 2100
1/16W5%
MF-LF402
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
FireWire Link (TSB83AA22)
051-7023 06
8637
SYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)
PP3V3_S3
PLT_RST_FW
SMC_RSTGATE_L
PP3V3_S0FW_PLT_RST_L
=FW_PCI_IDSEL
PCI_PAR
PCI_CLK_FW
PCI_C_BE_L<1>PCI_C_BE_L<2>
PCI_AD<22>
PCI_C_BE_L<3>
PCI_C_BE_L<0>
PCI_DEVSEL_LPCI_FRAME_LPCI_GNT3_LINT_PIRQD_LPCI_IRDY_LPCI_PERR_LPCI_PME_FW_LPCI_REQ3_L
PCI_RST_FW_LPCI_SERR_LPCI_STOP_LPCI_TRDY_L
TP_FW_CTL<0>TP_FW_CTL<1>
TP_FW_DATA<0>
FW_DATA<2>
TP_FW_DATA<1>
FW_DATA<3>FW_DATA<4>FW_DATA<5>FW_DATA<6>FW_DATA<7>CLKFW_LINK_LCLKFW_LKONFW_LPSFW_LREQCLKFW_LINK_PCLKFW_PINT
PCI_AD<0>PCI_AD<1>PCI_AD<2>PCI_AD<3>PCI_AD<4>PCI_AD<5>PCI_AD<6>PCI_AD<7>PCI_AD<8>PCI_AD<9>
PCI_AD<20>PCI_AD<21>
PCI_AD<23>PCI_AD<24>
PCI_AD<26>PCI_AD<25>
PCI_AD<27>
PCI_AD<29>PCI_AD<28>
PCI_AD<30>PCI_AD<31>
PCI_AD<10>PCI_AD<11>PCI_AD<12>PCI_AD<13>PCI_AD<14>PCI_AD<15>PCI_AD<16>PCI_AD<17>PCI_AD<18>PCI_AD<19>
FW_MFUNC
FW_SDAFW_SCL
CLKFW_PHY_LCLK
PCI_ACK64_L
PCI_REQ64_L
FW_LLC_PP1V8LDO_EN_L
PCI_RST_L
PP1V8_S3
PP3V3_S3
FW_PCI_IDSEL
FW_G_RST_L
PP3V3_S3
PLT_RST_BUF_L
PP3V3_S3
FW_G_RST_L
79 78 70
66 65 64 60 59
57 56 53 51 48
43 36 34 33 29
80
28
80
80
80
66
27
66
66
66
64
26
64
64
64
63
25
66
63
63
63
62
24
63
62
62
62
59
23
54
59
59
59
58
22
32
58
58
58
56
21
31
56
56
56
51
20
29
51
51
51
45
19
28
45
45
45
41
17
19
41
41
41
37
14
16
37
37
37
32
10
14
32
32
32
27
5
5
27
27
27
5
4
4
4
5
5
26
5
SE
SM
RESET
D7
D5
D6
D4
D3
D2
CPS
PD
BMODE
PC2
PC0
PC1
LREQ
LPS
DS1
LCLK
DS0
XI
R1
R0
TESTM
TESTW
TPBIAS0
TPBIAS1
TPB1N
TPB1P
TPB0N
TPB0P
TPA1N
TPA1P
TPA0P
TPA0N
PINT
PCLK
AVDD_3P3
DVDD_3P3
DVDD_CORE
PLLVDD_3P3
PLLVDD_CORE
PLLGND
LKON_DS2
CNA
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT TRI-ST/NC
VCC
GND
IN
IN
IN BI
OUT
BI
BI
BI
BI
BI
BI
BI
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
SINGLE PORT DEVICES ARE POWER CLASS 0 (’000’)IMPLEMENT 1K PULLUP OR PULLDOWN ON PORT PAGE
NC
RESET PULSE WHEN PHY FIRSTRECEIVES POWER
CAPACITOR IN CONJUCTION WITHINTERNAL PULLUP PROVIDES
Resistor can probably be removedfrom design after evaluation
1MA (MAX) BUS HOLDERSDUAL PORT DEVICES ARE POWER CLASS 4 (’100’)
C40501
2 X5R
0.22uF
402
20%6.3V
R40551 2390K
1/16W5%
402MF-LF
U3900
D10
D11
G5
H5
L9
M12
A5
D13
C9
C10
C12
B13
B11
A6
B8
D12
H12
J12
K7
K6
C5
C6
G13
L13
N13
K13
N4
M4
N5
H13
K11
M13
A10
A7
A8
A12
A13
L10
A4
B5
L11
N7
E2
E1
J1
J2
B1
C1
G1
G2
D2
K1
A9
CRITICALCRITICAL
(1 OF 2)
TSB83AA22BGA
C40101
220%16V
402CERM
0.01uF
C40021
2 10VX5R
10%1uF
402
C40211
2402X5R10V10%1uF
44
44
44
44
44
44
44
44
37
44
44
R40622 16.34K
1%1/16W
402MF-LF
C40011
2 10V
402
1uF10%
X5R
C40031
2
1uF10VX5R
10%
402
C40041
2 X5R
10%1uF
402
10V
C40111
2 10VX5R
10%1uF
402
C40121
2 10VX5R
10%1uF
402
C40131
2402
1uF10%
X5R10V
C40141
2402
1uF10%
X5R10V
G4080
2
3 1
4CRITICAL
98P3040MHZSM
37
37
37 37 38
37
37
37
37
37
37
37
R40451
2MF-LF1/16W
5%
402
1K
FW_B_BILINGUAL
R40431
2
1K1/16W
FW_A_BILINGUAL
5%
402MF-LF
R40441
2MF-LF
10K
FW_B_DS_ONLY
1/16W
402
5%
R40421
2MF-LF
402
5%1/16W
FW_A_DS_ONLY
10K
C4031 1
2
1uF
X5R402
10%10V
C4030 1
2X5R10V10%1uF
402
C40351
2 X5R
10%1uF
402
10V
44
R405612
MF-LF402
5%1/16W
10K
R40851 2
0
5%1/16WMF-LF402
NO STUFF
R40861 24.7
1/16W5%
402MF-LF
R40631
2
1K
NO STUFF
MF-LF402
1%1/16W
R40001 2
MF-LF1/16W5%
1
402
R40351 2
402
5%1/16WMF-LF
4.7
R40201 2
MF-LF1/16W5%
1
402
R40601 2
5%1/16W
402MF-LF
0
R40821
2
5%1/16W
100K
402
NO STUFF
MF-LF
R40801 2
5%
22
402MF-LF1/16W
C40801
2 X5R402
0.22uF20%6.3V
R40811
2
NO STUFF
100
MF-LF402
1%1/16W
R4061
2
1
1/16W5%
402MF-LF
1KR40911
2
1/16W
1K5%
MF-LF402
R40401
2MF-LF
1K
402
5%1/16W
R40901
2
5%1K
1/16W
402MF-LF
FireWire PHY (TSB83AA22)SYNC_DATE=(MASTER)
051-7023 06
8638
SYNC_MASTER=(MASTER)
FW_PORT1_TPB_PFW_PORT1_TPB_N
PP1V95_FWPHY
PP1V8_FWPHY_OSCVOLTAGE=1.83VMIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.20 mm
FW_B_DS
FW_LPS
FW_PC0
PPBUS_S5_FW_FET FW_CPS
FW_DATA<5>FW_DATA<4>FW_DATA<3>FW_DATA<2>
FW_LREQ
CLKFW_PHY_LCLK
FW_R1
FW_TESTMFW_TESTW
FW_PORT1_TPA_N
FW_PORT2_TPA_N
FW_PINT
CLKFW_PHY_PCLK CLKFW_LINK_PCLK
FW_PHY_RESET_L
CLK98P304_FW_XI
FW_DATA<7>FW_DATA<6>
FW_BMODE
FW_A_TPBIAS
FW_PORT2_TPB_P
FW_B_TPBIAS
FW_R0
FW_OSC_EN
CLK98P304M_FW_XI_R
FW_PORT2_TPB_N
FW_PORT1_TPA_P
FW_PORT2_TPA_P
PP3V3_FWPHY
FW_A_DS
FW_LKON
FW_LKON
PP1V95_FWPHY
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.38 mmVOLTAGE=1.95VPP1V95_FWPHY_PLLVDD
PP3V3_FWPHY_AVDDVOLTAGE=3.3VMIN_LINE_WIDTH=0.38 mmMIN_NECK_WIDTH=0.25 mmPP3V3_FWPHY
MIN_NECK_WIDTH=0.25 mm
PP3V3_FWPHY_PLLVDDMIN_LINE_WIDTH=0.38 mmVOLTAGE=3.3V
44
44
43
43
42
66 42
42 42
38
43 38
38 38
5
42 5
38
5 5
4
4 4
37
4
5
5
4
5
OUT
OUT
AVDDL0
AVDDL4
AVDD
THRML_PAD
VDDO_TTL0
AVDDL6
VDDO_TTL1
RX_N
TESTMODE
TSTPT
LINK*
LED_LINK10/100*
LED_LINK1000*
LED_ACT*
RSET
CTRL25
CTRL12
HSDACN
HSDACP
SWITCH_VAUX
SWITCH_VCC
VMAIN_AVLBL
VAUX_AVLBL
LOM_DISABLE*
XTALO
XTALI
SPI_DO
SPI_CLK
SPI_CS
SPI_DI
VPD_CLK
VPD_DATA
MDIP3
MDIN3
MDIN2
MDIP2
MDIN1
MDIP1
MDIN0
MDIP0
WAKE*
REFCLKN
TX_N
VDDO_TTL3
VDDO_TTL2
VDDO_TTL4
VDD0
VDD1
VDD3
VDD2
VDD6
VDD5
VDD4
VDD7
AVDDL1
AVDDL2
AVDDL5
VDD25
PERST*
REFCLKP
RX_P
AVDDL3
TX_P
PU_VDDO_TTL0
PU_VDDO_TTL1TEST
TESTTWSI
SPI
MAIN CLK
PCI EXPRESSANALOG
MEDIALED
E2
WC*
NC0NC1
VCC
VSS
SCL
SDA
IN
IN
BI
BI
BI
BI
BI
BI
BI
BI
IN
IN
IN
OUT
OUT
OUT
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
TRACE LENGTH <12MIL
PLACE C4135-C4139 NEAR VDDO_TTL0-VDD_TTL4 ON U4101
NO PULL-UP NEEDED
PLACE C4113 AND C4112 WITHIN
PLACE C4100-C4106 NEAR PINS AVDLL0-AVDLL6.SCHEME MATCHES DOC MVL100258-01
PLACE C4110 AND C4111 WITHIN12 MIL OF U4101 PIN 49 AND 50
PLACE C4107 NEAR U4101 AVDD
PLACE C4140 NEAR U4102 VCC
SCHEME MATCHES DOC MVL100258-01PLACE C4127-C4134 NEAR PINS VDD0-VDD7 ON U4101
SCHEME MATCHES DOC MVL100258-01
NC
NC
2. DO NOT ROUTE UNDER CRYSTAL
NC
NC
NC
NC
NC
NC
NC
1. KEEP ENET_XTALI AND ENET_XTALO
ASF IS UNAVAILABLE ON 8053
PLACE RESISTORS CLOSE TO U4101
OPTIONAL EXTERNAL LDO NC
NC
INTERNAL PULL-UP
NC
12 MIL OF U2100 E27 AND E28
C41511
2
27pF50VCERM
5%
402
R4122
12
5%
4.7K
1/16W
MF-LF
402
R4123
12
4.7K
MF-LF
5%
402
1/16W
6
6
C41011
2402
16VX5R
10%0.1UF
U4101
23
19
22
28
32
51
52
57
3
4
25
24
59
60
62
63
10
18
21
27
31
17
20
26
30
5
42
43
56
55
16
53
54
37
36
35
34
9
11
46
65
29
50
49
12
27
13
64
33
39
44
48
58 18
40
45
61
47
38
41
6
15
14
CRITICALOMIT
QFN88E8053
C41401
2 16V10%0.1UF
402X5R
U41023
1
2
6
5
8
4
7 SO8
CRITICAL
M24C08
OMIT
22
R4102
12
1/16W
1%
4.87K
MF-LF
402
22
C41071
2
0.1UF
X5R402
10%16V
40
40
40
40
40
40
40
40
C4110
1 2
402
10%16VX5R0.1UF
C4111
1 2
16V10%
0.1UF402
X5R C4112
1 2
10%0.1UF402
16V
X5R
C4113
1 2
402X5R16V10%
0.1UF
R41061
2 402MF-LF
1%49.91/16W
R41171
2402
1%1/16WMF-LF
49.9R41181
2 402MF-LF1/16W
49.91%
R41191
2
1%49.91/16WMF-LF402
R41201
2 402
1/16W1%
MF-LF
49.9R41031
2MF-LF
49.9
402
1%1/16W
R41041
2 402MF-LF1/16W1%49.9
R41051
2402MF-LF1/16W1%49.9
C41161
2 50V10%
402CERM
0.001UFC41181
2402
10%0.001UF50VCERM
C41171
2
0.001UF
CERM
10%
402
50V
C41151
2402
50V10%
CERM
0.001UF
C41001
2402CERM6.3V10%1UF
L4100
1 2
FERR-120-OHM-1.5A
0402
R41311
2
4.7K5%1/16WMF-LF402
R41301
2 402MF-LF1/16W5%4.7K
R4101
12
4.7K
1/16W
402
5%
MF-LF
C41051
2
0.001UF
CERM
10%50V
402
C41041
2 X5R
10%0.1UF
402
16V
C41031
2402
0.1UF
X5R
10%16V
C41021
210%0.1UF
X5R402
16V
C41061
2
0.001UF
402CERM50V10%
C41281
2402
16V
0.1UF
X5R
10%
C41331
2
0.001UF10%
402
50VCERM
C41341
2 50V
402CERM
0.001UF10%
C41311
2402CERM
0.001UF10%50V
C41321
210%0.001UF
CERM402
50V
C41271
2 16V10%
X5R402
0.1UFC41261
210%
X5R402
16V
0.1UFC41291
2 16V
402X5R
0.1UF10%
C41301
2 16V10%
402X5R
0.1UF
C41391
2402CERM
10%50V
0.001UFC41381
2
0.001UF50VCERM402
10%
C41371
2 16V
0.1UF
X5R402
10%
C41361
2402
10%
X5R
0.1UF16V
C41351
2402X5R
0.1UF10%16V
34
34
26
5 23
47
Y410124
13
25.0000MSM-3.2X2.5MM
CRITICAL
22
22
C41501
2
27pF
402CERM50V5%
06051-7023
86
SYNC_MASTER=M1_MLB SYNC_DATE=02/10/2006
ETHERNET CONTROLLER
39
ENET_XTALOENET_XTALI
PP1V2_S3
ENET_MDI_P<2>ENET_MDI_N<2>ENET_MDI_P<3>ENET_MDI_N<3>
ENET_MDI_P<1>
PCIE_A_R2D_N
PP3V3_S3AC
ENET_MDI_P<0>
PP2V5_S3_ENET_AVDDMIN_NECK_WIDTH=0.22MMMIN_LINE_WIDTH=0.4MM
VOLTAGE=2.5V
ENET_VPD_DATA
ENET_PU_VDD_TTL0
PM_SLP_S3_L
ENET_MDI_N<0>
ENET_VPD_CLK
ENET_VPD_DATA
PP3V3_S3AC
ENET_RST_L
ENET_CLK100M_PCIE_NENET_CLK100M_PCIE_P
ENET_PU_VDD_TTL1
PCIE_A_D2R_C_P
PP2V5_S3
PCIE_WAKE_L
ENET_PU_VDD_TTL1
PP3V3_S3AC
ENET_RSET
ENET_LOM_DIS_L
PCIE_A_R2D_P
ENET_PU_VDD_TTL0
ENET_MDI1
PCIE_A_R2D_C_N
ENET_MDI0
PCIE_A_R2D_C_P
ENET_MDI3
PP3V3_S3AC
PCIE_A_D2R_C_N PCIE_A_D2R_NPCIE_A_D2R_P
PP3V3_S3AC
ENET_VPD_CLK
NC_ENET_CTRL25NC_ENET_CTRL12
PP1V2_S3
ENET_MDI_N<1>
ENET_MDI2
65 64 54 50
66 66
43
66
66
66
66 66
62 41
32
41
66
41
41
41 62
39 39
40
23
39
62
39
39
39 39
5 5
5
39
39
5
39
39
5
39
5
39
5
6
39
5
5
39
5
SYM_VER2
NC2 NC3NC4
LINE
SIDE
CHIP
SIDENC1
SYM_VER2
NC2 NC3NC4
LINE
SIDE
CHIP
SIDENC1
IN
BI
BI
BI
BI
BI
BI
BI
BI
OUT
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
BOM options provided by this page:
Place close to connector
514-0277Short shielded RJ-45
PHYSICAL
PROVIDED
ELECTRICAL_CONSTRAINT_SET
Place one cap at each pin of transformer
NET_TYPE
SPACING
Page NotesPower aliases required by this page:
(NONE)Signal aliases required by this page:
(NONE)
- =PP2V5_ENET
BY
ETHERNET
PHY
Transformers should be
sides of the board
- =GND_CHASSIS_ENET
mirrored on opposite
R42101 2
1/16W
NO STUFF
5%
MF-LF
0
402
C42031
2
1uF6.3V10%
CERM402
C42021
2
1uF6.3V10%
CERM402
C420421
100pF
CERM1808
10%3KV
R42031
2
1/16W5%
402MF-LF
75R42021
2
1/16W5%
402MF-LF
75R42011
2
1/16W5%
402MF-LF
75R42001
2
1/16W5%
402MF-LF
75
C42011
2 6.3V
402
1uF10%
CERM
C42001
2
1uF
CERM6.3V10%
402
T42001
10
11
14
15
16
2
3
6
7
8 9
4
5 12
13
XFR-SM
CRITICAL1000BT-824-00275
T42011
10
11
14
15
16
2
3
6
7
8 9
4
5 12
13
XFR-SM
1000BT-824-00275CRITICAL
5 39
39
39
39
39
39
39
39
39
6 44 79
J4200
9
10
11
12
1
2
3
4
5
6
7
8
CRITICAL
JM36113-P2054-7FF-RT-TH-RJ45
SYNC_DATE=02/10/2006SYNC_MASTER=M1_MLB
Ethernet Connector
86
051-7023
40
06
ENETCONN_P<3>
ENET_100DENETCONN ENETCONN_P<2>
ENET_MDI_P<0>
ENET_MDI_P<3>
MIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mm
ENET_CTAP_COMMON
ENET_MDI_N<3>
ENET_MDI_N<2>
ENET_MDI_P<2>
ENET_MDI_P<1>
ENET_MDI_N<0>
ENET_100DENETCONN ENETCONN_N<2>ENET_100DENETCONN ENETCONN_P<3>
ENET_100DENETCONN ENETCONN_P<0>ENET_100DENETCONN ENETCONN_N<0>
ENET_100DENETCONN ENETCONN_N<1>
ENET_100DENETCONN ENETCONN_N<3>
ENET_100DENETCONN ENETCONN_P<1>
ENET_CTAP1
ENET_CTAP3
ENET_CTAP2
ENETCONN_N<3>
ENETCONN_N<1>
ENETCONN_N<2>
ENETCONN_P<2>
ENETCONN_N<0>
GND_CHASSIS_DVI_BOT
ENET_MDI_N<1>
PP2V5_S3_ENET_AVDD
ENETCONN_P<0>
ENETCONN_P<1>
ENET_CTAP0
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
G
D
S
N-CHN
S
D
G
P-CHN
G
DS
G
D
S
G
D
S
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
S0 AC 0V 3.3V 0V (3.3V ON) 3.3V 0V (2.5V ON) 3.3V (1.2V ON)
Allows powering Yukon down during battery sleep to save power
1.2V enable has pull-up to 3.3V
When ENETPWR_S3 BOMOPTION is active:
When ENETPWR_S3AC BOMOPTION is active:
State PM_SLP_S4_L PM_SLP_S3BATT PM_SLP_S3BATT_L P2V5S3_EN_L P1V2S3_RUNSS
State FWPWR_EN_L PM_SLP_S4_L PM_SLP_S3BATT PM_SLP_S3BATT_L P2V5S3_EN_L P1V2S3_RUNSS
S0 Batt 0V 3.3V 0V (3.3V ON) 3.3V 0V (2.5V ON) 3.3V (1.2V ON)
S3 AC 0V 3.3V 0V (3.3V ON) 3.3V 0V (2.5V ON) 3.3V (1.2V ON)
S3 Batt PBUS 3.3V PBUS (3.3V OFF) 0V 3.3V (2.5V OFF) 0V (1.2V OFF)
S5 AC 0V 0V PBUS (3.3V OFF) 0V Hi-Z (2.5V OFF) 0V (1.2V OFF)
S5 Batt PBUS 0V PBUS (3.3V OFF) 0V Hi-Z (2.5V OFF) 0V (1.2V OFF)
G3H Batt PBUS 0V PBUS (3.3V OFF) 0V Hi-Z (2.5V OFF) 0V (1.2V OFF)
S0 3.3V 0V (3.3V ON) 3.3V 0V (2.5V ON) 3.3V (1.2V ON)
S3 3.3V 0V (3.3V ON) 3.3V 0V (2.5V ON) 3.3V (1.2V ON)
S5 0V PBUS (3.3V OFF) 0V Hi-Z (2.5V OFF) 0V (1.2V OFF)
G3H 0V PBUS (3.3V OFF) 0V Hi-Z (2.5V OFF) 0V (1.2V OFF)
Yukon Power Control
R43021
2
5%1/16WMF-LF402
470K
Q43043
5
4
2N7002DW-X-FSOT-363
R43041
2MF-LF
100K1/16W5%
402
R43001 2
0
ENETPWR_S3AC
402MF-LF1/16W5%
R43011
2
0
402MF-LF1/16W5%
ENETPWR_S3
Q4300
6
2
1
SC70-6FDG6332C_NL
Q4300
3
5
4
FDG6332C_NLSC70-6
Q43023
1
2
2N7002SOT23-LF
Q43046
2
1
SOT-3632N7002DW-X-F
R43051
2 402
5%1/16WMF-LF
100K
SYNC_DATE=02/10/2006SYNC_MASTER=M1_MLB
Yukon Power Control
051-7023 06
8641
P1V2S3_RUNSS
PM_SLP_S3BATT
FWPWR_EN_L_OR_GND
PM_SLP_S4_L
PP3V3_S3ACPP3V3_S3
PPVIN_S3_P2V5S3_SVIN
PM_SLP_S3BATT_L P2V5S3_EN_LMAKE_BASE=TRUEP2V5S3_EN_L
PPBUS_G3H
FWPWR_EN_L
80 66
78
64
70
63
68
62
66
59
64
58
63
65
56
61
63
51
60
50
45
54
47
37
47
46
66 32
43
62
23
39 27
62 62
5
5
5
5
5 5
62
41 41
4
43
ADJ
BYPGND
OUT
NC
NC
SHDN
IN
ON/OFFGNDVOUT
FBVIN
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
NC
NC<Ra>
Vout = 1.22V * (1 + Ra/Rb) + (Iadj * Ra)
<Rb>
Iadj = 30nA @ 25 deg C
165MA MAX LOAD
C44011
2 6.3VPOLY
20%
B2
100uF
C44221
2 6.3V20%
X5R603
10uF
R44201
2
16.2K
402
1%1/16WMF-LF
R44211
2
27.4K1%1/16W
402MF-LF
C4421 1
216V20%
402CERM
0.01uF
U4420
2
3
4
8
6
7
1
5
MSOP-LFLT1962-ADJ
CRITICAL
C4420 1
2X5R6.3V10%
603
2.2uF
L4400
1 2
220uH-0.26A
CDH73-SM
CRITICAL
D4401
1
2
SOD-123MBR0540XXG
U4400
4
6 5
7
8
LM2594SM-LF
CRITICAL
C4400 1
2
10uFN20P20%
2320
50VCERM
D44001
2
3
SC-59
SMD20E40C-X-F
FW PHY Power SupplySYNC_DATE=(MASTER)SYNC_MASTER=(MASTER)
051-7023 06
8642
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.5 mmFWPHY3V3_SW
PP3V3_FWPHY
FWPHY_CORE_BYP
PP3V3_FWPHY
FWPHY_CORE_ADJPP5V_S0
PPBUS_S5_FW_FET
PP1V95_FWPHY
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=33VMIN_LINE_WIDTH=0.38 mm
PP5VR33V_FWPHY3V3
80 79 78 70 67 66 65 61 60 57 56 54 52
44 44
47
43 43
36
42 42
31
66
38 38
25
43
38
5 5
5
38
5
4 4
4
4
4
OUT
GND
OUT
VIN+ VIN-
V+
G
D
S
G
D
S
S
G
D
GND
SENSEB
OUTA
FAULTB_L
FAULTA_L
ONB
INB
ONA
ONQ1
INA
GATE1A
GATE2A
SENSEA
GATE1B
GATE2B
OUTB
V-
V+
S
G
D
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
FWLATEVG_3V_REF:2.95V when port power is on2.81V when port power is off
0.025 ohm => 2A0.030 ohm => 1.66A (Ideal)0.033 ohm => 1.5A
Current Limits
0.020 ohm => 2.4A
50V/V
FireWire Port Current Sense
1A = 1V
(NONE)
NC
NC
- =PP3V3_S0_FWPORTPWRSW
is running or on AC.Enables port power when machine
BOM options provided by this page:
Signal aliases required by this page:
- =PPBUS_S0_FWPWRSW (system supply for bus power)
Late-VG Event Detection
Current Limit/Active Late-VG Protection
Port Power Switch- =FWPWR_PWRON (see related text note below)
Power aliases required by this page:
Page Notes
spikes. Current limit has been set higher to compensate.tends to trip easily on devices that produce periodic currentand -1/128 if under the limit. As a result, the device
reaches 16. A new sample (taken every 125 us) is weightedMAX5944 current limiter trips if integrator (counter)
as +1 if over the limit (at any point during the period)
R45661
2402
1/16WMF-LF
330K5%
C4565 1
216V20%
402CERM
0.01uFR45651
2
470K1/16W5%
402MF-LF
Q4565
5
6
7
8
4
1
2
3
NDS9407SOI-LF
CRITICAL
C4595 1
2CERM402
6.3V10%1uF
54
U4595
2
15
3 4
SOT23-5
CRITICAL
INA194
R45701 2
MF
0.5%
0.02
1W
0612
Q45603
5
4
2N7002DW-X-FSOT-363
Q45606
2
1
2N7002DW-X-FSOT-363
F45651 21.1A-24V
MINISMDC
CRITICAL
R45211 2
1/8W5%
0
NO STUFF
MF-LF805
Q4520
3
1
2
SOT23-3SI2318DS
R45261 2
NO STUFF
1/8W
0
5%
MF-LF805
C45251
2
1uF10%35V
805X7R
C4520 1
2
1uF
X7R805
10%35V
R45201 2
CRITICAL
0.020
1%0.25W
805MF
U4520
3
11
15
7
14
6
12
1
9
2
10
4 13
5
16
8
MAX5944SOIC
CRITICAL
D45651 2
CRITICAL
B340XF
SMB
U45004
3
1
5
2LMC7211SM-LF
R45001 2
1/16W
402
1%
MF-LF
200K
C45001
2402CERM10V20%0.1UF
C45091
210%10VCERM-X5R603
0.33uF
D450012
MBR0540XXG
SOD-123
R45091
2402
5%1/16W
2.0M
MF-LFR45051
2
1%
402MF-LF1/16W
10K
R45251 20.020
MF805
1%0.25W
CRITICALC45011
25%50V
402CERM
100pFR45061
2MF-LF1/16W
1%
402
80.6K
R45011
2MF-LF402
5%10K1/16W
Q4525
3
1
2
SOT23-3SI2318DS
R45291
2MF-LF1/16W5%
402
100K
FW_PORT_FAULT_PU
SYNC_DATE=(11/03/2005)SYNC_MASTER=(M1_MLB)
FireWire Port Power
8643
051-7023 06
PPBUS_G3H
PM_SLP_S3_L
SMC_ADAPTER_EN
VOLTAGE=12.6V
MIN_LINE_WIDTH=0.5 mmPPBUS_S5_FW_FET_D
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.2 mmFWPWR_EN_L_DIV
MIN_NECK_WIDTH=0.2 mm PP3V3_S0
VOLTAGE=12.6VMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.5 mmPPBUS_S5_FWPWRSW_F
MIN_LINE_WIDTH=0.2 mmFWPWR_EN_L
MIN_NECK_WIDTH=0.2 mm
FWPWR_IOUT
MIN_LINE_WIDTH=0.5 mmPPBUS_S5_FW_FET_D_R
MIN_NECK_WIDTH=0.25 mmVOLTAGE=12.6V
PPBUS_S5_FW_FET
FW_PORTB_PWRCTRL
PPFW_PORTB_ISENSEMIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mmVOLTAGE=33V
PPBUS_S5_FW_FETPPFW_PORTA_ISENSE
VOLTAGE=33VMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.5 mm
PPFW_PORTB_VP_UFMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.5 mm
VOLTAGE=33V
FW_PORTA_PWRCTRL
PPFW_PORTA_VP_UFMIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mmVOLTAGE=33V
PP2V4_FWLATEVG
FW_PORTPWR_ENLATEVG_EVENT_L
FWLATEGV_3V_REF
PP2V4_FWLATEVG_RCFW_PORT_FAULT_L
PP3V3_FWPHY
79 78 70 66
65 64 60 59 57 56 53 51 48
37 36 34 33 29 28 27
78
26
70
25
68
24
66
23
64
22
63
65
21
61
64
20
60
54
19
54
50
17
66
66
44
47
39
14
43
43
42
41
32
67
10
42
42
38
5
23
51
5
38
38
44
44
5
4
5
50
4
41
4
4
4
4
44
4
SYM_VER-2
TPO#
TPI
TPO
TPI#
VGND
VP
SYM_VER-2
SYM_VER-2
SYM_VER-2
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
per 1394b V1.33
TerminationPlace close to FireWire PHY
and connection detection currents
"Snapback" & "Late VG" Protection
(FW_PORT1_BREF)
NC NC
VG
VP
TPA<R>
TPB+
TPA+
TPB-
INPUT
Cable Power
Signal aliases required by this page:
FireWire Design Guide (FWDG 0.6, 5/14/03)
FW spec calls out 0.33uFTI PHYs require 1uF even though
SPACING
PHY
- =PP3V3_S5_FWLATEVG
1394A
BY
- =PPFW_PORT1
ELECTRICAL_CONSTRAINT_SET
(Common to all ports)for snap-back diodesESD and late-VG rail
R4690 should be 390 Ohms max for a 3.3V railand should be biased to 2.4V for marginto at least 2.1V for FW signal integrity
Late-VG Protection Power
PP2V4_FWLATEVG needs to be biased
TPA-
Cable Powerall local grounds per 1394b spec
BREF should be hard-connected tologic ground for speed signaling
(GND_FW_PORT1_VG)
PORT 2
(TPA+)
(TPA-)
(TPB+)
(TPB-)
514-0255
"Snapback" & "Late VG" Protection
the necessary aliases to map the FireWire TPA/TPB pairs to their appropriate connectors and/or to properly terminate unused signals.
BOM options provided by this page:(NONE)
NOTE: FireWire TPA/TPB pairs are NOT constrained on this page. It is assumed that FireWire PHY page will
1394b implementation based on Apple
to apply to entire TPA/TPB XNets. provide the appropriate constraints
NOTE: This page is expected to contain(NONE)
- =GND_CHASSIS_FW_PORT1
Power aliases required by this page:
Page NotesPAGE
PROVIDED
NET_TYPE
(to avoid ground offset issue)there is no DC path between themconnected to a beta-only device,When a bilingual device is
AREF needs to be isolated from
(GND_FW_PORT2_VG)
(PPFW_PORT2_VP)
PHYSICAL
OUTPUTTPB<R>
(PPFW_PORT1_VP)
514S0121
BILINGUALPORT 1
C46501
2
1uF
CERM
10%6.3V
402
R46511
2
56.21%
1/16W
402MF-LF
R46501
2
56.2
MF-LF402
1%1/16W
R46531
2
1/16W1%
56.2
402MF-LF
R46521
2
56.21/16W1%
402MF-LF
R46541
2
4.99K
MF-LF402
1%1/16W
C46541
2
220pF
CERM402
5%25V
R46991 2
0
MF-LF402
5%1/16W
L4630
1 2
FERR-250-OHM
SM
C46341
2402
20%50V
0.001uF
CERM
FL4630
1
2 3
4
CRITICAL
2012120-OHM
DP4630
4
5
3
SOT-363BAV99DW-X-F
J4630
7 8 9 10
4
3
6
5
2
1
1394AF-RT-TH-LF
CRITICAL
C4636 1
2
0.01uF
CERM
20%16V
402
C46351
220%
CERM
0.01uF50V
603
FL4631
1
2 3
4
CRITICAL
2012120-OHMDP4631
4
5
3
SOT-363BAV99DW-X-F
C4631 1
2
0.001uF
CERM402
50V20%
DP4630
1
2
6
BAV99DW-X-FSOT-363C4630 1
2CERM402
20%50V
0.001uF
C4633 1
2
0.001uF
CERM402
50V20%
DP4631
1
2
6
BAV99DW-X-FSOT-363
C4632 1
2
0.001uF
CERM402
20%50V
R46631
2
1%
402
56.2
MF-LF1/16W
R46641
2
1/16W1%
402MF-LF
4.99K
R46621
2
1%
402
56.21/16WMF-LF
C46641
2
220pF
CERM402
5%25V
R46611
2402
1%56.21/16WMF-LF
C46601
2
1uF6.3V10%
402CERM
R46601
2
1%56.21/16W
402MF-LF
R46001
2MF-LF
402
1/16W5%1K
C46271
2402
0.01uF16V20%
CERM
NO STUFF
C4629 1
2603-1
X7R50V10%
0.1uF
R46291
2
1/16WMF-LF402
5%1M
C46241
2
0.001uF
CERM402
20%50V
L4620
1 2
FERR-250-OHM
SM
C4625 1
2
0.01uF20%50V
CERM603
C46261
2402CERM16V20%0.01uF
C4620 1
2CERM402
20%50V
0.001uF
DP4620
1
2
6
SOT-363BAV99DW-X-F
C4621 1
2CERM402
50V20%
0.001uF
DP4620
4
5
3
BAV99DW-X-FSOT-363
DP4621
1
2
6
BAV99DW-X-FSOT-363
DP4621
4
5
3
SOT-363BAV99DW-X-F
C4623 1
2
0.001uF
CERM402
20%50V
C4622 1
2
0.001uF
CERM402
20%50V
L4690
1 2
400-OHM-EMI
SM-1
R46901 2
1/16WMF-LF402
332
1%
C4691 1
2402
CERM
20%10V
0.1uFC4692 1
2
0.001uF
CERM402
10%50V
D4690
1
3 CRITICAL
MMBZ5227BSOT23
FL4622
1
2 3
4
NO STUFFCRITICAL
2012H90-OHM-300mA
FL4620
1
2 3
4
NO STUFFCRITICAL
90-OHM-300mA2012H
R46201 2
0
5%
MF-LF1/16W
402
R46211 2
402MF-LF1/16W5%
0
R46221 2
402MF-LF
0
5%1/16W
R46231 2
402
5%1/16WMF-LF
0
J4620
1
10
11
2
3
4
5
6
7
8
9
CRITICAL
F-RT-SM1394B-M9
SYNC_DATE=(MASTER)SYNC_MASTER=(MASTER)
FireWire Ports
051-7023 06
44 86
FW_PORT1_TPB_FL_N
FW_PORT1_TPB_FL_P
FW_PORT1_TPA_FL_N
FW_PORT2_TPA_N
PP2V4_FWLATEVG
FW_PORT2_TPA_FL_N
FW_PORT2_TPA_FL_P
FW_PORT2_TPB_FL_N
FW_PORT1_TPA_N
FW_PORT1_TPA_P
FW_PORT2_TPB_P
FW_PORT1_TPB_P
FW_PORT2_TPB_N
FW_PORT1_TPB_FL_PFW_110DFWFW_PORT1_TPB_FL_NFW FW_110D
FW_110DFW FW_PORT2_TPA_FL_PFW FW_110D FW_PORT2_TPA_FL_N
FW_PORT2_TPA_P
FW_PORT2_TPB_FL_P
GND_CHASSIS_DVI_BOT
GND_CHASSIS_USB
GND_CHASSIS_USB
PPFW_PORTA_VP_UF
PP3V3_FWPHY
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.38 mm
PP2V4_FWLATEVG_RVOLTAGE=2.4V VOLTAGE=2.4V
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.38 mmPP2V4_FWLATEVG
FW_PC0 FW_PC0MAKE_BASE=TRUE
PP3V3_FWPHY
MAKE_BASE=TRUEFW_PORT2_TPB_N
MAKE_BASE=TRUEFW_PORT1_TPA_P
MAKE_BASE=TRUEFW_PORT2_TPA_P
MAKE_BASE=TRUEFW_PORT2_TPA_N
MAKE_BASE=TRUEFW_PORT2_TPB_P
FW_110DFW FW_PORT2_TPB_FL_N
MAKE_BASE=TRUEFW_PORT1_TPB_N
FW_PORT1_TPA_C
MAKE_BASE=TRUEFW_PORT1_TPB_PMAKE_BASE=TRUEFW_PORT1_TPA_N
FW_A_TPBIAS
FW_PORT1_TPB_N
FW_PORT1_TPA_N
FW_PORT2_TPA_C
PPFW_PORTB_VP_UF
MIN_LINE_WIDTH=0.5 mmPPFW_PORT2_VP
MIN_NECK_WIDTH=0.25 mmVOLTAGE=33V
FW FW_110D FW_PORT2_TPB_FL_P
FW_PORT1_TPA_FL_PFW_110DFW
GND_CHASSIS_DVI_BOT
FW_PORT1_TPA_P
FW_PORT2_TPB_N
FW_PORT2_TPB_P
FW_PORT2_TPA_N
FW_PORT2_TPA_P
FW_B_TPBIAS
FW_PORT1_TPA_FL_NFW_110DFW
PPFW_PORT1_VPMIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mmVOLTAGE=33V
FW_PORT1_TPA_FL_P
FW_PORT1_AREF
FW_PORT1_TPB_P
FW_PORT1_TPB_N
PP2V4_FWLATEVG
44
44
43
43
79
42
42
79
44
46
46
38
38
44
44
44
44
44
44
44
44
44
40
44
44
43
5 44
44 44
5
44
44
44
44
44
44
44
44
44
44
43
40
44
44
44
44
44
44
44
44
44
44
44
38
43
44
44
44
38
38
38
38
38
44
44
44
44
38
44
6
6
6
4
4 43
38 38
4
38
38
38
38
38
44
38
38
38
38
38
38
4
44
44
6
38
38
38
38
38
38
44
44
38
38
43
BI
BI
BI
BI
BI
OUT
OUT
BI
IN
OUT
SYM_VER-2
SYM_VER-2BI
BI
BI
BI
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
LIO Temp Sensor Connector
NC
NC
Top-Case Connector
516S0350
Connector shield
Twin-Ax Pair 1
Camera Connector
518S0371
(40 AWG)
Connector shield
Standard wires
Twin-Ax Pair 2
(28 AWG)
(40 AWG)
5 23 27 28
29 33
47 5 23 27 28 29 33 47
27 50
27 50
J4900
1
10
11 12
13 14
15 16
2
3 4
5 6
7 8
9
M-ST-SMQT500166-L020
CRITICAL
6 22
5 50 51 54
50 51
J4931
7
8
1
2
3
4
5
6
F-RT-SMCAMERA-M1-CUS
CRITICAL
6 22
56
56
D4900
3
1
2
CRITICAL
RCLAMP0502B
SC-75
L4931
1 2
FERR-220-OHM
0402
L4930
1 2
0402
FERR-220-OHM
FL4936
1
2 3
4SM
165-OHM
CRITICAL
FL4935
1
2 3
4SM
165-OHM
CRITICAL
5 6 22
5 6 22
5 27 50 53
27
D4930
3
12NO STUFF
CRITICALSC-75
RCLAMP0502B
C4931 1
2
0.001uF
CERM402
20%50V
NO STUFF
PLACEMENT_NOTE=Place next to J4931 pin 7
C4930 1
250V20%
402CERM
0.001uF
NO STUFF
PLACEMENT_NOTE=Place next to J4931 pin 8
C49321
2 CERM402
20%0.01uF16V
J4990
5
6
1
2
3
4
F-RT-SM88460-0401
CRITICALLIO_TEMP
051-7023 06
8645
Internal USB ConnectionsSYNC_MASTER=M1_MLB SYNC_DATE=02/10/2006
SMBUS_SMC_0_S0_SCL_R
USB2_CAMERA_P
USB2_CAMERA_N
SMBUS_SMC_0_S0_SDASMBUS_ATS_SCL_FSMBUS_ATS_SDA_F
VOLTAGE=5V
MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.25 mm
PP5V_S3_CAMERA_F
USB2_CAMERA_P_F
MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.25 mmVOLTAGE=0VGND_CAMERA
USB2_CAMERA_N_F
PP5V_S3
PP3V42_G3HPP5V_S3
USB_TRACKPAD_NUSB_TRACKPAD_P
KBDLED_ANODE
SMBUS_SB_SCLSMBUS_SB_SDA
SMC_LID
SMC_ONOFF_LKBDLED_RETURN
PP3V3_S3
SMBUS_SMC_A_S3_SCLSMBUS_SMC_A_S3_SDA
80 66
68
64
67
63
66
62
65
59
54
58
52
56
80
51
80
51
66
50
66
41
61
35
61
37
51
27
51
32
45
26
45
27
5
5
5
5
SYM_VER-2BI
BI
OUT
VBUS
D-
D+
GND
PADTHRML
GND
OUT_2
OUT_1
OUT_0
OC*EN*
IN_0
IN_1
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
Right USB Port
Place L5200, L5205 and L5206 across moat
514S0115
Port Power Switch
L5200
1
2 3
4
CRITICAL
165-OHMSM
L5205
1 2
FERR-250-OHM
SM
C52961
2 6.3V20%
B2POLY
100UFC5295 1
2
10uF
CERM805-1
6.3V20%
C5290 1
2CERM
20%6.3V
10uF
805-1
C52911
2 10V20%
402CERM
0.1UF
C5205 1
2402
16VCERM
20%0.01uF
C5206 1
2
0.01uF20%
402
16VCERM
L5206
1 2
SM
FERR-250-OHM
6 22
6 22
6 22
J5200
1
2
3
4
5
6
7
8
F-RT-SM-USB-RGT1UAR2X
CRITICAL
D5200
3
12
CRITICAL
RTUSB_ESD
SC-75
RCLAMP0502B
U5290
4
1
2
3
5
8
7
6
9
TPS2051
CRITICAL
MSOP
R52921 2
0
402MF-LF1/16W5%
C52921
2402CERM-X5R6.3V20%
NO STUFF
0.47uF
External USB ConnectorSYNC_DATE=02/10/2006SYNC_MASTER=M1_MLB
051-7023 06
8646
RTUSB_OC_LRTUSB_OC_L_RC
MIN_NECK_WIDTH=0.5 mmVOLTAGE=5V
PP5V_S3_RTUSB_ILIMMIN_LINE_WIDTH=0.5 mm
VOLTAGE=0VMIN_NECK_WIDTH=0.5 mmMIN_LINE_WIDTH=0.5 mmGND_RTUSB
GND_CHASSIS_USB
USB2_RT_F_NUSB2_RT_F_P
USB2_RT_N
USB2_RT_P
PM_SLP_S4_L
PP5V_S5PP5V_S3_RTUSB_F
VOLTAGE=5VMIN_NECK_WIDTH=0.5 mmMIN_LINE_WIDTH=0.5 mm
70 67 66
65
65
63
64
50
63
47
61
41
51
44
23
25
6
5
5
IN
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
NCNC
Place XW5515 at 5V switcher
NC
516S0361(500 mA) (500 mA)
Left I/O Board Connector
Place XW5505 at 5V switcherNC
NC
NC
5 6 50
XW55151 2
SMXW5505
12
SM
J5500
1
10
1112
1314
1516
1718
19
2
20
2122
2324
2526
2728
29
3
30
3132
3334
3536
3738
39
4
40
4142
4344
4546
4748
49
5
50
5152
5354
5556
5758
59
6
60
6162
6364
6566
6768
69
7
70
7172
7374
7576
7778
79
8
80
81
8283
84
9
CRITICAL
F-ST-SMQT510806-L111-7F
47 86
06051-7023
Left I/O Board ConnectorSYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)
SMC_BC_ACOKLT2USB_OC_L
USB2_LT2_P LTUSB_OC_L
SYS_ONEWIREALS_GAIN
PCIE_MINI_R2D_C_N
PP5V_S0
PP1V5_S0
PPBUS_G3H
USB2_EXCARD_N
PCIE_CLK100M_MINI_N
PCIE_MINI_D2R_N
PCIE_EXCARD_D2R_P
PCIE_EXCARD_R2D_C_NPCIE_EXCARD_R2D_C_P
VOLTAGE=0VMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.4 mmGND_AUDIOPP5V_S0_AUDIO
MIN_LINE_WIDTH=0.4 mm
VOLTAGE=5VMIN_NECK_WIDTH=0.2 mm
PCIE_EXCARD_D2R_N
PCIE_CLK100M_EXCARD_PPCIE_CLK100M_EXCARD_N
PCIE_MINI_R2D_C_P
PCIE_MINI_D2R_P
PCIE_CLK100M_MINI_P
USB2_EXCARD_P
USB2_LT_P
SMBUS_SB_SDASMBUS_SB_SCLACZ_RST_L
ACZ_SYNCACZ_SDATAIN<0>ACZ_BITCLKACZ_SDATAOUT
PCIE_WAKE_LPM_SLP_S4_LSMC_EXCARD_PWR_ENPM_SLP_S3_LS5VSMC_EXCARD_CPEXCARD_OC_LMINI_CLKREQ_LEXCARD_CLKREQ_L
LIO_PLT_RESET_LLTALS_OUT
USB2_LT_N
USB2_LT2_N
80 79 78 70 67 66 65
78
61
70
60
66
68
57
65
66
56
25
64
54
24
63
52
19
61
45
45
65
42
17
60
33
33
63
68
36
16
54
29
29
50
67
31
13
43
28
28
46
51
51
22
22 22
51
25
9
41
22
49
49
49
49
22
22
27
27
86
86
86
86
86
39
41
65
51
22
34
34
22
22
50
5
6 6
50
49
5
8
5
6
34
22
22
49
49
22
34
34
49
22
34
6
6
23
23
21
21
21
21
21
23
23
50
61
50
6
33
33
26
56
6
6
5
4
5 5
5
5
4
5
4
5
5
5
5
5
5
5 5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
GND
OUT
VIN+ VIN-
V+
ALERT
A0
SCL
SDA
GNDS
V+
GND
OUT
VIN+ VIN-
V+
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
Placement Note:Place near R8307
near L8300 and
bottom side
Q8301 and Q8302
DCIn Current Sense
Place near R8308
Temp Sensor has address x90,x91
Placement Note:
Place sensor on
TMP106 Thermal Sensor
Battery Current Sense
R56511
2
1/16WMF-LF
NO STUFF
05%
402
R56501
2MF-LF402
5%1/16W
0
U5605
2
15
3 4
CRITICAL
INA193SOT23-5
C56151
210%6.3VCERM402
1uFC56051
26.3V10%
CERM402
1uF
C56501
2 10VCERM
0.1uF20%
402
U5650
C2
B2
A2
B1
A1
C1
WCSP-6TMP106
CRITICAL
U5615
2
15
3 4
CRITICAL
INA193SOT23-5
SYNC_DATE=(MASTER)SYNC_MASTER=(MASTER)
Current & Thermal Sensors
051-7023
48 86
06
CHGR_CSOP_R
CHGR_CSON_R
PP3V3_S0
LIO_BATT_ISENSE
TMPSNSR_A0
SMBUS_SMC_B_S0_SCL
SMBUS_SMC_B_S0_SDA
PP3V3_S0
LIO_DCIN_ISENSE
CHGR_CSI_P
PP3V3_S0
CHGR_CSIN_R
79
79
79 78
78
78 70
70
70 66
66
66 65
65
65
64
64
64 60
60
60 59
59
59 57
57
57 56
56
56 53
53
53 51
51
51 48
48
48 43
43
43
37
37
37 36
36
36 34
34
34 33
33
33 29
29
29 28
28
28 27
27
27 26
26
26 25
25
25 24
24
24 23
23
23 22
22
22 21
21
21 20
20
20 19
19
19 17
17
17 14
50
50
14
14 10
27
27
10
10 5
10
10
5
5
68
68
4
54
4
4
4
54
68
4
68
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
PCI-E x1 Port "F" = Unused
PCI-E x1 Port "E" = Unused
PCI-E x1 Port "D" = Unused
PCI-E x1 Port "C" = ExpressCard
PCI-E x1 Port "B" = PCI-E Mini Card
PCI-E x1 Port "A" = Ethernet (Yukon)
Place caps close to SB
Place caps close to SB
C57101 20.1uF
10%16VX5R402
C57111 20.1uF
10%16VX5R402
C57211 20.1uF
10%16VX5R402
C57201 20.1uF
10%16VX5R402
SYNC_DATE=02/10/2006SYNC_MASTER=M1_MLB
PCI-E Connections
051-7023 06
8649
TP_PCIE_F_R2DP
PCIE_B_R2D_C_P
PCIE_MINI_D2R_N
MAKE_BASE=TRUETP_PCIE_F_R2DN
PCIE_MINI_D2R_P
PCIE_MINI_D2R_N
PCIE_MINI_R2D_C_N
PCIE_MINI_R2D_C_P
PCIE_B_R2D_C_NMAKE_BASE=TRUEPCIE_MINI_R2D_C_N
PCIE_MINI_D2R_NMAKE_BASE=TRUE
PCIE_MINI_D2R_PPCIE_MINI_D2R_PMAKE_BASE=TRUE
PCIE_MINI_R2D_C_PMAKE_BASE=TRUE
PCIE_EXCARD_R2D_C_P
PCIE_EXCARD_R2D_C_N
PCIE_EXCARD_D2R_P
PCIE_EXCARD_D2R_N
PCIE_EXCARD_R2D_C_PMAKE_BASE=TRUE
PCIE_EXCARD_R2D_C_NMAKE_BASE=TRUE
PCIE_EXCARD_D2R_PMAKE_BASE=TRUEPCIE_EXCARD_D2R_N
MAKE_BASE=TRUE
PCIE_C_R2D_C_P
PCIE_C_R2D_C_N
PCIE_EXCARD_D2R_N
PCIE_EXCARD_D2R_P
MAKE_BASE=TRUETP_PCIE_D_D2RP
MAKE_BASE=TRUETP_PCIE_D_D2RN
MAKE_BASE=TRUETP_PCIE_D_R2DNMAKE_BASE=TRUETP_PCIE_D_R2DP
TP_PCIE_D_D2RP
TP_PCIE_D_D2RN
TP_PCIE_D_R2DN
TP_PCIE_D_R2DP
TP_PCIE_E_R2DP
TP_PCIE_E_R2DN
TP_PCIE_E_D2RN
TP_PCIE_E_D2RP
MAKE_BASE=TRUETP_PCIE_E_R2DP
MAKE_BASE=TRUETP_PCIE_E_R2DN
MAKE_BASE=TRUETP_PCIE_E_D2RNMAKE_BASE=TRUETP_PCIE_E_D2RP
TP_PCIE_F_R2DN
TP_PCIE_F_D2RN
TP_PCIE_F_D2RP
MAKE_BASE=TRUETP_PCIE_F_R2DP
MAKE_BASE=TRUETP_PCIE_F_D2RNMAKE_BASE=TRUETP_PCIE_F_D2RP
49
49
49
49
49
49
49 47
49 47
49
49
47
47 49
49
47
47
47
49
49
49
22
47 22
49
49
49
47
47
49
49
22
22 47
47
49
22
49
22
22
47
47
47
5
22 5
47
47
47
22
22
47
47
5
5 22
22
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
22
22
5
22
5
5
5
5
22 5
5
5
5
5
5
5
5
5
22
22
5
5
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
IN
IN
IN
OUT
OUT
OUT
OUT
IN
IN
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
IN
IN
OUT
OUT
OUT
P16
P51
P50
P42/SDA1
P97/IRQ15*/SDA0
P95/IRQ14*
P94/IRQ13*
P93/IRQ12*
P92/IRQ0*
P91/IRQ1*
P86/IRQ5*/SCK1/SCL1
P83/LPCPD*
P82/CLKRUN*
P80/PME*
P35/LRESET*
P34/LFRAME*
P10
P12
P13
P14
P15
P17
P31/LAD1
P30/LAD0
P32/LAD2
P33/LAD3
P36/LCLK
P37/SERIRQ
P44/TMO1
P77/AN7
P76/AN6
P81/GA20
P96/EXCL
P11
P47/PWX1/PWM1
P45
P46/PWX0/PWM0
P40/TMIO
P43/TMI1/EXSCK1
P27
P26
P25
P24
P23
P22
P21
P20
P41/TMO0
P52/SCL0
P60/KIN0*
P61/KIN1*
P62/KIN2*
P63/KIN3*
P64/KIN4*
P65/KIN5*
P66/IRQ6*/KIN6*
P67/IRQ7*/KIN7*
P70/AN0
P71/AN1
P72/AN2
P73/AN3
P74/AN4
P75/AN5
P84/IRQ3*/TXD1
P85/IRQ4*/RXD1
P90/IRQ2*
(1 OF 4)
PA2/KIN10*/PS2AC
PA3/KIN11*/PS2AD
PA5/KIN13*/PS2BD
PA4/KIN12*/PS2BC
PB2
PB3
PB4
PE0
PG6/EXIRQ14*/EXSDAB
PG5/EXIRQ13*/EXSCLA
PH1/EXIRQ7*
PH0/EXIRQ6*
PG7/EXIRQ15*/EXSCLB
PG4/EXIRQ12*/EXSDAA
PH3/EXEXCL
PH2/FWE
PB5
PF4/PWM4
PF2/IRQ10*/TMOY
PG2/EXIRQ10*/SDA2
PG0/EXIRQ8*/TMIX
PF7/PWM7
PC3/TIOCD0/TCLKB/WUE11*
PH5
PB7
PB6
PH4
PF5/PWM5
PF6/PWM6
PG1/EXIRQ9*/TMIY
PA6/KIN14*/PS2CC
PA7/KIN15*/PS2CD
PD0/AN8
PD1/AN9
PD2/AN10
PD3/AN11
PD4/AN12
PD5/AN13
PD6/AN14
PD7/AN15
PF0/IRQ8*/PWM2
PF1/IRQ9*/PWM3
PB0/LSMI*
PB1/LSCI
PC0/TIOCA0/WUE8*
PC1/TIOCB0/WUE9*
PC2/TIOCC0/TCLKA/WUE10*
PC4/TIOCA1/WUE12*
PC5/TIOCB1/TCLKC/WUE13*
PC6/TIOCA2/WUE14*
PC7/TIOCB2/TCLKD/WUE15*
PG3/EXIRQ11*/SCL2
PF3/IRQ11*/TMOX
PA1/KIN9*/PA2DD
PA0/KIN8*/PA2DC
PE1*/ETCK
PE2*/ETDI
PE3*/ETDO
PE4*/ETMS
(2 OF 4)
VCL
AVREF
VCC
VCC
VCC
AVCC
XTAL
EXTAL
AVCC
VCC
MD1
MD2
NMI
RES*
ETRST*
AVREF
AVSSVSS
(3 OF 4)
NC22
NC21
NC20
NC19
NC18
NC17
NC16
NC15
NC14
NC13
NC12
NC9
NC6
NC11
NC10
NC8
NC7
NC5
NC4
NC3
NC2
NC1
NC0
(4 OF 4)
OUT
OUT
BI
OUT
IN
IN
IN
OUT
IN
BI
IN
BI
OUT
OUT
IN
IN
OUT
OUT
IN
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
IN
IN
IN
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
OUT
IN
IN
OUT
OUT
IN
OUT
OUT
ININ
OUT
OUT
BI
BI
BI
BI
IN
IN
IN
OUT
OUT
OUT
BI
IN
IN
IN
IN
BI
BI
IN
IN
BI
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
THEY ARE SET BY SOFTWARE TO BEDRIVEN OUTPUTS ALWAYS SO THEY
LAYOUT NOTE:PLACE C5807 NEAR PIN F1
VCL IS INTERNAL RAILPLACE R5899 AND C5820 NEAR SMC PIN N14,N15
SMC
LAYOUT NOTE:
UNUSED PINS HAVE THE FORMAT
CAN BE LEFT NO-CONNECTED.
SMC_XXX WHERE XXX IS THE PORT NUMBER.
C58021
2805
20%6.3VCERM
22UF
5 23 51 52 59
5 51 52
5 45 51 54
C58071
2402
0.47UF20%6.3VCERM-X5R
C58031
2 10V0.1UF20%CERM402
C58201
2
0.1UF20%CERM10V402
R58991 2
5%1/16W
4.7
402MF-LF
C58041
2
0.1UF20%10VCERM402
XW58001 2
SM
23
5 60
C58051
240210V20%0.1UFCERM
5 23
23
51 64
26 65
4 37
5 23 C58061
220%10VCERM402
0.1UF
54
54
54
54
54
54
54
54
5 51 67
5 47 51 67 68
5 51 52
5 51 52
22 55
22 55
43 51 67
65 U5800B12C13A15B14B15C14D12C15
D13D14D15E12E14E15E13F14
D9C9A9B9D8C8A8D7
A5B5D5C3B1C2D3C1
G1G4F2
L13L14L15K12K13K14J12J13
N12R13P13R14P14R15N13P15
C7A7B7D6C6A6B6
K4J2J1J3J4H2H1G2
BGA
OMIT
SMC_H8S2116
U5800R3P3R2N3R1N2M4N1
B10A10D10A11B11C11A12D11
G14G15G13G12H14H15H13H12
M11P11R11N11P10R10N10M10
M3M2M1L4L2
M7P6R6N6M6R5P5N5
P9R9N9P8R8M8P7R7
E1F3K2C4D4B3
OMIT
SMC_H8S2116BGA
U5800
N14
N15
M14
M15
P12R12
L1
B2
E2K1
F4
E3
P2
P1J15
A1
F1
D1P4R4
F12
F13
B13
A13A4B4D2
A2
BGASMC_H8S2116
OMIT
U5800
G3H3
K15J14
F15A14C12C10C5A3B8E4
K3
H4M9N8
L3N4M5N7
M12M13L12
BGASMC_H8S2116
OMIT
51 68
51 68
27
51
R58091
2MF-LF5%
4021/16W10K
5 52
5 52
R58011
2MF-LF402
5%10K1/16W
R58021
21/16W5%10KMF-LF402
R58031
2
NOSTUFF
402MF-LF1/16W5%0R58981
2
10KMF-LF5%1/16W402
5 23 26
51 59
14 28 29 51
5 47 51
23
23
23
5 54
36
5 47 51
5 47
23
51
57
57
51
51
51
51
57
57
58
58
51 54
58
56
56
51 54
5 51 52
51
5 51 52
5 51 52
5 51 52
45 51
51
68
51
68
51
22 55
5 27 67
5 27 67
27 45
27 45
4 10 27 48
4 10 27 48
51
51
5 6 47
23 51
58
5 22 52
51
22
22 55
51
23
51
51
21
51
51
51
51 51
51
51
5 21 52 59
5 21 52 59
5 21 52 59
5 21 52 59
5 21 52 59
5 26
34
5 23 52 59
51
56
5 27 53
5 23 32 39 43 54 64 65
5 23 41 46 47 63 65
5 23 51
35
5 27 45 53
27
51
5 21 51 52
5 23 52 59
051-7023 06
50 86
TP_SMC_SYS_VSET
SMC_BATT_ISET
SMC_LIDTP_SMC_PF1
SMS_ONOFF_L
SMS_X_AXIS
SMS_Z_AXISTP_SMC_ANALOG_IDSMC_P1V05S0_ISENSESMC_P1V8S3_ISENSE
SMC_BS_ALRT_L
SMS_INT_L
SMC_CPU_ISENSE
SPI_SI
TP_SMC_FAN_2_CTL
SMC_EXCARD_OC_L
SMC_PM_G2_EN
TP_SMC_P22
SMC_XTALSMC_EXTAL
PP3V3_AVCC_SMCMIN_LINE_WIDTH=0.25 MMMIN_NECK_WIDTH=0.20 MM PP3V42_G3H
KBC_MDE
ALS_LEFT
SMC_MD1
PP3V3_AVREF_SMC
SMC_PROCHOT
SMC_TRST_L
SMC_NMI
GND_SMC_AVSS
SPI_ARB
SMC_XDP_TDO_3_3
SMC_SYS_LED_16B
GND_SMC_AVSS
PP3V42_G3H
FWH_INIT_L
TP_SMC_P23
SMC_BC_ACOK
SMC_FWE
ALS_RIGHT
SMS_Y_AXIS
TP_SMC_FAN_3_TACH
SMC_FAN_1_CTLSMC_FAN_0_CTL
TP_SMC_P21
SMC_BATT_TRICKLE_EN_L
TP_SMC_P20
SMC_BATT_CHG_ENTP_SMC_P26
SMC_CASE_OPENSMC_TCKSMC_TDISMC_TDOSMC_TMS
SMC_SYS_ISETTP_SMC_BATT_VSETSMC_ODD_DETECT
SMC_RUNTIME_SCI_L
SMBUS_SMC_0_S0_SDA
SMC_CPU_VSENSE
SMC_ADAPTER_EN
TP_SMC_PF0
SPI_CE_LSMC_XDP_TCK_3_3
SMC_CPU_RESET_3_3_L
SMC_GPU_ISENSE
SMC_DCIN_ISENSE
SMC_EXCARD_CP
SMC_VCL
PP3V42_G3H
PM_SLP_S5_LPM_SLP_S4_LPM_SLP_S3_L SMC_RST_L
ALS_GAIN
SMC_THRMTRIP
TP_SMC_XDP_TRST_L
PM_SYSRST_L
SMC_CLK32K_SUSCLK
SPI_SCLK
SPI_SOSMC_PROCHOT_3_3_L
SMC_GPU_VSENSE
SMC_PBUS_VSENSESMC_BATT_ISENSESMC_FWIRE_ISENSE
SMC_EXCARD_PWR_EN
ISENSE_CAL_EN
SMC_EXTSMI_L
SMC_RX_L
TP_SMC_XDP_TCK
TP_SMC_XDP_TMS
SMBUS_SMC_BSB_SDASMC_TPM_PP
TP_SMC_FAN_3_CTL
TP_SMC_FAN_2_TACHSMC_FAN_1_TACHSMC_FAN_0_TACH
PM_BATLOW_LSYS_ONEWIREPM_THRM_LPM_EXTTS_LSMC_TPM_RESET_L
BOOT_LPC_SPI_LSMC_RCIN_L
TP_SMC_P27
LPC_AD<0>LPC_AD<1>LPC_AD<2>LPC_AD<3>LPC_FRAME_LSMC_LRESET_LPCI_CLK_SMCINT_SERIRQ
SMC_TPM_GPIOPM_CLKRUN_LPM_SUS_STAT_LSC_TX_LSC_RX_L
SMC_ONOFF_L
SMBUS_SMC_BSB_SCL
SMC_WAKE_SCI_L
PM_PWRBTN_LIMVP_VR_ONPM_RSMRST_LSMC_SB_NMIRSMRST_PWRGDALL_SYS_PWRGD
PM_LAN_ENABLESMC_RSTGATE_L
SMBUS_SMC_0_S0_SCL
SMBUS_SMC_BSA_SDASMBUS_SMC_BSA_SCLSMBUS_SMC_A_S3_SDASMBUS_SMC_A_S3_SCLSMBUS_SMC_B_S0_SDASMBUS_SMC_B_S0_SCL
SMC_SYS_KBDLEDTP_SMC_SYS_LED
SMC_TX_L
68
68
68
67
67
67
66
66
66
65
65
65
54
54
54
52
52
52
51
51
51
50
50
50
45
45
45
35
56
56
35
35
27
54
54
27
27
26
52
51
51
26
26
51
51
51
51
5
5
51
50
50
5
51
51
51
51
51
5 51
G
D
S
G
D
S
IN OUT
GND
IN OUT
V-
V+
V-
V+OUT
NCCD
GND
OUT
VDD
OUT
OUT
G
D
SIN
OUT
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
SMC 1.05V to 3.3V Level Shifting
1.05V Mid-Reference
Silk: "SMC RST"
SMC Reset Button / Brownout Detect
NC
System (Sleep) LED Circuit
NOTE: R5965 acts as 10K pull-up for PGOOD signal
1.71V Reference
Silk: "PWR BTN"
Debug Power ButtonSMC 3.3V to 1.05V Level Shifting
SMC AVREF Supply
ISL6269 undervoltage threshold 81-87% (2.67 - 2.87V)
5V Comp threshold set to 4.480V (89.6%)
SMC Crystal Circuit
SMC PWRGD CircuitReports when 5V S5 and 3.3V S5 are in regulation
C5900 1
210V20%
402CERM
0.1uF
R59901 2
402MF-LF
5%
0
SMC_TPM_GPIO1
1/16WR59911 2
402MF-LF1/16W5%
SMC_TPM_GPIO2
0
Q59956
2
1
SOT-3632N7002DW-X-F
Q59953
5
4
SOT-3632N7002DW-X-F
R59921 2
5%
0
MF-LF1/16W
402R59931 2
402
5%
0
MF-LF1/16W
C5977 1
210V20%
402CERM
0.1uF
R59711
2
1/16W5%
402MF-LF
1K
R59701
2MF-LF1/16W
6.2K
402
5%
C59651
2402CERM-X5R
20%6.3V
0.47uF
C59671
2402CERM16V20%0.01uF
C5966 1
2603
10uF
X5R
20%6.3V
VR5965
3
1 2
CRITICAL
REF3133SOT23-3
C5960 1
2CERM402
20%10V
0.1uFR59611
2
1/16W1%
402MF-LF
10K
R59621
2
10K1/16W
1%
402MF-LF
R59651
2
1/16W
10K
MF-LF402
5%
50 51 64 50 51 64
U59774
3
1
5
2
SM-LFLMC7211
U59604
3
1
5
2
LMC7211SM-LF
R59941 2
402MF-LF
5%1/16W
0
R59951 2
0
402
5%
SMC_TPM_PP
MF-LF1/16W
R5931 1 210K1/16W5% MF-LF 402
R5932 1 2MF-LF5% 1/16W
10K402R5933 1 2
1/16W5% MF-LF 402100K
R5934 1 2402MF-LF5% 1/16W
10KR5935 1 210K
1/16W5% MF-LF 402R5936 1 21/16W 402MF-LF5%
100K
R5937 1 21/16W5% MF-LF 402
2.0KONEWIRE_PU
R5938 1 2100K1/16W5% MF-LF 402R5939 1 210K1/16W5% MF-LF 402R5940 1 2
MF-LF 4025% 1/16W10K
R5941 1 2MF-LF1/16W5% 402
10KR5942 1 2
MF-LF 4025% 1/16W10K
R5943 1 2402MF-LF5% 1/16W
10KR5944 1 2
402MF-LF5% 1/16W10K
R5945 1 210K1/16W5% MF-LF 402R5946 1 210K
402MF-LF5% 1/16WR5947 1 21/16W5% MF-LF 402
470KR5948 1 2
402MF-LF5% 1/16W10K
R5930 1 210K1/16W5% MF-LF 402
64 65
Y5920 1
2
CRITICAL
5X3.2-SM20.00MHZ
U5900
5
3
4
1
2
CRITICAL
RN5VD30A-FSOT23-5
R59641
2MF-LF402
1%1/16W
10K
R59631
2
1/16W1%
402MF-LF
16.2K
C59691
2 50V10%0.0022uF
402CERM
R5980 1 210K1/16W5% MF-LF 402R5981 1 2
402MF-LF1/16W10K
5%R5982 1 2402MF-LF5%
10K1/16W
R5983 1 2100K1/16W5% MF-LF 402R5984 1 2100K1/16W5% MF-LF 402
5 50 52
R59001
2
1K
MF-LF402
5%1/16W
R59011
2
1/10W5%
603MF-LF
0
OMIT
R59101
2
1/10W
0
OMIT
5%
603MF-LF
5 45 50 51 54
Q59523
1
2
SOT23-LF2N7002
Q59501
3
2
SOT23-LF2N3906
R59501
2
1/16W5%
402MF-LF
100R59511
2
1/16W5%
402MF-LF
2.2K
50
R59521
2
1/16W5%
402MF-LF
4.7K80
C59201 2
50V5%
402CERM
15pF
C59211 2
5%50VCERM402
15pF
C5901 1
2402
0.01UF16V10%
CERM
SMC Support
86
06051-7023
51
SYNC_MASTER=M1_MLB SYNC_DATE=02/10/2006
TPM_GPIO2
SMC_TPM_GPIO
SMS_INT_LSMC_TPM_RESET_L
SMC_LIDSMC_ONOFF_L
SMC_FWESMC_TX_LSMC_RX_L
PP3V42_G3H
PP3V3_S3PP3V3_S3
SYS_ONEWIRE
SMC_EXTAL
SMC_XTAL
SMC_TMSSMC_BS_ALRT_L
SMC_TDOSMC_TDI
SMC_XDP_TCK_3_3
SMC_TCKSMC_CPU_RESET_3_3_L
SMC_XDP_TDO_3_3
SMC_BATT_CHG_ENSMC_ADAPTER_ENSMC_CASE_OPENSMC_BC_ACOK
VOLTAGE=0V
MIN_LINE_WIDTH=0.4 mmMIN_NECK_WIDTH=0.2 mm
GND_SMC_AVSS
EXCARD_OC_L
PM_SLP_S5_LPM_SUS_STAT_LSMC_EXCARD_CP
SMC_BATT_TRICKLE_EN_L
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.4 mmPP3V3_AVREF_SMCMIN_NECK_WIDTH=0.2 mm
PP3V42_G3H
CPU_PROCHOT_L
PM_THRMTRIP_L
SMC_PROCHOT
SMC_THRMTRIP
SMC_ONOFF_L
PP5V_S5PP3V42_G3H
RSMRST_PWRGDMAKE_BASE=TRUE
P5VS5_PGOOD
P1V71_SMC_REF
P5VS5_COMP_POS
RSMRST_PWRGD
SYS_LED_ILIM
PP5V_S3
SYS_LED_L
SYS_LED_ANODE
SYS_LED_L_VDIV
SMC_SYS_LED_16B
PP3V42_G3H
SMC_MANUAL_RST_L SMC_RST_L
FWH_INIT_LMAKE_BASE=TRUE
FWH_INIT_L
MAKE_BASE=TRUESMC_P1V05S0_ISENSESMC_P1V05S0_ISENSE
PM_EXTTS_LPM_EXTTS_LMAKE_BASE=TRUE
MAKE_BASE=TRUESMC_P1V8S3_ISENSESMC_P1V8S3_ISENSE
MAKE_BASE=TRUETP_SMC_ANALOG_IDTP_SMC_ANALOG_ID
TP_SMC_SYS_LEDMAKE_BASE=TRUE
TP_SMC_SYS_LED
TP_SMC_BATT_VSETMAKE_BASE=TRUE
TP_SMC_BATT_VSET
TP_SMC_SYS_VSETMAKE_BASE=TRUE
TP_SMC_SYS_VSET
MAKE_BASE=TRUETP_SMC_FAN_2_CTLTP_SMC_FAN_2_CTL
MAKE_BASE=TRUETP_SMC_FAN_2_TACHTP_SMC_FAN_2_TACH
MAKE_BASE=TRUETP_SMC_FAN_3_TACHTP_SMC_FAN_3_TACH
TP_SMC_FAN_3_CTLMAKE_BASE=TRUE
TP_SMC_FAN_3_CTL
TP_SMC_XDP_TCKMAKE_BASE=TRUE
TP_SMC_XDP_TCK
TP_SMC_XDP_TMSMAKE_BASE=TRUE
TP_SMC_XDP_TMSMAKE_BASE=TRUETP_SMC_XDP_TDO_LTP_SMC_XDP_TDO_L
TP_SMC_XDP_TRST_LMAKE_BASE=TRUE
TP_SMC_XDP_TRST_L
TP_SMC_P20MAKE_BASE=TRUE
TP_SMC_P20
TP_SMC_P21MAKE_BASE=TRUE
TP_SMC_P21
MAKE_BASE=TRUETP_SMC_P22TP_SMC_P22
MAKE_BASE=TRUETP_SMC_P23TP_SMC_P23
MAKE_BASE=TRUETP_SMC_P26TP_SMC_P26
MAKE_BASE=TRUETP_SMC_P27TP_SMC_P27
MAKE_BASE=TRUETP_SMC_PF0TP_SMC_PF0
TP_SMC_PF1MAKE_BASE=TRUE
TP_SMC_PF1
P0V46_SMC_LSREFVOLTAGE=0.46V
PP3V3_S0
CPU_PROCHOT_L
SMC_PROCHOT_3_3_L
SC_TX_L
SMC_EXCARD_OC_L
SMC_TPM_PP
SC_RX_L
TPM_PP
SMC_RX_L
TPM_GPIO1
SMC_TX_L
79 78 70 66 65 64 60 59
57 56 53
48 43 37 36 34 33 29
80
80
28
66
66
27
68
64
64
68
68
68
26
67
63
63
67
67
67
25
66
62
62
66
66
66
24
65
59
59
65
70
65
65
23
54
58
58
54
67
54
54
22
52
56
56
52
66
52
52
21
51
51
51
51
65
51
51
20
50
45
45
50
64
50
50
19
54
45
41
41
68
59
45
63
45
80
45
52
51 51
17
51
52
52
35
37
37
67
47
52
35
61
35 66
35
51
50 50
14
52
52 50
51
51
27
32
32
50
52
67
52
52
52
67
50
56
22
50
50
50
27
21
46
27 61
27
50
54 54
29 29
54 54
10
51
51
50
59
50
45
50
50
26
27
27
47
50
50
50
50
50
68
50
47
54
6
23
23
47
68
26
51
14
25
26 45
26
21
51 51
28 28
51 51
51 51
51 51
51 51
51 51
51 51
51 51
51 51
51 51
51 51
51
51 51
51 51
51 51
51 51
51 51
51 51
51 51
51 51
51 51
5
51
50
50
59
50
23
50
45
5
50
5
5
5
5
5
5
50
50
5
5
5
5
50
5
50
50
50
43
50
5
50
5
5
5
5
50
50 5
7
7
50
50
5
5 5
5
5
50 50
14 14
50 50
50 50
50 50
50 50
50 50
50 50
50 50
50 50
50 50
50 50
50
51 51
50 50
50 50
50 50
50 50
50 50
50 50
50 50
50 50
50 50
4
7
50
50
50
50
50
59
5
59
5
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
(GPIO15)
NC
516S0384NC
NCNC
J6000
1
10
1112
1314
1516
1718
19
2
20
2122
2324
2526
2728
29
3
30
3132
3334
4
56
78
9
QT500306-L021-9FM-ST-SM
LPCPLUSCRITICAL
LPC+ Debug ConnectorSYNC_DATE=02/10/2006SYNC_MASTER=M1_MLB
051-7023 06
8652
PP3V42_G3HPP5V_S0
FWH_INIT_LPCI_CLK_PORT80_LPC
LPC_AD<2>LPC_AD<3>
INT_SERIRQPM_SUS_STAT_LSMC_TDISMC_TCKSMC_RST_LSMC_NMISMC_RX_L
SV_SET_UP
LPC_AD<0>LPC_AD<1>
BOOT_LPC_SPI_L
LPC_FRAME_LPM_CLKRUN_L
SMC_TMSDEBUG_RST_LSMC_TRST_LSMC_TDOSMC_MD1SMC_TX_L
80 79 78 70 67 66 65
68
61
67
60
66
57
65
56
54
54
51
47
50
42
45
36
59
35
31
51
59
59
59
51
59
59
59
59
27
25
50
50
50
50
50
51
51
51
51
50
50
50
50
50
51
51
51
26
5
21
34
21
21
23
23
50
50
50
50
50
23
21
21
22
21
23
50
26
50
50
50
50
5
4
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
SMBDATA
SMBCLK
ALERT*
OT2*
DXP2
OT1*
DXN
DXP1
GND
VCC
BI
BI
D+
D-
ALERT*/
THM*
SCLK
SDATA
VDD
GND
THM2*
SYM_1
SYM_1
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL
Right-Side/Fin Stack Thermal Sensor
Place near speaker holePlacement note:
518S0226
NC
NC
Placement note:Place in between VRAM
518S0226
NC
NC
Placement note:Place near GPU center
Minimize stubsLayout note:
Place U6150 below and to thePlacement note:
GPU / Heat Pipe Thermal Sensor
left of the speaker hole.
NC
NCNC
these R’s and R1001 & R1002Minimize stubs betweenLayout note:
programatically unstuff those parts to stuff these.
Placement note:Place near CPU center
CPU Back-Up Thermal Diode
R1001 / R1002 are not currently BOMOPTIONed. Can not
to U6100 as possibleKeep all 4 XWs as closePlacement note:
U6100
8
3
2
4
6
5
10
7
9
1
UMAXMAX6695AUB
CRITICALC6120 1
2
HSTHMSNS_HAS
402CERM50V10%
0.0022uF
XW61201 2
SM
XW61211 2
SM
XW61111 2
SM
R61101
2
GPUTHM_A_GPU
402MF-LF1/16W5%0
R61111
2
GPUTHM_A_GPU
402MF-LF1/16W
5%0
R61151 2
1/16W
GPUTHM_A_DIODE
MF-LF
5%
402
0
R61161 2
0
5%1/16WMF-LF402
GPUTHM_A_DIODEQ6115 1
3
2SOT23
2N3904LF
XW61101 2
SM
R61901 2
5%1/16WMF-LF402
0
CPUTHM_DIODE
R61911 2
CPUTHM_DIODE
402
0
5%1/16WMF-LF
Q6190 1
3
2SOT23
2N3904LF
R61521
2
10K
MF-LF402
5%1/16W
5 27 45 50 53
5 27 50 53
R61511
2
1/16W5%
402MF-LF
10K
U61506
2
3
5
8
7
4
1
MSOP
ADT7461
CRITICAL
C6150 1
2
0.1UF
X5R402
10%16V
C61601
2
0.001UF
CERM402
20%50V
R61601 2
1%
499
402MF-LF1/16W
R61611 2
1%
499
MF-LF402
1/16W
C61001
2 10V20%
402CERM
0.1uF
J6120
3
4
1
2
CRITICAL
88460-0201F-RT-SM
J6160
3
4
1
2
88460-0201F-RT-SM
CRITICAL
R61001 2
1/16W5%
402MF-LF
47
C6110 1
250V
0.0022uF
CERM402
10%
116S0004 1 RES,0,1/16W,0402 C6120 HSTHMSNS_NOT
Thermal Sensors
53 86
06051-7023
SYNC_DATE=02/10/2006SYNC_MASTER=M1_MLB
GPUTHMSNS_DX_A_N
CPUTHMSNS_DIO_N THRM_CPU_DX_N
THRM_CPU_DX_PCPUTHMSNS_DIO_P
GPUTHMSNS_DXP1
GPUTHMSNS_DXP2
PP3V3_S0_GPUTHMSNS_R
GPUTHMSNS_DXNSMBUS_SMC_0_S0_SDASMBUS_SMC_0_S0_SCL
PP3V3_S0
RSTHMSNS_THM_L
RSTHMSNS_ALERT_L
SMBUS_SMC_0_S0_SCLSMBUS_SMC_0_S0_SDA
PP3V3_S0
HSTHMSNS_DX_P
ATI_TDIODE_NATI_TDIODE_P
GPUTHMSNS_DX_A_PGPUTHMSNS_DX_A_DIO_P
GPUTHMSNS_DX_A_DIO_N
HSTHMSNS_DX_N
RSFSTHMSNS_D_P
RSFSTHMSNS_D_N
RSFSTHMSNS_D_R_PRSFSTHMSNS_D_R_N
79
79
78
78
70
70
66
66
65
65
64
64
60
60
59
59
57
57
56
56
53
53
51
51
48
48
43
43
37
37
36
36
34
34
33
33
29
29
28
28
27
27
26
26
25
25
24
24
23
23
22
22
21
21
20
20
19
19
53
17
17
50
53
14
14
45
50
10
10
27
27
5
5
10
10
5
5
4
4
5
76
76
5
5
5
IN
OUT
G
S D
D S
G
N-CHN
S
D
G
P-CHN
G
DS
N-CHN
S
D
G
P-CHN
G
DS
D
S
G
D
S
G
D
S
G
D
S
G
OUT
OUTIN OUTIN
OUTIN IN OUT
OUTINOUTIN
OUTIN
OUT
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
CPU Current Sense Filter
Place RC close to SMC
Rthevanin = 4573 ohms
PBUS Voltage Sense Enable & Filter
Place RC close to SMC
SMC_ONOFF_L is low (power buttonEnables PBUS VSense divider when
Enables PBUS VSense divider when high.
1.8V S3 (Memory) Current Sense Filter
1.0A / 1.8W
Place RC close to SMC Place RC close to SMC
Place RC close to SMC Place RC close to SMC
1.05V S0 (NB) Current Sense Filter
Place RC close to SMC
Place RC close to SMC
1.2A / 1.44W 1.05A / 1.1W
FireWire Current Sense Filter
Place RC close to SMC
Battery Current Sense Filter
Place RC close to SMC
Place short near U8400 centerThis half of Q6216 acts as adiode to keep Q6215 frompulling SMC_ONOFF_L low.
DCIN Current Sense Filter
pressed or driven low by SMC)
between PBUS and 3.42Vas a level-shifterThis half of Q6216 acts
R5808 is pull-up
Switches in fixed load on power supplies to calibrate current sense circuits
Current Sense Calibration Circuit
GPU Current Sense Filter
GPU Voltage Sense / Filter
Place short near U0700 center
CPU Voltage Sense / Filter
5 50
R62281
2402MF-LF1/16W5%470K
R62271
2
100K5%
1/16WMF-LF
402
R62151
2
100K
402MF-LF1/16W
1%
50
R62851
2402MF-LF1/16W
1%27.4K
C62851
220%
X5R402
0.22UF6.3V
R62861
2
1%1/16WMF-LF
402
5.49K
Q6216
3
5
4
SOT-3632N7002DW-X-F
Q62166
2
1
SOT-3632N7002DW-X-F
Q6229
6
2
1
SC70-6FDG6332C_NL
Q6229
3
5
4
SC70-6FDG6332C_NL
Q6215
6
2
1
SC70-6FDG6332C_NL
Q6215
3
5
4
SC70-6FDG6332C_NL
Q6220
5
4
1 2 3
MICROFET3X3
CRITICAL
FDM6296Q6221
5
4
1 2 3
MICROFET3X3FDM6296
CRITICALQ6222
5
4
1 2 3
MICROFET3X3
CRITICAL
FDM6296Q6223
5
4
1 2 3
MICROFET3X3
CRITICAL
FDM6296
50
C62591
2402X5R6.3V20%0.22UF
R62591 24.53K
402MF-LF1/16W1%
50
R62701 2
1%
MF-LF402
4.53K
1/16W C62701
220%
X5R402
0.22UF6.3V
60 50
C62751
2 6.3V
0.22UF
402X5R
20%
R62751 24.53K
402MF-LF1/16W1%
70
50
C62801
220%
X5R402
0.22UF6.3V
R62801 2
1%1/16WMF-LF402
4.53K48 48
R62901 24.53K
402MF-LF1/16W1%
C62901
26.3V
0.22UF
402X5R
20%
50
50 51
C62401
2 6.3V
0.22UF
402X5R
20%
R62401 24.53K
402MF-LF1/16W1%
64 50 51
C62351
220%
X5R402
0.22UF6.3V
R62351 2
1/16W1%
MF-LF402
4.53K63
50
C62301
2
0.22UF6.3V
402X5R
20%
R62301 24.53K
402MF-LF1/16W1%
43
XW62591 2
SM
50
R62091 2
1/16WMF-LF
4.53K
1%
402C62091
2
0.22UF20%6.3VX5R402
XW62091 2
SM
R62201
2
1.001%
1/4WMF-LF1206
R62291
2402MF-LF1/16W
5%470K
R62211
2
1.001%
1/4WMF-LF1206
R62221
21206MF-LF1/4W
1%1.82
R62231
21206MF-LF1/4W1%
1.00
SYNC_DATE=01/05/2006SYNC_MASTER=M1_MLB
051-7023 06
8654
Current & Voltage Sensing
ISENSE_CAL_EN_LS5V
PP3V42_G3H
SMC_ONOFF_L PBUSVSENS_PWRBTN_L
SMC_FWIRE_ISENSE
P1V05S0_IOUT
PP1V05_S0PPVCORE_S0_GPUPPVCORE_S0_CPU
GND_SMC_AVSS
PPVCORE_S0_GPU
GND_SMC_AVSS
SMC_CPU_VSENSE
SMC_GPU_VSENSE
CPUVSENSE_IN
GPUVSENSE_IN
GND_SMC_AVSSGND_SMC_AVSSGND_SMC_AVSS
SMC_P1V05S0_ISENSESMC_P1V8S3_ISENSEP1V8S3_IOUTSMC_GPU_ISENSEGPUVCORE_IOUTCPUVCORE_IOUT
GND_SMC_AVSS
SMC_BATT_ISENSELIO_BATT_ISENSE
GND_SMC_AVSS
SMC_DCIN_ISENSEFWPWR_IOUT
PPVCORE_S0_CPU
GND_SMC_AVSS
LIO_DCIN_ISENSE
PP1V8_S3
GND_SMC_AVSS
ISENSE_CAL_EN_L
PP5V_S0
ISENSE_CAL_EN
PM_SLP_S3_L
PPBUS_G3H
PBUSVSENS_EN_L
PPBUS_G3H_VSENSEVOLTAGE=12.6V
SMC_PBUS_VSENSE
GND_SMC_AVSS
SMC_CPU_ISENSE
MIN_NECK_WIDTH=0.20 mmMIN_LINE_WIDTH=0.50 mmCPUVCORE_ISENSE_CAL
MIN_NECK_WIDTH=0.20 mmMIN_LINE_WIDTH=0.50 mmGPUVCORE_ISENSE_CAL
MIN_NECK_WIDTH=0.20 mmMIN_LINE_WIDTH=0.50 mmP1V8S3_ISENSE_CAL
MIN_NECK_WIDTH=0.20 mmMIN_LINE_WIDTH=0.50 mmP1V05S0_ISENSE_CAL
80 79 78 66
70
64
67
34
66
25
65
78
68
24 66
61
70
67
21 63
60
68
66
19 37
57
66
65
17 32
56
64
52
16 31
52
65
63
51
13 29
47
64
61
50
12 76 66
76
66
28
42
50
60
45
11 71 60
71
60
19
36
43
47
35
51
9 70 54
56
70
56
56 56 56
56 56
54
56
16
56
31
39
43
56
27
50
8 66 9
54
66
54
54 54 54
54 54
9
54
14
54
25
32
41
54
26
45
7 54 8
51
54
51
51 51 51
51 51
8
51
5
51
5
23
5
51
5
5
5 5 5
50
5
50
50 50 50
50 50
5
50
4
50
4
5
4
50
SCK
SOWP*
SI
VDD
CE*
HOLD*VSS
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
R6307 AND R6306 SHOULD BE PLACED LESS THAN 100 MILS FORM ICH7M
R6303 SHOULD BE PLACED LESS THAN 100 MILS FORM FLASH ROM ICH7M AND TEKOA(LAN CHIP) R6309 IS NOT NEEDED WHEN SHARING SPI FLASH WITH
C63121
2402CERM10V20%0.1UFR63011
2
1/16W402
5%MF-LF
3.3KR63021
2402
3.3K5%
1/16WMF-LF
C63011
2
22pF
402CERM5%50V
R63071 2
MF-LF402
5%1/16W
47
C63081
2402
22pF50V5%CERM
C63091
25%CERM50V402
22pF
R63031 2
402MF-LF
475%
1/16W
R63061 247
1/16WMF-LF5%
402
C63111
2
22pF
402CERM5%50V
U6301
1
7
6 5
2
8
4
3
OMITCRITICAL
16MBIT
SST25VF016B
SOI
R6308
12
402
5%10K1/16WMF-LF
R6309
12
NOSTUFF
10K5%1/16WMF-LF402
55
SPI BOOTROM
051-7023 06
86
SYNC_MASTER=M1_MLBSYNC_DATE=02/10/2006
PP3V3_S5
SPI_SO_R
SPI_SI_RSPI_SCLK SPI_SCLK_R SPI_SI
SPI_SOSPI_CE_L
SPI_HOLD_LSPI_WP_L
78 66 65 64 62 26 25 24 23 22 11
50 50
50 50
5
22 22
22 22
V+
V-
G
D
SIN
OUT
NC
CNTRL
THRML_PAD
VDD SW
AGNDPGND
FB
VOUT
ININ
OUT
OUT
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
Left ALS circuit has 1K series-R
Left ALS Filter
Keyboard LED Driver
NC
NC
Right ALS Circuit
RTALS_OP_IN and RTALS_OP_COMP need to be matched U6405
3
4
1
5
6
2
MAX4236EUTTSOT23-6-LF
CRITICAL
C6405 1
2CERM402
20%10V
0.1UF
R64061
2
120K
MF-LF402
5%1/16W
C6406 1
2
0.22UF
X5R402
20%6.3V
R64071
2
15.0K
MF-LF402
1%1/16W
R64081
2
1K
MF-LF402
1%1/16W
R64011 2
MF-LF402
1%1/16W
1K
PD64001
2
BS520EOFTH
CRITICAL
R64001
2
5.1M
MF-LF402
5%1/16W
C64001
2
0.01UF
CERM
20%16V
402
Q64083
1
2
2N7002SOT23-LF
6
50
R64101 24.53K
MF-LF402
1%1/16W C64101
2
0.22UF
X5R
20%6.3V
402
U6450
2
3
46
5
7
9
1
8
MM3120LLP
CRITICAL
L6450
1 2
22uH
3.8x3.8x1.5MM
CRITICAL
C6450 1
2
1uF
CERM402
10%6.3V
R64511
2
KBDLED_NOT
10K
MF-LF402
5%1/16W
R64521
2MF-LF
5%1/16W
KBDLED_HAS
10K
402
50
C64551
2
0.22uF20%25VX5R603
R64551
2
25.5
805
1%1/8WMF-LF
45
45
50
C64301
2 6.3V20%
402X5R
0.22UF
R64301 2
1/16W1%
402MF-LF
3.48K
ALS Support
56 86
051-7023 06
SYNC_MASTER=M1_MLB SYNC_DATE=02/10/2006
RTALS_GAIN
RTALS_OP_COMP
PP3V3_S3
ALS_RT_OUT ALS_RIGHT
GND_SMC_AVSS
RTALS_OP_INRTALS_PHOTODIODE
RTALS_GAIN_L
SMC_SYS_KBDLED
PP3V3_S0
KBDLED_RETURN
KBDLED_ANODE
KBDLED_SWPP5V_S0
GND_SMC_AVSS
LTALS_OUT ALS_LEFT
79 78 70
66 65 64 60 59 57 53 51 48 43
37 36
80
34
79
33
78
29
70
28
67
80
27
66
66
26
65
64
25
61
63
24
60
62
23
57
59
22
54
58
21
52
51
20
47
45
19
42
41
17
36
37
56
14
31
56
32
54
10
25
54
27
51
5
5
51
47
5
50
4
4
50
5
G
S D
G
S D
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
Left Fan
518S0293518S0293
NC
NC
NC
NC
Right Fan
R65501
2
1/16W
47K
402MF-LF
5%
R65551 2
5%1/16WMF-LF402
47K
R65601
2402MF-LF1/16W
5%47K
R65651 247K
402MF-LF1/16W5%
R65511
2402MF-LF
5%1/16W
100K
J65505
6
1
2
3
4
CRITICAL
SM-2MT-LFJ65605
6
1
2
3
4
SM-2MT-LF
CRITICAL
Q6560
3
5
4
2N7002DW-X-FSOT-363
R65611
2
100K1/16W
5%
MF-LF402
Q6560
6
2
1
SOT-3632N7002DW-X-F
Fan Connectors
06051-7023
8657
SYNC_MASTER=M1_MLB SYNC_DATE=02/10/2006
FAN_RT_TACHFAN_LT_TACH
PP5V_S0
SMC_FAN_0_TACH
SMC_FAN_0_CTL
PP3V3_S0
FAN_LT_PWM SMC_FAN_1_CTL FAN_RT_PWM
SMC_FAN_1_TACH
PP3V3_S0PP5V_S0
79 79
78 78
70 70
66 66
65 65 64
64
60
60
59
59
57
57
56
56
53
53
51
51
48
48
43
43
80
37 37
80
79
36 36
79
78
34 34
78
70
33 33
70
67
29 29
67
66
28 28
66
65
27 27
65
61
26 26
61
60
25 25
60
57
24 24
57 56
23 23
56 54
22 22
54 52
21 21
52 47
20 20
47 42
19 19
42 36
17 17
36 31
14 14
31 25
10 10
25 5
5 5
5
5 5
4
50
50
4
5 50 5
50
4
4
OUTPUTY
OUTPUTZ
DNC
RSVD
TESTSELF
PS
PARITY
RSVD
RSVD
RSVD
GND PADTHRML
OUTPUTX
VDD
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
NC
NC
+X
+Z (up)
+Y1
Package Top Top-through View
+Y
+Z (dn)
+X
Desired orientation whenDesired orientation when
1
placed on board top-side: placed on board bottom-side:
M1 placement: Bottom-side
C66201
2
0.1uF
CERM402
20%10V
U6620
1
3 12
2
13
145
9
4
6
7
11
10
15
8
QFNKXM52-2050
CRITICALR66212
1402
1/16W5%
MF-LF
10K
R66201
2
10K
MF-LF402
5%1/16W
C66051
2
0.033UF
X7R402
20%10V
C66061
2 10V20%
402X7R
0.033UFC66041
2 10V20%
402X7R
0.033UF
58 86
06051-7023
Sudden Motion Sensor (SMS)SYNC_MASTER=M1_MLB SYNC_DATE=02/10/2006
SMS_ACC_SELFTEST
SMS_ONOFF_L SMS_Y_AXIS
SMS_X_AXIS
PP3V3_S3
SMS_Z_AXIS
80 66 64 63 62 59 56 51 45 41 37 32 27
50 50
50
5
50
IN
BI
BI
BI LAD1
LAD2
LCLK
LFRAME*
LRESET*
LPCPD*
SERRIRQ
LAD0
CLKRUN/GPIO*
PP/GPIO
GPIO_EXPRESS_00
GPIO/SM_DAT
GPIO/SM_CLK
XTALI/32K_IN
TESTBI/BADD/GPIO
TESTI
3V0
3V1
3V2
3VSB
VNC
VBAT
XTALO
GND2
GND3
GND0
GND1
LAD3
BI
BI
IN
IN
BI
IN
IN
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
(INT PD)
GND
NC
NC
VSB
VDD
VDD
VDD
NC
PP
GPIO
CLKRUN*
NC
NC
NC
BASE ADDR = 0X2E/2F
LAYOUT NOTE:PLACE WHERE ACCESSIBLE
LAYOUT NOTE:PLACE R6702-03 WHERE ACCESSIBLE
NOTE: SINCE CURRENT OF VSB IS NOT YET ON SPEC,1/8W (R6704/R6705) IS USED FOR NOW
TESTBI/BADDGPIO2
BASE ADDR = 0X4E/4F
5 23 50 51 52
5 23 50 52
C67001
2
0.1UF10%16VX5R402
C67011
210%16VX5R402
0.1UFC67021
2402X5R16V10%0.1UF
5 21 50 52
C67031
2402X5R16V10%0.1UFR67001
2402MF-LF1/16W5%0
NOSTUFF
5 21 50 52
U6700 101924
5
15
4111825
216
26232017
2122
2816
7
27
98
12
3
1314
TPMTSSOP
OMIT
R67021
2402
10K5%1/16WMF-LF
R67031
2402
10KMF-LF1/16W5%
NOSTUFF
5 23 50 52
R67041 20
5%1/8WMF-LF805
R67051
2
05%1/8WMF-LF805
NOSTUFF
R67981 2
4021/16WMF-LF5%
0
R67991 2
4021/16W
NOSTUFF
05%
MF-LF
5 21 50 52
5 26
50 51
5 21 50 52
34
5 21 50 52
8659
06051-7023
SYNC_MASTER=M1_MLB SYNC_DATE=02/10/2006
TPM
PP3V3_TPM_3VSBVOLTAGE=3.3VMIN_LINE_WIDTH=0.6MMMIN_NECK_WIDTH=0.15MM
TPM_PPTPM_GPIO1
TPM_GPIO2
LPC_AD<3>
PP3V3_S0
PP3V3_S3
PM_CLKRUN_L
TPM_XTALITPM_XTALO
PP3V3_S0
INT_SERIRQPM_SUS_STAT_L
LPC_FRAME_LPCI_CLK_TPM
LPC_AD<2>LPC_AD<1>LPC_AD<0>
TPM_BADD
TPM_RST_L
TPM_LRESET_L
SMC_TPM_RESET_L
79
79
78
78
70
70
66
66
65
65
64
64
60
60
59
59
57
57
56
56
53
53
51
51
48
48
43
43
37
37
36
36
34
34
33
33
29
29
28
28
27
80
27
26
66
26
25
64
25
24
63
24
23
62
23
22
58
22
21
56
21
20
51
20
19
45
19
17
41
17
14
37
14
10
32
10
5
27
5
51
51
51
4
5
35
35
4
TPADVSS
BOOT2
BOOT1
PHASE1
UGATE1
LGATE1
PGND1
ISEN1
UGATE2
PHASE2
LGATE2
PVCCVDDVIN
PGND2
VID6
VID5
VID4
VID2
VID3
VID1
VID0
ISEN2
VSUM
OCSET
VO
DROOP
DFB
VSEN
RTN
DPRSTP*
DPRSLPVR
PSI*
PGD_IN
3V3
CLK_EN*
PGOOD
VR_ON
NTC
VR_TT*
SOFT
RBIAS
VDIFF
FB2
FB
COMP
VW
NC
IN
IN
IN
IN
OUT
IN
OUT
OUT
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
(GND_IMVP6_SGND)
These caps for Q7500
(GND_IMVP6_SGND)
These caps for Q7550
DPRSLPVR DPRSTP* PSI* Operation Mode
(GND)
(IMVP6_VO)
(IMVP6_NTC)
CPU VCore Current Sense
<Ra + Rb>
<Rc>
Vout = Gain * ((2.1 mV/A * Iload) + Voffset)
(IMVP6_FB)
0 1 1 2-Phase CCM
1 1 0 1-Phase DCM
Vout @ 36A = 2.44V-2.60V
Gain = Rc / (Ra + Rb)
Voffset worst-case ~2.3mV (+/- ~1A offset)
Voffset = (Vdrp_offset * Kdroop) + Vamp_offset <Rc>
(IMVP6_VO)
(IMVP6_VSUM)
<Ra>
(IMVP6_ISEN2)
<Rb>
(IMVP6_PHASE2)
(IMVP6_ISEN1)
(IMVP6_PHASE2)
36A max outputVout = Variable
(Inductors limit)
(GND)
0 1 0 1-Phase CCM
1 0 1 1-Phase DCM
(IMVP6_COMP)
(IMVP6_VW)
C75011
2 50V
0.0022UF10%
NO STUFF
CERM402
C75021
2
0.0022UF
NO STUFF
50V10%
CERM402
R75051 2
1%1/16WMF-LF
10K
402
C75051 20.22UF
6.3VX5R402
20%
R75061
2
1/10W
603
1%
MF-LF
3.65K
R75321
2MF-LF402
1/16W1%147KC7532 1
2X7R16V10%
0.015uF
402
C7531 1
2
0.1uF16V10%
X5R402
U7530
48
36
26
47
10
17
45
46
16
11
12
24
23
32
30
25
6
8
3
33
291
34
28
2
31
4
15
7
49
35
27
22
13
37
38
39
40
41
42
43
20
18
44
5
14
21
19
9
ISL6262QFN
OMIT
R75351
2
1/16W1%
1.82K
402MF-LF
R75371
2
4.42K
MF-LF
1%
402
1/16W
C7537 1
250V5%
47pF
402CERM
R75341
2
182K1/16W
402MF-LF
1%
C7535 1
2
330pF
CERM402
10%50V
C75001
220%0.22uF
603X5R25V
C7550 1
2X5R
20%0.22uF
25V
603
R75421
2
9.31K
402
1/16W1%
MF-LF
R75401 23.01K
MF-LF402
1%1/16W
R75411
2
1/16W1%1K
MF-LF402
C7540 1
2CERM402
5%50V
180pF
R75451 2
MF-LF1/16W1%
499
402
5 7 21
5 14 23 86
7
5 64 65
26 33
5 50
5 14 26
Q7501
5
4
1 2 3
CRITICAL
HAT2165HLFPAK
Q7502
5
4
1 2 3
LFPAK
CRITICAL
HAT2165H
Q7500
5
4
1 2 3
HAT2168HLFPAK
CRITICAL
C7512 1
2603
1uF10%16VX5R
R75551 2
1%
MF-LF1/16W
10K
402
Q7550
5
4
1 2 3
HAT2168HLFPAK
CRITICAL
C75551 2
6.3VX5R402
20%
0.22UF
R75561
2
1/10W
603
3.65K1%
MF-LF
Q7552
5
4
1 2 3
LFPAKHAT2165H
CRITICAL
C75521
2
NO STUFF
402
50V10%
CERM
0.0022UF
Q7551
5
4
1 2 3
LFPAKHAT2165H
CRITICAL
C75511
2
NO STUFF
50V10%0.0022UF
CERM402
C7530 1
2CERM6.3V
402
10%1uF
R75301 2
402
10
5%1/16WMF-LF
C7513 1
2603
10%1uF16VX5R
R75361
2
NO STUFF
2.0K1%1/16WMF-LF402
R75331
2MF-LF402
1/16W
1.40K1%
C7533 1
2402
10%470pF
50VCERM
C7544 1
220%
X5R
0.22uF
402
6.3V
R75431
2MF-LF
1%1/16W
11K
402
R75931 230.1K
1%1/16W
402MF-LF
R75911 230.1K
1%
402
1/16WMF-LF
C7528 1
216V
1uF10%
X5R603
C75291
2603
20%6.3VCERM
4.7uF
R75311 2
5%
10
MF-LF1/16W
402R75281 2
MF-LF402
5%1/16W
10
C7546 1
2
0.01uF
402
10%16V
CERM
R75471
2MF-LF
4.02K1%
402
1/16W
R75441
2MF-LF
4991%1/16W
402
C7541 1
2
0.22UF
402X5R
6.3V20%
C7580 1
2
0.0068uF25V
402CERM
10%
C7542 1
2CERM402
10%50V
0.001uF
NO STUFF
R75481
2
3.92K1%
402
1/16WMF-LF
C75431
2402CERM16V10%0.01uF
R75071
2402
5%1
1/16WMF-LF
R75571
2402
1
MF-LF1/16W
5%
C75811
2402
0.01uF16V10%
CERM
NO STUFFC7582 1
210%16V
0.01uF
CERM402
R75811 2
0
402
5%
MF-LF1/16W R7582
1 20
402MF-LF1/16W5%
R75981 2
402
1M
1%1/16WMF-LF
U7595
3
4
1
5
2
LMV2011MFSOT23-5
R75921 2
1%
1M
MF-LF402
1/16W
54
C7595 1
2CERM6.3V10%
402
1uF
R7549
1
2
CRITICAL
0603-LF
10KOHM-5%
C75981 2470pF
50V10%
CERM402
C75921 2
402
470pF
CERM50V10%
C75341
2 CERM50V10%390pF
402
D7500
1
2
B340LBXFSMB
CRITICAL
D7550
1
2
SMBB340LBXF
CRITICAL
R7546
1
2
CRITICAL
402
470K
L7505
1 2
0.36uH
SM-PCC
CRITICAL
L7555
1 2
SM-PCC
0.36uH
CRITICAL
R75941 2
5%
0
1/16W
402MF-LFC75941
2
0.1uF
NO STUFF
20%10VCERM402
XW753012
SM
C7510 1
2
CASED2E-SMPOLY
CRITICAL
33uF20%16V
C7563 1
2
1uF
603
10%16VX5R
C7562 1
2603
10%1uF16VX5R
C7560 1
2
CASED2E-SMPOLY
CRITICAL
33uF20%16V
SYNC_MASTER=M1_MLB SYNC_DATE=02/08/2006
8660
06051-7023
IMVP6 CPU VCore Regulator
IMVP6_COMPIMVP6_VW
P1V5P1V05S0_PGOODCPU_PSI_LIMVP_DPRSLPVR
IMVP6_VSEN_P
IMVP6_DFB
PP5V_S0
PP3V3_S0
PM_DPRSLPVRIMVP6_VID<6>IMVP6_VID<5>IMVP6_VID<4>
IMVP6_VID<0>
CPU_DPRSTP_L
IMVP6_VID<1>
IMVP6_COMP_RC
IMVP6_NTC_R
IMVP6_VDIFF_RC
VOLTAGE=12V
PPVIN_S0_IMVP6_RMIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mmIMVP6_UGATE1
IMVP6_ISEN1
CPUISENS_POS
CPUVCORE_IOUT
CPU_VCCSENSE_N
CPU_VCCSENSE_P
IMVP6_DROOP
IMVP6_PHASE2 MIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mm
IMVP6_BOOT2IMVP6_BOOT1
PP3V3_S0_IMVP6_R
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.25 mm
PP5V_S0_IMVP6_VDDMIN_LINE_WIDTH=0.25 mm
VOLTAGE=5VMIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.5 mmIMVP6_UGATE2 MIN_NECK_WIDTH=0.25 mm
CPUISENS_NEG CPUISENS_NEG_RCPP3V3_S0
IMVP6_VO_R
MIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mmIMVP6_LGATE2
IMVP6_PHASE1 MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.5 mm
IMVP6_NTCIMVP6_VR_TT
PPVCORE_S0_CPU
MIN_LINE_WIDTH=0.5 mmIMVP6_LGATE1 MIN_NECK_WIDTH=0.25 mm
IMVP6_VID<2>
IMVP6_FBIMVP6_FB2
IMVP6_VDIFF
IMVP6_VID<3>
PPBUS_G3H
PPBUS_G3H
IMVP6_VSEN_N
IMVP6_ISEN2
IMVP6_VSUMIMVP6_OCSETIMVP6_VOIMVP6_DROOP
IMVP6_RBIAS
GND_IMVP6_SGND
IMVP6_SOFT
VR_PWRGOOD_DELAYIMVP_VR_ONVR_PWRGD_CK410_L
79
79
78
78
70
70
66
66
65
65
64
64
60
60
59
59
57
57
56
56
53
53
51
51
48
48
43
43
37
37
80
36
36
79
34
34
78
33
33
70
29
29
67
28
28
66
27
27
78
78
65
26
26
70
70
61
25
25
68
68
57
24
24
66
66
56
23
23
64
64
54
22
22
63
63
52
21
21
61
61
47
20
20
60
60
42
19
19
54
54
36
17
17
66 47
47
31
14
14
54 43
43
25
10
10
9 41
41
86
5
5
9
9
9
9
9
86
86
5
8
9
9
5
5
5
86
4
4
5
5
5
5
5
8
8
60
4
5
5
5
4
4
86
60
5
NC4
NC3
NC2
NC1
EXTVCC
FCB
INTVCC
PGOOD
3_3VOUT
RUN_SS2
ITH2
RUN_SS1
ITH1
SW1
TG1
BOOST1
BG1
PLLIN
SENSE1+
SENSE1-
VOSENSE1
BOOST2
TG2
BG2
SW2
PLLFLTR
SENSE2+
VOSENSE2
SENSE2-
THRML_PAD
SGND
PGND
VIN
D
S
G
D
S
G
D
S
G
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
5V S0 FETNOTE: Be aware of pull-ups to VIN on these signals.
<Rb>
5V S3 FET
If unconnected, powers up with VIN.
(L7660 & Q7660 limit)8A max outputVout = 1.49V
<Rb>
<Ra>
Vout = 0.8V * (1 + Ra / Rb)
NC
NC
NCNCNC
NC
Vout = 4.98V
(L7620 limit)8A max output
<Ra>
Connect to RUNSS pins to control outputs.
5V S0 FET
D76241
2
CRITICAL
CMDSH-3SOD-323
C7605 1
2
1uF
CERM402
10%6.3V
C76071
2 16V10%
402
0.01uF
CERM
R76301
2MF-LF1/16W5%
402
1M
C76301
2
0.1uF20%
CERM402
10V
R76251
2
22K5%1/16W
402MF-LF
C7625 1
250V10%
402
470pF
CERM
C76261
2 50V5%
402
47pF
CERM
R76001
2
10
402
1/16WMF-LF
5%
C76001
210%
X5R603
1uF16V
U7600
7
18
17
21
4
20
5 8
10
16
29
32
19
27
2
28 13
30 12
11
6
15
26 14
33
1 9
CRITICAL
QFNLTC3728LXC
D76641
2
CRITICAL
CMDSH-3SOD-323
C7670 1
210V20%
402CERM
0.1uF
C76651
2 CERM50V10%
402
470pFC7666 1
2
100pF
CERM402
5%50V
R76651
2
10K
MF-LF402
5%1/16W
C76621
2 CERM50V
0.001uF
402
10%
C76271
2 CERM
10%50V
402
470pFR76271
2
52.3K1/16W
402MF-LF
1%
C76281
2 25V
402X7R
1000pF10%
NO STUFFR76281
2
10K1/16WMF-LF
402
1%
L7660
1 2
IHLP2525CZ-SM
CRITICAL
2.2uH-14A
R76681
2402
1%1/16WMF-LF
39.2KC7668 1
2
NO STUFF
25V10%
402X7R
1000pF
R76671
2
34.0K1/16W1%
MF-LF402
C7667 1
250V10%
402CERM
470pF
R76701
2MF-LF1/16W
5%
402
1M
C76021
2402
6.3V10%1uF
CERM
C7601 1
2603
6.3V20%
4.7uF
CERM
R76031
2
30K
MF-LF402
5%1/16W
R76041
2
10K
MF-LF402
5%1/16W
C76041
2
0.01uF
CERM402
10%16V
C76411
210%1uF16VX5R603
R76641
2MF-LF402
1/16W
05%
R76241
2MF-LF
0
402
5%1/16W
D76211
2
SMBB240-X-F
CRITICAL
C7661 1
2
NO STUFF
10%25VX7R402
1000pF
C7664 1
2402
0.1uF
CERM10V20%
C76901
2805CERM6.3V20%22UF
C7691 1
2805
CERM6.3V20%
22UF
C76241
2
0.1uF20%10VCERM402
C76211
2402X7R25V10%1000pF
NO STUFF
C7622 1
210%
CERM50V
0.001uF
402
C7652 1
220%
CRITICAL
SMC-LFPOLY6.3V
150uFC7650 1
220%
22UF6.3VCERM805
C76511
2 CERM805
22UF20%6.3V
R76061
2
1/16W5%
402MF-LF
0
P5VP1V5_SKIP
R76071
2
P5VP1V5_CONT
0
MF-LF402
5%1/16W
XW76001 2
SM
C7620 1
216VX5R402
10%0.1uF
R76201
2
1%3.65K
402MF-LF1/16W
C76231
2
0.1uF10%16VX5R402
R76231
2
2.26K1/16WMF-LF
402
1%
C76601
210%16VX5R402
0.1uFR76601
2
1%
402
1/16WMF-LF
3.65K
C7663 1
2402X5R16V10%
0.1uFR76631
2
1%909
402MF-LF1/16W
C76921
2 2V
CASE-D2-SM
20%
POLY
CRITICAL
330uF
Q7661
5 6 7 8
4
1 2 3
CRITICAL
IRF7832PBFSO-8
L7620
1 2
1.8uH-10.4A
CRITICAL
SM
R76691
2MF-LF1/16W
402
1%1.21K
R76291
2
6.04K
402
1/16WMF-LF
1%
C76171
2
22UF
805CERM6.3V20%
NO STUFF
C7616 1
220%
6.3VCERM805
22UF
NO STUFF
C76151 2
10%50VCERM402
0.0022uF
NO STUFF
Q7615
1
2
5
6
3
4
SM-LFFDC638P
NO STUFF
R76151 2
402MF-LF1/16W5%
100K
NO STUFF
Q7610
1
2
5
6
3
4
FDC638PSM-LF
C76101 2
0.0022uF
402CERM
10%50V
R76101 2
MF-LF1/16W5%
402
100K
Q7621
5
4
123
CRITICAL
MICROFET3X3FDM6296
Q7620
5
4
123
MICROFET3X3FDM6296
CRITICALQ7660
5
4
1 2 3
MICROFET3X3FDM6296
CRITICAL
C76401
2
CASED2E-SMPOLY16V20%33uF
CRITICALC7681 1
2
1uF10%16VX5R603
C7680 1
2
CASED2E-SMPOLY
33uF20%16V
CRITICAL
C7696 1
220%
6.3VCERM805
22UF
C76951 2
10%50VCERM402
0.0022uF
Q7695
1
2
5
6
3
4
SM-LFFDC638P
R76951 2100K
402MF-LF1/16W5%
C76971
220%6.3VCERM805
22UF
C76181
2 6.3V20%
POLY
CRITICALNO STUFF
150uF
CASE-D2-LF
SYNC_DATE=02/10/2006SYNC_MASTER=M1_MLB
5V / 1.5V Power Supply
051-7023 06
8661
PP5V_S0
P5VS0_EN2_L_RC
P5VP1V5_FSEL
P5VS5_ITH
VOLTAGE=5VMIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.25 mm
PP5V_S5_P5VP1V5_INTVCC
MIN_LINE_WIDTH=0.6 mm
VOLTAGE=12VMIN_NECK_WIDTH=0.25 mm
PPVIN_S5_P5VP1V5_R
P1V5S0_RUNSS
P5VS5_ITH_RC P1V5S0_ITH_RC
PP5V_S5
P5VS3_EN_L_RC
PP5V_S3
MIN_NECK_WIDTH=0.25 mm P5VS5_BOOSTMIN_LINE_WIDTH=0.6 mm
MIN_LINE_WIDTH=0.6 mmP5VS5_BOOST_RC
MIN_NECK_WIDTH=0.25 mm
PP5V_S5_P5VP1V5_INTVCC
P5VS5_RUNSS
TP_P5V_P1V5_PGOOD
PM_SLP_S4_LS5V
MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.25 mmP1V5S0_BOOST
MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.25 mmP1V5S0_BG
PP5V_S5_P5VP1V5_INTVCC
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.6 mm P5VS5_TG P1V5S0_TG MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.25 mmP1V5S0_SW
P5VS5_BGMIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.25 mm P5VS5_SW
P5VP1V5_FCB
P5VS5_VOSNS
P1V5S0_ITH
PM_SLP_S3_LS5V
P5VP1V5_FSEL
MIN_LINE_WIDTH=0.6 mmVOLTAGE=0V
MIN_NECK_WIDTH=0.25 mm
GND_P5VP1V5_SGND
PP5V_S5
P5VS0_EN_L_RCPM_SLP_S3_LS5V
PP5V_S5
PP5V_S0
PP5V_S5
P1V5S0_VOSNS
PPBUS_G3H
P1V5S0_SNS_R_P
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.6 mm
MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.25 mm
P1V5S0_SNS_R_N
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.6 mmP1V5S0_BOOST_RC
PP1V5_S0_REG
MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.25 mm
P5VS5_SNS_P
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.6 mm
P5VS5_SNS_N
PP5V_S5_REG
80
80
79
79
78
78
70
70
67
67
66
66
65
65
61
61
78
60
60
70
57 70
70
70
57
70
68
56 67
67
67
56
67
66
54 66
66
66
54
66
64
52 65
65
65
52
65
63
47 64
64
64
47
64
60
42 63
63
63
42
63
54
36 61 80
61
61
36
61
47
31 51 66
65
51
65
51
31
51
43
25 46 51
61
46
61
46
25
46
41
5 25 45
65
65
47
25
47
25
5
25
5
4
61
61
5 5
61
5
65
64
61
5
61
5
5
5
4
5
4
66 66
PVINSVIN
SHDN/RT
SYNC/MODE
SW
VFB
ITHPGOOD
PGND SGND
SW
SGND PGND PADTHERM
SVIN PVIN
PGOOD
VFB
ITHSYNC/MODE
RUN/SSRT
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
1.2V S0 FET
(Switcher limit)1.25A max output
<Rb>
(Switcher limit)2.5A max outputVout = 1.205V
Vout = 2.52V<Ra>
1.2V S3 Regulator
<Ra>
<Rb>
<Rc>
Vout = 0.8V * (1 + Ra / (Rb + Rc))
Vout = 0.8V * (1 + Ra / Rb)
2.5V S0 FET
2.5V S3 Regulator
ModeContinuous
If unconnected, powers up with PVIN.Connect RUNSS off-page to control
NOTE: Be aware of pull-up on this signal.
Burst
Continuous
U7700
10
5
8
6
3
1
7
4
2 9
MSOP-LF
CRITICAL
LTC3411
C7703 1
250V
402
100pF
CERM
5%
R77061
2
1/16W1%
402MF-LF
4.99K
C77041
2 50V10%
402CERM
0.0033uF
L7700
1 2
CRITICAL
CDRH4D18-SM
2.2uH-1.32A
C7706 1
250V
402CERM
5%22pF
R77071
2402MF-LF
1%1/16W
10K
R77081
2
1/16W1%
402MF-LF
4.7K C77091
2 6.3V20%22UF
CERM805
C77011
2 6.3V10%
402CERM
1uF
R77001 2
10
MF-LF402
5%1/16W
C77001
220%6.3VX5R603
10UF
R77051
2
1/16W
324K1%
402MF-LF
R77041
2
1/16W5%
402MF-LF
1M
R77011
2
1M
MF-LF402
5%1/16W
XW77001 2
SM
C77561
2
22UF
805
20%6.3VCERM
C7755 1
2
22UF
CERM805
20%6.3V
C77521
2 6.3V20%
805CERM
22UFC7751 1
220%
6.3VCERM
22UF
805
C77501
2
22pF
CERM402
5%50V
R77501
2
47.0K
MF-LF402
1%1/16W
R77511
2
61.9K1/16W
1%
402MF-LF
L7750
1 2
1.0UH-3.48A
CRITICAL
SM-LF
R77521
2
30.9K1/16W
1%
402MF-LF
U7750
3
12
13
2
9 16
5
7
8
110
11
14
15
6
17
4
LTC3412TSSOP-LF
CRITICAL
XW77501 2
SM
R77541
2
1/16W1%
402MF-LF
309KC7757 1
210%
402CERM
470pF50V
R77551
2
NO STUFF
0
MF-LF402
5%1/16W
R77571
2MF-LF
402
5%1/16W
1M
R77561
2
1/16W5%
402MF-LF
0
C7754 1
2
22pF50V5%
402CERM
R77531
2
8.25K1/16W
1%
402MF-LF
C77531
2
0.0022uF50V10%
402CERM
Q77201
2
5
6 3
4
TSOP-LFSI3446DV
C7720 1
2402
CERM
10%0.0022uF
50V
R77201 2100K
MF-LF1/16W5%
402
Q77701
2
5
6 3
4
SI3446DVTSOP-LF
C7770 1
2CERM402
50V10%
0.0022uF
R77701 2
402MF-LF1/16W5%
100K
8662
051-7023 06
2.5V & 1.2V RegulatorsSYNC_MASTER=M1_MLB SYNC_DATE=02/10/2006
PP3V3_S3
P1V2S3_RT
P1V2S3_VFB_DIV
P1V2S3_ITH_RC
P1V2S3_RUNSS
P1V2S3_MODEP1V2S3_ITH
GND_P1V2S3_SGNDVOLTAGE=0VMIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.25 mm
P2V5S3_SHDNRT
P2V5S3_MODE
PP3V3_S5
P2V5S3_EN_L
PP2V5_S3 PP2V5_S0
PM_SLP_S3_LS5V_L P1V2S0_EN_RC
PP1V2_S3 PP1V2_S0
PM_SLP_S3_LS5V_L P2V5S0_EN_RC
P2V5S3_P1V2S3_PGOOD
MIN_LINE_WIDTH=0.5 mm
P2V5S3_SWMIN_NECK_WIDTH=0.25 mm
P1V2S3_SWMIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.25 mm
PP1V2_S3
P2V5S3_VFB
PP2V5_S3_REG
P2V5S3_ITH_RC
P2V5S3_P1V2S3_PGOOD
VOLTAGE=3.3VMIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mm
PPVIN_S3_P2V5S3_SVIN
VOLTAGE=0V
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.38 mm
GND_P2V5S3_SGND
P2V5S3_ITH
P1V2S3_VFB
80 66 64
78
63
66
59
65
58
64
56
55
51
26
77
45
25
76
41
24
66
76
37
23
65
66 69 66
32
22
66 19
70
62 66
70
62
27
41
11
39 17
65
39 65
65
39
65
5
5
5
5
5
5
41
5 5
62
5 5
62
5
66
62
41
PGND
PHASE
UG
LG
PVCC
FCCM
EN
PGOOD
COMP
FSET
ISEN
FB
VO
BOOT
VIN
THRMLPAD
VCC
OUT
G
SD
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
Vout = 1.83V
Keep C7890, R7890,Placement Note:
close to inductor
NC
<Ra>
R7894 and R7897
(P1V8S3_FB)
<Rb>
Vout = 0.6V * (1 + Ra / Rb)
17A max output(Q7820 limit)
1.8V S3 Current Sense
1.8V S0 FET
C7842 1
2CASE-D2-SM
2V20%
POLY
330uFR78211
2
1/16WMF-LF
402
3.32K1%
R78221
2
1.62K
MF-LF402
1%1/16W
L7820
1
2
3
SM1
CRITICAL
1.0uH-20.5
Q7820
5
4
1 2 3
LFPAKHAT2168H
CRITICAL
D7820
1
2CRITICAL
B340LBXFSMB
R78101 23.01K
1/16W1%
402MF-LF
C7802 1
26.3V
2.2UF
603CERM1
20%
C7800 1
2603
CERM1
2.2UF20%
6.3V
C7801 1
2603
10%1uF16VX5R
U7800
13
5
4
6
3
7
9
11
10
16
15
12
17
14
2
1
8
CRITICALQFN
ISL6269
C7807 1
2
15PF
CERM402
5%50V
R78081
2
64.9K
MF-LF402
1%1/16W
C7808 1
250V10%
0.0022uF
402CERM
R78041
2MF-LF
05%
1/16W
NO STUFF
402
R78051
2
1/16W5%
402MF-LF
0
R78061
2
57.6K
MF-LF402
1%1/16W
C7806 1
2
0.01UF
CERM402
10%16V C7840 1
2
22UF20%
CERM6.3V
805
C78411
2805
6.3VCERM
22UF20%
C78431
2CASE-D2-SM
2V
330uF20%
POLY
C7822 1
2
1000pF
402X7R25V10%
NO STUFFC78211
2402
10%1000pF
X7R25V
NO STUFF
XW78001 2
SM
C78331
2603
10%1uF16VX5R
C78321
2603
1uF10%16VX5R
R78021
2
NO STUFF
402MF-LF1/16W5%0
Q7822
5
4
1 2 3
HAT2165H
CRITICAL
LFPAK
Q7821
5
4
1 2 3
CRITICAL
LFPAKHAT2165H
54
C78951
2
1uF
CERM402
10%6.3V
C789812
10%
CERM402
470pF
50VR78981 2
1/16W1%
1M
MF-LF402
U7895
3
4
1
5
2
LMV2011MFSOT23-5
C789212
50VCERM
10%
402
470pF
R78921 2
1%
1M
1/16WMF-LF402
R7897
1
2
10KOHM-5%
CRITICAL
0603-LF
R78961
2
1%1K
402
1/16WMF-LF
R78931 220.0K
MF-LF402
1/16W1%
R78911 2
1/16W
20.0K
402MF-LF
1%
R78941 2
NO STUFF
1/16WMF-LF402
1K
1%
C789012
1uF
402CERM6.3V10%
R78901
2MF-LF
402
1/16W
6491%
C78471
220%
CERM805
6.3V
22UFC7846 1
2CERM
22UF
805
6.3V20%
C78451
2402CERM50V10%0.0022uF
R78451 2
5%1/16WMF-LF402
0
C78091
2
0.22uF
402
6.3V20%
X5R
R78091
2
05%
1/16WMF-LF
402
C7820 1
2402
CERM
10%0.0022uF
50V
NO STUFF
R78201
2
5%
NO STUFF
01/16WMF-LF402
R78461
2402MF-LF1/16W
5%470K
Q7845
5
4
1
2
3FDM6296MICROFET3X3
CRITICAL
C78301
2
CRITICAL
33uF20%16VPOLYCASED2E-SM
C78311
2
CRITICAL
16V20%33uF
POLYCASED2E-SM
SYNC_DATE=02/10/2006SYNC_MASTER=M1_MLB
1.8V Supply
051-7023
63 86
06
PP5V_S5PPBUS_G3H
PP1V8_S3
P1V8S0_EN
TP_P1V8S3_PGOOD
PM_SLP_S4_LP1V8S3_FCCM
MIN_LINE_WIDTH=0.25 mmP1V8S3_BOOT_R
MIN_NECK_WIDTH=0.25 mm
P1V8S3_BOOTMIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.25 mm
P1V8S3_FB_RC
P1V8S3_LGMIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.25 mm
P1V8S3_FSET
P1V8S3_COMP_R
GND_P1V8S3_SGND
P1V8S3_COMPP1V8S3_ISEN
P1V8ISENS_NTC
P1V8ISENS_NEG
P1V8S3_IOUT
P1V8ISENS_POS
PP3V3_S3
P1V8S3_FB
P1V8ISENS_RC
PPBUS_G3H
PP1V8_S0
P1V8S0_EN_RC
PP1V8_S3
PP5V_S3_P1V8S3_VCC
VOLTAGE=5V
MIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.6 mmP1V8S3_UG
P1V8S3_PHASE
SWITCH_NODE=TRUE
MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.25 mm
78
80
78
70
66
66
70
66
68
63
64
68
63
66
54
62
66
54
70
64
37
59
64
37
67
63
32
58
63
32
66
61
31
56
61
31
65
60
29
65
51
60
29
64
54
28
50
45
54
28
61
47
19
47
41
47
19
51
43
16
46
37
43
16
46
41
14
41
32
41
66
14
25
5
5
23
27
5
65
5
5
4
4
65
65
5
5
5
5
4
5
4
PGND
PHASE
UG
LG
PVCC
FCCM
EN
PGOOD
COMP
FSET
ISEN
FB
VO
BOOT
VIN
THRMLPAD
VCC
OUT
D
S
G
D
S
G
D
S
G
PGND
PHASE
UG
LG
PVCC
FCCM
EN
PGOOD
COMP
FSET
ISEN
FB
VO
BOOT
VIN
THRMLPAD
VCC
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
10A max output(Q7970 & L7970 limit)
3.3V S0 FET
1.05V S0 Regulator
1.05V Current Sense
4.5A max output
3.3V S3 FET
Vout = 3.32V
<Rb>
<Ra>
(L7920 limit)
3.3V S5 Regulator
Vout = 1.05V
Placement Note:Keep C7990, R7990,R7994 and R7997close to inductor
NC
<Ra>
(P1V05S0_FB)
<Rb>
Vout = 0.6V * (1 + Ra / Rb)
Vout = 0.6V * (1 + Ra / Rb)
C7951 1
2603X5R
10%1uF16V
U7950
13
5
4
6
3
7
9
11
10
16
15
12
17
14
2
1
8
QFNISL6269
CRITICAL
C7957 1
250V5%
402CERM
15PF
C7958 1
2CERM402
20%16V
0.01uF
R79581
2MF-LF402
1%1/16W
30.9K
R79541
2
1/16W5%
MF-LF
0
NO STUFF
402
R79551
2
0
MF-LF402
5%1/16W
R79561
2
57.6K1%
402MF-LF1/16W
C7956 1
216V10%
402CERM
0.01UFQ7971
5 6 7 8
4
1 2 3
SO-8
CRITICAL
IRF7832PBF
C79891
2POLY
20%330uF2V
CASE-D2-SM
C79811
2603
1uF10%16VX5R
D7920
1
2
SMB
CRITICAL
MBRS140XXG
C79301
2603
10%1uF16VX5R
R79021
2
NO STUFF
1/16WMF-LF402
5%0
R79521
2402
0
MF-LF
5%1/16W
NO STUFF
C799812
50V
470pF
CERM
10%
402C79951
2
1uF
CERM402
10%6.3V
R79981 2
402MF-LF1/16W
1M
1%
U7995
3
4
1
5
2
LMV2011MFSOT23-5
C799212
50V
470pF
402CERM
10%
R79921 2
402MF-LF1/16W
1M
1%
R7997
1
2
0603-LF
10KOHM-5%
CRITICALR79961
2402MF-LF1/16W
1K1%
R79931 2
1%1/16W
402MF-LF
20.0K
C799012
10%6.3VCERM402
1uF
R79911 2
MF-LF
1%1/16W
20.0K
402
R79941 2
1%
1K
402MF-LF1/16W
NO STUFF
R79901
2
1%1/16W
402MF-LF
649
54
R79491 2
0
402
5%
MF-LF1/16W
C79491
220%16V
0.01uF
NO STUFF
402CERM
C79201
2402
10%25VCERM
0.0047uF
R792012
0
1/16WMF-LF402
5%
C79471 2
402CERM
10%
0.0047uF
25V
Q7947
1
2
5
6
3
4
SM-LFFDC638P
R79471 2
402MF-LF1/16W5%
100K
C79451 2
0.0022uF
402CERM50V10%
Q7945
1
2
5
6
3
4
SM-LFFDC638P
R79451 2
402MF-LF1/16W5%
100KR79091
2402MF-LF1/16W
05%
C79091
220%6.3VX5R402
0.22uF
R79591
2402MF-LF1/16W
5%0 C79591
2
0.22uF
402X5R6.3V20%
C7970 1
2402
CERM
10%0.0022uF
50V
NO STUFF
R79701
2402MF-LF1/16W
05%
NO STUFF
Q7920
5
4
1 2 3
MICROFET3X3FDM6296
CRITICAL
Q7921
5
4
1 2 3
MICROFET3X3FDM6296
CRITICAL
Q7970
5
4
1 2 3
MICROFET3X3
CRITICAL
FDM6296
C79311
2
33uF20%16V
CRITICAL
POLYCASED2E-SM
R79101 2
1/16W1%
402
5.62K
MF-LF
C79801
2 16V20%33uF
CRITICAL
POLYCASED2E-SM
C79421
2SMC-LFPOLY
20%150uF6.3V
C7902 1
2603
CERM1
20%6.3V
2.2UF
C7921 1
2
1000pF
402X7R25V10%
NO STUFF
XW79001 2
SM
C7900 1
2
2.2UF
603
20%6.3VCERM1
C7901 1
210%
603X5R16V
1uF
U7900
13
5
4
6
3
7
9
11
10
16
15
12
17
14
2
1
8
ISL6269QFN
CRITICAL
C7907 1
210%
470pF
CERM402
50V
C7908 1
2
0.022uF
CERM-X5R
10%16V
402
R79041
2
NO STUFF
MF-LF1/16W5%0
402
R79081
2
51.1K
402MF-LF1/16W1%
R79051
2
5%
402MF-LF
01/16W
R79061
2
1/16WMF-LF
1%
402
57.6KC7906 1
216V10%
402CERM
0.01UF
C7941 1
2
22UF
805
6.3VCERM
20%
C79401
2805
22UF20%6.3VCERM
R79211
2
3.32K
MF-LF402
1%1/16W
R79221
2MF-LF
402
1%1/16W
732
L7920
1 2
4.7uH
CRITICAL
IHLP
C7952 1
2
2.2UF
CERM1603
20%6.3V
C7986 1
220%
22UF
CERM6.3V
805
C79851
2805
22UF20%6.3VCERM
R79711
2
1/16W1%
402MF-LF
3.32K
R79721
2
1/16W1%
MF-LF
4.42K
402
L7970
1
2
3
SM
1.53uH
CRITICAL
R79601 2
402MF-LF
1%1/16W
2.8K
C7971 1
2
1000pF
402X7R25V10%
NO STUFF
XW79501 2
SM
C7950 1
2
2.2UF
CERM1603
20%6.3V
051-7023
64 86
06
SYNC_DATE=02/10/2006SYNC_MASTER=M1_MLB
3.3V / 1.05V Power Supplies
PPBUS_G3H
P3V3S5_FSET
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.25 mm
VOLTAGE=5V
PP5V_S5_P3V3S5_VCC
P3V3S5_ISEN
P3V3S5_PHASE
SWITCH_NODE=TRUE
MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.6 mmP3V3S5_LG
MIN_NECK_WIDTH=0.25 mm
PP3V3_S5_REG
P3V3S5_UGMIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.25 mmP3V3S5_BOOT
MIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.25 mmP3V3S5_EN_RC
P3V3S5_FCCM
GND_P3V3S5_SGND
P1V05S0_IOUT
P1V05S0_FB
P1V05ISENS_NEG
P1V05ISENS_POS
PP3V3_S0
P1V05S0_FB_RC
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.25 mm
VOLTAGE=5V
PP5V_S0_P1V05S0_VCC
P1V05S0_FCCMP1V5P1V05S0_PGOOD
PM_SLP_S3_L
GND_P1V05S0_SGND
P1V05S0_FSET
P1V05S0_COMP
PP5V_S5
P1V05S0_COMP_R
P1V05S0_ISEN
PP5V_S5
P3V3S5_FB_RC
PP3V3_S0
PP3V3_S5
P3V3S5_COMP
P5VS5_PGOOD
RSMRST_PWRGD
PM_SLP_S4_LS5V P3V3S3_EN_L_RC
PP3V3_S3
P3V3S5_COMP_R
PP3V3_S5
P1V05ISENS_NTC
MIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.25 mm
P3V3S5_BOOT_R
P1V05S0_LGMIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.6 mmP1V05S0_UG
P1V05S0_BOOT_RMIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.25 mm
P1V05S0_PHASE
SWITCH_NODE=TRUE
MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.25 mmP1V05S0_BOOT
PP1V05_S0
P1V05ISENS_RC
PPBUS_G3H
P3V3S5_FB
P3V3S0_EN_L_RCP3V3S0_EN_L
79
79
78
78
70
70
66
66
65
65
64
64
60
60
59
59
57
57
56
56
53
53
51
51
48
48
43
43
37
37
36
36
34
34
33
33
29
29
66
28
28
54
78
27
27
80
34
78
70
26
26
78
66
78
25
70
68
25
25
66
63
66
24
68
66
24
70
70
24
65
62
65
21
66
64
23
67
67
23
64
59
64
19
64
63
22
66
66
22
62
58
62
17
63
61
21
65
65
65
21
55
56
55
16
61
60
20
54
64
64
20
26
51
26
13
60
54
19
50
63
63
19
25
45
25
12
54
47
17
43
61
61
17
24
41
24
11
47
43
14
39
51
51
14
23
37
23
9
43
41
10
65
32
46
46
10
22
32
22
8
41
5
5
60
23
25
25
5
11
65
51
65
27
11
7
5
4
5
66
4
5
5
5
5
5
5
4
5
5
51
50
61
5
5
5
4
65
FB
BIAS
SWSHDN*
NC
VIN BOOST
GND
G
D
S
V-
V+
OUT
THRML
V2V1
RST*
V3
V4
VADJ1
VADJ2
GND PAD
IN
G
D
S
G
D
S
OUT
G
D
S
G
D
S
G
D
S
G
D
S
G
D
S
G
D
S
IN
IN
IN
IN
IN
IN
IN
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
0.89V Reference
3.425V "G3Hot" SupplySupply needs to guarantee 3.31V delivered to SMC VRef generator
State
Soft-Off (S5)
Sleep (S3)
Run (S0)
Battery Off (G3Hot) 01
11
SMC_PM_G2_ENABLE
00
11
PM_SLP_S4_L
0001
PM_SLP_S3_L
(Switcher limit)200mA max outputVout = 3.425
<Ra>
<Rb>
NC
Vout = 1.25V * (1 + Ra / Rb)
before enabling GPU VCore to supportremoving ethernet power in battery sleep.
Ensure 1.2V and 2.5V S3 supplies are up
by ethernet power control circuit.2.5V S3 and 1.2V S3 supplies are controlled
5V Enable has pull-up to PBUS
(PM_SLP_S3_L)
(P5VS5_PGOOD)
(PM_SLP_S4_L)
PowerPlay is changingdeassert while GPU
GPU core voltage.
Need to ensure that
Power Control Signals
LTC2908 sources 6uA at 5.0V
and 3.3V level-shifter.
1.5V Comp threshold set to 1.32V (88%)
LTC2908 threshold is 95% (4.75V, 3.135V, 2.375V, 1.71V, 1.14V, 0.86V)
ISL6269 undervoltage threshold 81-87% (0.85 - 0.91V)NOTE: R8065 acts as 10K pull-up for PGOOD signal
Reports when 1.5V S0 and 1.05V S0 are in regulation
ISL6269 PGOOD does not
1.8V Enable has pull-up to PBUS
Unused PGOOD Signals
3.3V rise after VCore is up.GPU requires 1.2V, 1.8V, 2.5V and
1.5V Enable has pull-up to PBUS 1.5V / 1.05V PWRGD Circuit
Reports when 5V S0, 3.3V S0, 2.5V S0, 1.8V S0, 1.2V S0 and 0.9V S0 are in regulation
Other S0 Rails PWRGD Circuit
R8076 serves as pull-down
U8000
7
6
8
4
2
1 5
3
TSOT23-8
CRITICAL
LT3470
R80601 2
0
402
5%1/16WMF-LF
NO STUFF
Q80563
5
4
2N7002DW-X-FSOT-363
C8000 1
2
10uF
X5R1206
10%25V
C80151
2
22UF
CERM805
20%6.3V
R80111
2
200K
MF-LF402
1%1/16W
R80651
2
1/16W5%
402MF-LF
10K
C8060 1
210V20%
402CERM
0.1uF
U80604
3
1
5
2
SM-LFLMC7211
U8080
3
2
1
4
5SC70MC74VHC1G08
C8080 1
2402
CERM10V
0.1UF20%
5 60 64 65
C80711
2 10V20%
402CERM
0.1uF
U8070
1
2
9
5 4
7
3
6
8
LLPLTC2908
CRITICAL
R80761
2
549K1%
MF-LF402
1/16W
R80631
2
1/16W1%
402MF-LF
4.99KR80611
2
1/16W1%
402MF-LF
27.4K
R80641
2
1/16W1%
402MF-LF
10KR80621
2
1/16W1%
402MF-LF
10K
C8070 1
210V20%
402CERM
0.1uF
R80721
2
124K1/16W1%
402MF-LF
R80731
2
100K1/16W1%
402MF-LF
5 60 64 65
R80741
2
1/16W1%
402MF-LF
68.1K
R80751
2
1/16W1%
402MF-LF
100K
R80511
2
1/16W5%
402MF-LF
10KR80501
2
1/16W5%
402MF-LF
10K
Q80576
2
1
SOT-3632N7002DW-X-F
Q80506
2
1
SOT-3632N7002DW-X-F
26 50
R80541
2
1/16W5%
402MF-LF
100K
Q80573
5
4
SOT-3632N7002DW-X-F
R80101
2
348K
MF-LF402
1%1/16W
R80551
2
5%
402MF-LF
10K1/16W
Q80556
2
1
SOT-3632N7002DW-X-F
Q80553
5
4
2N7002DW-X-FSOT-363
L8010
1 2
CRITICAL
33uH
CDPH4D19F-SM
Q80593
5
4
2N7002DW-X-FSOT-363
R80591
2
470K
MF-LF402
5%1/16W
Q80596
2
1
2N7002DW-X-FSOT-363
Q80503
5
4
SOT-3632N7002DW-X-F
62 65 70
C8010 1
2
22pF
CERM402
5%50V
R80561
2
1/16W5%
402
100K
MF-LF
5 23 32 39 43 50 54
64 65
R80571
2
1/16W5%
402MF-LF
100K
5 23 41 46 47 50 63
65
R80581
2
1/16W5%
402MF-LF
100K
51 64 65
50
C8005 1
2
0.22uF
X5R402
20%6.3V
62 65
62 65 R80531
2MF-LF402
5%1/16W
10K
R80521
2
10K
MF-LF402
5%1/16W
3.3V G3Hot Supply & Power ControlSYNC_MASTER=M1_MLB
06051-7023
65 86
SYNC_DATE=02/10/2006
S0PGOOD_PWROK
PP3V3_S0
MAKE_BASE=TRUEP2V5S3_P1V2S3_PGOOD
PP3V42_G3H
PP5V_S5
PM_SLP_S3_LS5V_LMAKE_BASE=TRUE
MAKE_BASE=TRUEP3V3S0_EN_L
TP_P1V8S3_PGOOD TP_P1V8S3_PGOODMAKE_BASE=TRUE
TP_P5V_P1V5_PGOOD TP_P5V_P1V5_PGOODMAKE_BASE=TRUE
P1V8S0_ENMAKE_BASE=TRUEP1V8S0_EN
PM_SLP_S3_LS5V_LPM_SLP_S3_LS5V_L
P3V3S0_EN_L
MAKE_BASE=TRUEPM_SLP_S3_LS5V
P1V5P1V05S0_PGOOD
S0PGOOD_1V2_DIV
S0PGOOD_0V9_DIV
P1V5S0_COMP_POS
P1V0_P1V5PG_REF
P1V5S0_PGOOD
P1V5P1V05S0_PGOOD
ALL_SYS_PWRGD
PP3V3_S5
PP5V_S0
MAKE_BASE=TRUEP1V5P1V05S0_PGOOD
PP3V3_S0
PP1V8_S0PP2V5_S0
PP1V2_S0PP0V9_S0
PP1V5_S0
PM_SLP_S3_LS5V_L
MAKE_BASE=TRUEP5VS5_PGOOD
P2V5S3_P1V2S3_PGOODP2V5S3_P1V2S3_PGOOD
SMC_PM_G2_EN
SMC_PM_G2_EN_L
P5VS5_PGOOD
PM_SLP_S4_LPM_SLP_S4_LPM_SLP_S4_L
PM_SLP_S4_LS5VPM_SLP_S4_LS5V
MAKE_BASE=TRUEGPUVCORE_EN GPUVCORE_EN
PM_SLP_S3
PM_SLP_S3_LPM_SLP_S3_LPM_SLP_S3_LPM_SLP_S3_L
PM_SLP_S3_LS5VPM_SLP_S3_LS5V
PM_SLP_S4_L
MAKE_BASE=TRUE
MAKE_BASE=TRUEPM_SLP_S4_LS5V
MAKE_BASE=TRUE
PM_SLP_S3_L
PP3V42_G3H
P5VS5_RUNSS
PP5V_S5
P1V5S0_RUNSS
PP3V42_G3H
P3V42G3H_FB
MIN_NECK_WIDTH=0.25 mmSWITCH_NODE=TRUE
P3V42G3H_SWMIN_LINE_WIDTH=0.5 mm
PPDCIN_G3HP3V42G3H5_BOOST
79
79
78
78
70
70
66
66
65
65
64
64
60
60
59
59
57
57
56
56
53
53
51
51
48
48
43
43
37
37
36
80
36
34
79
34
33
78
33
29
70
29
28
67
28
27
66
27
26
68
61
26
68
68
25
67
78
60
25
67
67
24
66
70
66
57
24
66
66
70
66
23
65
67
64
56
23
47
65
67
65
22
54
66
62
54
22
25
65
65
65
65
54
66
54
21
52
65
55
52
21
24
65
65
65
64
64
64
64
52
65
52
20
51
64
26
47
20
77
19
63
63
63
54
54
54
54
51
64
51
19
50
63
25
42
19
76
17
50
50
50
50
50
50
50
50
63
50
17
45
61
24
36
17
66
76
16
47
47
47
43
43
43
43
45
61
45
14
35
51
65
23
31
14
62
69
66
13
46
46
46
39
39
39
39
65
65
35
51
35
68
10
27
46
70 70
70
61
22
25
10
66
19
66
31
9
65
41
41
41
65
65
32
32
32
32
61
61
65
27
46
27
67
5
65
26
25
65
65
65 65
65 65
65 65
65
65
65
47
11
5
5
63
17
62
30
8
64
23
23
23
64
64
70 70
23
23
23
23
47
47
64
26
61
25
61
26
66
4
62
5
5
62
64
63 63
61 61
63 63
62
62
64
5
5
4
4
5
5
5
5
5
51
5
5
5
61
61
65 65
5
5
5
5
5
5
61
5
5
5
5
5
5
4
JUMPER
JUMPER
JUMPER
JUMPER
JUMPER
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
"S3AC" rail is ON in S3 on AC, OFF in S3 on battery
XW81151 2
PLACEMENT_NOTE=Place on top-side of boardOPEN
R81331 2
805
5%1/8WMF-LF
0
PLACEMENT_NOTE=Place on top-side of board
XW81331 2
OPENPLACEMENT_NOTE=Place on top-side of board
XW81501 2
OPENPLACEMENT_NOTE=Place on top-side of board
XW81191 2
PLACEMENT_NOTE=Place on top-side of boardOPEN
XW81251 2
PLACEMENT_NOTE=Place on top-side of boardOPEN
66
06051-7023
86
Power AliasesSYNC_DATE=12/19/2005SYNC_MASTER=M1_MLB
PP1V8_S3MIN_LINE_WIDTH=0.6 mm
VOLTAGE=1.8VMAKE_BASE=TRUE
MIN_NECK_WIDTH=0.25 mm
PP1V8_S3
MIN_LINE_WIDTH=0.38 mm
VOLTAGE=0.9V
PP0V9_S0MIN_NECK_WIDTH=0.25 mm
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mmVOLTAGE=1.05V
PP1V05_S0
MAKE_BASE=TRUE
PP1V05_S0PP1V05_S0
PP1V2_S0MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.25 mmVOLTAGE=1.2VMAKE_BASE=TRUE
PP1V8_S0MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.25 mm
MAKE_BASE=TRUEVOLTAGE=1.8V
PP2V5_S3_REGMIN_LINE_WIDTH=0.6 mm
VOLTAGE=2.5VMAKE_BASE=TRUE
MIN_NECK_WIDTH=0.3 mm
PPVCORE_S0_GPU
MAKE_BASE=TRUEVOLTAGE=1.2VMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.6 mm
PP1V5_S0
PP1V5_S0
PP3V3_S0 PP3V3_S0
PP3V42_G3H
VOLTAGE=3.425VMAKE_BASE=TRUE
MIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.2 mm
PP3V42_G3H
PP3V3_S5
PP3V3_S5
PP3V42_G3H
PP3V42_G3HPP3V42_G3H
PP3V3_S3AC
PPBUS_G3HPPBUS_G3HPPBUS_G3HPPBUS_G3H
PP3V3_S5
PP3V42_G3H
PP1V8_S0
PP2V5_S3_REG
PP3V42_G3H
PP3V3_S3
PP3V3_S5PP3V3_S5
PP3V3_S5PP3V3_S5PP3V3_S5
PP3V3_S5PP3V3_S5PP3V3_S5PP3V3_S5
PP3V42_G3H
PP3V42_G3H
PP3V42_G3HPP3V42_G3H
PP3V42_G3H
PP1V05_S0PP1V05_S0PP1V05_S0
PP3V3_S5_REG
MAKE_BASE=TRUEVOLTAGE=3.3V
MIN_LINE_WIDTH=0.4 mmMIN_NECK_WIDTH=0.25 mm
PP1V2_S3
VOLTAGE=1.2V
MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.22 mm
MAKE_BASE=TRUEPP1V2_S3
PP1V5_S0PP1V5_S0PP1V5_S0
PP1V5_S0PP1V5_S0PP1V5_S0PP1V5_S0
PP1V5_S0PP1V5_S0PP1V5_S0
PP1V8_S3PP1V8_S3PP1V8_S3
PP1V8_S0_GPU
PP2V5_S0PP2V5_S0PP2V5_S0PP2V5_S0
PPVCORE_S0_GPUPPVCORE_S0_GPU
PPDCIN_G3H
PP1V2_S0
PP1V5_S0_REG
PP2V5_S0
PPVCORE_S0_GPU
PPDCIN_G3H
PP1V05_S0
PP1V2_S3
MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.4 mm
MAKE_BASE=TRUEVOLTAGE=18.5V
PPDCIN_G3H
PP1V5_S0_REGMIN_NECK_WIDTH=0.4 mmMIN_LINE_WIDTH=0.6 mm
VOLTAGE=1.5VMAKE_BASE=TRUE
PP5V_S5_REG
VOLTAGE=5V
MIN_LINE_WIDTH=0.6 mm
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.3 mm
PPBUS_S5_FW_FETPPBUS_S5_FW_FET
PP5V_S5PP5V_S5PP5V_S5PP5V_S5PP5V_S5
PP5V_S5PP5V_S5
PP5V_S5
PP5V_S5PP5V_S5
PP5V_S5
PP5V_S3PP5V_S3
PP5V_S5_REG
MIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.3 mm
MAKE_BASE=TRUEVOLTAGE=33V
PPBUS_S5_FW_FET
PPBUS_G3H
PPBUS_G3H
PPBUS_G3HPPBUS_G3HPPBUS_G3HPPBUS_G3HPPBUS_G3H
PPBUS_G3H
VOLTAGE=12.6VMAKE_BASE=TRUE
MIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mm
PP3V3_S5PP3V3_S5
PP5V_S3
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.6 mm
MAKE_BASE=TRUE
PP5V_S5
VOLTAGE=5V
PP5V_S0
VOLTAGE=5VMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.6 mm
MAKE_BASE=TRUE
PP5V_S0PP5V_S0
PP5V_S0PP5V_S0PP5V_S0
PP5V_S0PP5V_S0PP5V_S0
PP5V_S0PP5V_S0
PP5V_S0PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S3PP5V_S3
MIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mm
PP5V_S3
MAKE_BASE=TRUEVOLTAGE=5V
PPVCORE_S0_CPU
PPBB_S0_GPU
PNBB_S0_GPU
PPVCORE_S0_CPU
PPBB_S0_GPU
PNBB_S0_GPU
MIN_NECK_WIDTH=0.2 mm
PPVCORE_S0_CPU
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.5 mm
VOLTAGE=1.1V
MIN_NECK_WIDTH=0.25 mmVOLTAGE=1.9V
PPBB_S0_GPU
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.25 mm
PP3V3_S0MIN_LINE_WIDTH=0.5 mm
MAKE_BASE=TRUEVOLTAGE=3.3VMIN_NECK_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.5 mm
MAKE_BASE=TRUEVOLTAGE=3.3V
PP3V3_S0_GPU
PP3V3_S0PP3V3_S0
PP3V3_S0PP3V3_S0PP3V3_S0PP3V3_S0
PP3V3_S0PP3V3_S0
PP3V3_S0
PP3V3_S0PP3V3_S0
PP3V3_S0PP3V3_S0
PP3V3_S0
PP3V3_S0_GPUPP3V3_S0_GPU
PP3V3_S0_GPUPP3V3_S0_GPU
PP3V3_S0_GPUPP3V3_S0_GPUPP3V3_S0_GPU
PP3V3_S3
PP1V05_S0
PP0V9_S0
PP3V3_S0PP3V3_S0PP3V3_S0PP3V3_S0PP3V3_S0PP3V3_S0PP3V3_S0
PP3V3_S0PP3V3_S0
PP3V3_S0PP3V3_S0PP3V3_S0PP3V3_S0PP3V3_S0PP3V3_S0PP3V3_S0
PP3V3_S0
PP3V3_S0PP3V3_S0
PP3V3_S0PP3V3_S0
PP3V3_S0PP3V3_S0
PP1V2_S0
PP1V05_S0
PP1V05_S0
PP2V5_S3MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.25 mmVOLTAGE=2.5VMAKE_BASE=TRUE
PP2V5_S0MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.25 mm
MAKE_BASE=TRUEVOLTAGE=0
PP2V5_S0
PP2V5_S3
PP1V8_S0_GPU
PP2V5_S3
PP1V8_S0_GPU
PP1V8_S0_GPUMIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.25 mm
MAKE_BASE=TRUEVOLTAGE=1.8V
PP1V8_S3
PP1V8_S3
PP1V5_S0
PP1V5_S0
PP1V5_S0PP1V5_S0PP1V5_S0
PP1V5_S0MIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mm
MAKE_BASE=TRUEVOLTAGE=0
PP1V2_S0PP1V2_S0PP1V2_S0
PP1V2_S3
PP3V3_S5_REG
PP3V42_G3H
PP0V9_S0
PP3V3_S3PP3V3_S3
PP3V3_S3PP3V3_S3PP3V3_S3PP3V3_S3PP3V3_S3PP3V3_S3PP3V3_S3PP3V3_S3PP3V3_S3PP3V3_S3
MIN_NECK_WIDTH=0.2 MMVOLTAGE=3.3VMAKE_BASE=TRUE
PP3V3_S3MIN_LINE_WIDTH=0.5 MM
MAKE_BASE=TRUEVOLTAGE=3.3V
MIN_LINE_WIDTH=0.4 mmPP3V3_S5MIN_NECK_WIDTH=0.25 mm
PP3V3_S3ACMAKE_BASE=TRUEVOLTAGE=3.3VMIN_NECK_WIDTH=0.22 mmMIN_LINE_WIDTH=0.38 mmPP3V3_S3AC
PNBB_S0_GPUMIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.25 mmVOLTAGE=-0.7VMAKE_BASE=TRUE
MIN_NECK_WIDTH=0.2 mm
GNDMIN_LINE_WIDTH=0.5 mm
VOLTAGE=0V
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45
45
45
45
25
19
19
66
11
11
11
69
71
16
16
17 17
45
45
24
24
45
45
45
47
47
47
47
24
45
45
41
24
24
24
24
24
24
24
24
24
45
45
45
45
45
11
11
11
16
16
16
16
16
16
16
16
16
16
19
19
19
75
65
65
65
65
71
71
68
69
65
71
68
11
68
66 66
61
61
61 61
61
61
61
66
66
66
47
47
47
47
47
24
24
66
61
36
36
36
36
36
36
36
36
66
66
60
60
17
17
17
17
17
17
17
17
17
17
17
17
41
11
66
17
17
17
17
17
17
17
17
17
17
69
11
11
65
65
75
75
75
19
19
16
16
16
16
16
69
69
69
45
66
41
41
41
41
41
41
41
41
41
41
41
41
41
24
16
16
65
9
9
9
66
66
70
13
13
14 14
35
35
23
23
35
35
35
43
43 43
43
23
35
66
35
37
23
23
23
23
23
23
23
23
23
35
35
35
35
35
9
9
9
66
66
13
13
13
13
13
13
13
13
13
13
16
16
16
74
62
62
62
62
70
70
67
66
62
70
67
9
66
67
43 43
51
51
51
51
51
51
51
61
61
43
43
43
43
43
43 23
23
61
51
31
31
31
31
31
31
31
31
61
61
54
54
14
76
14
14
14
14
14
14
14
14
14
14
14
76
76
76
76
76
76
76
37
9
65
14
14
14
14
14
14
14
14
14
14
66
9
9
66
62
62
66
74
66
74
74
16
16
13
13
13
13
13
66
66
66
66
35
65
37
37
37
37
37
37
37
37
37
37
37
37
37
23
66
66
14
14
31
8
8
8
65
65
66
9
9
10 10
27
27
22
22
27
27
27
41
41
41
41
22
27
65
27
32
22
22
22
22
22
22
22
22
22
27
27
27
27
27
8
8
8
62
62
9
9
9
9
9
9
9
9
9
9
14
14
14
72
19
19
19
19
66
66
66
65
19
66
66
8
62
66
42 42
46
46 46
46
46
46
46
51
51
42
41 41
41
41
41
22
22
51
46
25
25
25
25
25
25
25
25
51
51
71
9
71
71
9
71
10
73
10
10
10 10
10
10
10
10
10
10
10
73
73
73
73
73
73
73
32
8
31
10
10
10
10
10
10
10
10
10
10
65
8
8
62
19
19
62
72
62
72
72
14
14
9
9
9
9
9
65
65
65
62
27
31
32
32
32
32
32
32
32
32
32
32
32
32
32
22
41
41
71
5
5
30
7
7
7
62
63
66
54
8
8
5 5
26
26
11
11
26
26
26
5
5
5
5
11
26
63
66
26
27
11
11
11
11
11
11
11
11
11
26
26
26
26
26
7
7
7
39
39
8
8
8
8
8
8
8
8
8
8
5
5
5
71
17
17
17
17
54
54
65
62
66
17
54
65
7
39
65
66
66
38 38
25
25
25
25
25
25
25
45
45
66
38
5
5
5
5
5 11
11
45
25
5
5
5
5
5
5
5
5
45
45
70
8
70
70
8
70
5
70
5
5
5
5
5
5
5
5
5
5
5
70
70
70
70
70
70
70
27
7
30
5
5
5
5
5
5
5
5
5
5
62
7
7
39
17
17
39
71
39
71
71
5
5
8
8
8
8
8
62
62
62
39
66
26
30
27
27
27
27
27
27
27
27
27
27
27
27
27
11
39
39
70
4
4
5
5
5
5
5
5
62
5
5
5
4 4
5
5
5
5
5
5
5
4
4
4
4
5
5
5
62
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
4
4
4
66
5
5
5
5
5
5
4
5
61
5
5
4
5
5
4
61
61
4 4
5
5
5
5
5
5
5
5
5
61
4
4
4
4
4
4 5
5
5
5
4
4
4
4
4
4
4
4
5
5
66
5
66
66
5
66
4
66
4
4
4
4
4
4
4
4
4
4
4
66
66
66
66
66
66
66
5
5
5
4
4
4
4
4
4
4
4
4
4
5
5
5
5
5
5
5
66
5
66
66
4
4
5
5
5
5
5
5
5
5
5
64
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
66
BI
OUT
V-
V+
S1
GATE
S2
S3 D4D3
D2D1
G
D
S
BI
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
(2 Amps)
(2 Amps)
DC-In Connector
Inrush Limiter
Vref = 3.42V * (R2a / (R1a + R2a))Vth = (Vref / (R2b / (R1b + R2b))
Vref = 1.20VVth = 13.4V
ACIN Detection
<R1a>
<R2a><R2b>
<R1b>
Place XW8200/8210 at 5V switcher
518S0146
(HOST_DETECT_L)
Battery Connector
518S0391
5 27 50
J8290
1
2
3
4
5
6
7
8
M-RT-SM
CRITICAL
87438-0832
D82011 21SS355
SOD-323
XW82001 2
SM
XW82101 2
SM
5 50 51
R82071 2
47
5%1/8WMF-LF805
U82004
3
1
5
2
CRITICAL
LMC7211SM-LF
Q8250
5
6
7
8
4
1
2
3
CRITICAL
SO-8SI4405DY-E3
C82501
2
0.22uF25V20%
603X5R
R821612
1M
MF-LF402
5%1/16W
R82141
2
102K
MF-LF402
1%1/16W
R82151
2
54.9K
MF-LF402
1%1/16W
R82121
2
102K
MF-LF402
1%1/16W
R82131
2
10K
MF-LF402
1%1/16W
C82101
2 CERM402
0.1uF20%10V
R82211
2
470K1/16WMF-LF
402
1%
R82501
2
330K
MF-LF
5%1/16W
402
Q82103
1
2
2N7002SOT23-LF
U8250
3
2
1
4
5SC70MC74VHC1G08
J8250
1
10
2
3
4
5
6
7
8
9
87438-1043M-RT-SM
CRITICAL
5 27 50
SYNC_MASTER=(MASTER)
051-7023
67
DC-In & Battery Connectors
86
06
SYNC_DATE=(MASTER)
PPDCIN_G3HVOLTAGE=18.5V
MIN_NECK_WIDTH=0.20mm
PPDCIN_G3H_RMIN_LINE_WIDTH=0.50mm
PP18V5_DCINVOLTAGE=18.5VMIN_LINE_WIDTH=0.60mmMIN_NECK_WIDTH=0.20mm
PP5V_S5
SMBUS_SMC_BSA_SCL
SMC_BS_ALRT_LBATT_NEGMAKE_BASE=TRUEMIN_LINE_WIDTH=0.6mmMIN_NECK_WIDTH=0.25mmBATT_NEG
BATT_POSMIN_LINE_WIDTH=0.6mmMAKE_BASE=TRUE
MIN_NECK_WIDTH=0.25mm
PP18V5_G3H_CHGR
BATT_POS
BATT_NEG
BATT_POS
SMBUS_SMC_BSA_SDA
VOLTAGE=0VMIN_NECK_WIDTH=0.4 mmMIN_LINE_WIDTH=0.6 mmGND_AUDIO_PWR
ACIN_DIV
MIN_LINE_WIDTH=0.2mmMIN_NECK_WIDTH=0.2mm
ACIN_ENABLE_DIV_L
ACIN_ENABLE_DIV2_L
ACIN_1V20_REFACOK_AND_PS_ON
SMC_ADAPTER_EN
PP18V5_G3H_CHGR
PP18V5_G3H_CHGRMIN_LINE_WIDTH=0.6mmMIN_NECK_WIDTH=0.2mm
MAKE_BASE=TRUE
VOLTAGE=18.5V
SMC_BC_ACOK
PP3V42_G3H PP3V42_G3H
PP18V5_DCIN
PP5V_S0
MIN_LINE_WIDTH=0.6 mm
VOLTAGE=5VMIN_NECK_WIDTH=0.4 mm
PP5V_S0_AUDIO_PWR80 79 78 70 66 65
68
68
61
67
67
60
66 66
57
70
65
65
56
66
54
54
54
65
52 52
52
64
51
51
47
63
50
50
42
61
68
45 45
36
68
51
51
35
35
31
66
46
68
68
68
68
68
51
50
27
27
25
65
67
25
67
67
67
68
67
67
50
68
68
47
26 26
67
5
4
5
5
5
5
5
67
5
5
5
43
67
67
5
5 5
5
4
5
VDDPVDD
ACLIM
ICM
ICOMP
VCOMP
VADJ
CELLS
CSOP
CHLIM
CSON
ACPRN
VREF
SGATE
CSIN
DCIN
BGATE
BOOT
UGATE
LGATE
PHASE
DCSET
PGND
THRML_PAD
DCPRN
CSIP
EN
ACSET
GND
G
D
S
G
D
S
G
D
S
G
D
S
S1
GATE
S2
S3 D4D3
D2D1
G
D
S
S1
GATE
S2
S3D4D3
D2D1
S1
GATE
S2
S3 D4D3
D2D1
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
10A max, limited by L8300, Q8301
NC
If stuffed, R8364+R8365 > 70Kso Iref < 100uA
PBUS SUPPLY
Using PWM drive
Using PWM drive
As shown, Ichg = 3.9A max
BATTERY CHARGER
U8300
8
23
27
17
142
7
20
19
22
21
25
24
28
1
10
5
3
12
11
16
18
29
15
9
4
26
13
6
QFN
CRITICAL
ISL6255AHRZ
R83641
2
0
MF-LF402
5%1/16W
NO STUFF
R83651
2
0
MF-LF402
5%1/16W
NO STUFF
XW83001 2
SM
R83021 2
MF-LF1/16W1%
100
402
C83121
2
1uF
CERM6.3V10%
402
C83111 2
402CERM6.3V10%
1uF
Q8340
3
1
2
IRLML5203-2.6A
S
D
GSM
Q83223
5
4
SOT-3632N7002DW-X-F
Q83226
2
1
SOT-3632N7002DW-X-F
C83401
2 25V20%0.1uF
X5R402
Q83243
5
4
2N7002DW-X-FSOT-363
Q83246
2
1
SOT-3632N7002DW-X-F
C83141 2
CERM
10%
0.068UF
NO STUFF
10V
402
D83211 2
SOD-323
1SS355
R83601 2
402MF-LF1/16W1%
10K
C83611
2 CERM
0.1UF20%10V
402
R83621 224.3K
1/16W1%
MF-LF402
C83621
2 10V20%
402CERM
0.1UF
R83631
2MF-LF402
1%1/16W
11K
R83661
2402MF-LF
1%1/16W
6.04K
R83201 2
27
5%
MF3W
2525
C83301
2 50V10%
402CERM
0.001UF
C83051
2
10UF
X5R1206
10%25V
R83411
2
1/16W
402MF-LF
1%10K
R83421
2
1/16W1%
MF-LF
93.1K
402
R83401
2
1%
402MF-LF1/16W
118K
C8319 1
2CERM50V
402
10%0.0033uF
Q8302
5
4
1 2 3
LFPAK
CRITICAL
HAT2165H
Q8321
5
6
7
8
4
1
2
3
SO-8SI4405DY-E3
CRITICAL
F83021 2
CRITICAL
1206
8AMP-24V
R83671
2
24.3K1/16W
402
1%
MF-LF
C83151 2
NO STUFF
10%50V
680pF
CERM402
R83031 22.2
402MF-LF1/16W5%
R83041 2
402MF-LF
5%1/16W
270
C83071
2
NO STUFF
0.1UF
603
25V20%
CERM
R83111 2
MF-LF
5%
0
1/16W
402
C8325 1
2CERM
0.22uF10V10%
402
R83301
2
470K
402
1%1/16WMF-LF
R83701 2
0.5%
603MF-LF
49.9
1/16W
C83701
2603
0.0022uF
CERM50V10%
R83441
2MF-LF
402
1%1/16W
100K
C83081
2
CASED2E-SMPOLY
20%16V
33uF
CRITICAL
C83101
210%1uF
X5R16V
603
R83211 2
47
1/8WMF-LF805
5%
D83401
3SOT23MMBD914XXG
R83431
2
10K
MF-LF402
1%1/16W C83411
2 X5R402
10%16V
0.1uF
R83521
2
1/16W1%
402MF-LF
100K
R83501
2
1/16W1%
402MF-LF
100K
Q83503
1
2
SOT23-LF2N7002
C83001 2
CHGR_ICOMP_R
402
10%
0.033uF
X5R16V
C83011 2
0.022uF
CERM-X5R16V10%
402
R83011 2
1/16W1%
MF-LF
34.8K
402
Q8300
5
6
7
8
4
1
2
3
SI4405DY-E3
CRITICAL
SO-8
R83101
2
1/16W1%
402MF-LF
100K
NO STUFF
C83041
2 CERM402
20%10V
0.1UF
D8300SOD-123
B0530WXF
R83001 2
402
4.7
1/16WMF-LF
5%
C83031 2
25V20%
0.1uF
X5R402
C83021
2 X7R
10%0.0082uF25V
402
R83071
2
0.02
MF0612
0.5%1W
R8305
1 2
MF-LF
5%
402
181/16W
Q8301
5
4
1 2 3
CRITICAL
LFPAKHAT2168H
L8300
1
2
34.7UH
SM
C83161
2
10UF10%25V
1206X5R
R83081 20.01
0.5%1W
0612MF
C83061
2
10UF
X5R1206
10%25V
C83091
2
100uF16VELEC
20%
6.3X5.5SM1
R83061 22.2
MF-LF
5%1/16W
402
XW8304
1
2
SMXW8303
1
2
SM
XW83011 2
SM
XW83021 2
SM
Q8320
5
6
7
8
4
1
2
3
CRITICAL
SI4405DY-E3SO-8
R83311
2
1/16W5%
402MF-LF
330K
R83221
2
1/16W1%
402MF-LF
39.2K
R83231
2
1/16W1%
402MF-LF
35.7K
C83201
2 CERM
0.01uF10%16V
402
C83211
2 X5R
0.1uF10%
402
16V
C83241
2402
0.01UF20%16V
NO STUFF
CERM
C83221
2
NO STUFF
CERM16V10%0.01UF
402
R83251 210K
MF-LF402
1%1/16W
C8323 1
210V20%
402CERM
0.1UF
R83241
2
1/16W1%
402MF-LF
100K
L8321
1 2
FERR-50-OHM
SM-LF
L8320
1 2
FERR-50-OHM
SM-LF
C83271
2
0.001UF
402
10%50VCERM
06
SYNC_DATE=12/19/2005
051-7023
SYNC_MASTER=M1_LIO
8668
PBus Supply & Batt. Charger
PPDCIN_G3H CHGR_CSOP_R
MIN_NECK_WIDTH=0.25mmMIN_LINE_WIDTH=0.6mmPPVBAT_G3H_CHGR_OUT
PPVBAT_G3H_CHGR_OUT
CHGR_ICOMP
CHGR_CSO_PCHGR_CSO_N
MIN_NECK_WIDTH=0.2mmMIN_LINE_WIDTH=0.2mmCHG_EN_DIV_L
CHGR_VREF
CHGR_CSI_P
CHGR_SGND
SMC_BATT_ISET CHGR_CHLIM
SMC_SYS_ISET
CHGR_DCPRNCHGR_ACPRN
SMC_BC_ACOK
CHGR_ACLIM
CHGR_SGND
CHGR_ACPRNCHGR_ACSET
CHGR_CHLIM
CHGR_BOOT_R
CHGR_ICM_R
CHGR_DCIN
CHGR_ACSET_D
CHGR_EN
CHGR_CSO_P
CHGR_CSO_NCHGR_CSON_R
CHGR_ACPRN
CHGR_ACLIM
CHGR_VDD
MIN_NECK_WIDTH=0.25mmMIN_LINE_WIDTH=0.6mmPPVBATT_G3H_FUSE
GND_BATT_CHGND
MIN_NECK_WIDTH=0.25mmMIN_LINE_WIDTH=0.6mmBATT_POS
BATT_NEGMIN_NECK_WIDTH=0.25mmMIN_LINE_WIDTH=0.6mm
CHGR_DCSET
CHGR_SGND
CHGR_SGND
CHGR_VADJ
NO_TEST=TRUENC_CHGR_BGATE
MIN_NECK_WIDTH=0.2mmMIN_LINE_WIDTH=0.2mmTCHG_EN_DIV_L
CHG_EN_DIV2_L
SMC_BATT_CHG_EN
TCHG_EN_DIV2_L
SMC_BATT_TRICKLE_EN_L
PP3V42_G3H
SMC_BC_ACOK_R
CHGR_VDD
CHGR_SGND
CHGR_VDDP
CHGR_ACSET
CHGR_CSIN_R
CHGR_VDDPMIN_NECK_WIDTH=0.25mm
PPVDCIN_G3H_RMIN_LINE_WIDTH=0.6mm
CHGR_VREF
CHGR_CSON_R CHGR_VCOMP_C1
CHGR_EN
CHGR_ICM
CHGR_PHASE_R
CHGR_VREF
CHGR_DCPRNCHGR_DCSET
CHGR_SGND
MIN_LINE_WIDTH=0.6mmMIN_NECK_WIDTH=0.25mm
PPVDCIN_G3H_PRE
CHGR_BOOT MIN_LINE_WIDTH=0.6mmMIN_NECK_WIDTH=0.2mm
CHGR_VADJ
CHGR_SGND
CHGR_VCOMP
MIN_NECK_WIDTH=0.2mmMIN_LINE_WIDTH=0.6mm
CHGR_LGATE
CHGR_PHASEMIN_LINE_WIDTH=0.6mm
SWITCH_NODE=TRUEMIN_NECK_WIDTH=0.2mm
MIN_LINE_WIDTH=0.6mmMIN_NECK_WIDTH=0.2mm
CHGR_UGATE
CHGR_DCIN
CHGR_CSI_N
MIN_NECK_WIDTH=0.2mmMIN_LINE_WIDTH=0.2mm
CHGR_SGATE
PPBUS_G3H
CHGR_VDDPP18V5_G3H_CHGR
PPVBATT_G3H_PRE
PPVBATT_G3H_FETMIN_LINE_WIDTH=0.6mmMIN_NECK_WIDTH=0.25mm
PPVBATT_G3H_DIO
MIN_NECK_WIDTH=0.25mmMIN_LINE_WIDTH=0.5mmVOLTAGE=12.6V
78
67
70
66
66
65
64
54
63
52
61
51
60
50
54
67
45
47
67
51
35
43
66
50
27
41
65
47
68
67
67
51
26
68
5
4 48
68
68
68
68
68
48
68
50 68
50
68
68
5
68
68
68
68
68
68
68
68
68 48
68
68
68
5
5
68
68
68
68
50
5
68
68
68
48
68
68
48
68
68
68
68
68
68
68
68
4
68
67
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
PCIE_PVSS
PCIE_VDDR_12
PCIE_PVDD_12
PCIE_VSS
(1.2V)
(1.2V)
PCIE_VSS
(2 OF 7)
PCI EXPRESS POWER & GROUND
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
PCIE_REFCLKP
PCIE_REFCLKN
PERST*
PERST*_MASK
PCIE_TEST
PCIE_RX15N
PCIE_RX14P
PCIE_RX13N
PCIE_RX12N
PCIE_RX12P
PCIE_RX1P
PCIE_TX0P
PCIE_TX0N
PCIE_TX1P
PCIE_TX2N
PCIE_TX1N
PCIE_TX2P
PCIE_TX3P
PCIE_TX3N
PCIE_TX4P
PCIE_TX4N
PCIE_TX5P
PCIE_TX5N
PCIE_TX6P
PCIE_TX6N
PCIE_TX7P
PCIE_TX7N
PCIE_TX8N
PCIE_TX8P
PCIE_TX9P
PCIE_TX10P
PCIE_TX9N
PCIE_TX10N
PCIE_TX11P
PCIE_TX11N
PCIE_TX12P
PCIE_TX12N
PCIE_TX13N
PCIE_TX13P
PCIE_TX14N
PCIE_TX14P
PCIE_TX15N
PCIE_TX15P
PCIE_CALRP
PCIE_CALRN
PCIE_CALI
PCIE_RX1N
PCIE_RX2N
PCIE_RX2P
PCIE_RX3P
PCIE_RX3N
PCIE_RX4P
PCIE_RX4N
PCIE_RX5P
PCIE_RX5N
PCIE_RX6N
PCIE_RX6P
PCIE_RX7N
PCIE_RX7P
PCIE_RX8P
PCIE_RX8N
PCIE_RX9P
PCIE_RX9N
PCIE_RX10P
PCIE_RX10N
PCIE_RX11P
PCIE_RX11N
PCIE_RX13P
PCIE_RX14N
PCIE_RX0N
PCIE_RX0P
PCIE_RX15P
PCI-EXPRESS BUS INTERFACE
(1 OF 7)
OUT
OUT
OUT
OUT
OUT
OUT
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
2000mA
NC
100mA
13
C8481 1 2
X5R 402
0.1uF
16V10%
C8482 1 2
402
0.1uF
X5R16V10%
13
13
C8479 1 20.1uF
40216V10% X5R
C8480 1 2
402
0.1uF
X5R16V10%
13
13
C8477 1 2
402
0.1uF
X5R16V10%
C8478 1 2
402X5R16V10%
0.1uF
13
13
C8475 1 2
402
0.1uF
X5R16V10%
C8476 1 2
402
0.1uF
X5R16V10%
13
13
C8473 1 2
402
0.1uF
X5R16V10%
C8474 1 2
402
0.1uF
X5R16V10%
13
C8420 1 2
40210% 16V X5R
0.1uF
13
C8471 1 2
402
0.1uF
X5R16V10%
C8472 1 2
402
0.1uF
X5R16V10%
13
13
C8469 1 2
402
0.1uF
X5R16V10%
C8470 1 2
402
0.1uF
X5R16V10%
13
13
C8467 1 2
402
0.1uF
X5R16V10%
C8421 1 2
10%
0.1uF
16V X5R 402
C8468 1 2
402
0.1uF
X5R16V10%
13
13
C8465 1 2
402
0.1uF
X5R16V10%
C8466 1 2
402
0.1uF
X5R16V10%
13
13
C8463 1 2
402
0.1uF
X5R16V10%
C8464 1 2
402
0.1uF
X5R16V10%
13
C8450 1 2
10% 16V X5R
0.1uF
402
13
C8461 1 2
402
0.1uF
X5R16V10%
C8462 1 20.1uF
402X5R16V10%
13
13
C8459 1 2
402
0.1uF
X5R16V10%
C8460 1 2
402
0.1uF
X5R16V10%
13
13
C8457 1 2
402
0.1uF
X5R16V10%
C8451 1 2
10% 16V X5R 402
0.1uF
C8458 1 20.1uF
402X5R16V10%
R84961
2MF-LF1/16W
402
1%562
R84951
2
1%2.0K
MF-LF402
1/16W
R84971
2
1.47K1%
402MF-LF1/16W
U8400
N23
P23
U23
V23
W23
N25
N26
AM28
AM29
AM30
AM31
N27
N28
N29
AL29
AL30
AL31
AL32
AM27
N24
N30
R25
R26
R29
R31
T24
T26
T27
T29
U24
U26
P24
U28
U29
U30
V24
V25
V26
V29
V31
W24
W26
P25
W27
W29
Y24
Y26
Y28
Y29
Y30
AA23
AA25
AA26
P26
AA29
AA31
AB23
AB26
AB27
AB29
AC23
AC24
AC26
AC28
P28
AC29
AC30
AD25
AD26
AD29
AD31
AE26
AE27
AE29
AF26
P29
AF28
AF29
AF30
AG25
AG26
AG29
AG31
AH24
AH26
AH27
P30
AH29
AJ26
AJ28
AJ29
AJ30
AJ32
AK26
AK29
AK30
AK31
R23
AK32
AL27
R24
BGAM56P
OMITC8402 1
2CERM
1uF6.3V
402
10%
C8448 1 2
10% 16V X5R
0.1uF
402
C8401 1
2402
CERM
10%6.3V
1uF
C8407 1
210%
6.3VCERM402
1uF
C8449 1 2
10% 16V X5R
0.1uF
402
C8413 1
210%
6.3VCERM402
1uF
C8406 1
2
1uF
402CERM6.3V10%
C8411 1
2
1uF
402CERM6.3V10%
C8412 1
210%
6.3VCERM402
1uF
C84001
220%
CERM805
6.3V
22UF
C84101
2
22UF6.3V
805CERM
20% C8446 1 2
10% 16V X5R
0.1uF
402
C84051
2
22UF6.3V
805CERM
20%
L8400
1
2
200-OHM-EMI0402
C8447 1 2
10% 16V X5R
0.1uF
402
C8444 1 2
10% 16V X5R
0.1uF
402
C8445 1 2
10% 16V X5R
0.1uF
402
C8442 1 2
10% 16V X5R
0.1uF
402
C8443 1 2
10% 16V X5R
0.1uF
402
C8440 1 2
10% 16V X5R
0.1uF
402
C8441 1 2
10% 16V X5R
0.1uF
402
C8438 1 2
10% 16V X5R
0.1uF
402
C8439 1 2
10% 16V X5R 402
0.1uF
C8436 1 2
10% 16V X5R
0.1uF
402
C8437 1 2
10% 16V X5R
0.1uF
402
C8434 1 2
10% 16V X5R
0.1uF
402
C8435 1 2
10% 16V X5R
0.1uF
402
C8432 1 2
10% 16V X5R
0.1uF
402
C8433 1 2
10% 16V X5R
0.1uF
402
C8430 1 2
10% 16V X5R
0.1uF
402
C8431 1 2
10% 16V X5R 402
0.1uF
C8428 1 2
10% 16V X5R
0.1uF
402
C8429 1 2
10% 16V X5R
0.1uF
402
C8426 1 2
10% 16V X5R
0.1uF
402
C8427 1 2
10% 16V X5R
0.1uF
402
C8424 1 2
16V X5R
0.1uF
40210%
C8425 1 2
10% 16V X5R
0.1uF
402
C8422 1 20.1uF
10% X5R 40216V
C8423 1 2
10% 16V X5R
0.1uF
402
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
34
34
5 26
C8455 1 2
10% 16V X5R
0.1uF
402
C8456 1 2
10% 16V X5R
0.1uF
402
13
U8400
AB24
AE24
AD24
AK28
AL28
AH31
AJ31
V30
W30
U32
V32
T31
U31
R30
T30
P32
R32
N31
P31
AG30
AH30
AF32
AG32
AE31
AF31
AD30
AE30
AC32
AD32
AB31
AC31
AA30
AB30
Y32
AA32
W31
Y31
AA24
AJ27
AK27
W25
Y25
V28
W28
U27
V27
T25
U25
R28
T28
P27
R27
AH25
AJ25
AG28
AH28
AF27
AG27
AE25
AF25
AD28
AE28
AC27
AD27
AB25
AC25
AA28
AB28
Y27
AA27
AG24
AF24
M56PBGA
OMIT
13
13
13
C8485 1 2
402
0.1uF
X5R16V10%
C8486 1 2
402
0.1uF
X5R16V10%
13
13
C8483 1 2
402
0.1uF
X5R16V10%
C8484 1 2
402
0.1uF
X5R16V10%
13
051-7023
SYNC_DATE=02/10/2006
06
8669
ATI M56 PCI-ESYNC_MASTER=M1_MLB
PP1V2_S0
PP1V2_S0_PCIE_GPU_PVDD_F
VOLTAGE=1.2V
MIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.25 mm
PEG_D2R_N<1>
PEG_D2R_N<12>
PEG_R2D_P<5>
PEG_R2D_C_P<9>
PP1V2_S0
PEG_D2R_C_N<2>
PEG_R2D_N<4>
PEG_R2D_C_P<5>
PEG_R2D_C_N<13>
PEG_R2D_C_P<14>
PEG_R2D_C_N<14>
GPU_PCIE_CALRP
GPU_PCIE_CALI
PEG_R2D_N<0>
PEG_R2D_N<1>
PEG_R2D_N<2>
PEG_R2D_N<3>
PEG_R2D_N<6>
PEG_R2D_N<5>
PEG_R2D_N<9>
PEG_R2D_N<8>
PEG_R2D_N<7>
PEG_R2D_N<11>
PEG_R2D_N<10>
PEG_R2D_N<12>
PEG_R2D_N<13>
PEG_R2D_N<14>
PEG_R2D_N<15>
PEG_R2D_P<0>
PEG_R2D_P<1>
PEG_R2D_P<2>
PEG_R2D_P<3>
PEG_R2D_P<4>
PEG_R2D_P<6>
PEG_R2D_P<7>
PEG_R2D_P<8>
PEG_R2D_P<9>
PEG_R2D_P<10>
PEG_R2D_P<11>
PEG_R2D_P<12>
PEG_R2D_P<13>
PEG_R2D_P<14>
PEG_R2D_P<15>
PEG_R2D_C_N<0>
PEG_R2D_C_P<0>
PEG_R2D_C_N<1>
PEG_R2D_C_P<1>
PEG_R2D_C_P<2>
PEG_R2D_C_N<2>
PEG_R2D_C_P<3>
PEG_R2D_C_N<3>
PEG_R2D_C_P<4>
PEG_R2D_C_N<4>
PEG_R2D_C_P<6>
PEG_R2D_C_N<5>
PEG_R2D_C_N<6>
PEG_R2D_C_P<7>
PEG_R2D_C_N<7>
PEG_R2D_C_N<8>
PEG_R2D_C_P<8>
PEG_R2D_C_N<9>
PEG_R2D_C_P<10>
PEG_R2D_C_N<10>
PEG_R2D_C_P<11>
PEG_R2D_C_N<11>
PEG_R2D_C_P<12>
PEG_R2D_C_P<13>
PEG_R2D_C_N<12>
PEG_R2D_C_P<15>
PEG_CLK100M_GPU_P
PEG_RESET_L
PEG_CLK100M_GPU_N
PEG_R2D_C_N<15>
GPU_PCIE_CALRN
PEG_D2R_C_N<0>
PEG_D2R_C_N<1>
PEG_D2R_C_N<3>
PEG_D2R_C_N<4>
PEG_D2R_C_N<5>
PEG_D2R_C_N<6>
PEG_D2R_C_N<7>
PEG_D2R_C_N<8>
PEG_D2R_C_N<9>
PEG_D2R_C_N<10>
PEG_D2R_C_N<11>
PEG_D2R_C_N<12>
PEG_D2R_C_N<13>
PEG_D2R_C_N<14>
PEG_D2R_C_N<15>
PEG_D2R_P<0>
PEG_D2R_N<0>
PEG_D2R_P<1>
PEG_D2R_N<2>
PEG_D2R_P<2>
PEG_D2R_N<3>
PEG_D2R_P<3>
PEG_D2R_N<4>
PEG_D2R_P<4>
PEG_D2R_P<5>
PEG_D2R_P<6>
PEG_D2R_N<5>
PEG_D2R_N<6>
PEG_D2R_P<7>
PEG_D2R_N<7>
PEG_D2R_P<8>
PEG_D2R_N<8>
PEG_D2R_N<9>
PEG_D2R_P<9>
PEG_D2R_N<10>
PEG_D2R_P<10>
PEG_D2R_N<11>
PEG_D2R_P<11>
PEG_D2R_P<12>
PEG_D2R_P<13>
PEG_D2R_P<14>
PEG_D2R_N<13>
PEG_D2R_P<15>
PEG_D2R_N<14>
PEG_D2R_N<15>
PEG_D2R_C_P<0>
PEG_D2R_C_P<1>
PEG_D2R_C_P<2>
PEG_D2R_C_P<3>
PEG_D2R_C_P<4>
PEG_D2R_C_P<5>
PEG_D2R_C_P<6>
PEG_D2R_C_P<7>
PEG_D2R_C_P<8>
PEG_D2R_C_P<9>
PEG_D2R_C_P<10>
PEG_D2R_C_P<11>
PEG_D2R_C_P<12>
PEG_D2R_C_P<13>
PEG_D2R_C_P<14>
PEG_D2R_C_P<15>
PP1V2_S0
76
76
76
69
69
69
66
66
66
65
65
65
62
62
62
5
5
5
PGND
PHASE
UG
LG
PVCC
FCCM
EN
PGOOD
COMP
FSET
ISEN
FB
VO
BOOT
VIN
THRMLPAD
VCC
PG
EN
VIN
ADJ
VOUT
GND
G
D
S
OUT
G
D
S
G
D
S
G
D
S
CAP-
FB
OUT
SHDN_L
CAP+
LIN/SKIP_L
IN
GND
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
17A max output(Q8520 limit)
Vout(low) = 0.6V * (1 + Ra / Rb)Vout(high) = 0.6V * (1 + Ra / Req)Req = Rb || Rc
<Rc>
<Rb>
Back-Bias Positive SupplyBack-bias positive supply provides VDDC + 0.5V when active.
Vout(high) = 0.59V * (1 + Ra/Req)
pull-up must be powered before VCore
NOTE: BBP tracks VDDC based on GPU voltage GPIO.
Pull-up voltage must be high enough to
SI3446DV max Vgs is 1.6VVin must be > 2.8V
For proper M56 power sequence, this
When inactive, provides VDDC to BBP pins.
<Rb>
<Ra>
satisfy BBP FET Vgs (where Vs = 1.2V)
NC
<Ra>
Vout = -Vin * Rb / Ra
(Regulator limit)125mA max output
close to inductor
GPU VCore Supply
Placement Note:
<Ra>
R8594 and R8597Keep C8590, R8590,
(GPUVCORE_FB)
<Rc>
Vout(low) = 0.59V * (1 + Ra/Rb)
Req = Rb || Rc
Vout = (1.58V /) 1.50V180mA max output(LDO limit)
When inactive, provides VSS to BBN pins.
Back-Bias Negative Supply
Rb = -Vout / 50 uARa = Vin / 50 uARecommended values:<Rb>
Vout = 1.10V / 0.95V
Vout = -0.55V
Back-bias negative supply provides VSS - 0.55V when active.
GPU VCore Current Sense
C8542 1
2
330uF
POLY
20%2V
CASE-D2-SM
R85211
2402
1%
MF-LF1/16W
3.01K
R85221
2402
1%5.11K
MF-LF1/16W
C85321
2603X5R16V10%1uF
L8520
1
2
3
SM1
1.0uH-20.5
CRITICAL
Q8520
5
4
1 2 3
CRITICAL
HAT2168HLFPAK
D8520
1
2CRITICAL
B340LBXFSMB
Q8522
5
4
1 2 3
CRITICAL
LFPAKHAT2165H
R85101 2
MF-LF402
3.01K
1%1/16W
C8502 1
2603
20%6.3V
2.2UF
CERM1
C8500 1
2
2.2UF
603
20%
CERM16.3V
C8501 1
2
1uF
X5R
10%16V
603
U8500
13
5
4
6
3
7
9
11
10
16
15
12
17
14
2
1
8
CRITICAL
ISL6269QFN
C8507 1
25%
15pF50V
402CERM
R85081
2
150K1/16W1%
402MF-LF
C8508 1
2
470pF
CERM50V
402
10%
R85041
2402
5%
MF-LF
01/16W
R85051
2
01/16W5%
402MF-LF
NO STUFF
R85061
2
57.6K
MF-LF402
1%1/16W
C8506 1
2
0.01UF
CERM402
10%16V
C85301
2603X5R16V10%1uF
C8540 1
2
22UF
805CERM
20%6.3V
C85411
2805
6.3V20%
CERM
22UF
Q8521
5
4
1 2 3
CRITICAL
HAT2165HLFPAK
XW85001 2
SM
C8522 1
225V
1000pF
X7R402
10%
NO STUFFC85211
2402
25V10%
X7R
1000pF
NO STUFF
C8556 1
26.3V20%
805CERM
22UF
C85571
2805
6.3VCERM
20%22UF
R85551
2
24.9K1%
402MF-LF1/16W
R85561
2MF-LF402
1%1/16W
16.2K
C8555 1
2
0.01UF
CERM402
10%16V
U8550
53
2
4
1 6
CRITICAL
SOT23-6-LFFAN2558
C8551 1
220%
6.3V
2.2uF
603CERM1
C85431
2
330uF20%
POLY2V
CASE-D2-SM
R85231 2
1/16WMF-LF
1%
402
12.4K
R85021
2
NO STUFF
402
0
MF-LF
5%1/16W
R85601
2
10K
MF-LF402
5%1/16W
Q85703
1
2
SOT23-LF2N7002
R85701
2402
1/16W5%
MF-LF
100K
C85701
2 CERM402
10%0.0022uF50V
R85611 2
1/16W5%
402MF-LF
0
GPU_BB_CTL
C859812
10%
CERM402
470pF
50V
54
C859212
10%
CERM
470pF
50V
402
R85981 2
1/16W1%
1M
MF-LF402
U8595
3
4
1
5
2
SOT23-5LMV2011MF
R85921 2
1/16WMF-LF
1%
1M
402
C85951
2 6.3V10%
402CERM
1uF
R85931 2
1%1/16W
402MF-LF
20.0K
R85911 2
1/16W
402MF-LF
1%
20.0K
R85901
2
6491%
402MF-LF1/16W
R85941 2
NO STUFF
1/16WMF-LF402
1K
1%
C859012
6.3V
1uF
402
10%
CERM
R8597
1
2
0603-LF
CRITICAL
10KOHM-5%
R85961
2
1%1K
1/16WMF-LF
402
R85541
2MF-LF402
174K1/16W1%
NO STUFF
C8523 1
2402
10%16V
0.022uF
CERM-X5R
R85241
2
10K
402MF-LF1/16W
5%
R85251 2
1/16W5%
MF-LF402
10K
C8520 1
2402
CERM50V10%
NO STUFF
0.0022uF
R85261
2402
5%1/16WMF-LF
10K
Q85233
5
4
SOT-3632N7002DW-X-F
Q85236
2
1
SOT-3632N7002DW-X-F
Q85543
1
2
SOT23-LF2N7002
NO STUFFR85871
2
1%
MF-LF1/16W
402
68.1K
R85881
2MF-LF1/16W
402
1%11.3KC85811
220%6.3VCERM1603
2.2uF
C8580 1
2603
20%10uF
X5R6.3V
C85891
2 6.3V20%
CERM
22UF
805
U8580
3
2
6
7
8
1
5
4
MAX1673SOI
CRITICAL
Q85751
2
5
63
4
TSOP-LFSI3446DV
R85201
2
NO STUFF
0
MF-LF402
5%1/16W
C85091
220%6.3VX5R402
0.22UFR85091
2
5%0
1/16WMF-LF
402
C85311
2
33uF20%16V
CRITICAL
POLYCASED2E-SM
SYNC_DATE=02/10/2006
GPU (M56) Core Supplies
70
06
86
SYNC_MASTER=M1_MLB
051-7023
PPBUS_G3H
GPUBBN_FB
PP3V3_S0_GPU
PNBB_S0_GPU
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.6 mm
SWITCH_NODE=TRUE
GPUVCORE_PHASE
PP5V_S5
GPUISENS_NTC
GPUVCORE_FB_LOW
GPUVCORE_FB_RC
GPUISENS_POS
GPUISENS_NEG
GPUISENS_RC
GPUVCORE_BOOTMIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.25 mm
GPUBB_EN
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.38 mmGPUBBN_CAPP
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.38 mmGPUBBN_CAPN
PP3V3_S0_GPU
GPU_VCORE_HIGH_RC
GPU_VCORE_LOW
GPU_VCORE_HIGH
GPUVCORE_ISEN
MIN_NECK_WIDTH=0.25 mm
GPUVCORE_UGMIN_LINE_WIDTH=0.6 mm
MIN_LINE_WIDTH=0.6 mmGPUVCORE_LG
MIN_NECK_WIDTH=0.25 mm
GPUVCORE_IOUT
PP3V3_S0
PM_SLP_S3_LS5V_L
GPUVCORE_ENGPUVCORE_FCCM
GPUVCORE_COMP
GPUVCORE_COMP_R
GPUBBP_ADJ_LOW
PP3V3_S0_GPU
GPUBB_EN
GPU_VCORE_HIGH
PP5V_S0
GPU_GENERICDGPUBB_EN
PPBB_S0_GPU
GPUBB_EN_L
PPVCORE_S0_GPU
GPUBB_EN_L
GPUBBP_ADJ
GND_GPUVCORE_SGND
GPUVCORE_FB
GPUVCORE_FSET
MIN_LINE_WIDTH=0.25 mmGPUVCORE_BOOT_R
MIN_NECK_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.25 mm
VOLTAGE=5V
PP5V_S0_GPUVCORE_VCC
PPVCORE_S0_GPU
79 78 66 65
64 60 59 57 56 53 51 48 43
37 36
80
34
79
33
78
29
67
28
66
27
65
78
26
61
68
25
60
66
24
57
64
67
23
56
63
66
22
54
61
65
21
52
60
64
20
47
54
63
19
42
76
76
47
61
17
36
71
71
43
76
51
76
14
76
31
70
70
41
73
46
73
10
73
25
66
66
5
70
71
25
70
76
5
65
70
5
71
54
54
4
66
66
5
70
66
73
70
4
62
65
5
66
70
70
4
76
70
66
70
5
70
5
5
5
MEMORY & CORE POWER / GROUND
(1.0V/1.2V)
(1.0V/1.2V)
(7 OF 7)
VDDR1
VSS
VSS
(1.8V/2.0V) VSS
VDDC
BBP BBN
VDDCI
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
(NONE)
(NONE)
- =PP1VR1V3_GPU_VCORE
BOM options provided by this page:
Signal aliases required by this page:
Page NotesPower aliases required by this page:- =PP1V5_GPU_VDD15
14.2A @ 445/452MHz Core/Mem Clk for VDDC+VDDCI
2.0A @ 500MHz 1.8V GDDR3
100mA (Preliminary)
100mA (Preliminary)
U8400
K15
R10
Y23
AC17
K18
M23
V10
AC14
P14
P18
U15
U16
U17
V14
V15
V16
V18
W14
W15
W19
P19
AC11
AC12
AD11
R15
R17
R18
R19
T16
T17
T18
K14
P16
T14
T23
U19
W10
W17
A3
A9
F32
H13
H19
J1
J10
J11
J13
J18
J19
J20
A12
J32
K11
K13
K19
K20
K21
K24
L23
L24
L32
A15
M1
M10
N9
N10
P8
P9
P10
R1
R9
V1
A18
Y8
Y9
Y10
AA1
A21
A24
A30
C1
C32
K23
A2
B1
R3
R6
R14
R16
T10
T15
T19
U1
U5
U6
B32
U7
U8
U9
U10
U14
U18
V3
V6
V17
V19
C4
W16
W18
Y1
Y5
Y6
Y7
AA4
AA6
AC9
AC10
C5 AD6
AD7
AD8
AD9
AD10
AD13
AD14
AD15
AD16
AD17
C6
AE8
AE14
AE15
AE16
AE17
AF14
AF16
AG11
AG16
AG23
C9
AH10
AH11
AH16
AJ10
AK16
AL1
AL13
AM2
AM13
C10
C15
C18
C20
A8
C21
C24
C27
D11
D30
E5
E8
E9
E12
E13
A11
E16
E19
E25
E28
E30
E32
F3
F6
F10
F13
A13
F15
F16
F18
F19
F21
F22
F24
F27
F30
G13
A16
G16
G19
G20
G21
G22
G25
H1
H5
H7
H16
A19
H20
H21
H28
H32
J3
J6
J9
J12
J16
J21
A22
J24
J28
J30
K10
K12
K16
K17
K27
K30
L1
A25
L6
L7
L29
M3
M6
M7
M8
M9
M24
M28
A31
M32
N3
N7
N8
P1
P5
P6
P7
P15
P17
OMIT
BGAM56P
C8697 1
2
0.1uF
402X5R16V10%
C8696 1
210%
402
1uF
CERM6.3V
C86911
210%
402
1uF
CERM6.3V
C86921
2
0.1uF
402X5R16V10%
C86101
2 CERM6.3V
1uF
402
10%
C86091
26.3VCERM
1uF
402
10%
C86081
26.3VCERM
1uF
402
10%
C86071
26.3VCERM
1uF
402
10%
C86061
26.3VCERM
1uF
402
10%
C86051
26.3VCERM
1uF
402
10%
C86041
2402
6.3VCERM
1uF10%
C86161
210%
402
1uF
CERM6.3V
C86151
210%
402
1uF
CERM6.3V
C86141
210%
402
1uF
CERM6.3V
C86131
210%
402
1uF
CERM6.3V
C86121
210%
402
1uF
CERM6.3V
R86301
2
1/10W
603
05%
MF-LF
C86341
26.3VCERM
1uF
402
10%
C86331
26.3VCERM
1uF
402
10%
C86321
26.3VCERM
1uF
402
10%
C86311
26.3VCERM
1uF
402
10%
C86601
2 6.3VCERM
1uF
402
10%
C86661
210%
402
1uF
CERM6.3V
C86591
2 6.3VCERM
1uF
402
10%
C86581
2 6.3VCERM
1uF
402
10%
C86571
2 6.3VCERM
1uF
402
10%
C86651
210%
402
1uF
CERM6.3V
C86641
210%
402
1uF
CERM6.3V
C86631
210%
402
1uF
CERM6.3V
C86561
2 6.3VCERM
1uF
402
10%
C86621
210%
402
1uF
CERM6.3V
C86551
2 6.3VCERM
1uF
402
10%
C86611
210%
402
1uF
CERM6.3V
C86721
26.3VCERM
1uF
402
10%
C86781
210%
402
1uF
CERM6.3V
C86711
26.3VCERM
1uF
402
10%
C86701
26.3VCERM
1uF
402
10%
C86691
26.3VCERM
1uF
402
10%
C86771
210%
402
1uF
CERM6.3V
C86761
210%
402
1uF
CERM6.3V
C86751
210%
402
1uF
CERM6.3V
C86681
26.3VCERM
1uF
402
10%
C86741
210%
402
1uF
CERM6.3V
C86671
2 CERM6.3V
1uF
402
10%
C86731
210%
402
1uF
CERM6.3V
C8653 1
26.3VCERM
22UF
805
20%
C8652 1
220%
6.3VCERM805
22UFC8651 1
2CERM6.3V
22UF
805
20%
C8650 1
2
22UF
805CERM6.3V20%
C86831
210%
402
1uF
CERM6.3V
C86821
210%
402
1uF
CERM6.3V
C86811
210%
402
1uF
CERM6.3V
C86801
210%
402
1uF
CERM6.3V
C86791
26.3VCERM
1uF
402
10%
C8601 1
2
22UF
805CERM6.3V20%
C86111
26.3VCERM
1uF
402
10%
C8690 1
220%
6.3VCERM805
22UF
C86951
220%6.3VCERM805
22UF
C8630 1
220%
6.3VCERM805
22UF
C8600 1
220%
6.3VCERM805
22UF
ATI M56 Core PowerSYNC_MASTER=M1_MLB SYNC_DATE=02/10/2006
06051-7023
8671
PPVCORE_S0_GPU
MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.5 mm
PPVCORE_S0_GPU_VDDCIVOLTAGE=1.2V
PPBB_S0_GPU
PP1V8_S0_GPU
PNBB_S0_GPU
76 70
75
66
74
54
70
72
70
5
66
66
66
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
IN
IN
IN
IN
IN
IN
IN
BI
BI
BI
BI
BI
BI
BI
BI BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
DQA_58
DQA_59
WEA1*
DQA_61
DQA_62
MVREFD_0
MVREFS_0
VDDRH0
MAA_0
MAA_1
MAA_2
MAA_3
MAA_4
MAA_5
MAA_6
MAA_7
MAA_8
MAA_9
MAA_10
MAA_11
MAA_12
MAA_13
MAA_14
MAA_15
DQMA_0*
DQMA_1*
DQMA_2*
DQMA_3*
DQMA_4*
DQMA_5*
DQMA_6*
DQMA_7*
QSA_1
QSA_2
QSA_0
QSA_3
QSA_4
QSA_5
QSA_6
QSA_7
QSA_0*
QSA_1*
QSA_2*
QSA_3*
QSA_4*
QSA_5*
QSA_6*
QSA_7*
CLKA0
CLKA0*
CSA0_0*
CKEA0
RASA0*
CASA0*
WEA0*
ODTA0
CLKA1*
CSA1_0*
CKEA1
RASA1*
CASA1*
ODTA1
DQA_0
DQA_1
DQA_2
DQA_3
DQA_4
DQA_5
DQA_6
DQA_7
DQA_8
DQA_9
DQA_10
DQA_11
DQA_12
DQA_13
DQA_14
DQA_15
DQA_16
DQA_17
DQA_18
DQA_19
DQA_20
DQA_21
DQA_22
DQA_23
DQA_24
DQA_25
DQA_26
DQA_27
DQA_28
DQA_29
DQA_30
DQA_31
DQA_32
DQA_33
DQA_34
DQA_35
DQA_36
DQA_37
DQA_38
DQA_39
DQA_40
DQA_41
DQA_42
DQA_43
DQA_45
DQA_44
DQA_46
DQA_47
DQA_48
DQA_50
DQA_51
DQA_49
DQA_52
DQA_53
DQA_54
DQA_55
DQA_56
DQA_57
DQA_60
DQA_63
VSSRH0
CLKA1
CSA0_1*
CSA1_1*
WRITE STROBE
READ STROBE
MEMORY INTERFACE A
(3 OF 7)
2.0V)(1.8V/
DQB_62
VDDRH1
MVREFS_1
MAB_0
MAB_1
MAB_2
MAB_3
MAB_4
MAB_5
MAB_6
MAB_7
MAB_8
MAB_9
MAB_10
MAB_11
MAB_12
MAB_15
MAB_14
MAB_13
DQMB_0*
DQMB_1*
DQMB_2*
DQMB_3*
DQMB_4*
DQMB_5*
DQMB_6*
DQMB_7*
QSB_0
QSB_1
QSB_2
QSB_4
QSB_3
QSB_5
QSB_6
QSB_7
QSB_0*
QSB_1*
QSB_2*
QSB_3*
QSB_4*
QSB_5*
QSB_6*
QSB_7*
CLKB0*
CLKB0
CSB0_0*
CKEB0
RASB0*
WEB0*
CASB0*
ODTB0
CLKB1
CLKB1*
CKEB1
RASB1*
WEB1*
CASB1*
ODTB1
DRAM_RST
DQB_0
DQB_1
DQB_2
DQB_3
DQB_4
DQB_5
DQB_6
DQB_7
DQB_8
DQB_9
DQB_10
DQB_11
DQB_12
DQB_15
DQB_14
DQB_13
DQB_16
DQB_17
DQB_18
DQB_20
DQB_19
DQB_22
DQB_21
DQB_23
DQB_25
DQB_24
DQB_27
DQB_26
DQB_28
DQB_30
DQB_29
DQB_33
DQB_31
DQB_32
DQB_35
DQB_34
DQB_37
DQB_36
DQB_38
DQB_40
DQB_41
DQB_42
DQB_43
DQB_44
DQB_45
DQB_46
DQB_48
DQB_47
DQB_52
DQB_53
DQB_56
DQB_55
DQB_54
DQB_58
DQB_57
DQB_60
DQB_59
DQB_61
DQB_63
MVREFD_1
VSSRH1
TEST_MCLK
TEST_YCLK
MEMTEST
DQB_39
CSB1_0*
DQB_51
DQB_50
DQB_49
CSB0_1*
CSB1_1*
WRITE STROBE
READ STROBE
MEMORY INTERFACE B
(4 OF 7)
(1.8V/ 2.0V)
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
- =PP1V8R2V0_S0_FB_GPU
BOM options provided by this page:
Signal aliases required by this page:
Power aliases required by this page:
(NONE)
(NONE)
NC
NC NC
NC
Page Notes
74
74
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74
74
74
74
74
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74
74
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74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
73
74
74
74
74
74
74
74
74
74
74
74
75
75
75
75
75
75
75
75
75
75
75
75
75
73
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
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75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
R87221
2
1%1/16WMF-LF402
40.2R87201
2
1%1/16WMF-LF
402
40.2
C87231
2
0.1uF
402X5R16V10%
R87231
2
100
402MF-LF1/16W1%
R87211
2
1/16W
100
402MF-LF
1%
C8721 1
216V
0.1uF
402X5R
10%
75
75
75
75
75
75
75
75
74
74
74
74
74
74
74
74 75
75
75
75
75
75
75
75
C87131
210%16VX5R402
0.1uF
R87121
2
1%1/16WMF-LF402
40.2
R87131
2
100
402MF-LF
1%1/16W
C8711 1
2402X5R16V10%
0.1uF
R87101
2
1%1/16WMF-LF
402
40.2
R87111
2
100
402MF-LF1/16W
1%
R87321
2 402
2431%1/16WMF-LF
R87311
2MF-LF1/16W
5%4.7K
402
R87301
2
4.7K
402
5%1/16WMF-LF
75
75
75
75
74 75
R87331
2
5%1/16WMF-LF402
4.7K
74
74
74
74
74
74
74
74
74
74
74
74
74
74
U8400
C29
B22
B30
C22
D31
E31
B20
C19
B29
C28
B23
C23
M31
M30
L28
L27
J27
H29
G29
G27
M26
L26
M25
L25
L31
J25
G28
H27
H26
F26
G26
H25
H24
H23
H22
L30
J23
J22
E23
D22
D23
E22
E20
F20
D19
D18
H30
B19
B18
C17
B17
C14
B14
C13
B13
D17
E18
G31
E17
F17
E15
E14
F14
D13
H18
H17
G18
G17
G30
G15
G14
H14
J14
F31
M27
M29
H31
J29
J26
G23
E21
B15
D14
J17
D26
F28
D29
B27
E27
E29
B25
C25
D28
D25
E24
E26
D27
F25
C26
B26
C31
C30
F29
D24
J31
K31
K29
K28
K25
K26
F23
G24
D20
D21
B16
C16
D16
D15
H15
J15
B28
B24
A27
A28
B31
B21
M56PBGA
OMIT
U8400
D3
L2
C2
L3
B4
B5
N2
P3
D2
E3
K2
K3
B12
C12
E11
F11
F9
D8
D7
F7
G12
G11
H12
H11
B11
H9
E7
F8
G8
G6
G7
H8
J8
K8
L8
C11
K9
L9
K5
L4
K4
L5
N5
N6
P4
R4
C8
P2
R2
T3
T2
W3
W2
Y3
Y2
T4
R5
B7
T5
T6
V5
W5
W6
Y4
R8
T8
R7
T7
C7
V7
W7
W8
W9
B6
F12
D12
B8
D9
G9
K7
M5
V2
W4
T9
AA3
G4
E6
D4
F2
F5
D5
H2
H3
E4
H4
J5
G5
F4
H6
G3
G2
AA7
B3
C3
D6
J4
B9
B10
D10
E10
H10
G10
K6
J7
N4
M4
U2
U3
U4
V4
V8
V9
E2
J2
AA5
AA2
F1
E1
B2
M2
M56PBGA
OMIT
C8716 1
26.3V
402
10%
CERM
1uFC8715 1
210%
402CERM6.3V
1uFC8726 1
210%
402
1uF
CERM6.3V
C8725 1
26.3VCERM
1uF
402
10%
L8725
1 2
FERR-220-OHM
0402
L8715
1 2
FERR-220-OHM
0402
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
SYNC_MASTER=M1_MLB
ATI M56 Frame Buffer I/FSYNC_DATE=02/10/2006
06051-7023
8672
PP1V8_S0_GPU VOLTAGE=1.8VPP1V8R2V0_S0_GPU_VDDRH0
MIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.25 mm PP1V8_S0_GPU MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mmVOLTAGE=1.8V
PP1V8R2V0_S0_GPU_VDDRH1
FB_B_DQ<17>FB_B_DQ<18>
FB_A_CLK_P<0>
FB_A_CS_L<0>
FB_A_BA<2>
PP1V8_S0_GPUPP1V8_S0_GPU
FB_A_CLK_N<0>
FB_A_BA<0>
FB_B_MA<11>FB_B_MA<10>
FB_A_MA<4>FB_A_MA<3>
FB_A_DQ<0>
FB_B_DQ<62>
GPU_MVREFS1
FB_B_MA<0>FB_B_MA<1>FB_B_MA<2>FB_B_MA<3>FB_B_MA<4>FB_B_MA<5>FB_B_MA<6>FB_B_MA<7>FB_B_MA<8>FB_B_MA<9>
NC_FB_B_MA12
FB_B_BA<1>FB_B_BA<0>FB_B_BA<2>
FB_B_DQM_L<0>FB_B_DQM_L<1>FB_B_DQM_L<2>FB_B_DQM_L<3>FB_B_DQM_L<4>FB_B_DQM_L<5>FB_B_DQM_L<6>FB_B_DQM_L<7>
FB_B_RDQS<0>FB_B_RDQS<1>FB_B_RDQS<2>
FB_B_RDQS<4>FB_B_RDQS<3>
FB_B_RDQS<5>FB_B_RDQS<6>FB_B_RDQS<7>
FB_B_WDQS<0>FB_B_WDQS<1>FB_B_WDQS<2>FB_B_WDQS<3>FB_B_WDQS<4>FB_B_WDQS<5>FB_B_WDQS<6>FB_B_WDQS<7>
FB_B_CLK_N<0>FB_B_CLK_P<0>
FB_B_CS_L<0>
FB_B_CKE<0>
FB_B_RAS_L<0>
FB_B_WE_L<0>
FB_B_CAS_L<0>
TP_FB_B_ODT<0>
FB_B_CLK_P<1>FB_B_CLK_N<1>
FB_B_CKE<1>
FB_B_RAS_L<1>
FB_B_WE_L<1>
FB_B_CAS_L<1>
TP_FB_B_ODT<1>
FB_DRAM_RST
FB_B_DQ<0>FB_B_DQ<1>FB_B_DQ<2>FB_B_DQ<3>FB_B_DQ<4>FB_B_DQ<5>FB_B_DQ<6>FB_B_DQ<7>FB_B_DQ<8>FB_B_DQ<9>FB_B_DQ<10>FB_B_DQ<11>FB_B_DQ<12>
FB_B_DQ<15>FB_B_DQ<14>FB_B_DQ<13>
FB_B_DQ<16>
FB_B_DQ<20>FB_B_DQ<19>
FB_B_DQ<22>FB_B_DQ<21>
FB_B_DQ<23>
FB_B_DQ<25>FB_B_DQ<24>
FB_B_DQ<27>FB_B_DQ<26>
FB_B_DQ<28>
FB_B_DQ<30>FB_B_DQ<29>
FB_B_DQ<33>
FB_B_DQ<31>FB_B_DQ<32>
FB_B_DQ<35>FB_B_DQ<34>
FB_B_DQ<37>FB_B_DQ<36>
FB_B_DQ<38>
FB_B_DQ<40>FB_B_DQ<41>FB_B_DQ<42>FB_B_DQ<43>FB_B_DQ<44>FB_B_DQ<45>FB_B_DQ<46>
FB_B_DQ<48>FB_B_DQ<47>
FB_B_DQ<52>FB_B_DQ<53>
FB_B_DQ<56>FB_B_DQ<55>FB_B_DQ<54>
FB_B_DQ<58>FB_B_DQ<57>
FB_B_DQ<60>FB_B_DQ<59>
FB_B_DQ<61>
FB_B_DQ<63>
GPU_MVREFD1
GPU_TEST_MCLKGPU_TEST_YCLKGPU_MEMTEST
FB_B_DQ<39>
FB_B_CS_L<1>
FB_B_DQ<51>FB_B_DQ<50>FB_B_DQ<49>
FB_A_DQ<58>FB_A_DQ<59>
FB_A_WE_L<1>
FB_A_DQ<61>FB_A_DQ<62>
GPU_MVREFD0
FB_A_MA<0>FB_A_MA<1>FB_A_MA<2>
FB_A_MA<5>FB_A_MA<6>FB_A_MA<7>
FB_A_MA<11>NC_FB_A_MA12
FB_A_DQM_L<0>FB_A_DQM_L<1>FB_A_DQM_L<2>FB_A_DQM_L<3>FB_A_DQM_L<4>
FB_A_CKE<0>
FB_A_RAS_L<0>
FB_A_CAS_L<0>
FB_A_WE_L<0>
TP_FB_A_ODT<0>
FB_A_CLK_N<1>
FB_A_CS_L<1>
FB_A_CKE<1>
FB_A_RAS_L<1>
FB_A_CAS_L<1>
TP_FB_A_ODT<1>
FB_A_DQ<1>FB_A_DQ<2>FB_A_DQ<3>FB_A_DQ<4>FB_A_DQ<5>FB_A_DQ<6>FB_A_DQ<7>FB_A_DQ<8>FB_A_DQ<9>FB_A_DQ<10>FB_A_DQ<11>FB_A_DQ<12>FB_A_DQ<13>FB_A_DQ<14>FB_A_DQ<15>FB_A_DQ<16>FB_A_DQ<17>FB_A_DQ<18>FB_A_DQ<19>FB_A_DQ<20>FB_A_DQ<21>FB_A_DQ<22>FB_A_DQ<23>FB_A_DQ<24>FB_A_DQ<25>FB_A_DQ<26>FB_A_DQ<27>FB_A_DQ<28>FB_A_DQ<29>FB_A_DQ<30>FB_A_DQ<31>FB_A_DQ<32>FB_A_DQ<33>FB_A_DQ<34>FB_A_DQ<35>FB_A_DQ<36>FB_A_DQ<37>FB_A_DQ<38>FB_A_DQ<39>FB_A_DQ<40>FB_A_DQ<41>FB_A_DQ<42>FB_A_DQ<43>
FB_A_DQ<45>FB_A_DQ<44>
FB_A_DQ<46>FB_A_DQ<47>FB_A_DQ<48>
FB_A_DQ<50>FB_A_DQ<51>
FB_A_DQ<49>
FB_A_DQ<52>FB_A_DQ<53>FB_A_DQ<54>FB_A_DQ<55>FB_A_DQ<56>
FB_A_DQ<63>
FB_A_CLK_P<1>
FB_A_MA<9>FB_A_MA<8>
FB_A_MA<10>
FB_A_BA<1>
FB_A_DQM_L<7>FB_A_DQM_L<6>
FB_A_RDQS<0>FB_A_RDQS<1>FB_A_RDQS<2>FB_A_RDQS<3>FB_A_RDQS<4>FB_A_RDQS<5>
FB_A_RDQS<7>FB_A_RDQS<6>
FB_A_WDQS<0>FB_A_WDQS<1>
FB_A_WDQS<3>FB_A_WDQS<2>
FB_A_WDQS<4>FB_A_WDQS<5>FB_A_WDQS<6>FB_A_WDQS<7>
FB_A_DQ<60>
FB_A_DQM_L<5>
FB_A_DQ<57>
GPU_MVREFS0
75 75
75 75
74 74
74 74
72 72
72 72
71 71
71 71
66 66
66 66
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
Required for debug access
Required for debug access
Required for debug access
Required for debug access
0000 = 128MB0010 = 256MB
0110 = Reserved0100 = 64MB
ROMCFGID[3..0]
Required for debug access
Also required: GPIO10 - GPIO13
Renamed signals
Unused signals
TESTIN[0] TX_PWRS_ENb
TESTIN[6] Reserved
TESTIN[5] Reserved
TESTIN[3] Reserved
VDD_VCL TESTIN[2] Reserved
TESTOUT[11] ROMIDCFG[2]
TESTIN[4] DEBUG_ACCESS
TESTIN[9] PWRCNTL
IPD
Serial ROM TestBus Misc Straps
TESTIN[1] TX_DEEMPH_EN
IPD
TESTIN[8]
IPD
IPD
IPD
IPD
TESTOUT[10] ROMIDCFG[1]
ROMSCK TESTOUT[8]
ROMSI ROMIDCFG[3]
ROMSO TESTWR Reserved
ENA_BL TESTIN[7]
IPD
TESTOUT[9] ROMIDCFG[0]
SS_IN
Thm Mon Int
R88001
2
1/16W5%
10K
MF-LF402
R88011
2 402MF-LF1/16W5%10K
GPU_DEEPMH_EN
R88021
2
NO STUFF
402
10K1/16W
5%
MF-LF
R88031
2
NO STUFF
10K
402MF-LF1/16W5%
R88061
2
NO STUFF
MF-LF402
1/16W
10K5%
R88041
2
NO STUFF
MF-LF
10K5%
1/16W
402
R88081
2
NO STUFF
5%
402
10K
MF-LF1/16W
R88051
2
5%1/16WMF-LF402
10K
R88121
2
10K
402MF-LF1/16W
GPU_MEM_256M
5%
R88091
2
NO STUFF
10K5%
402MF-LF1/16W
R88111
2MF-LF402
10K1/16W5%
NO STUFFR88131
2
GPU_MEM_64M
5%1/16W
10K
MF-LF402
R93911
2
5%4.7K
MF-LF402
1/16W
R93901
2
5%4.7K1/16W
402MF-LF
R88241
2
GPU_MEM_256M
5%10K1/16W
402MF-LF
R88271
2
GPU_MEM_HYNIX
5%
402
10K
MF-LF1/16W
73 86
06051-7023
SYNC_MASTER=M1_MLB SYNC_DATE=02/10/2006
GPU Straps
GPU_CLK27MSS_IN
NC_GPU_GPIO_17
NC_GPU_GPIO_18
NC_GPU_GPIO_19
NC_GPU_GPIO_20
NC_GPU_GPIO_14
GPU_BLON
TP_GPU_GPIO_10
NC_GPU_GPIO_22NO_TEST=TRUEMAKE_BASE=TRUE
NC_GPU_GPIO_32NO_TEST=TRUEMAKE_BASE=TRUE
NC_GPU_GPIO_33NO_TEST=TRUEMAKE_BASE=TRUE
NC_GPU_GPIO_34NO_TEST=TRUEMAKE_BASE=TRUE
NC_GPU_GPIO_29NO_TEST=TRUEMAKE_BASE=TRUE
MAKE_BASE=TRUENC_GPU_GPIO_30
NO_TEST=TRUE NC_GPU_GPIO_31NO_TEST=TRUEMAKE_BASE=TRUE
NC_GPU_GPIO_28NO_TEST=TRUEMAKE_BASE=TRUE
NC_GPU_GPIO_26MAKE_BASE=TRUENO_TEST=TRUE
NC_GPU_GPIO_23MAKE_BASE=TRUENO_TEST=TRUE
NC_GPU_GPIO_19MAKE_BASE=TRUENO_TEST=TRUE NC_GPU_GPIO_20NO_TEST=TRUEMAKE_BASE=TRUE
NO_TEST=TRUE
NC_GPU_GPIO_18MAKE_BASE=TRUE
NO_TEST=TRUENC_GPU_GPIO_17MAKE_BASE=TRUE
NO_TEST=TRUENC_GPU_GPIO_14MAKE_BASE=TRUE
GPU_VCORE_LOW
NC_GPU_GPIO_21
NC_GPU_GPIO_23
NC_GPU_GPIO_22
NC_GPU_GPIO_26
NC_GPU_GPIO_25
NC_GPU_GPIO_28
NC_GPU_GPIO_31
NC_GPU_GPIO_30
NC_GPU_GPIO_29
NC_GPU_GPIO_34
NC_GPU_GPIO_33
NC_GPU_GPIO_32
GPU_CLK27MSS_INMAKE_BASE=TRUE
MAKE_BASE=TRUETP_GPU_GPIO_10
GPU_BLONMAKE_BASE=TRUE
GPU_GPIO_0
GPU_GPIO_1
NO_TEST=TRUEMAKE_BASE=TRUE
NC_GPU_GPIO_21
NC_GPU_GPIO_25NO_TEST=TRUEMAKE_BASE=TRUE
GPU_MEM_256M
GPU_MEMID
GPU_VCORE_LOWMAKE_BASE=TRUE
GPU_DDC_B_CLKGPU_DDC_B_DATA
PP3V3_S0_GPU
ATI_DVPDATA<15..0>NO_TEST=TRUEMAKE_BASE=TRUE
NC_ATI_DVPDATA<15..0>
ATI_DVPCNTL<2..0>NO_TEST=TRUEMAKE_BASE=TRUE
NC_ATI_DVPCNTL<2..0>
NC_LVDS_L_DATAN<3>MAKE_BASE=TRUE NO_TEST=TRUENC_LVDS_L_DATAN<3>
NC_ATI_DVPCLKMAKE_BASE=TRUE NO_TEST=TRUENC_ATI_DVPCLK
NC_LVDS_L_DATAP<3>MAKE_BASE=TRUE NO_TEST=TRUENC_LVDS_L_DATAP<3>
NC_LVDS_U_DATAN<3>MAKE_BASE=TRUE NO_TEST=TRUENC_LVDS_U_DATAN<3>
NC_LVDS_U_DATAP<3>MAKE_BASE=TRUE NO_TEST=TRUENC_LVDS_U_DATAP<3>
NC_GPU_TV_COMPNO_TEST=TRUEMAKE_BASE=TRUE
NC_GPU_TV_COMP
NC_GPU_TV_YMAKE_BASE=TRUE NO_TEST=TRUENC_GPU_TV_Y
NC_GPU_TV_CNO_TEST=TRUEMAKE_BASE=TRUE
NC_GPU_TV_C
TP_GPU_VGA_VSYNCMAKE_BASE=TRUETP_GPU_VGA_VSYNC
TP_GPU_VGA_HSYNCMAKE_BASE=TRUETP_GPU_VGA_HSYNC
NC_GPU_VGA_BMAKE_BASE=TRUE NO_TEST=TRUENC_GPU_VGA_B
NC_GPU_VGA_RNO_TEST=TRUEMAKE_BASE=TRUE
NC_GPU_VGA_R
NC_GPU_VGA_GMAKE_BASE=TRUE NO_TEST=TRUENC_GPU_VGA_G
NC_GPU_GENERICCMAKE_BASE=TRUE NO_TEST=TRUENC_GPU_GENERICC
NC_GPU_GENERICBNO_TEST=TRUEMAKE_BASE=TRUE
NC_GPU_GENERICB
NC_GPU_GENERICAMAKE_BASE=TRUE NO_TEST=TRUENC_GPU_GENERICA
NC_FB_B_MA12NO_TEST=TRUEMAKE_BASE=TRUE
NC_FB_B_MA12
NC_FB_A_MA12NO_TEST=TRUEMAKE_BASE=TRUE
NC_FB_A_MA12
NC_ATI_ROMCS_LNO_TEST=TRUEMAKE_BASE=TRUE
NC_ATI_ROMCS_L
NC_GPU_XTALOUTNO_TEST=TRUEMAKE_BASE=TRUE
NC_GPU_XTALOUT
GPU_CLK27MMAKE_BASE=TRUEGPU_CLK27M
ATI_DVPDATA<23..16>MAKE_BASE=TRUETP_ATI_DVPDATA<23..16>
GPU_GPIO_5
GPU_GPIO_4
GPU_GPIO_12
GPU_GPIO_8
GPU_GPIO_6
GPU_GPIO_11
GPU_GPIO_3
GPU_GPIO_9
GPU_GPIO_2
GPU_GPIO_13
GPU_MEM_256MMAKE_BASE=TRUE
GPU_MEMIDMAKE_BASE=TRUE
PP3V3_S0_GPU
76
76
76
78
76
76
78
76
73
76 76
73
73
76
76
76
76
76
76
76
76
76
76
76
76
76
76
76
76
76
76
76
76
76
76
73
76
76
76
76
76
76
76
76
76
76
76
76
73
76
76
76
76
76
76
73
70
77 77
76 76
77 77
77 77
77 77
77 77
77 77
77 77
77 77
77 77
77 77
77 77
77 77
76 76
76 76
76 76
73 73
73 73
76 76
76 76
73 73
76
76
70
34
73
73
73
73
73
73
73
73
73
73
73
73
73
73
73
73
73
73
73
73
73
73
70
73
73
73
73
73
73
73
73
73
73
73
73
34
73
73
76
76
73
73
73
73
70
77
77
66
76
76
73 73
73 73
73 73
73 73
73 73
73 73
73 73
73 73
73 73
73 73
73 73
73 73
73 73
73 73
73 73
73 73
72 72
72 72
73 73
73 73
34 34
76
76
76
76
76
76
76
76
76
76
76
73
73
66
DQ1
DQ0
DQ2
DQ3
DQ5
DQ6
DQ4
DQ8
DQ7
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ24
DQ23
DQ22
DQ25
DQ26
DQ27
DQ29
DQ28
DQ30
DQ31
RDQS3
RDQS2
RDQS1
RDQS0
SEN
RESET
MF
ZQ
RAS*
CAS*
WE*
CS*
CK*
A9
A6
A7
A3
A4
A2
A0
A1
CK
WDQS2
WDQS1
WDQS0
WDQS3
BA0
BA2
BA1
RFU1
RFU2
DM3
DM2
DM1
DM0
A5
A11
A8/AP
A10
CKE
MFHIGH
MFHIGH
MFHIGH
(1 OF 2)
VSS0
VSS1
VSS2
VSS5
VSS3
VSS4
VSS7
VSS6
VSSA0
VSSA1
VSSQ0
VSSQ1
VSSQ2
VSSQ3
VSSQ5
VSSQ6
VSSQ4
VSSQ7
VSSQ8
VSSQ9
VSSQ10
VSSQ11
VSSQ12
VSSQ13
VSSQ14
VSSQ16
VSSQ15
VSSQ17
VSSQ18
VSSQ19VDDQ19
VDDQ20
VDDQ21
VREF1
VREF0
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ18
VDDQ16
VDDQ17
VDDQ9
VDDA1
VDDQ0
VDDQ1
VDDQ2
VDDQ5
VDDQ3
VDDQ4
VDDQ6
VDDQ7
VDDQ8
VDD0
VDD1
VDD2
VDD5
VDD3
VDD4
VDD6
VDD7
VDDA0
(2 OF 2)
IN
IN
IN
IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
DQ1
DQ0
DQ2
DQ3
DQ5
DQ6
DQ4
DQ8
DQ7
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ24
DQ23
DQ22
DQ25
DQ26
DQ27
DQ29
DQ28
DQ30
DQ31
RDQS3
RDQS2
RDQS1
RDQS0
SEN
RESET
MF
ZQ
RAS*
CAS*
WE*
CS*
CK*
A9
A6
A7
A3
A4
A2
A0
A1
CK
WDQS2
WDQS1
WDQS0
WDQS3
BA0
BA2
BA1
RFU1
RFU2
DM3
DM2
DM1
DM0
A5
A11
A8/AP
A10
CKE
MFHIGH
MFHIGH
MFHIGH
(1 OF 2)
VSS0
VSS1
VSS2
VSS5
VSS3
VSS4
VSS7
VSS6
VSSA0
VSSA1
VSSQ0
VSSQ1
VSSQ2
VSSQ3
VSSQ5
VSSQ6
VSSQ4
VSSQ7
VSSQ8
VSSQ9
VSSQ10
VSSQ11
VSSQ12
VSSQ13
VSSQ14
VSSQ16
VSSQ15
VSSQ17
VSSQ18
VSSQ19VDDQ19
VDDQ20
VDDQ21
VREF1
VREF0
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ18
VDDQ16
VDDQ17
VDDQ9
VDDA1
VDDQ0
VDDQ1
VDDQ2
VDDQ5
VDDQ3
VDDQ4
VDDQ6
VDDQ7
VDDQ8
VDD0
VDD1
VDD2
VDD5
VDD3
VDD4
VDD6
VDD7
VDDA0
(2 OF 2)
IN
IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
IN
BI
BI
IN
IN
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
BOM options provided by this page:
Signal aliases required by this page:
Power aliases required by this page:
Page Notes
NOTE: U8900 DQ0-7 MUST connect to GPU
within byte-lane, but software must know
U8900.J12U8900.J1Connect to designated pin, then GND
NCNCNC
NC
U8900.J1 U8900.J12
- =PP1V8_S0_FB_VDDQ- =PP1V8_S0_FB_VDD
(NONE)
(NONE)
GDDR3 vendor/device identification scheme.how these bits are mapped for GPU to support
DQA0-7 or DQA8-15. Bits can be swapped
Connect to designated pin, then GND
R89301
2
1/16W1%
402MF-LF
2.37K
R89311
2402
1/16W1%
MF-LF
5.49K
C89031
2 16V10%
402X5R
0.1uFC89021
2
0.1uF16V10%
402X5R
C89041
2 16V10%
402X5R
0.1uFC89011
2 16V10%
402X5R
0.1uF
C89221
2 16V10%
402X5R
0.1uFC89231
2 X5R16V10%
402
0.1uFC89241
2 16V10%
402X5R
0.1uFC89251
2 16V10%
402X5R
0.1uFC89261
2
0.1uF16V10%
402X5R
U8900K9
H11
K11
L9
K10
M9
K4
H2
K3
L4
K2
M4
G9
G4
H3
F9
J11
J10
H9
F4
E3
E10
N10
N3
B2
B3
C11
C10
E11
F10
F11
G10
M11
L10
N11
M10
C2
R11
R10
T11
T10
M2
L3
N2
M3
R2
R3
C3
T2
T3
E2
F3
F2
G3
B11
B10
A9
H10
D3
D10
P10
P3
V9
J2
J3
V4
D2
D11
P11
P2
H4
A4
16MX32-GDDR3-500MHZ
K4J52324QC-BC20
OMITCRITICAL
FBGA
U8900A2
A11
F1
F12
M1
M12
V2
V11
K1
K12
A1
A12
J4
J9
N1
N4
N9
N12
R1
R4
R9
R12
C1
V1
V12
C4
C9
C12
E1
E4
E9
E12
H1
H12
A3
A10
G1
G12
L1
L12
V3
V10
J1
J12
B1
B4
L2
L11
P1
P4
P9
P12
T1
T4
T9
T12
B9
B12
D1
D4
D9
D12
G2
G11
OMITCRITICAL
16MX32-GDDR3-500MHZ
K4J52324QC-BC20
FBGA
R89491
2
1001/16W5%
402MF-LF
R89411
2
1K1/16WMF-LF402
5%
R89481
2
1/16W1%
402MF-LF
243
R89451
2
1/16W1%
402MF-LF
60.4
R89461
2
60.4
MF-LF402
1%1/16W
C89331
2
0.1uF
X5R402
10%16V
R89321
2
2.37K
MF-LF402
1%1/16W
R89331
2
1/16W1%
402MF-LF
5.49K
C89211
210%0.1uF
X5R402
16V
L8910
1 2
FERR-220-OHM
0402
L8915
1 2
FERR-220-OHM
0402
C89151
2 16V10%
402X5R
0.1uFC89101
210%16V
402X5R
0.1uF
R89401
2
1%121
MF-LF402
1/16W
R89471
2
1%121
MF-LF402
1/16W
R89441
2
1/16W
402MF-LF
1211%
R89431
2MF-LF
1%121
402
1/16W
R89421
2
1/16W
402MF-LF
1211%
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72 74
72 74
72 74
72 74 75
72 74
72
72
72
72
72
72
72
72 74
72 74
72 74
72 74
72 74
72 74
72 74
72 74
72 74
72 74
72 74
72
72
72
72
72
72
72
72
66 71 72 74 75
66 71 72 74 75
72 74
72 74
72 74
72
72
72
72
72
72
72
72
72 74 75
72
72
72
72
72
72
72
72 74
72 74
72 74
72 74
72 74
72 74
72 74
72 74
72 74
72 74
72 74
72 74
R89911
2
1K1/16W5%
402MF-LF
R89901
2
1/16W
402MF-LF
1211%
R89921
2
1%121
MF-LF402
1/16W
C89711
210%0.1uF
X5R402
16V
C89721
2
0.1uF
X5R402
10%16V
R89981
2
243
MF-LF402
1%1/16W
R89991
2
100
MF-LF402
5%1/16W
U8950K9
H11
K11
L9
K10
M9
K4
H2
K3
L4
K2
M4
G9
G4
H3
F9
J11
J10
H9
F4
E3
E10
N10
N3
B2
B3
C11
C10
E11
F10
F11
G10
M11
L10
N11
M10
C2
R11
R10
T11
T10
M2
L3
N2
M3
R2
R3
C3
T2
T3
E2
F3
F2
G3
B11
B10
A9
H10
D3
D10
P10
P3
V9
J2
J3
V4
D2
D11
P11
P2
H4
A4
CRITICALOMIT
16MX32-GDDR3-500MHZ
K4J52324QC-BC20
FBGA
R89931
2
1/16W
402MF-LF
1211%
R89951
2
60.4
MF-LF402
1%1/16W
R89941
2
1%121
MF-LF402
1/16W
R89971
2
1/16W
402MF-LF
1211%
R89961
2
1/16W1%
402MF-LF
60.4
R89811
2
5.49K
MF-LF402
1%1/16W
R89801
2
2.37K
MF-LF402
1%1/16W
R89831
2
5.49K
MF-LF402
1%1/16W
R89821
2
1/16W1%
402MF-LF
2.37K
C89731
2
0.1uF
X5R402
10%16V
C89811
2
0.1uF
X5R402
10%16V
C89741
2
0.1uF
X5R402
10%16V
C89751
2
0.1uF
X5R402
10%16V
C89831
2 16V10%
402X5R
0.1uF
U8950A2
A11
F1
F12
M1
M12
V2
V11
K1
K12
A1
A12
J4
J9
N1
N4
N9
N12
R1
R4
R9
R12
C1
V1
V12
C4
C9
C12
E1
E4
E9
E12
H1
H12
A3
A10
G1
G12
L1
L12
V3
V10
J1
J12
B1
B4
L2
L11
P1
P4
P9
P12
T1
T4
T9
T12
B9
B12
D1
D4
D9
D12
G2
G11
CRITICALOMIT
16MX32-GDDR3-500MHZ
K4J52324QC-BC20
FBGA
C89761
2
0.1uF
X5R402
10%16V
66 71 72 74 75
L8965
1 2
0402
FERR-220-OHM
L8960
1 2
0402
FERR-220-OHM
66 71 72 74 75
C89511
2 X5R
0.1uF
402
10%16V
C89521
2402
0.1uF
X5R
10%16V
C89601
2
0.1uF
X5R402
10%16V
C89531
2
0.1uF
X5R402
10%16V
C89651
2
0.1uF
X5R402
10%16V
C89541
2
0.1uF
X5R402
10%16V
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
C8900 1
2
22UF20%
805CERM6.3V
C8920 1
2CERM
22UF
805
6.3V20%
C8950 1
220%
6.3VCERM805
22UF
C8970 1
2805
20%6.3VCERM
22UF
C89311
2 16V10%
402X5R
0.1uF
GDDR3 Frame Buffer A
74 86
06051-7023
SYNC_MASTER=M1_MLB SYNC_DATE=02/10/2006
PP1V8_S0_GPU
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.25 mmFB_A0_VREF0
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.25 mmFB_A1_VREF0
FB_A_CKE<1>
FB_A_MA<10>
FB_A_MA<8>
FB_A_MA<11>
FB_A_MA<5>
FB_A_DQM_L<4>FB_A_DQM_L<5>FB_A_DQM_L<6>FB_A_DQM_L<7>
FB_A_BA<1>FB_A_BA<0>
FB_A_WDQS<7>
FB_A_WDQS<4>FB_A_WDQS<5>FB_A_WDQS<6>
FB_A_CLK_P<1>
FB_A_MA<1>FB_A_MA<0>
FB_A_MA<2>
FB_A_MA<4>FB_A_MA<3>
FB_A_MA<7>FB_A_MA<6>
FB_A_MA<9>
FB_A_CLK_N<1>FB_A_CS_L<1>FB_A_WE_L<1>FB_A_CAS_L<1>
FB_A1_ZQFB_A1_MF
FB_DRAM_RSTFB_A1_SEN
FB_A_RDQS<4>FB_A_RDQS<5>
FB_A_DQ<58>FB_A_DQ<63>
FB_A_DQ<62>FB_A_DQ<56>
FB_A_DQ<57>FB_A_DQ<61>FB_A_DQ<59>
FB_A_DQ<54>FB_A_DQ<53>FB_A_DQ<60>
FB_A_DQ<55>FB_A_DQ<52>FB_A_DQ<51>FB_A_DQ<50>FB_A_DQ<49>FB_A_DQ<48>FB_A_DQ<45>FB_A_DQ<47>FB_A_DQ<44>
FB_A_DQ<39>
FB_A_DQ<35>
FB_A_DQ<32>
FB_A_MA<10>
FB_A_MA<8>
FB_A_DQM_L<0>
FB_A_DQM_L<2>FB_A_DQM_L<3>
FB_A_BA<1>FB_A_BA<0>
FB_A_WDQS<3>
FB_A_WDQS<0>
FB_A_MA<1>
FB_A_MA<9>
FB_A_CLK_N<0>FB_A_CS_L<0>FB_A_WE_L<0>
FB_A0_ZQFB_A0_MF
FB_A_DQ<31>FB_A_DQ<28>
FB_A_DQ<29>FB_A_DQ<30>
FB_A_DQ<27>FB_A_DQ<26>FB_A_DQ<25>
FB_A_DQ<20>FB_A_DQ<22>FB_A_DQ<24>
FB_A_DQ<21>FB_A_DQ<23>FB_A_DQ<17>FB_A_DQ<18>FB_A_DQ<16>FB_A_DQ<19>FB_A_DQ<13>FB_A_DQ<12>FB_A_DQ<14>FB_A_DQ<15>FB_A_DQ<11>FB_A_DQ<10>FB_A_DQ<9>
FB_A_DQ<7>FB_A_DQ<8>
FB_A_DQ<4>
FB_A_DQ<6>FB_A_DQ<5>
FB_A_DQ<3>FB_A_DQ<2>
FB_A_DQ<0>FB_A_DQ<1>
FB_A_MA<7>FB_A_MA<6>
FB_A_MA<11>
FB_A_WDQS<2>FB_A_WDQS<1>
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.25 mmFB_A0_VREF1
PP1V8_S0_GPU
FB_A_RAS_L<1>
FB_A_BA<2>FB_A_BA<2>
FB_A_DQM_L<1>
FB_A_CLK_P<0>
FB_A_RDQS<3>FB_A_RDQS<2>FB_A_RDQS<1>
FB_A0_SEN
FB_A_RDQS<0>
FB_DRAM_RST
FB_A_CAS_L<0>
FB_A_CKE<0>
FB_A_MA<4>FB_A_MA<5>
FB_A_DQ<34>FB_A_DQ<33>
FB_A_DQ<36>FB_A_DQ<37>FB_A_DQ<38>
FB_A_DQ<40>FB_A_DQ<41>FB_A_DQ<42>FB_A_DQ<43>FB_A_DQ<46>
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.25 mmFB_A1_VREF1
PP1V8_S0_FB_A1_VDDA0MIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.25 mmVOLTAGE=1.8V
PP1V8_S0_FB_A1_VDDA1MIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.25 mmVOLTAGE=1.8V
PP1V8_S0_GPU
PP1V8_S0_FB_A0_VDDA1MIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.25 mmVOLTAGE=1.8V
PP1V8_S0_FB_A0_VDDA0MIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.25 mmVOLTAGE=1.8V
PP1V8_S0_GPU
FB_A_MA<3>FB_A_MA<2>
FB_A_MA<0>
FB_A_RAS_L<0>
FB_A_RDQS<6>FB_A_RDQS<7>
DQ1
DQ0
DQ2
DQ3
DQ5
DQ6
DQ4
DQ8
DQ7
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ24
DQ23
DQ22
DQ25
DQ26
DQ27
DQ29
DQ28
DQ30
DQ31
RDQS3
RDQS2
RDQS1
RDQS0
SEN
RESET
MF
ZQ
RAS*
CAS*
WE*
CS*
CK*
A9
A6
A7
A3
A4
A2
A0
A1
CK
WDQS2
WDQS1
WDQS0
WDQS3
BA0
BA2
BA1
RFU1
RFU2
DM3
DM2
DM1
DM0
A5
A11
A8/AP
A10
CKE
MFHIGH
MFHIGH
MFHIGH
(1 OF 2)
VSS0
VSS1
VSS2
VSS5
VSS3
VSS4
VSS7
VSS6
VSSA0
VSSA1
VSSQ0
VSSQ1
VSSQ2
VSSQ3
VSSQ5
VSSQ6
VSSQ4
VSSQ7
VSSQ8
VSSQ9
VSSQ10
VSSQ11
VSSQ12
VSSQ13
VSSQ14
VSSQ16
VSSQ15
VSSQ17
VSSQ18
VSSQ19VDDQ19
VDDQ20
VDDQ21
VREF1
VREF0
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ18
VDDQ16
VDDQ17
VDDQ9
VDDA1
VDDQ0
VDDQ1
VDDQ2
VDDQ5
VDDQ3
VDDQ4
VDDQ6
VDDQ7
VDDQ8
VDD0
VDD1
VDD2
VDD5
VDD3
VDD4
VDD6
VDD7
VDDA0
(2 OF 2)
IN
IN
IN
IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
DQ1
DQ0
DQ2
DQ3
DQ5
DQ6
DQ4
DQ8
DQ7
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ24
DQ23
DQ22
DQ25
DQ26
DQ27
DQ29
DQ28
DQ30
DQ31
RDQS3
RDQS2
RDQS1
RDQS0
SEN
RESET
MF
ZQ
RAS*
CAS*
WE*
CS*
CK*
A9
A6
A7
A3
A4
A2
A0
A1
CK
WDQS2
WDQS1
WDQS0
WDQS3
BA0
BA2
BA1
RFU1
RFU2
DM3
DM2
DM1
DM0
A5
A11
A8/AP
A10
CKE
MFHIGH
MFHIGH
MFHIGH
(1 OF 2)
VSS0
VSS1
VSS2
VSS5
VSS3
VSS4
VSS7
VSS6
VSSA0
VSSA1
VSSQ0
VSSQ1
VSSQ2
VSSQ3
VSSQ5
VSSQ6
VSSQ4
VSSQ7
VSSQ8
VSSQ9
VSSQ10
VSSQ11
VSSQ12
VSSQ13
VSSQ14
VSSQ16
VSSQ15
VSSQ17
VSSQ18
VSSQ19VDDQ19
VDDQ20
VDDQ21
VREF1
VREF0
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ18
VDDQ16
VDDQ17
VDDQ9
VDDA1
VDDQ0
VDDQ1
VDDQ2
VDDQ5
VDDQ3
VDDQ4
VDDQ6
VDDQ7
VDDQ8
VDD0
VDD1
VDD2
VDD5
VDD3
VDD4
VDD6
VDD7
VDDA0
(2 OF 2)
IN
IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
IN
BI
BI
IN
IN
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
Page NotesPower aliases required by this page:
BOM options provided by this page:
Signal aliases required by this page:(NONE)
(NONE)
- =PP1V8_S0_FB_VDD- =PP1V8_S0_FB_VDDQ
U9000.J12U9000.J1
NCNC NC
NC
U9000.J1 U9000.J12Connect to designated pin, then GNDConnect to designated pin, then GND
R90301
2
2.37K
MF-LF402
1%1/16W
R90311
2
5.49K
MF-LF402
1%1/16W
C90031
2402
0.1uF
X5R
10%16V
C90021
2
0.1uF
X5R402
10%16V
C90041
2
0.1uF
X5R402
10%16V
C90011
2
0.1uF
X5R
10%16V
402
C90221
2
0.1uF
X5R402
10%16V
C90231
2
0.1uF
X5R402
10%16V
C90241
2
0.1uF
X5R402
10%16V
C90251
2
0.1uF
X5R402
10%16V
C90261
2 16V
402
0.1uF
X5R
10%
U9000K9
H11
K11
L9
K10
M9
K4
H2
K3
L4
K2
M4
G9
G4
H3
F9
J11
J10
H9
F4
E3
E10
N10
N3
B2
B3
C11
C10
E11
F10
F11
G10
M11
L10
N11
M10
C2
R11
R10
T11
T10
M2
L3
N2
M3
R2
R3
C3
T2
T3
E2
F3
F2
G3
B11
B10
A9
H10
D3
D10
P10
P3
V9
J2
J3
V4
D2
D11
P11
P2
H4
A4
OMITCRITICAL
FBGA
K4J52324QC-BC20
16MX32-GDDR3-500MHZ
U9000A2
A11
F1
F12
M1
M12
V2
V11
K1
K12
A1
A12
J4
J9
N1
N4
N9
N12
R1
R4
R9
R12
C1
V1
V12
C4
C9
C12
E1
E4
E9
E12
H1
H12
A3
A10
G1
G12
L1
L12
V3
V10
J1
J12
B1
B4
L2
L11
P1
P4
P9
P12
T1
T4
T9
T12
B9
B12
D1
D4
D9
D12
G2
G11
FBGA
OMITCRITICAL
K4J52324QC-BC20
16MX32-GDDR3-500MHZ
R90491
2
100
MF-LF402
5%1/16W
R90411
2
1K1/16W5%
402MF-LF
R90481
2
243
MF-LF402
1%1/16W
R90451
2
60.4
MF-LF402
1%1/16W
R90461
2
1/16W1%
402MF-LF
60.4
C90331
2 16V10%
402X5R
0.1uF
R90321
2
2.37K1/16W
1%
402MF-LF
R90331
2
5.49K
MF-LF402
1%1/16W
C90211
2402
0.1uF
X5R
10%16V
L9010
1 2
0402
FERR-220-OHM
L9015
1 2
0402
FERR-220-OHM C90151
2
0.1uF
X5R402
10%16V
C90101
2
0.1uF
X5R402
10%16V
R90401
2
1/16W
402MF-LF
1211%
R90471
2
1/16W
402MF-LF
1211%
R90441
2
1%121
MF-LF402
1/16W
R90431
2
1/16W
402MF-LF
1211%
R90421
2
1%121
MF-LF402
1/16W
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72 75
72 75
72 75
72 74 75
72 75
72
72
72
72
72
72
72
72 75
72 75
72 75
72 75
72 75
72 75
72 75
72 75
72 75
72 75
72 75
72
72
72
72
72
72
72
72
66 71 72 74 75
66 71 72 74 75
72 75
72 75
72 75
72
72
72
72
72
72
72
72
72 74 75
72
72
72
72
72
72
72
72 75
72 75
72 75
72 75
72 75
72 75
72 75
72 75
72 75
72 75
72 75
72 75
R90911
2
1K
MF-LF402
5%1/16W
R90901
2
1%121
MF-LF402
1/16W
R90921
2
1/16W
402
1%121
MF-LF
C90711
2
0.1uF16V10%
402X5R
C90721
2
0.1uF16V10%
402X5R
R90981
2
1%243
MF-LF402
1/16W
R90991
2
1005%
MF-LF402
1/16W
U9050K9
H11
K11
L9
K10
M9
K4
H2
K3
L4
K2
M4
G9
G4
H3
F9
J11
J10
H9
F4
E3
E10
N10
N3
B2
B3
C11
C10
E11
F10
F11
G10
M11
L10
N11
M10
C2
R11
R10
T11
T10
M2
L3
N2
M3
R2
R3
C3
T2
T3
E2
F3
F2
G3
B11
B10
A9
H10
D3
D10
P10
P3
V9
J2
J3
V4
D2
D11
P11
P2
H4
A4
FBGA
CRITICALOMIT
K4J52324QC-BC20
16MX32-GDDR3-500MHZ
R90931
2
1211/16W
402MF-LF
1%
R90951
2
60.41/16W1%
402MF-LF
R90941
2402
1%1/16WMF-LF
121
R90971
2
121
MF-LF1/16W1%
402
R90961
2
60.4
MF-LF402
1%1/16W
R90811
2
1/16W1%
5.49K
MF-LF402
R90801
2
1/16W1%
2.37K
MF-LF402
R90831
2
1%1/16W
402
5.49K
MF-LF
R90821
2
2.37K1%
1/16W
402MF-LF
C90731
2
0.1uF16VX5R402
10%
C90811
2 16V10%
402X5R
0.1uF
C90741
2
0.1uF
X5R402
10%16V
C90751
2
0.1uF16V10%
402X5R
C90831
2
0.1uF
X5R16V10%
402
U9050A2
A11
F1
F12
M1
M12
V2
V11
K1
K12
A1
A12
J4
J9
N1
N4
N9
N12
R1
R4
R9
R12
C1
V1
V12
C4
C9
C12
E1
E4
E9
E12
H1
H12
A3
A10
G1
G12
L1
L12
V3
V10
J1
J12
B1
B4
L2
L11
P1
P4
P9
P12
T1
T4
T9
T12
B9
B12
D1
D4
D9
D12
G2
G11
16MX32-GDDR3-500MHZ
FBGA
CRITICALOMIT
K4J52324QC-BC20
C90761
2
0.1uF16V10%
402X5R
66 71 72 74 75
L9065
1 2
FERR-220-OHM
0402
L9060
1 2
FERR-220-OHM
0402
66 71 72 74 75
C90511
2 16V10%
402X5R
0.1uFC90521
2 16V10%
402X5R
0.1uF
C90601
2
0.1uF
X5R402
10%16V
C90531
2
0.1uF
X5R402
10%16V
C90651
2
0.1uF
X5R402
10%16V
C90541
2 16V10%
402X5R
0.1uF
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
C9000 1
220%
6.3VCERM805
22UF
C9020 1
220%
6.3VCERM805
22UF
C9050 1
220%
6.3VCERM805
22UF
C9070 1
2
22UF20%
6.3VCERM805
C90311
2 X5R
0.1uF
402
10%16V
051-7023
SYNC_MASTER=M1_MLB
GDDR3 Frame Buffer BSYNC_DATE=02/10/2006
06
8675
FB_B_MA<4>
FB_B_CS_L<1>
FB_B_MA<9>
FB_B_DQ<2>FB_B_DQ<7>
FB_B_DQ<24>
FB_B_DQ<13>FB_B_DQ<14>FB_B_DQ<12>FB_B_DQ<15>
FB_B_DQM_L<3>
FB_B_WDQS<1>
FB_B_RDQS<0>FB_B_RDQS<3>FB_B_RDQS<2>
FB_DRAM_RST
FB_B0_ZQ
FB_B0_SEN
FB_B_DQ<23>
FB_B_CLK_N<1>
FB_B_CAS_L<1>FB_B_WE_L<1>
FB_B_RAS_L<1>FB_B1_ZQ
FB_B_DQ<61>
FB_B_DQ<46>
FB_B_CLK_P<1>
FB_B_MA<1>FB_B_MA<2>FB_B_MA<3>
FB_B_CKE<1>
FB_B_DQ<58>FB_B_DQ<59>
PP1V8_S0_GPU
FB_B_MA<5>
FB_B_MA<7>
FB_B_BA<0>FB_B_BA<1>
FB_B_CKE<0>
FB_B_DQ<9>FB_B_DQ<11>
FB_B_DQ<8>
FB_B_DQ<18>FB_B_DQ<10>
FB_B_DQ<17>FB_B_DQ<19>FB_B_DQ<16>FB_B_DQ<20>FB_B_DQ<22>
FB_B_DQ<21>FB_B_DQ<29>FB_B_DQ<30>FB_B_DQ<28>FB_B_DQ<31>FB_B_DQ<27>
FB_B_DQ<1>FB_B_DQ<25>FB_B_DQ<26>
FB_B_DQ<6>FB_B_DQ<0>FB_B_DQ<5>FB_B_DQ<3>
FB_B_DQ<4>
FB_B_RDQS<1>
FB_B0_MF
FB_B_CAS_L<0>FB_B_WE_L<0>FB_B_CS_L<0>FB_B_CLK_N<0>
FB_B_MA<9>
FB_B_MA<6>FB_B_MA<7>
FB_B_MA<0>FB_B_MA<1>
FB_B_WDQS<3>FB_B_WDQS<2>
FB_B_WDQS<0>
FB_B_DQM_L<0>
FB_B_DQM_L<2>FB_B_DQM_L<1>
FB_B_MA<5>
FB_B_MA<11>
FB_B_MA<8>
FB_B_MA<10>
FB_B_DQ<53>FB_B_DQ<54>
FB_B_DQ<52>FB_B_DQ<55>
FB_B_DQ<48>FB_B_DQ<49>
FB_B_DQ<50>
FB_B_DQ<44>FB_B_DQ<51>
FB_B_DQ<47>FB_B_DQ<45>
FB_B_DQ<43>FB_B_DQ<41>FB_B_DQ<42>FB_B_DQ<40>FB_B_DQ<37>FB_B_DQ<32>FB_B_DQ<39>FB_B_DQ<34>FB_B_DQ<36>FB_B_DQ<35>
FB_B_DQ<63>FB_B_DQ<33>
FB_B_DQ<62>FB_B_DQ<60>FB_B_DQ<56>
FB_B_DQ<57>
FB_B_RDQS<7>FB_B_RDQS<4>
FB_B_RDQS<6>
FB_B1_SENFB_DRAM_RST
FB_B1_MF
FB_B_MA<6>
FB_B_WDQS<4>FB_B_WDQS<5>FB_B_WDQS<6>
FB_B_WDQS<7>
FB_B_BA<0>FB_B_BA<1>
FB_B_DQM_L<7>FB_B_DQM_L<4>FB_B_DQM_L<5>FB_B_DQM_L<6>
FB_B_MA<11>
FB_B_MA<8>
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.25 mmFB_B1_VREF1
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.25 mmFB_B1_VREF0
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.25 mmFB_B0_VREF1
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.25 mmFB_B0_VREF0
FB_B_RAS_L<0>
FB_B_BA<2> FB_B_BA<2>
FB_B_RDQS<5>
FB_B_MA<10>
FB_B_DQ<38>
PP1V8_S0_GPU
FB_B_MA<4>FB_B_MA<3>FB_B_MA<2>
FB_B_CLK_P<0>
PP1V8_S0_FB_B1_VDDA1MIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.25 mmVOLTAGE=1.8V
PP1V8_S0_FB_B1_VDDA0MIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.25 mmVOLTAGE=1.8V
PP1V8_S0_GPU
PP1V8_S0_FB_B0_VDDA0MIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.25 mmVOLTAGE=1.8V
PP1V8_S0_FB_B0_VDDA1MIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.25 mmVOLTAGE=1.8V
PP1V8_S0_GPU
FB_B_MA<0>
GPIO_0
GPIO_1
TESTEN
GPIO_2
GPIO_27
PLLTEST
XTALOUT
XTALIN
MPVSS
MPVDD
PVSS
PVDD
GPIO_16
GPIO_17
GPIO_15
GPIO_14
GPIO_13
GPIO_12
GPIO_11
GPIO_10
GPIO_9
GPIO_8
GPIO_7_BLON
GPIO_6
GPIO_5
GPIO_4
GPIO_3
VREFG
GPIO_33
GPIO_31
GPIO_32
GPIO_25
GPIO_26
GPIO_24
GPIO_21
GPIO_20
GPIO_19
DMINUS
DPLUS
ROMCS*
GPIO_34
GPIO_29
GPIO_30
NC_DVOVMODE_0
NC_DVOVMODE_1
DVPCLK
DVPCNTL_0
DVPCNTL_1
DVPCNTL_2
DVPDATA_2
DVPDATA_1
DVPDATA_0
DVPDATA_4
DVPDATA_3
DVPDATA_5
DVPDATA_7
DVPDATA_6
DVPDATA_9
DVPDATA_8
DVPDATA_10
DVPDATA_11
DVPDATA_13
DVPDATA_12
DVPDATA_15
DVPDATA_14
DVPDATA_16
DVPDATA_18
DVPDATA_17
DVPDATA_19
DVPDATA_21
DVPDATA_20
DVPDATA_23
DVPDATA_22
GENERICA
GENERICB
GENERICC
GENERICD
DIGON
VARY_BL
NC0
GPIO_18
VDDPLL
GPIO_28
GPIO_22
GPIO_23
GENERAL PURPOSE I/O
(1.2V)
(2.5V)
ROM
TEST
PLL & XTAL
VIP HOST / EXTERNAL TMDS
PANELCONTROL
VDDR3(3.3V)
(2.5V)VDD25
VDDR5
(1.8V/3.3V)
(1.8V/3.3V)
VDDR4
DIODETHERMAL
(2.5V)
(6 OF 7)
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
100mA
BOM options provided by this page:
Typically <50mA
Typically <50mA
Typically <50mA
20mA
external TMDS transmitters
- =PP2V5_PVDD
(NONE)
external TMDS transmitters
- =PP1V8_GPU_LVDS_PLL
- =PP3V3_GPU_GPIOS
- =I2C_GPU_TMDS_SDA - I2C data line for
(PP2V5_S0_GPU_PVDD_F)
Signal aliases required by this page:
NC
NC
NCNC
(PP1V0R1V2_S0_GPU_MPVDD)
Page Notes
- =I2C_GPU_TMDS_SCL - I2C clock line for
Power aliases required by this page:
70mA total for VDD25
20mA
C91121
210%16VX5R
0.1uF
402
C91111
2 6.3VCERM
1uF
402
10%
C91161
2402
1uF6.3VCERM
10%
C91171
2 6.3VCERM
1uF10%
402
C91371
210%
X5R402
0.1uF16V
C91361
26.3VCERM402
10%1uF
L9135
1 2
FERR-220-OHM
0402
C91411
2 6.3VCERM
1uF
402
10%
L9140
1 2
FERR-220-OHM
0402
C91421
2 X5R16V
0.1uF10%
402
R91951
2
5%1/16WMF-LF402
1K
R91911
2
1%4991/16WMF-LF402
R91901
2
1%499
402MF-LF1/16W
C9100 1
2
22UF
805CERM6.3V20%
C9110 1
220%
6.3VCERM805
22UF
C9115 1
2
22UF
805CERM6.3V20%
C9120 1
220%
6.3VCERM805
22UF
C9125 1
2
22UF
805CERM6.3V20%
C91321
210%
402
1uF6.3VCERM
C9130 1
2
22UF
805CERM6.3V20%
C9135 1
2805
CERM6.3V20%
22UF
C9140 1
2
22UF
805CERM6.3V20%
C9191 1
210%16VX5R402
0.1uF
U8400
AE11
AH12
AG12
AG1
AF2
AF1
AF3
AG2
AG3
AL3
AM3
AE6
AF4
AF5
AG4
AJ3
AH4
AJ4
AG5
AH2
AH5
AF6
AE7
AG6
AH3
AJ2
AJ1
AK2
AK1
AK3
AL2
AK22
AF23
AE23
AD23
AD4
AD2
AC4
AB3
AB4
AB5
AD5
AB8
AA8
AB7
AE13
AF13
AD1
AF9
AG7
AE10
AE9
AF7
AF8
AH6
AF10
AG10
AH9
AD3
AJ8
AH8
AG9
AH7
AG8
AC1
AC2
AC3
AB2
AC6
AC5
A6
A5
AB6
AK4
AL4
AG14
AJ14
AH14
AC7
AG22
AD12K22
L10
AA10
AC13
AC16
AC18
AC15
AA9
AB9
AB10
AC19
AC20
AD18
AD19
AD20
AJ5
AK5
AL5
AM5
AE2
AE3
AE4
AE5
AC8
AL26
AM26
OMIT
BGAM56P
C91271
2
0.1uF
402X5R16V10%
C91261
210%
402
1uF
CERM6.3V
C91221
210%16VX5R
0.1uF
402
C91211
26.3VCERM
1uF10%
402
L9120
1 2
FERR-220-OHM
0402
L9125
1 2
FERR-220-OHM
0402
L9130
1 2
200-OHM-EMI
0402
C91311
210%
402CERM6.3V
1uF
C91011
210%
402
1uF
CERM6.3V
C91021
26.3V
1uF10%
402CERM
C91031
26.3VCERM
1uF
402
10%
SYNC_DATE=02/10/2006SYNC_MASTER=M1_MLB
ATI M56 GPIO/DVO/Misc
76 86
06051-7023
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.25 mm
VOLTAGE=2.5V
PP2V5_S0_GPU_PVDD_F
MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.2 mm
VOLTAGE=1.2V
PPVCORE_S0_GPU_MPVDDPPVCORE_S0_GPU
PP2V5_S0
PP1V2_S0
MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.2 mm
VOLTAGE=1.2V
PP1V2_S0_GPU_VDDPLL
PP3V3_S0_GPU
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.25 mm
VOLTAGE=3.3V
PP1V8R3V3_S0_GPU_VDDR5_F
PP3V3_S0_GPU
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.25 mm
VOLTAGE=3.3V
PP1V8R3V3_S0_GPU_VDDR4_F
GPU_GPIO_4GPU_MEM_256M
ATI_VREFG
PP3V3_S0_GPU
ATI_TESTEN
NC_GPU_GPIO_23NC_GPU_GPIO_22
NC_GPU_GPIO_28
NC_GPU_GPIO_18
GPU_VARY_BLGPU_DIGON
GPU_GENERICDNC_GPU_GENERICCNC_GPU_GENERICBNC_GPU_GENERICA
TP_ATI_DVPDATA<22>TP_ATI_DVPDATA<23>
TP_ATI_DVPDATA<20>TP_ATI_DVPDATA<21>
TP_ATI_DVPDATA<17>TP_ATI_DVPDATA<18>
TP_ATI_DVPDATA<16>
NC_ATI_DVPDATA<14>NC_ATI_DVPDATA<15>
NC_ATI_DVPDATA<12>NC_ATI_DVPDATA<13>
NC_ATI_DVPDATA<11>NC_ATI_DVPDATA<10>
NC_ATI_DVPDATA<8>NC_ATI_DVPDATA<9>
NC_ATI_DVPDATA<6>NC_ATI_DVPDATA<7>
NC_ATI_DVPDATA<5>
NC_ATI_DVPDATA<3>NC_ATI_DVPDATA<4>
NC_ATI_DVPDATA<1>
NC_ATI_DVPCNTL<2>NC_ATI_DVPCNTL<1>NC_ATI_DVPCNTL<0>
NC_ATI_DVPCLK
NC_GPU_GPIO_29
NC_GPU_GPIO_34
NC_ATI_ROMCS_L
ATI_TDIODE_N
NC_GPU_GPIO_19NC_GPU_GPIO_20NC_GPU_GPIO_21
NC_GPU_GPIO_26NC_GPU_GPIO_25
NC_GPU_GPIO_32NC_GPU_GPIO_33
GPU_GPIO_3
GPU_GPIO_5GPU_GPIO_6GPU_BLON
GPU_GPIO_9TP_GPU_GPIO_10GPU_GPIO_11GPU_GPIO_12GPU_GPIO_13NC_GPU_GPIO_14GPU_VCORE_LOW
NC_GPU_GPIO_17GPU_CLK27MSS_IN
GPU_CLK27MNC_GPU_XTALOUT
GPU_MEMID
GPU_GPIO_2GPU_GPIO_1GPU_GPIO_0
ATI_TDIODE_P
NC_ATI_DVPDATA<2>
TP_ATI_DVPDATA<19>
NC_ATI_DVPDATA<0>
GPU_GPIO_8
NC_GPU_GPIO_31NC_GPU_GPIO_30
PP2V5_S0
PP2V5_S0
PP3V3_S0_GPU
77
77
77
76
76
76
66
66
66
71
65
69
65
65
70
62
66
76
76
76
62
62
76
66
19
65
73
73
73
19
19
73
54
17
62
70
70
70
78
73
73
73
17
17
70
5
5
5
66
66
73 73
66
73
73
73
73
78
78
70
73
73
73
73
73
73
73
73
73
73
73
73
73
73
73
73
73
73
73
73
73
73
73
73
73
73
73
73
73
73
73
53
73
73
73
73
73
73
73
73
73
73
73
73
73
73
73
73
73
70
73
34
34
73
73
73
73
73
53
73
73
73
73
73
73
5
5
66
DDC3DATA
DDC3CLK
DDC2DATA
DDC2CLK
DDC1DATA
DDC1CLK
TXOUT_L3N
TXOUT_L3P
TXOUT_L2N
TXOUT_L2P
TXOUT_L1N
TXOUT_L1P
TXOUT_L0N
TXOUT_L0P
TXCLK_LP
TXCLK_LN
TXOUT_U3N
TXOUT_U2N
TXOUT_U3P
TXOUT_U2P
TXOUT_U1N
TXOUT_U1P
TXOUT_U0N
TXOUT_U0P
TXCLK_UN
TXCLK_UP
COMP
C
Y
V2SYNC
H2SYNC
B2
G2
R2
VSYNC
HSYNC
B
G
R
TX2M
TX2P
TX1M
TX0M
TX1P
TX0P
TXCM
HPD1
LPVSS
LPVDD
R2SET
VDD2DI
VSS2DI
A2VSSQ
NC_A2VDDQ
VSS1DI
RSET
AVSSQ
VDD1DI
TXCP
TPVSS
TPVDD
TX3P
TX3M
TX4P
TX4M
TX5P
TX5M
A2VSS
A2VDD(2.5V)
AVSS
(2.5V)AVDD
TXVSSR
IDENTIFICATION
(5 OF 7)
LVDDR
LVSSR
DAC (CRT)
DAC2 (TV/CRT2)
LVDS
MONITOR
TXVDDR
(2.5V)
(2.5V)
(2.5V)
(2.5V)
(2.5V)
(2.5V)
INTEGRATED TMDS
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
Page NotesPower aliases required by this page:
Signal aliases required by this page:
20mA peak
Composite/S-Video VGA Component
Y G YC R Pr
Comp B Pb
200mA peak
65mA peak
150mA peak
NC
BOM options provided by this page:
(NONE)
(NONE)
- =PP2V5_S0_GPU- =PP1V8R2V5_S0_GPU_LVDDR
130mA peak
20mA peak
20mA peak
20mA peak
Sum of peak currents on this page: 605mAU8400
AL16
AM16
AL17
AM17
AK13
AL25
AM25
AJ24
AK25
AK23AL24
AL15
AJ13
AH15
AH23
AH22
AG13
AH13
AF12
AE12
AM24
AM15
AF15
AF11
AJ23
AE19
AE18
AC21
AC22
AD21
AD22
AE20
AE21
AE22
AF19
AF20
AF17
AF18
AF21
AF22
AG17
AG19
AH17
AH19
AJ19
AK17
AL14
AK24
AK15
AK14
AL22
AM8
AL8
AK10
AL10
AL11
AM11
AL12
AM12
AK9
AJ9
AK11
AJ11
AK12
AJ12
AL18
AM18
AK21
AJ21
AL9
AM9
AK19
AL19
AL20
AM20
AL21
AM21
AK18
AJ18
AH18
AG18
AJ20
AK20
AH20
AG20
AG21
AH21
AJ6
AK6
AL6
AM6
AJ7
AK7
AK8
AL7
AM7
AG15
AM23
AJ16
AL23
AJ17
AJ22
AJ15
BGAM56P
OMIT
R93501
2
1/16W1%
402MF-LF
499
C93461
2
0.1uF
X5R402
10%16V
C93421
2
0.1uF
X5R402
10%16V
C93411
26.3V
402CERM
1uF10%
L9300
1 2
0402
FERR-220-OHM
C93011
2
1uF
CERM
10%6.3V
402
C93061
2
1uF
CERM402
10%6.3V
L9305
1 2
0402
FERR-220-OHM
C93071
210%
402X5R
0.1uF16V
L9330
1 2
0402
FERR-220-OHM
C93311
26.3V10%
402CERM
1uF
C93221
2 X5R402
10%0.1uF16V
C93211
2
1uF
402
10%
CERM6.3V
L9320
1 2
0402
FERR-220-OHM
C93121
210%
402X5R
0.1uF16V
C93111
2 6.3V10%
CERM
1uF
402
L9310
1 2
0402
FERR-220-OHM
79
C93171
2 16V10%
X5R
0.1uF
402
C93161
2402CERM6.3V10%1uF
C93271
216V10%
402X5R
0.1uFC93261
26.3V
402CERM
10%1uF
L9325
1 2
0402
FERR-220-OHM
L9315
1 2
0402
FERR-220-OHM
L9345
1 2
0402
FERR-220-OHM
73
73
73
78 81
78 81
78 81
73
73
78 81
78 81
78 81
78 81
78 81
78 81
78 81
78 81
78 81
78 81
78 81
78 81
78 81
73
73
73
73
78 79 86
78 79 86
79
79
79
79
79
79
79
79
79
79
79
79
79
79
73
73
78
78
C93471
2
0.1uF
X5R402
10%16V
C9340 1
220%
6.3VCERM805
22UFC9345 1
220%
6.3VCERM805
22UF
C93321
26.3V10%
402CERM
1uF
C93021
2
1uF
CERM
10%
402
6.3V
C9300 1
26.3VCERM805
22UF20%
C9305 1
2
22UF
805CERM6.3V20%
C9310 1
220%
6.3VCERM805
22UF
C9315 1
2
22UF
805CERM6.3V20%
C9320 1
220%
CERM
22UF
805
6.3V
C9325 1
2CERM6.3V20%
22UF
805
C9330 1
220%
6.3V
805
22UF
CERM
79
79
78 79
78 79
78 79
73
73
73
R93511
2
715
MF-LF402
1%1/16W
77 86
06051-7023
SYNC_MASTER=M1_MLB SYNC_DATE=02/10/2006
ATI M56 Video Interfaces
PP2V5_S0_GPU_VDD2DIMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.2 mm
VOLTAGE=2.5V
PP2V5_S0
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.35 mm
VOLTAGE=2.5V
PP2V5_S0_GPU_LVDDR
MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.2 mmPP2V5_S0_GPU_LPVDD
VOLTAGE=2.5V
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.3 mm
VOLTAGE=2.5V
PP2V5_S0_GPU_A2VDD
PP2V5_S0_GPU_VDD1DIMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.2 mm
VOLTAGE=2.5V
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.25 mmPP2V5_S0_GPU_AVDD
VOLTAGE=2.5V
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.3 mmPP2V5_S0_GPU_TXVDDR
VOLTAGE=2.5V
PP2V5_S0_GPU_TPVDDMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.2 mm
VOLTAGE=2.5V
TMDS_DATA0_P
TMDS_DATA1_P
TMDS_DATA2_P
TMDS_DATA3_P
TMDS_DATA4_P
TMDS_DATA5_P
TMDS_CLK_P
GPU_H2SYNC
GPU_DDC_C_DATAGPU_DDC_C_CLK
LVDS_L_CLK_N
LVDS_U_DATA_P<2>LVDS_U_DATA_N<2>
ATI_R2SETATI_RSET
GPU_DDC_A_DATA
GPU_DDC_B_CLKGPU_DDC_B_DATA
GPU_DDC_A_CLK
NC_LVDS_L_DATAN<3>NC_LVDS_L_DATAP<3>
LVDS_L_DATA_P<2>LVDS_L_DATA_N<2>
LVDS_L_DATA_N<1>
TMDS_DATA3_N
TMDS_DATA4_N
TMDS_DATA5_N
TMDS_DATA2_N
TMDS_DATA1_N
TMDS_DATA0_N
TMDS_CLK_N
LVDS_U_DATA_N<0>LVDS_U_DATA_P<0>
LVDS_U_CLK_NLVDS_U_CLK_P
TP_GPU_VGA_HSYNCTP_GPU_VGA_VSYNC
LVDS_L_DATA_N<0>LVDS_L_DATA_P<1>
LVDS_L_DATA_P<0>
LVDS_L_CLK_P
LVDS_U_DATA_P<1>LVDS_U_DATA_N<1>
NC_LVDS_U_DATAP<3>NC_LVDS_U_DATAN<3>
GPU_HPD
ATI_RSET
ATI_R2SET
GPU_V2SYNC
GPU_B2GPU_G2GPU_R2
NC_GPU_VGA_BNC_GPU_VGA_GNC_GPU_VGA_R
NC_GPU_TV_Y
NC_GPU_TV_COMP
NC_GPU_TV_C
76 66 65 62 19 17 5
5
5
5
5
5
5
77
77
77
77
N-CHN
S
D
G
P-CHN
G
DS
G
D
S
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
LCD (LVDS) INTERFACE
no-panel case (development)
INVERTER EXPECTS ACTIVE HIGH PWM SIGNAL
518S0289
518S0293
NCPanel has 2K pull-ups
100K pull-ups are for
NET_TYPE
NC
NC
INVERTER INTERFACE
PHYSICALELECTRICAL_CONSTRAINT_SET SPACING
R94501
2
100K
MF-LF402
5%1/16W
C9454 1
2
0.001uF
CERM402
20%50V
C94521
2 50V20%
402CERM
0.001uF
C94501
2 CERM
0.001uF50V20%
402
C9451 1
2
10UF
X5R603
20%6.3V
L9450
1 2
SM
FERR-1K-OHM-EMI
L9454
1 2
SM-1
400-OHM-EMI
C9453 1
210V20%
402CERM
0.1uF
INVERTER_BUF
L9452
1 2
SM-1
400-OHM-EMI
C9420 1
2
0.001uF
CERM
20%50V
402
R94101
2
1/16W5%
402MF-LF
100K
C9410 1
2402
0.001uF
CERM
20%50V
R94111
2
1/16W5%
402MF-LF
100K
C942112
0.001uF
20%
CERM402
50V
J9400
33
34
1
10
11
12
13
14
15
16
17
18
19
2
20
21
22
23
24
25
26
27
28
29
3
30
4
5
6
7
8
9
MSC-RB30-5-FAF-RT-SM
CRITICAL
L9455
1
2
SM60-OHM-EMI
C94551
2
0.001uF
402
20%50VCERM
C9401 1
2
0.001uF
CERM
20%50V
402
L9400
SM
FERR-250-OHM
C94001 2
50VCERM
0.0022uF
10%
402R9401100K
MF-LF402
1/16W5%
R94001
2MF-LF
402
5%1/16W
100K
Q9400
12563
4
SI3443DVTSOP-LF
R94891
2
5%1/16WMF-LF
402
10K
R94941
2
100K
402MF-LF1/16W
5%
R94961 2
INVERTER_UNBUF
5%1/16W
402
0
MF-LF
U9453
3
2
1
4
5 MC74VHC1G08SC70
INVERTER_BUF
J94505
6
1
2
3
4
SM-2MT-LF
CRITICAL
Q9450
6
2
1
SC70-6FDG6332C_NL
Q9450
3
5
4
SC70-6FDG6332C_NL
Q94016
2
1
2N7002DW-X-FSOT-363
SYNC_DATE=01/09/2006SYNC_MASTER=M1_MLB
78 86
06051-7023
Internal Display Connectors
LCD_PWREN_L
GPU_DIGON
GND_INVERTERMIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mmVOLTAGE=0V
PP5V_INVERTER_SWMIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mmVOLTAGE=5V
GPU_DDC_C_DATA
GPU_B2VGA VGA
GPU_G2VGA VGA
GPU_R2VGA VGA
LVDS_U_DATA_N<2..0>LVDS LVDS
LVDS_U_DATA_P<2..0>LVDS LVDS
LVDS_U_CLK_NLVDSLVDS
LVDS_U_CLK_PLVDSLVDS
LVDS_L_DATA_N<2..0>LVDSLVDS
LVDS_L_DATA_P<2..0>LVDS LVDS
LVDS_L_CLK_NLVDS LVDS
LVDS_L_CLK_PLVDSLVDS
TMDS_DATA_P<5..3>TMDS TMDSTMDS_DATA_N<5..3>TMDS TMDS
TMDS_DATA_N<2..0>TMDS TMDS
TMDS_DATA_P<2..0>TMDS TMDS
TMDS_CLK_NTMDS TMDS
TMDS_CLK_PTMDS TMDS
LVDS_L_DATA_CONN_N<2..0>LVDS LVDS
LVDS_L_DATA_CONN_P<2..0>LVDSLVDS
LVDS_L_CLK_NLVDSLVDS
LVDS_L_CLK_PLVDS LVDS
LVDS_U_DATA_CONN_N<2..0>LVDSLVDS
LVDS_U_DATA_CONN_P<2..0>LVDSLVDS
LVDS_U_CLK_NLVDS LVDS
LVDSLVDS LVDS_U_CLK_P
LVDS_U_CLK_PLVDS_U_CLK_N
LVDS_U_DATA_CONN_P<2>LVDS_U_DATA_CONN_N<2>
LVDS_U_DATA_CONN_P<1>LVDS_U_DATA_CONN_N<1>
LVDS_U_DATA_P<0>
LVDS_L_DATA_CONN_N<1>LVDS_L_DATA_CONN_P<1>
LVDS_L_DATA_CONN_N<2>LVDS_L_DATA_CONN_P<2>
LVDS_L_CLK_PLVDS_L_CLK_N
LVDS_U_DATA_N<0>
LVDS_L_DATA_N<0>LVDS_L_DATA_P<0>
PP3V3_S0
GPU_DDC_C_CLK
GPU_VARY_BL
PP3V3_S0
INVERTER_PWM_F
GND_CHASSIS_INVERTER
PPBUS_G3H
PP3V3_S5
LCD_PWREN_L_RC
VOLTAGE=3.3VMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.5 mmPP3V3_LCD_SW
GND_CHASSIS_LVDS
PP3V3_LCD_CONNMIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mmVOLTAGE=3.3V
GND_CHASSIS_LVDS
GND_CHASSIS_LVDS
VOLTAGE=12.8V
MIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mm
PPBUS_S0_INVERTER
FP_PWR_EN_L
GPU_BLON
PP5V_INVERTER_SW_FMIN_LINE_WIDTH=0.5 mm
VOLTAGE=5VMIN_NECK_WIDTH=0.25 mm
PP5V_S0
GND_CHASSIS_LVDS
INVERTER_PWM
79
79
78
78
70
70
66
66
65
65
64
64
60
60
59
59
57
57
56
56
53
53
51
51
48
48
43
43
37
37
36
36
80
34
34
79
33
33
70
29
29
67
28
28
66
27
27
65
26
26
70
61
25
25
68
66
60
24
24
66
65
57
23
23
64
64
56
22
22
63
62
54
21
21
61
55
52
20
20
60
26
47
19
19
54
25
42
17
17
47
24
36
14
14
43
23
31
81
81
81
81
81
81
81
81
86
86
81
81
81
81
81
81
81
81
81
81
81
81
10
10
41
22
25
79
79
79
78
78
78
78
78
78
78
78
79
79
81
81
78
78
81
81
78
78
78
78
81
81
81
81
78
81
81
81
81
78
78
78
78
78
5
5
5
11
78
78
78
76
5
78
76
77
77
77
77
77
77
77
77
77
77
77
77
86
86
86
86
77
77
78
78
77
77
78
78
77
77
77
77
78
78
78
78
77
78
78
78
78
77
77
77
77
77
4
77
76
4 6
4
5
6
6
6
73
4
6
G
SD
G
SD
G
SD
LCFILTER
LCFILTER
LCFILTERSYM_VER-1
SYM_VER-1
SYM_VER-1
SYM_VER-1
SYM_VER-1
SYM_VER-1
SYM_VER-1
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
TMDS FilteringPlace series R’s and common-mode filtering close to GPU, common mode chokes near connector.
PLACE CLOSE TO CONNECTORANALOG FILTERING
(DAC2 C)
(DAC2 Y)
(DAC2 Comp)
3V LEVEL SHIFTERS
(55mA requirement per DVI spec)DVI INTERFACEDVI DDC CURRENT LIMIT
Isolation required for DVI power switch
VGA SYNC BUFFERS
PLACE R9750 & R9751 CLOSE TO DVI CONNECTOR
(PP5V_S0_DDC)
PLACE NEAR C5A & C5B
PLACE NEAR 3, 11 & 19
514-0278
R97211
2
1/16W5%
MF-LF
10K
402
R97201
2
1/16W5%
402MF-LF
10K
Q9711
6
2
1
SOT-3632N7002DW-X-F
Q9711
3
5
4
SOT-3632N7002DW-X-F
R97221
2
1/16W5%
402MF-LF
100KC97131
2 50V5%
402CERM
100pF
R97121
2
4.7K
MF-LF402
5%1/16W
R97101
2
1/16W5%
402MF-LF
4.7K
C97111
2
100pF
CERM402
5%50V
C9710 1
2
0.01uF
CERM603
20%50V
L9710
1 2
400-OHM-EMI
SM-1
Q9714
3
5
4
SOT-3632N7002DW-X-F
F97101 2
SM-LF
CRITICAL
0.5AMP-13.2V
D97101 2
B0530WXF
SOD-123
C97141
2402
100pF
CERM
5%50V
R97111 2100
MF-LF402
5%1/16W
R97131 2100
MF-LF402
5%1/16W
R97141 2100
MF-LF402
5%1/16W
R973012
0
MF-LF402
5%1/16WR9731
120
MF-LF
5%1/16W
402
C97411
2
3.3pF
CERM402
0.25%50V
R97421
2
1/16W1%
402MF-LF
75
R97401
2
1/16W1%
402MF-LF
75
R97411
2
1/16W1%
402MF-LF
75
C97421
2
3.3pF
CERM402
0.25%50V
C97401
2
3.3pF
CERM402
0.25%50V
FL9740
1 2
3 4
CRITICAL
SM-220MHZ-LF
FL9741
1 2
3 4
SM-220MHZ-LF
CRITICAL
FL9742
1 2
3 4
CRITICAL
SM-220MHZ-LF
L9702
1
2 3
4
2012H90-OHM-300mA
CRITICAL
L9701
1
2 3
4
CRITICAL
90-OHM-300mA2012H
R97501 2
33
5%1/16WMF-LF402
R97511 2
1/16W5%
402MF-LF
33
L9703
1
2 3
4
90-OHM-300mA2012H
CRITICAL
L9704
1
2 3
4
90-OHM-300mA2012H
CRITICAL
L9705
1
2 3
4
2012H90-OHM-300mA
CRITICAL
L9700
1
2 3
4
90-OHM-300mA2012H
CRITICAL
J9700
C1
C2
C3
C4
C5AC5B
31
32
33
34
1
10
11
12
13
14
15
16
17
18
19
2
20
21
22
23
24
3
4
5
6
7
8
9
QH11121-RIG02-4F
CRITICAL
F-RT-TH-DVI
R97151
2
5%1/16WMF-LF
402
20K
R97871
2
1%1/16WMF-LF
402
90.9R97861
2MF-LF402
1/16W1%90.9
R97851 2
402
0
MF-LF1/16W5%
R97841 2
402
0
MF-LF1/16W5%
C97861 2
50V
0.001uF
402CERM
10%
R97831
2
1%1/16WMF-LF
402
90.9R97821
2 402MF-LF1/16W1%90.9
R97801 2
0
402MF-LF1/16W5% R9781
1 20
402MF-LF1/16W5%
C97821 2
10%50VCERM402
0.001uF
R97791
2402
1%1/16WMF-LF
90.9
R97771 2
0
402MF-LF1/16W5%
R97761 2
0
402MF-LF1/16W5%
R97781
2
1/16WMF-LF402
1%90.9
C97781 2
10%50VCERM402
0.001uF
R97751
2
1%1/16WMF-LF
402
90.9R97741
2MF-LF402
1/16W1%90.9
R97731 2
402
1/16W5%
0
MF-LF
R97721 2
5%
402
0
MF-LF1/16W
C97741 2
0.001uF
402CERM50V10%
R97711
2
1%1/16WMF-LF
402
90.9R97701
2 402MF-LF1/16W1%90.9
R97691 2
402
1/16W
0
MF-LF
5%
C97701 2
0.001uF
10%50VCERM402
R97681 2
1/16WMF-LF
0
402
5%
R97671
2MF-LF
1%1/16W
402
90.9R97661
2
1%1/16WMF-LF402
90.9
R97651 2
5%1/16WMF-LF
0
402
C97661 2
402
10%50VCERM
0.001uF
R97641 2
5%1/16WMF-LF
0
402
R97631
2
1%1/16WMF-LF
402
90.9R97621
2
1%1/16WMF-LF402
90.9
R97611 2
402MF-LF1/16W5%
0
C97621 2
0.001uF
10%50VCERM402
R97601 2
0
402
1/16W5%
MF-LF
L9706
1
2 3
4
370-OHMSM
CRITICAL
C9751 1
2402
0.1uF
CERM10V20%
C9750 1
2
0.1uF
402CERM10V20%
U9750
3
2
1
4
5SC70
MC74VHC1G08
U9751
3
2
1
4
5SC70
MC74VHC1G08
SYNC_DATE=11/18/2005SYNC_MASTER=M1_MLB
External Display Connector
051-7023 06
8679
TMDS_DATA1_PMAKE_BASE=TRUETMDS_DATA1_P
TMDS_DATA1_R_NNET_SPACING_TYPE=TMDSNET_PHYSICAL_TYPE=TMDS
GND_CHASSIS_DVI_BOT
TMDS_DATA0_F_N
TMDS_CLK_F_P
GNDGND_CHASSIS_DVI_BOT
TMDS_DATA0_F_P
DVI_DDC_CLK_R
DVI_DDC_DATA_R
VGA_VSYNC
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.38 mmVOLTAGE=5VPP5V_S0_DDC
TMDS_DATA5_F_NNET_SPACING_TYPE=TMDSCONNNET_PHYSICAL_TYPE=TMDSCONN
TMDS_DATA5_F_PNET_SPACING_TYPE=TMDSCONNNET_PHYSICAL_TYPE=TMDSCONN
TMDS_DATA5_R_PNET_SPACING_TYPE=TMDSNET_PHYSICAL_TYPE=TMDS
TMDS_DATA5_R_NNET_SPACING_TYPE=TMDSNET_PHYSICAL_TYPE=TMDS
TMDS_DATA4_F_NNET_SPACING_TYPE=TMDSCONNNET_PHYSICAL_TYPE=TMDSCONN
TMDS_DATA4_F_PNET_SPACING_TYPE=TMDSCONNNET_PHYSICAL_TYPE=TMDSCONN
TMDS_DATA4_R_PNET_SPACING_TYPE=TMDSNET_PHYSICAL_TYPE=TMDS
TMDS_DATA4_R_NNET_SPACING_TYPE=TMDSNET_PHYSICAL_TYPE=TMDS
TMDS_DATA3_F_NNET_SPACING_TYPE=TMDSCONNNET_PHYSICAL_TYPE=TMDSCONN
TMDS_DATA3_F_PNET_SPACING_TYPE=TMDSCONNNET_PHYSICAL_TYPE=TMDSCONN
TMDS_DATA3_R_PNET_SPACING_TYPE=TMDSNET_PHYSICAL_TYPE=TMDS
TMDS_DATA3_R_NNET_SPACING_TYPE=TMDSNET_PHYSICAL_TYPE=TMDS
TMDS_CLK_F_NNET_SPACING_TYPE=TMDSCONNNET_PHYSICAL_TYPE=TMDSCONN
TMDS_CLK_F_PNET_SPACING_TYPE=TMDSCONNNET_PHYSICAL_TYPE=TMDSCONN
TMDS_CLK_R_PNET_SPACING_TYPE=TMDSNET_PHYSICAL_TYPE=TMDS
TMDS_CLK_R_NNET_PHYSICAL_TYPE=TMDSNET_SPACING_TYPE=TMDS
TMDS_DATA2_F_NNET_SPACING_TYPE=TMDSCONNNET_PHYSICAL_TYPE=TMDSCONN
TMDS_DATA2_R_PNET_SPACING_TYPE=TMDSNET_PHYSICAL_TYPE=TMDS
TMDS_DATA2_R_NNET_SPACING_TYPE=TMDSNET_PHYSICAL_TYPE=TMDS
TMDS_DATA1_F_PNET_SPACING_TYPE=TMDSCONNNET_PHYSICAL_TYPE=TMDSCONN
TMDS_DATA0_F_NNET_SPACING_TYPE=TMDSCONNNET_PHYSICAL_TYPE=TMDSCONN
TMDS_DATA0_F_PNET_SPACING_TYPE=TMDSCONNNET_PHYSICAL_TYPE=TMDSCONN
GPU_V2SYNC
VGA_R
GND_CHASSIS_DVI_TOP
PP3V3_S0
PP3V3_S0
GPU_H2SYNCVGA_HSYNC_R
VGA_VSYNC_R VGA_VSYNC
DVI_HPD_R
VGA_HSYNC
GPU_R2
GPU_G2 VGA_G
VGA_R
VGA_B
VOLTAGE=0.275VTMDS_D2_CMF
PP5V_S0
VOLTAGE=5VPP5V_S0_DDC_PULLUPSMIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.25 mm
GPU_DDC_A_CLK
GPU_DDC_A_DATA
GPU_HPD
GND_CHASSIS_DVI_TOP
PP5V_S0_DDC_FVOLTAGE=5VMIN_LINE_WIDTH=0.38 mmMIN_NECK_WIDTH=0.25 mm
DVI_HPD
DVI_DDC_CLK
DVI_DDC_DATA
TMDS_CLK_F_N
VGA_B
VGA_HSYNC
VOLTAGE=0.275VTMDS_D0_CMF
VOLTAGE=0.275VTMDS_D1_CMF
VOLTAGE=0.275VTMDS_CLK_CMF
VOLTAGE=0.275VTMDS_D3_CMF
VOLTAGE=0.275VTMDS_D4_CMF
VOLTAGE=0.275VTMDS_D5_CMF
TMDS_CLK_N
PP3V3_S0
TMDS_DATA1_R_PNET_SPACING_TYPE=TMDSNET_PHYSICAL_TYPE=TMDS
TMDS_DATA1_F_NNET_SPACING_TYPE=TMDSCONNNET_PHYSICAL_TYPE=TMDSCONN
TMDS_DATA2_F_PNET_SPACING_TYPE=TMDSCONNNET_PHYSICAL_TYPE=TMDSCONN
TMDS_CLK_P
VGA_G
TMDS_DATA2_F_NTMDS_DATA1_F_N
TMDS_DATA1_F_P
TMDS_DATA3_F_PTMDS_DATA4_F_PTMDS_DATA3_F_NTMDS_DATA4_F_N
TMDS_DATA2_F_P
GPU_B2
TMDS_DATA0_N
TMDS_DATA0_P
MAKE_BASE=TRUETMDS_DATA0_N
TMDS_DATA0_PMAKE_BASE=TRUE
TMDS_DATA1_N
MAKE_BASE=TRUETMDS_DATA1_N
TMDS_DATA2_P
TMDS_DATA2_N
MAKE_BASE=TRUETMDS_DATA2_N
MAKE_BASE=TRUETMDS_DATA2_P
TMDS_DATA3_N
MAKE_BASE=TRUETMDS_DATA3_N
MAKE_BASE=TRUETMDS_DATA3_P
TMDS_DATA3_P
TMDS_DATA4_N
MAKE_BASE=TRUETMDS_DATA4_N
MAKE_BASE=TRUETMDS_DATA4_P
TMDS_DATA4_P
TMDS_DATA5_N
MAKE_BASE=TRUETMDS_DATA5_N
MAKE_BASE=TRUETMDS_DATA5_P
TMDS_DATA5_P
NET_PHYSICAL_TYPE=TMDSNET_SPACING_TYPE=TMDSTMDS_DATA0_R_P
TMDS_DATA0_R_NNET_PHYSICAL_TYPE=TMDSNET_SPACING_TYPE=TMDS
TMDS_DATA5_F_P
TMDS_DATA5_F_N
79
79
79
78
78
78
70
70
70
66
66
66
65
65
65
64
64
64
60
60
60
59
59
59
57
57
57
56
56
56
53
53
53
51
51
51
48
48
48
43
43
43
37
37
37
36
36
80
36
34
34
78
34
33
33
70
33
29
29
67
29
28
28
66
28
27
27
65
27
26
26
61
26
25
25
60
25
24
24
57
24
23
23
56
23
22
22
54
22
21
21
52
21
20
20
47
20
19
19
42
19
17
17
36
17
79
14
14
31
14
44
10
10
25 86
10
86
79
79
40
86
86
86
79
5
5
78
78
5
79
86
78
5
78
78
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
77
77
6
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
79
77
79
6
4
4
77
79
79
77
77 79
79
79
4
77
77
77
6
79
79
79
77
4
79
79
77
79
79
79
79
79
79
79
79
79
77
77
77
77
77
77
77
77
77
77
77
77
77
77
77
77
77
77
77
77
77
77
77
79
79
BI
BI
IN
IN
IN
OUT
OUT
BI
BISYM_VER-2
SYM_VER-2
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
518S0388
516S0350
NC
NC
NC
Bluetooth (M13P) & SATA HDD Flex Connector
IR & Sleep LED Connector
6 22
J4960
1
10
1112
1314
1516
2
34
56
78
9
QT500166-L020M-ST-SM
CRITICAL
6 22
21
21
C49612 1
402
25VCERM
0.0047uF
10%
PLACEMENT_NOTE=Place C4961 next to C4960
C49602 1
0.0047uF
10%
CERM25V
402
PLACEMENT_NOTE=Place C4960 close to southbridge
51
21
21
6 22
6 22
FL4960
1
2 3
42012H
90-OHM-300mA
PLACEMENT_NOTE=Place FL4960 close to southbridge
FL4965
1
2 3
42012H
90-OHM-300mA
PLACEMENT_NOTE=Place FL4965 close to J4960
C49662 1
0.0047uF
402
25VCERM
10%
PLACEMENT_NOTE=Place C4965 close to J4960
C49652 1
0.0047uF
10%
CERM25V
402
PLACEMENT_NOTE=Place C4966 next to C4965
J9800
7
8
1
2
3
4
5
6
53780-0670M-RT-SM
CRITICAL
80 86
06051-7023
SYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)
M9 Specific Connectors
PP5V_S3
USB_IR_NUSB_IR_P
SYS_LED_ANODE
PP3V3_S3
PP5V_S0
USB_BT_PUSB_BT_N
SATA_C_R2D_C_P
SATA_C_R2D_C_N
SATA_C_D2R_P
SATA_C_D2R_N
SATA_C_R2D_PSATA_C_R2D_N
SATA_C_D2R_UF_NSATA_C_D2R_C_N
SATA_C_D2R_UF_P
SATA_C_D2R_C_P
SATA_C_R2D_UF_N
SATA_C_R2D_UF_P
79 78 70 67 66
66
65
64
61
63
60
62
57
59
56
58
54
56
52
51
47
45
42
66
41
36
61
37
31
51
32
25
45
27
5
5
5
4
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
on LVDS signals when they should be 0V.the pump-up in the panel, though some voltage will still be seen
requirements. Resulting pump-up in LCD panel can cause startup
M56 part. Bias voltage is present on LVDS interface pins evenNOTE: These parts are to counter an invalid state caused by the
LVDS Interface Pull-downs
when they should be tri-stated to meet panel power sequence
and long-term reliability issues. Pull-down resistors reduce
RP99021 88.2K
SM-LF
LVDS_PD
1/16W5%
RP99023 68.2K
SM-LF
LVDS_PD
1/16W5%
RP99024 58.2K
SM-LF
LVDS_PD
5%1/16W
RP99032 78.2K
SM-LF
LVDS_PD
1/16W5%
RP99031 88.2K
SM-LF
LVDS_PD
5%1/16W
RP99033 68.2K
SM-LF
LVDS_PD
1/16W5%
RP99034 58.2K
SM-LF
LVDS_PD
5%1/16W
RP99001 8
SM-LF
8.2K
LVDS_PD
5%1/16W
RP99004 5
SM-LF1/16W5%
LVDS_PD
8.2K
RP99014 58.2K
SM-LF
LVDS_PD
5%1/16W
RP99011 8
1/16W5%
LVDS_PD
SM-LF
8.2K
RP99013 68.2K
LVDS_PD
1/16W5%
SM-LF
RP99003 6
SM-LF
8.2K
1/16W
LVDS_PD
5%
RP99002 7
SM-LF
8.2K
LVDS_PD
1/16W5%
RP99012 7
SM-LF
5%1/16W
LVDS_PD
8.2K
RP99022 78.2K
SM-LF
LVDS_PD
5%1/16W
LVDS Interface Pull-downsSYNC_DATE=12/19/2005SYNC_MASTER=M1_MLB
81 86
06051-7023
LVDS_L_DATA_CONN_N<2>
LVDS_L_DATA_CONN_P<2>
LVDS_L_DATA_N<0>
LVDS_L_DATA_P<0>
LVDS_L_CLK_PLVDS_L_CLK_PMAKE_BASE=TRUE
LVDS_U_DATA_CONN_P<1>
LVDS_L_DATA_CONN_N<1>
LVDS_L_CLK_N
LVDS_U_DATA_P<0>
LVDS_U_DATA_N<0>
LVDS_U_DATA_CONN_N<1>
LVDS_L_DATA_CONN_P<1>
LVDS_U_DATA_CONN_P<2>
LVDS_U_DATA_CONN_N<2>
LVDS_U_CLK_P
LVDS_U_CLK_N
MAKE_BASE=TRUELVDS_L_DATA_P<0>
MAKE_BASE=TRUELVDS_L_DATA_N<0>
LVDS_L_DATA_P<1>MAKE_BASE=TRUE
MAKE_BASE=TRUELVDS_L_DATA_P<2>
MAKE_BASE=TRUELVDS_L_DATA_N<2>
LVDS_L_CLK_NMAKE_BASE=TRUE
LVDS_U_DATA_P<0>MAKE_BASE=TRUE
MAKE_BASE=TRUELVDS_U_DATA_N<0>
LVDS_U_DATA_P<1>MAKE_BASE=TRUE
LVDS_U_DATA_N<1>MAKE_BASE=TRUE
MAKE_BASE=TRUELVDS_U_DATA_P<2>
MAKE_BASE=TRUELVDS_U_DATA_N<2>
LVDS_U_CLK_PMAKE_BASE=TRUE
LVDS_U_CLK_NMAKE_BASE=TRUE
LVDS_L_DATA_N<1>MAKE_BASE=TRUE
81
81
81 81
81
81
81
81
81
81
81
81
81
81
81
81
78
78
78 78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
77
77
77 77
78
78
77
77
77
78
78
78
78
77
77
77
77
77
77
77
77
77
77
77
77
77
77
77
77
77
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
12-01-05: -Changed L4400 to Pb-free part-Changed J4620 to M9 part
-Added PM_SUS_STAT_L and PM_SLP_S5_L pulldowns-Removed dual voltage support for trackpad-Added ESD/EMI protection to camera connector
EVT
Proto
-Changed IDE reset pulldown to 15K-RC value changes on CPU Core current sense
12-01-05:
11-30-05:
11-29-05:
Revision History
-Turned on M56_REV_B24 BOMOPTION
-Added CRITICAL property to 3-pin caps, ESD diodes, and FW chokes-Added ITPCONN BOMOPTION
-Release for Proto
Revision HistorySYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)
051-7023 06
8682
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
Worst-case spacing is 2:1 within Data bus, with 3:1 spacing to the DSTBs.DSTB complementary pairs are spaced 3:1, even in constraint areas.
Worst-case spacing is 2:1 within Addr bus, with 3:1 spacing to the ADSTBs.
Disk Interface Constraints
SOURCE: Napa Platform DG, Rev 0.9 (#17978), Sections 10.6 & 10.7.2
SOURCE: Napa Platform DG, Rev 0.9 (#17978), Sections 7.2, 9.2 & 10.5.2
PCI-Express / DMI Bus Constraints
Design Guide recommends FSB signals be routed only on internal layers.
SOURCE: Napa Platform DG, Rev 0.9 (#17978), Section 10.10.1.2
Internal Interface Constraints
DG says minimum spacing 50 mils to clocks
SOURCE: Napa Platform DG, Rev 0.9 (#17978), Section 10.9.1
Audio Interface Constraints
SOURCE: Napa Platform DG, Rev 0.9 (#17978), Section 6.2
SOURCE: Napa Platform DG, Rev 0.9 (#17978), Sections 4.4, 4.6.2, & 5.8.2.4
Need to support MEM_*-style wildcards!
Some signals require 27.4-ohm single-ended impedance.
NOTE: Design Guide allows closer spacing if signal lengths can be shortened.
Design Guide recommends each strobe/signal group is routed on the same layer.
NOTE: Design Guide does not indicate FSB spacing to other signals, assumed 3:1.
All FSB signals with impedance requirements are 55-ohm single-ended.
CPU Signal Constraints
DDR2 Memory Bus Constraints
Most CPU signals with impedance requirements are 55-ohm single-ended.
USB 2.0 Interface Constraints
Clock Signal Constraints
SOURCE: Napa Platform DG, Rev 0.9 (#17978), Section 10.17.1.1
FSB (Front-Side Bus) Constraints
SOURCE: Napa Platform DG, Rev 0.9 (#17978), Sections 4.2 & 4.3
DG recommends at least 25 mils, >50 mils preferred
=3:1_SPACING*FSB_DSTB ?
=3:1_SPACING*FSB_DATA2DSTB ?
=2:1_SPACING*FSB_DATA2DATA ?
=3:1_SPACINGFSB_DATA * ?
Napa Platform ConstraintsSYNC_DATE=02/10/2006SYNC_MASTER=M1_MLB
051-7023 06
8683
**MEM_DATA MEM_2OTHER
* *MEM_CMD MEM_2OTHER
?PCIE * 20 MIL
?DMI * 20 MIL
AUDIO_55S * Y =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD
?AUDIO * =1.8:1_SPACING
=STANDARD=STANDARD=55_OHM_SE=55_OHM_SE=55_OHM_SEY*SPI_55S
?USB2 =4:1_SPACING*
=STANDARD=STANDARD=55_OHM_SE=55_OHM_SE=55_OHM_SEY*SMB_55S
?USB2_2CLK * 25 MIL
=STANDARD=STANDARD=55_OHM_SE=55_OHM_SEY*CLK_SLOW_55S =55_OHM_SE
?* =2:1_SPACINGMEM_CTRL2CTRL
* *MEM_DQS MEM_2OTHER
?*MEM_2OTHER 25 MIL
?MEM_CLK2MEM =4:1_SPACING*
=85_OHM_DIFF =85_OHM_DIFF* =85_OHM_DIFF=85_OHM_DIFFMEM_85D Y =85_OHM_DIFF
=55_OHM_SE =55_OHM_SE =STANDARD=STANDARDMEM_55S Y* =55_OHM_SE
?*CPU_GTLREF 25 MIL
?CPU_COMP * 25 MIL
?=3:1_SPACINGFSB_ADSTB *
* Y =27P4_OHM_SE =27P4_OHM_SE =27P4_OHM_SE =STANDARD =STANDARDCPU_27P4S
* =STANDARD=45_OHM_SE =STANDARDMEM_45S Y =45_OHM_SE =45_OHM_SE
*MEM_CLK MEM_CTRL2MEMMEM_CTRL
MEM_CTRL MEM_CTRL2CTRL*MEM_CTRL
?=3:1_SPACING*MEM_CTRL2MEM
?IDE =1.8:1_SPACING*
?CPU_2TO1 * =2:1_SPACING
FSB_DSTBFSB_DATA * FSB_DATA2DSTB
*FSB_ADDR FSB_ADDR FSB_ADDR2ADDR SATA_100D Y* =100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF
IDE_55S * Y =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD
MEM_DQS *MEM_CMD MEM_CMD2MEM
?=2:1_SPACING*FSB_COMMON
* YDMI_100D =100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF
Y*PCIE_100D =100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF
?CLK_SLOW * 10 MIL
?CLK_MED * 20 MIL
?=3:1_SPACING*SMB
MEM_CTRL MEM_CTRL2MEM*MEM_CMD
?*MEM_DATA2DATA =1.5:1_SPACING
?* =3:1_SPACINGMEM_DATA2MEM
?=3:1_SPACING*MEM_DQS2MEM
* *MEM_CLK MEM_2OTHER
**MEM_CTRL MEM_2OTHER
MEM_DATA * MEM_DQS2MEMMEM_DQS
FSB_ADDR2ADSTBFSB_ADDR FSB_ADSTB *
?SATA * 20 MIL
Y*USB2_90D =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF
FSB_55S =55_OHM_SE* =55_OHM_SEY =55_OHM_SE =STANDARD =STANDARD
?CLK_PCIE * 20 MIL
?=3:1_SPACING*MEM_CMD2MEM
?CLK_FSB * 25 MIL
=70_OHM_DIFFMEM_70D =70_OHM_DIFF =70_OHM_DIFF=70_OHM_DIFF* Y =70_OHM_DIFF
CPU_55S =55_OHM_SE=55_OHM_SE* =55_OHM_SEY =STANDARD =STANDARD
=STANDARD=STANDARD=55_OHM_SEY*CLK_MED_55S =55_OHM_SE=55_OHM_SE
Y* =100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFFCLK_PCIE_100D =100_OHM_DIFF
Y* =100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFFCLK_FSB_100D =100_OHM_DIFF
?=1.8:1_SPACINGSPI *
?=1.5:1_SPACING*MEM_CMD2CMD
MEM_DQSMEM_DQS MEM_DQS2MEM*
MEM_CLK MEM_CMD2MEM*MEM_CMD
*MEM_DATA MEM_DATA MEM_DATA2DATAMEM_DATA MEM_CMD2MEMMEM_CMD *
MEM_CMD MEM_CLK2MEMMEM_CLK *
MEM_CLK MEM_CTRL MEM_CLK2MEM*
MEM_CLK MEM_CLK MEM_CLK2MEM*
MEM_CLK * MEM_DQS2MEMMEM_DQS
MEM_CTRL * MEM_DQS2MEMMEM_DQS
MEM_CMDMEM_DQS MEM_DQS2MEM*
MEM_DQS MEM_CLK2MEMMEM_CLK *
MEM_CTRL MEM_DATA2MEMMEM_DATA *
MEM_CLKMEM_DATA MEM_DATA2MEM*
MEM_CMD *MEM_DATA MEM_DATA2MEM
MEM_DQS *MEM_DATA MEM_DATA2MEM
MEM_CTRL MEM_CMD2MEMMEM_CMD *
MEM_CMD2CMDMEM_CMDMEM_CMD *
MEM_CTRL2MEM*MEM_CTRL MEM_DQS
MEM_CTRL * MEM_CTRL2MEMMEM_DATAMEM_DATA *MEM_CLK MEM_CLK2MEM
?CPU_VCCSENSE * 25 MIL
?=2:1_SPACING*CPU_ITP
FSB_DATA2DATAFSB_DATA *FSB_DATA
?=3:1_SPACING*FSB_ADDR2ADSTB
?=2:1_SPACINGFSB_ADDR2ADDR *
?FSB_ADDR =3:1_SPACING*
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
Video Signal ConstraintsSOURCE: ATI Layout Guide, Rev 0.5 (DSG-216MOBRADEON-05), Sections 7 & 8.1.2.
note
DQ/DQM/DQS lines are 40-ohm single-ended impedence.CTRL lines are 55-ohm single-ended impedence.
LVDS and TMDS signals are 100-ohm +/- 10% differential impedence.LVDS and TMDS pairs should be kept at least 25 mils apart.Ground shields can be used around each pair if spacing cannot be met.
Ground shields recommended around VGA signals.
VGA should be routed as close to 75-ohms single-ended impedence as possible.
SOURCE: ATI Layout Guide, Rev 0.5 (DSG-216MOBRADEON-05), Sections 7 & 8.1.2.
NOTE: Layout Guide does not specify LVDS/TMDS spacing to other traces other than "do not run close"
High-Speed I/O Interface Constraints
PCI Bus Constraints
NOTE: CLK lines are specified in Layout Guide as 40-ohm single-ended. We treat as 75-ohm differential.
GDDR3 (Frame Buffer) Memory Bus Constraints
ADDR/CTRL lines should route 35-ohms to T, then 55-ohms to each VRAM device.
NOTE: Layout Guide does not specify LVDS/TMDS spacing to other traces other than "do not run close"
VGA signals should be kept at least 15 mils from other traces.
*TMDS_PAIR2PAIR 25 MIL ?
*LVDS_PAIR2PAIR 25 MIL ?
051-7023 06
8684
More System ConstraintsSYNC_MASTER=M1_MLB SYNC_DATE=02/10/2006
Y =55_OHM_SE =STANDARD=STANDARD=55_OHM_SE* =55_OHM_SEFB_55S
FB_35S_TO_55S =35_55_OHM_SE =STANDARD=STANDARD* Y =35_OHM_SE =55_OHM_SE
=100_OHM_DIFFTMDS_100D * Y =100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF
?=3:1_SPACINGENET *
?=3:1_SPACINGFW *
?15 MIL*VGA
?=3:1_SPACING*TMDS
?* =3:1_SPACINGLVDS
=STANDARD* Y =STANDARD=75_OHM_SE =75_OHM_SE =75_OHM_SEVGA_75S
FB_40S =40_OHM_SE* =STANDARD =STANDARD=40_OHM_SE=40_OHM_SEY
?FB_CLK =2.5:1_SPACING*
TMDS TMDS_PAIR2PAIR*TMDS
=100_OHM_DIFFLVDS_100D Y* =100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF
FB_75D =75_OHM_DIFF=75_OHM_DIFF=75_OHM_DIFF=75_OHM_DIFF=75_OHM_DIFFY*
LVDS * LVDS_PAIR2PAIRLVDS
?*PCI =2:1_SPACING
PCI_55S =55_OHM_SE* =55_OHM_SE =STANDARD =STANDARD=55_OHM_SEY
?*FB_ADCTRL =2.5:1_SPACING
?=2.5:1_SPACING*FB_DATA
* Y =110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFFFW_110D
ENET_100D =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF* Y
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
OVERRIDEOVERRIDE OVERRIDE OVERRIDE
TABLE_SPACING_RULE_OVERRIDE
PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPETABLE_PHYSICAL_ASSIGNMENT_HEAD
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE
TABLE_PHYSICAL_RULE_ITEM
OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_BOARD_INFO
VERSIONALLEGRO
(MIL or MM)BOARD UNITSBOARD LAYERS BOARD AREAS
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_ASSIGNMENT_ITEM
TABLE_PHYSICAL_ASSIGNMENT_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_RULE_ITEM
OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_PHYSICAL_ASSIGNMENT_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
OVERRIDEOVERRIDE OVERRIDE OVERRIDE
TABLE_SPACING_RULE_OVERRIDE
TABLE_PHYSICAL_ASSIGNMENT_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
OVERRIDEOVERRIDE OVERRIDE OVERRIDE
TABLE_SPACING_RULE_OVERRIDE
OVERRIDEOVERRIDE OVERRIDE OVERRIDE
TABLE_SPACING_RULE_OVERRIDE
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
OVERRIDEOVERRIDE OVERRIDE OVERRIDE
TABLE_SPACING_RULE_OVERRIDE
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
OVERRIDEOVERRIDE OVERRIDE OVERRIDE
TABLE_SPACING_RULE_OVERRIDE
OVERRIDEOVERRIDE OVERRIDE OVERRIDE
TABLE_SPACING_RULE_OVERRIDE
OVERRIDEOVERRIDE OVERRIDE OVERRIDE
TABLE_SPACING_RULE_OVERRIDE
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
OVERRIDEOVERRIDE OVERRIDE OVERRIDE
TABLE_SPACING_RULE_OVERRIDE
OVERRIDEOVERRIDE OVERRIDE OVERRIDE
TABLE_SPACING_RULE_OVERRIDE
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
M1 Board-Specific Spacing & Physical Constraints
"Stale" physical / spacing types
Unsupported rule
Allow 0.1 MM on blind-to-buried via dogbones (layers 2 & 11)
Rules for "Topology #3" for FSB signals, Napa DG tables 4-7 & 4-12.
PCI_2PCIPCIPCI *
0.1 MMPCI_2PCI * ?0.5 MMMEM_2OTHER * ?
*FSB_DATA2DATA =STANDARD ?
FSB_DATA2DSTB =2:1_SPACING* ?
FSB_DSTB * =2:1_SPACING ?
*FSB_DATA =2:1_SPACING ?
=DEFAULTBGA_P2MM * ?
BGA_P3MM * =DEFAULT ?
=DEFAULT*BGA_P1MM ?
*STANDARD =DEFAULT ?
0.1 MM*DEFAULT ?
0.3 MM3:1_SPACING * ?
0.4 MM4:1_SPACING * ?
2.5:1_SPACING 0.25 MM* ?
1.8:1_SPACING * 0.18 MM ?
0.15 MM1.5:1_SPACING * ?
* 0.2 MM2:1_SPACING ?
ISL2,ISL11 0.1 MMSATA ?
CLK_MED ISL2,ISL11 0.1 MM ?
ISL2,ISL11 0.1 MMMEM_2OTHER ?
PCIE 0.1 MMISL2,ISL11 ?
CLK_PCIE 0.1 MMISL2,ISL11 ?
CLK_FSB ISL2,ISL11 0.1 MM ?
0.1 MMISL2,ISL11VGA ?
ISL2,ISL11 0.1 MMTMDS_PAIR2PAIR ?
CPU_GTLREF 0.1 MMISL2,ISL11 ?
CPU_COMP ISL2,ISL11 0.1 MM ?
ISL2,ISL11 0.1 MMDMI ?
CPU_VCCSENSE ISL2,ISL11 0.1 MM ?
0.1 MMISL2,ISL11LVDS_PAIR2PAIR ?
CLK_SLOW 0.1 MMISL2,ISL11 ?
?FSB_ADDR2ADDR * =STANDARD
?=2:1_SPACING*FSB_ADDR
?4:1_SPACING ISL2,ISL11 0.1 MM
=STANDARD =STANDARD=STANDARDY*45_OHM_SE 0.105 MM0.105 MM
LVDS_100D*LVDS
?=2:1_SPACING*FSB_ADDR2ADSTB
0.090 MM =STANDARD0.090 MM50_OHM_SE =STANDARD=STANDARDY*
75_OHM_SE 0.076 MM 0.076 MM =STANDARD=STANDARDY* =STANDARD
0.130 MM 0.220 MM0.220 MM0.130 MM90_OHM_DIFF YTOP,BOTTOM
Y 0.220 MM0.220 MM0.102 MM0.102 MM90_OHM_DIFF * =STANDARD
0.125 MM0.125 MMTOP,BOTTOM 0.161 MM0.161 MM75_OHM_DIFF Y
0.335 MM 0.335 MM27P4_OHM_SE YTOP,BOTTOM
* BGA BGA_P2MMMEM_CLK
* BGACLK_PCIE BGA_P2MM
BGA_P2MM*CLK_FSB BGA
0.076 MM35_55_OHM_SE * Y =STANDARD =STANDARD0.165 MM =STANDARD
0.240 MM =STANDARD=STANDARD0.240 MM27P4_OHM_SE =STANDARDY*
VGA_75S*VGA
TMDSCONN * * TMDS
SMBI2C * *
STANDARD* *MEM_PP1V8_S3
=STANDARD35_OHM_SE 0.165 MM0.165 MM =STANDARD=STANDARDY*
*MEM_45S 0.100 MM
?2.5:1_SPACING 0.1 MMISL2,ISL11
BGA_P1MMBGA* *
Y55_OHM_SE =STANDARD =STANDARD =STANDARD0.076 MM 0.076 MM*
?3:1_SPACING 0.1 MMISL2,ISL11
?1.5:1_SPACING ISL2,ISL11 0.1 MM
?2:1_SPACING 0.1 MMISL2,ISL11
* BGA BGA_P2MMFB_CLK
BGAFSB_DSTB BGA_P3MMFSB_DSTB
?1.8:1_SPACING 0.1 MMISL2,ISL11
BGA_P2MMBGA*CLK_SLOW
BGA_P2MMCLK_MED BGA*
0.100 MM55_OHM_SE Y 0.100 MMTOP,BOTTOM
TMDSCONN TMDS_100D*
TMDS TMDS_100D*
0.185 MM40_OHM_SE 0.185 MMYTOP,BOTTOM
0.131 MM =STANDARD=STANDARD=STANDARDY*40_OHM_SE 0.100 MM
0.330 MM0.330 MM0.089 MM0.089 MMY110_OHM_DIFF TOP,BOTTOM
0.125 MM0.125 MM0.140 MM0.140 MM80_OHM_DIFF YTOP,BOTTOM
80_OHM_DIFF * =STANDARD 0.125 MM0.125 MM0.111 MM0.115 MMY
* 0.125 MM0.125 MM0.131 MM0.131 MM75_OHM_DIFF Y =STANDARD
70_OHM_DIFF 0.125 MM0.125 MM0.185 MM0.185 MMYTOP,BOTTOM
70_OHM_DIFF 0.125 MM0.125 MM0.149 MM0.149 MM* =STANDARDY
0.200 MM0.200 MM0.099 MM0.099 MM100_OHM_DIFF TOP,BOTTOM Y
0.080 MM 0.200 MM0.200 MM0.080 MM* Y =STANDARD100_OHM_DIFF
0.125 MM0.125 MM0.125 MM0.125 MMY85_OHM_DIFF TOP,BOTTOM
0.101 MM 0.125 MM0.101 MM* Y =STANDARD85_OHM_DIFF 0.125 MM
0.077 MM0.077 MM 0.330 MM0.330 MM110_OHM_DIFF * Y =STANDARD
=DEFAULT =DEFAULT=DEFAULTSTANDARD * =DEFAULTY 12.7 MM
DEFAULT =55_OHM_SE=55_OHM_SE 0 MM0 MMY* 30 MM
FB_PP1V8 STANDARD**
STANDARDGND **
Y 0.230 MMTOP,BOTTOM35_55_OHM_SE 0.100 MM
0.230 MM0.230 MM35_OHM_SE YTOP,BOTTOM
TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM MM 15.2NO_TYPE,BGA
0.124 MM0.124 MM50_OHM_SE YTOP,BOTTOM
0.100 MMMEM_85D *
MEM_70D 0.100 MM*
ENETCONN * * ENET
FSB_ANALOG * FSB_COMMON*
FSB_P2MM FSB_COMMON**
SYNC_DATE=02/10/2006SYNC_MASTER=M1_MLB
051-7023 06
8685
M1 Spacing & Physical Constraints
?=2:1_SPACING*FSB_ADSTB
0.150 MM0.150 MM45_OHM_SE TOP,BOTTOM Y
GND
FSB_ANALOG
PCI PCI_55S
FB_PP1V8
MEM_PP1V8_S3
FSB_P2MM
I2C
DSIZE
OFSHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWINGPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
12345678
12345678
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.SCALE
NONE
ELECTRICAL_CONSTRAINT_SET SPACING
NET_TYPE
PHYSICAL
I70
I71
I72
I73
SYNC_MASTER=M1_MLB
86 86
06051-7023
M1 Net PropertiesSYNC_DATE=02/10/2006
TMDSCONN TMDSCONN TMDS_DATA_F_N<2..0>
TMDSCONN TMDSCONN TMDS_DATA_F_N<5..3>TMDSCONN TMDSCONN TMDS_DATA_F_P<2..0>
TMDSCONN TMDSCONN TMDS_DATA_F_P<5..3>
TMDS TMDS TMDS_DATA_N<2..0>
TMDS TMDS TMDS_DATA_N<5..3>TMDS TMDS TMDS_DATA_P<2..0>
TMDS TMDS TMDS_DATA_P<5..3>
TMDSCONN TMDSCONN TMDS_CLK_F_PTMDSCONN TMDSCONN TMDS_CLK_F_N
FSB_55S FSB_COMMON FSB_LOCK_L
MEM_85DMEM_DQS
FB_75DFB_CLK
SATA_100DSATA
ENET_100DENET
CPU_55S CPU_COMP CPU_COMP<1>
SMB_55SSMB
FSB_55S FSB_COMMON FSB_BPRI_L
CLK_FSB_100D CPU_ITP CPU_XDP_CLK_N
CPU_27P4S CPU_VCCSENSE IMVP6_VSEN_P
CPU_55S CPU_INTR
FSB_55S FSB_ADSTB FSB_ADSTB_L<3..0>
FSB_55S FSB_DATA FSB_D_L<63..0>
FSB_55S FSB_COMMON FSB_DRDY_L
FSB_55S FSB_COMMON FSB_RS_L<2..0>
USB2_90DUSB2
FW_110DFW
CLK_FSB_100DCLK_FSB
FSB_55S FSB_COMMON FSB_TRDY_LFSB_55S FSB_COMMON FSB_CPURST_L
FSB_55S FSB_COMMON FSB_DBSY_L
FSB_55S FSB_DSTB FSB_DSTBP_L<3..0>FSB_55S FSB_DATA FSB_DINV_L<3..0>
FSB_55S FSB_DSTB FSB_DSTBN_L<3..0>
CPU_27P4S CPU_COMP CPU_COMP<2>CPU_55S CPU_COMP CPU_COMP<3>CPU_55S CPU_GTLREF CPU_GTLREF
CPU_55S CPU_2TO1 PM_DPRSLPVR
CPU_55S CPU_IGNNE_LCPU_55S CPU_DPSLP_LCPU_55S CPU_A20M_LCPU_55S CPU_NMI
CPU_55S CPU_PWRGD
CPU_55S CPU_2TO1 IMVP_DPRSLPVR
CPU_55S FSB_FERR_L
FSB_55S FSB_ADDR FSB_A_L<31..3>
CPU_27P4S CPU_VCCSENSETHERM CPU_VCCSENSE_N
CPU_27P4S CPU_VCCSENSE IMVP6_VSEN_N
CPU_27P4S CPU_COMP CPU_COMP<0>
CLK_FSB_100D CPU_ITP CPU_XDP_CLK_PCPU_55S CPU_ITP XDP_BPM_L<5..0>
FSB_55S FSB_COMMON FSB_BREQ0_L
FSB_55S FSB_COMMON FSB_ADS_LMEM_55SMEM_CMD
MEM_70DMEM_CLK
MEM_45SMEM_CTRL
MEM_55SMEM_DATA
CPU_55S CPU_SMI_LCPU_55S CPU_INIT_L
FB_55SFB_ADCTRL
FB_35S_TO_55SFB_ADCTRL
FB_40SFB_DATA
DMI_100DDMI
CPU_55S FSB_IERR_L
CPU_55S CPU_2TO1 CPU_THERMTRIP_L
FSB_55S FSB_COMMON FSB_HIT_L
IDE_55SIDE
CLK_PCIE_100DCLK_PCIE
CLK_MED_55SCLK_MED
AUDIO_55S AUDIO SB_ACZ_RST_LAUDIO_55S AUDIO ACZ_RST_L
AUDIO_55S AUDIO ACZ_SDATAOUTAUDIO_55S AUDIO SB_ACZ_SDATAOUTAUDIO_55S AUDIO ACZ_SDATAIN<0>
AUDIO_55S AUDIO ACZ_SYNC
TMDS TMDS TMDS_CLK_N
AUDIO_55S AUDIO SB_ACZ_SYNC
FSB_55S FSB_COMMON FSB_DEFER_L
FSB_55S FSB_COMMON FSB_HITM_L
FSB_55S FSB_COMMON FSB_BNR_L
TMDS TMDS TMDS_CLK_P
PCIE_100DPCIE
TMDS_100DTMDS
LVDS_100DLVDS
VGA_75SVGA
CPU_55S CPU_STPCLK_L
FSB_55S FSB_ADDR FSB_REQ_L<4..0>
FSB_55S FSB_COMMON FSB_DPWR_L
SPI_55SSPI
CLK_SLOW_55SCLK_SLOW
AUDIO_55S AUDIO ACZ_BITCLKAUDIO_55S AUDIO SB_ACZ_BITCLK
CPU_27P4S CPU_VCCSENSETHERM CPU_VCCSENSE_PCPU_55S CPU_2TO1 CPU_VID<6..0>CPU_55S CPU_2TO1 CPU_VID<6..0>
CPU_55S CPU_ITP ITPRESET_L
12
60
12
12
12
12
11
12
12
12
12
23
21
21
12
12
12
12
47
47
47
47
79
12
12
79
21
12
12
47
86
86
7
12
34
21
7
7
7
12
12
7
7
7
7
7
14
21
7
21
21
7
60
7
60
34
11
7
7
21
21
7
21
21
21
21
78
12
7
7
78
7
7
7
21
60
9
9
78
78
78
78
79
79
5
7
7
11
60
7
5
5
5
7
7
5
5
5
5
5
7
7
7
5
7
5
7
7
5
5
5
8
60
7
11
7
5
5
7
7
7
5
21
5
5
21
5
5
77
21
7
5
5
77
5
5
5
5
21
8
8
8
11