M. tech vlsi 2015 list
2
SAK INFORMATICS (0)9603999243, 9000188676 #C4, KVR Enclave, Near ICICI Bank, Ameerpet, Hyderabad [email protected] www.sakinformatics.com M. TECH VLSI 2015 LIST S. No. PROJECT TITLE IEEE 1 VLSI implementation of an improved multiplier for FFT computation in biomedical applications 2015 2 Design of optimized reversible Binary and BCD adders 2015 3 A novel realization of reversible LFSR for its application in cryptography 2015 4 Trace Buffer Attack: Security versus observability study in post-silicon debug 2015 5 FPGA implementation of efficient AES encryption 2015 6 A secure and lightweight authentication protocol for RFID 2015 7 Low power high speed VLSI architecture for 1-D Discrete wavelet transform 2015 8 FPGA implementation of Discrete Wavelet Transform using Distributed Arithmetic Architecture 2015 9 Parallel and High-Speed Computations of Elliptic Curve Cryptography Using Hybrid-Double Multipliers 2015 10 High performance and area efficient Signed Baugh-Wooley multiplier with Wallace tree using compressors 2015 11 Design of low power and high speed Carry Select Adder using Brent Kung adder 2015 12 Fine-grained pipelining for multiple constant multiplications 2015 13 Implementation of redundant carry save adders on FPGA 2015 14 A Modified Partial Product Generator for Redundant Binary Multipliers 2015 15 Design of carry select adder for low-power and high speed VLSI applications 2015 16 Analysis of test sequence generators for built-in self-test implementation 2015 17 An enhanced architecture for high performance BIST TPG 2015
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Transcript of M. tech vlsi 2015 list
SAK INFORMATICS (0)9603999243, 9000188676 #C4, KVR Enclave, Near ICICI Bank, Ameerpet, Hyderabad [email protected]
www.sakinformatics.com
M. TECH VLSI 2015 LIST
S. No. PROJECT TITLE IEEE
1 VLSI implementation of an improved multiplier for FFT computation in
biomedical applications
2015
2 Design of optimized reversible Binary and BCD adders 2015
3 A novel realization of reversible LFSR for its application in cryptography 2015
4 Trace Buffer Attack: Security versus observability study in post-silicon
debug
2015
5 FPGA implementation of efficient AES encryption 2015
6 A secure and lightweight authentication protocol for RFID 2015
7 Low power high speed VLSI architecture for 1-D Discrete wavelet
transform
2015
8 FPGA implementation of Discrete Wavelet Transform using Distributed
Arithmetic Architecture
2015
9 Parallel and High-Speed Computations of Elliptic Curve Cryptography
Using Hybrid-Double Multipliers
2015
10 High performance and area efficient Signed Baugh-Wooley multiplier
with Wallace tree using compressors
2015
11 Design of low power and high speed Carry Select Adder using Brent
Kung adder
2015
12 Fine-grained pipelining for multiple constant multiplications 2015
13 Implementation of redundant carry save adders on FPGA 2015
14 A Modified Partial Product Generator for Redundant Binary Multipliers 2015
15 Design of carry select adder for low-power and high speed VLSI
applications
2015
16 Analysis of test sequence generators for built-in self-test implementation 2015
17 An enhanced architecture for high performance BIST TPG 2015
SAK INFORMATICS (0)9603999243, 9000188676 #C4, KVR Enclave, Near ICICI Bank, Ameerpet, Hyderabad [email protected]
www.sakinformatics.com
18 A concurrent BIST scheme for read only memories 2015
19 SoC test integration platform 2015
20 A fault tolerant response analyzer with self-error-correction capability 2015
21 Design and Testing of Combinational Logic Circuits Using Built in Self
Test Scheme for FPGAs
2015
22 Fault Tolerant Parallel FFTs Using Error Correction Codes and Parseval
Checks
2015
23 Efficient Coding Schemes for Fault-Tolerant Parallel Filters 2015
24 Fault Tolerant Parallel Filters Based on Error Correction Codes 2015
25 An efficient floating point multiplier design for high speed applications
using Karatsuba algorithm and Urdhva-Tiryagbhyam algorithm
2015
26 High speed 16-bit digital Vedic multiplier using FPGA 2015
27 FPGA implementation of delay optimized single precision floating point
multiplier
2015
28 Implementation of a high speed multiplier for high-performance and low
power applications
2015
29 A 32 BIT MAC unit design using Vedic multiplier and reversible logic
gate
2015
30 Generalized parallel CRC computation on FPGA 2015
31 FPGA implementation of efficient AES encryption 2015
32 Serial and parallel interleaved modular multipliers on FPGA platform 2015
33 FPGA realization of multiplier less FIR filter architectures 2015
34 Wireless sensor network specific low power FIR filter design and
implementation on FPGA
2015
35 New Regular Radix-8 Scheme For Elliptic Curve Scalar Multiplication
Without Pre-Computation
2015
36 Index-based Round-Robin Arbiter for NoC Routers 2015
