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SEMICONDUCTORS 3501 ED BLUESTEIN BLVD., AUSTIN, TEXAS 78721

MC6847/MC6847Y VIDEO DISPLAY GENERATOR (VDG)

The video display generator (VDG) provides a means of interfacing the M6800 microprocessor family (or stmilar products) to a standard col­or or black and white NTSC televtsion recetver. Applications of the VDG include video games, process control displays, home computers, education, communications, and graphics applications.

The VDG reads data from memory and produces a video signal which will allow the generation of alphanumeric or graphic displays. The generated video signal may be modulated to etther channel 3 or 4 by using the compatible MC1372 (TV chroma and video modulator). This modulated signal is suitable for reception by a standard unmodified television receiver. A typical TV game is shown in Figure 1.

• Compattble with the M6800 Family. the M68CXJO Family, and Other Microprocessor Families

• Generates Four Different Alphanumeric Display Modes, Two Semi­graphic Modes, and Eight Graphic Display Modes

• The Alphanumeric Modes Display 32 Characters Per Line by 16 Lines Using Either the Internal ROM or an External Character Generator

• Alphanumeric and Sem1graph1c Modes May Be Mixed on a Char­acter-by-Character Basis

• Alphanumeric Modes Support Selectable Inverse on a Character­by-Character Basis

• Internal ROM May Be Mask Programmed with a Custom Pattern

• Full Graphic Modes Offer 64 x 64, 128 x 64, 128 x 96, 128 x 192, or 256 x 192 Densities

• Full Graphic Modes Use One of Two 4-Color Sets or One of Two 2-Color Sets

• Compatible with the MC1372 and MC1373 Modulators Via Y, R-Y lq,AI, and B-Y I<PBI Interface

• Compatible with the MC6883 174LS783) Synchronous-Address Multi­plexer

• Available in Either an Interlace INTSC Standard) or Non-Interlace Version

MC6847 Non-Interlace MC6847Y

Interlace

MOS (N-CHANNEL, SILICON-GATE)

Vss1

006

DDO[

DOl

002!

003

004

005

CHB

~B

~A

MS

DA5

DA6(

DA7

DAB!

Veer DA9

DA 10[

DAll

M0"!('f11'1 fl. IN(

VIDEO DISPLAY GENERATOR

L SUFFIX CERAM\C PACKAGE

CASE 715

S SUFFIX CERD\P PACKAGE

CASE 734

PIN ASSIGNMENT

1. 40 007

2 39 css 3 38 HS

4 37 FS

5 36 RP

6 35 A/G

34 A;s 8 33 CLK

9 32 INV 10 31 INT /EXT

11 30 GMO

12 29 GM1

13 28 Jy

14 27 ~GM2

" 26 JDA4

16 25 JDA3

11 24 DA2

18 23 JDA1

19 22 DAO

20 21 DA12

1~184 ) ~;4f]}"l f' ,

MC6847•MC6847Y

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FIGURE 1 - BLOCK DIAGRAM OF A TV GAME USING THE VDG AND THE MC6809E MPU

f3 SO S2

E MC6883

4X Color Burst Freq. 14 38 MHz

rl 0 h Synchronous

Address CLK 1 CLK

RF Sign al to TV

L M MC6809E c

Multiplexer DAO DAO I t MPU 0 0

ZO Z7 WE CAS RAS RS HS r--- 3 AO·A15 <i>B 7

8 q,A r--- 2

16

J_ MC6847 y r--- RF

-Game Paddles

00-07

A0-A15

A0-A15

D0-07

Me6846 ROM

1/0 Ttmer

es

B

2

ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS

Characteristics

Supply Voltage

Input Voltage Any Pin

Operating Temperature

Storage Temperature

THERMAL CHARACTERISTICS Characteristics

Thermal Resistance Ceramic Plastic Cerdip

Dynamic RAM Array

IMeM4027, MCM4116, MCM6633

or MCM66651

'El" u F F E R .___

r---L A T cs e -- H

'---

Symbol Value

Vee 0_3 to + 7_0

V,n 0_3 to + 7_0

TA 0 to + 70

T stg 65 to + 150

Symbol Value

8JA 50 100 60

Unit

v v oc oc

Unit

°C/W

Vtdeo Dtsplay

Mod

L Generator

A T ~ 00-07 e H

'----

Mode

5

This devtce contains ctrcuttry to protect the in­puts against damage due to high static voltages or electric ftelds; however, 11 is advised that nor· mal precauttons be taken to avoid application of any voltage higher than maximum rated voltages to th1s h1gh impedance c1rcu1t. Reliability of operation 1s enhanced If unused Inputs are t1ed to an appropriate log1c voltage (e.g . either Vss or

Vccl

MOTOROLA Semiconductor Products Inc. 2

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MC6847•MC6847Y

DC {STATIC) CHARACTERISTICS I Vee= 50 V ± 5% Vss = 0 0 V T A= ooc to 70°C unless otherw1so notedl

Characteristic Symbol Min Typ Max Unit

Input H1gh Voltage eLK v,H Vss-+ 2.4 - Vee v Other Inputs Vss+2.0 - Vee

Input Low Voltage eLK v,L Vss-0.3 - Vss+0.6 v Other Inputs Vss-o3 - v55 + o.s

Input Leakage Current. Fo~ce 5.25 Von Pin Under Test,

VCC''"5.5 V CLK, GMO-GM2, INV, INT/EXT, MS, Vss. l,n - - 2.5 "A ooo-oo7. A;s, A.;G

Three-State I Off State) Input Current DAO-DA 12 1oL - - ±10 "A Force 2.4 V and 0.4 Von Pin Under Test

Output H1gh Voltage ICLoad = 30 pF, I Load= - 100 p,A RP,HS,FS VoH 24 - - v

Output H1gh Voltage ICLoad- 55 pF, I Load- - 100p.AI DAD DA12 VoH 24 - - v

Output low Voltage ICLoad- 30 pF, I Load 1.6mAI RP, HS, FS VoL Vss+DA v

Output Low Voltage ICLoad 55pF, I Load 1.6mAI DAD DA12 VoL vss+D.4 v

Output High Current (Sourcing) All Outputs (Except 1oH -100 "A

IVoH~ 2.4 Vl ¢A, ¢8, Y, and CHBl - -

Output Low Current ($inking) All Outputs (Except 'oL 1.6 - - mA

I VoL= 0.4 Vl ¢A, ¢8, Y, and CHBl

Input Capacitance IV1n- 0, T A 25°C, f 1_0 MHzl All inputs C;n 7.5 pF

Internal Power DISSipatiOn (Measured at T A 0 to 70°Cl PINT 600 mW Chroma ¢A Voltage (Figure 31 v,H 1.8 2.0 2.2

(Cload=20 pF, A load= 100 knl VR 1.34 1.5 1.66 v (Note 1) VoL 0.8 1.0 1.2

Chroma ¢8 Voltage (figure 3) v,H 1.8 2.0 2.2

(Cload=20 pF, A load= 100 knl VR 134 1 5 1.66 v

(Note 11 VoL 0.80 1.0 1.2

Vsurst , .07 1.25 1.43

Luminance Y Voltage (figure 3)

ICLoad = 20 pF, A Load= 100 knl (Voltage Synchronization) Vs 0.9 1 0 11 !Voltage Blank) Vs1ank 0.63 0.77 0.9

v (Voltage Black) VB lack 0.58 072 0 83 (Voltage White Low) VwL 0.51 0.65 0.75 (Voltage White Medium) VwM 0.40 0.54 0.65 (Voltage White Highl (Note 11 VwH 0.27 042 0.53

Chroma B1as Voltage ICLoad 20 pF, A Load 100 kill VA o 27 vee o3 Vee o.33 Vee v

Resistor % of Vss Tracking (Analog Outputs Linearity Error) RT 1.0 3.0 %

NOTE 1 The specified minimum and max1mum number reflect performance ol the VDG of the spec1f1ed temperature range Overlapping vol­

tage levels will not occur. Refer to F1gure 2

MOTOROLA Semiconductor Products Inc. 3

MC6847•MC6847Y

POWER CONSIDERATIONS

The average chip-junction temperature, T J, in °( can be obtained from:

TJ~TA+IPo•OJAI

Where:

T A= Ambient Temperature, 0(

8JA= Package Thermal Resistance, Junction-to-Ambient, °C/W

PI)~ PiNT+ PPORT PINT= Icc x Vee, Watts - Chip Internal Power

PpoRT=<Port Power Dissipation, Watts- User Determined

Ill

For most applications PpQRT-<PiNT and can be neglected_ PpQRT may become significant if the device 1s conf1gured to drive Darlington bases or sink LED loads

An approximate relationship between Po and T J (if PPORT is neglected) is:

Po~ K+ IT J + 273°CI 121 Solving equations 1 and 2 for K gives:

K ~ Po• IT A+ 273°CI + 0JA•Po2 131 Where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring Po {at equilibrium)

for a known T A· Using this value of K the values of Po and T J can be obtained by solving equations ( 1) and (2) iteratively for any value ofT A

FIGURE 2 - PSEUDO ANALOG LUMINANCE RESISTOR CHAIN

+5V Vsync _l__

Vetank _l__

Vetack __L_

y

NOTE The chromnoance output chain is S1milar m design to the luminance chain

MOTOROLA Semiconductor Products Inc. 4

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MC6847•MC6847Y

AC (DYNAMIC) CHARACTERISTICS I Vee= 50 V ± 5% TA=0°C to 70°Cl (Load C1r'-u1t of F1gure 3) Characteristic Symbol Min M"

CLK (Frequency (3.579545 Color Burst Frequency) f 3.579535 3 597555

CLK Duty Cycle CLKdc 45

Clock A1se T1me lCLKr Clock Fall T1me ICLKf -

Clock Pulse Width PWcLK 120 Horizontal D1splay Addrc~s Delay from Counter DAO-DA3 tHOAD -

DA4 IHDA4D HoriZOntal Display Address Hold T1me IHDAH 0

IHOA4H 0

Display Data Setup T 1me CSS, \NV, A/S, INT/EXT, 000·007 toos 70

Display Data Hold Time CSS, I NV, A/S, INT/EXT, 000-007 tooH 140

Honzontal Sync IR'S) Delay Fall toHSf -Rise IQHSr

Row Preset IRP) Delay Fall IQRPt -

Rise lOR Dr Vertical Display Address Delay from Counter DA5"DA12 'VDAD Vertical D1splay Address Hold T1me tvoAH -

Field Sync (FS) Delay Fall tOFSf -

R1se tDFSr Memory Select Low to Display Address High Impedance toMST -Memory Select H1gh to Display Address Valid toMSV -Chroma Rise and Fall Tw1es

(rj,A Rise T1mel 1rCrPA -trq,A -

(¢A Fall T1mel 1fC¢A -1f¢A -

l<tJB Rise T1me) trC<tJB -

tr<tJB -I¢B Fall Time) lfC¢8 ~·

lf¢8 -

Color Burst R1se T1me on q,B Output tcBr -

Color Burst Fall Time on <tJB Output tCBf Chroma Phase Delay (Measured with Respect to "Y" Output)

¢A tyA -50 ¢8 tyg -50

Luminance R1se Time t,y

Luminance Fall T1me lfy Honzontal Sync Rise Time on Y Output tHe

Horizontal Sync Fall Time on Y Output 1Hf Horizontal Blanking Rise T1me on Y Output tHBr

Horizontal Blanking Fall T1me on Y Output tHBf

Front Porch Duaration Time (7x 1/f) lFP 1.8

Back Porch Duration Tirne (17.5x 1/f) tgp 4.5

Left Border Duration T1me 129.5 x 1 /f) lLB 7 5

R1ght Border Duration T1me 128 x 1/fl 'RB 7 5

Color Burst Durat1on T1me 110 5x 1/0 tea 2 7

FIGURE 3 - TEST LOADS

AO-A12, i'S. RP, HS 4.75 v M . .pB, Y, CHB MMD6150

Test or EQUIV 2.50 kn TestPo1nt~

Pomt

J30pF 24 k I

1 ()() k MMD7CXXJ or Equ1v

~ "'=-

MOTOROLA Semiconductor Products Inc. 5

55

50

50 160

490

550 -

~

-

-

550

740

660 540

6.0

220 520

600

80

400

100 100 100

100 100 100 100 100

100 100

140 140

100

100

100

100

100

100

24

51

8.3

8.3

3.2

Unit Figure

MH' 4 ~

% 4

ns 4

ns 4

ns 4

'" 4. !'i, 0

ns 5, 6

ns 4, 5, 6

ns 4, 5, 6

ns 4, 5, 6

ns 7

ns 7

"s 7

ns 7

ns 8

ns 9

ns 9

ns 12

ns 12 ns 12

ns 11

ns 12

ns 12

ns 12

ns 12

ns 12

ns 12

"s 12

"s 12

"s 12

"s 12

"s 12

MC6847•MC6847Y

1CLKr

CLK !Note 11 r-DAO-DA3

000.007, css

NOTES:

FIGURE 4 - CLOCK AND LONG CYCLE HORIZONTAL ACCESS TIMING

1 The VDG may power-up using either the rising or falling edge of the clock (dotted line). 2. Transitions of DA4-DA 12 occur outside the display area. DAO-DA3 access the 16 bytes of data displayed during each scan line in the dis­

play area. 3. Long cycle timing applies to CGl, RG1. RG2, and RG3 modes (see Table J)_ AIG is high; AS, INT /EXT, and INV input levels do not affect

the VDG in long cycle modes 4 Usable RAM access time for the long cycle may be calculated ustng the following equation:

lRACL = 8•1/fmax- tHOADmax- toosmm- tcLKr If address and data buffers are used, the access time must be adjusted accordingly.

5 All timing is measured to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts unless otherwise specified

NOTES'

FIGURE 5- SHORT CYCLE HORIZONTAL ACCESS TIMING

tcLKr

DAO-DA3

DA4

DDO-DD7 CSS, A/G, A/S, I NT/EXT

1 The VDG may power-up using either the r1sing or falling edge of the clock as shown in Figure 4 2. Transitions of OA5-DA 12 occur outside the display area. DAO-DA4 access the 32 bytes of data displayed during each scan line in the dis­

play area. 3. Short cycle timing applies to the four alphanumenc modes, two sem1graph1c modes, and to the CG2, CG3, CG6. RG6 modes (see Table 3)

For the four graphiC modes, A!G is high and the AIS, INT/EXT, and INV mput levels do not affect the VDG 4 Usable RAM access time tor the short cycle may be calculated us1ng the following equat1on

tRACS =4•1 If max- 'HDA4Dmax- toosmin- lCLKr If address and data buffers are used, the access time must be nd1ustcd accordingly

5 All timmg is measured to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts unless otherwise speCified

MOTOROLA Semiconductor Products Inc. 6

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@ ! 0 a ~ ... ~ (/)

~CD

3 o· 0

~ 0 .... 'tl a ~ Cit s fl

r-

FIGURE 6- HORIZONTAL ADDRESS AND VALID DATA SETUP AND HOLD TIMING (Timing Relationships Shown From Beginning of Line)

~-

c .• q~ U0~(\-~~~ b:;;!j 'C~'o I ,..Jj.

J4.0 OAJ ~~X:_-_-_: Valrd Address _X X) :_-_:-_x Vaird Address x.l)..!.-.:_-:_-x JHA40

~A4 X ~x=~---_- X Val•d Addreso X_ X_ c_-_-::: Valid Add·ess x:x::: ['" Ll IRACL ~CHARL I

~IHD r IHD -,~ IHB J-' t ~cl~ ''o tz_

r:~ ,,.., ..:.'~.P..e 2 o v --- '. ---- . h ·'•'I_E';. Ll '''' t~~dDat '-JI•CDa;a

00000' ---,V , OBV 1---- ----ai•O Da.a :F,rs: (>,a·ac:w on Scree~ After Borderl .L --- __ ---- __ ___ .

DAJ-OAJ A~X____ Valrd Address --x ____ - Val·d Address ___ x__- -- va"c Ac!C·ess

:cA 0" t:x:.:::~ Vo11d Address :::x::=::_ Volrd Add res; -_-:x_::::_ <a"~ Acc·e''

--IRACS :cHARS ! •oos1 I _ . s~ '"D , . 1~[)DH :su -~tore lprc-~ I

DOC 007

S S ~N·,.

;~c' DD'

////!fljii!I!V/J///!)I/Jfl/T!//[i/!/IJ!//!T!I(//l/0/12tcfj.:: ... afd)Jt v~;§!~C?(//1;////!J[I(!I!f/)11!/lfl/ka:S.~a~ 'vaiod Data

·N~. ExT

Long elemenl,access rT'oaes CG'. RGt F>G2. RG3 '' S'c" ~IPr"en• <Kcess -r;1Ce CG2 CGJ CG6. f!G6 A'pha~umerrc,, SemrqraPI>rcs

FIGURE 7- VERTICAL ADDRESS, ROW PRESET AND HORIZONTAL SYNCHRONIZATION TIMING

YS " lDRPf

RP - /] 1'4--------~~~~ ~a~:j ~~~~ ~

DA5 DA12' Valrd Address 220r<s Val 1d Address

tvoAH

~(;TES

I 4.1 · - ·-g ·o n•f><1~cHed w anCll·orn a tow voltage of 0 8 volts and a hogh voltage of 2 0 volts unless otrerw1se speC1f1ed HS o"'~P '~rd:'", rrav De deter<nr;ed by :wHS = 16 5.1 if- IOHSF .._ IOHSr HS tc i>P "'al' De determ1red bv 'I-1SRP = 3 5·1 if- 1QHSr ~ 1QRPI

4 qp 8ulsp ·~rutt· ~'a·, be de:erll'r~eCl by IWRP= 3 5·1.·1- '::JRPt + 'DRPr 5 DA5 DA ·,2 ·,\·• er·arge dur r•g tne r'lacnve po·t 0'1 ot tr·e drspla1· 6 'PHS~227:,.· f

'JC''

MC6847•MC6847Y

CLK

NOTES

FIGURE 8 - FIELD SYNC (F$) TIMING

~--------lWFS--------~ Note 1

~------------------lPFS------------------~~ Note 2

1 twFs=32·tPHsr= 32·1277.5·1/fl

2 trFs=262·tPHST=262·1227.5·1/l) lor MC6847 lpfS = 262.5·1PHST = 262.5·1227_5•1 /fl for MC6847Y

FIGURE 9 - MEMORY SELECT (MS) TIMING

MS Note 1

MAO-MA 12 V

NOTES

alid Address

1\

~lDMST-.

Val1d Address 1\ 'f

1 MS 1s asserted asynchronously w1th respect to CLK

'DMSV

Val1d Address

MOTOROLA Semiconductor Products Inc. 8

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MC6847•MC6847Y

FIGURE 10- VIDEO AND CHROMINANCE OUTPUT WAVEFORM RELATIONSHIPS

VBurst VOL

AIG + A!G•CSS

u I A_i_S!._. ~ css

(Burst is removed foe

AIG•CSS•GMOl

Blue

I I I I I I I I I I I I I I I ! I

l I I I I I

I I I I I I I Red I I I Buff

A/G•CSS J I Green

NOTES' 1. tHco~3.5.1it 2. 'Av~t2B·1it 3 'Avs~1B5.5-1/t 4. Refer to Figure 7 5. tHBNK=42·1/f

FIGURE 11 -CHROMA PHASE DELAY

y _____ ___,.l

tyA-. ~ ~---

¢A ------f----/

¢B ______ ~

MOTOROLA Semiconductor Products Inc. 9

Vsync

Vslank

Vslack

VwL VwM

IFP

y

FIGURE 12- TIMING DIAGRAMS VIDEO RISE AND FALL TIMES (111ustrates Beginning of One Horizontal Line)

'LB--1

90%

10% IHf

VwH ---------------------90o/o 10%---

Vsurst

VQL

lfY

tcsr

~B ------------~10~%~

test

lfQ>A

90%

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MC6847•MC6847Y

FIGURE 13- DISPLAY AREA TIMING

Vert1cal Blanking 13 H L1nes

Top Border 25 H Lines

-- -- -

~

Active Display Area 192 H Lines m < ~

N

~

Falling Edge of FS *

~ -- -- -Bottom Border 26 H Lines

-Vert1cal Retrace 6 H Lines

'AV . lAVB

1HST

*Typically 2.4 JLS after start of vertical blank.

FIGURE 14 - TYPICAL FORMAT OF THE TELEVISION SCREEN

BORDER I Black 1n all alpha/sem1graph1c modes Green or but! loll-white)

1n all graphiC modes. Controlled by the VDG )

\ ]\ ~r··· ~

256 Dots ----

. ~

DISPLAY AREA . 0 0 149,152 dots, all under VDG N m control 1n all modes Each

T one of up to 8 colors when on

l dependmg on mode l

~ Ont! on each non-1nterlaced l1ne. lor 111tcrlace. the l1nes of the odd

held arc copied mto the ever1 l1dc1 trw<:, doublmg the nurntJP.r ()f 1j1s

playr•d clots

MOTOROLA Semiconductor Products Inc. 11

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MC6847•MC6847Y

VIDEO DISPLAY GENERATOR DESCRIPTION

The MC6847/MC6847Y v1deo display generators provtde a simple interface for display of digital information on a color monitor or standard color/black and white television receiver.

Television transmissions in North and South America and .JF!pan conform to the National Television System Commit­tee (NTSC) standards. This system is based on a field repeti­tion rate of 60 fields per second. There are 525 interlaced lines per frame or one-half th1s number per field

The MC6847 scans one f1eld of 2621ines 60 times per sec­ond. The MC6847 non-interlace VOG is recommended for use in systems {i.e., TV games and personal computers) where absolute NTSC compatibility is not required. If NTSC compatibility is required, perhaps for caption overlays on broad-case signals, then the MC6847Y 1nterlace VDG is recommended.

NOTE

A system with the MC6847 VOG and the MC1372 video modulator forms a transmitter, transmittmg at 61.2 MHz (channel3) or 67.25 MHz {channel41 depen­ding on component values chosen. This being a Class I TV dev1ce, care must be taken to meet FCC re­quirements Part 15, Subpart H. However, if the com­posite video output from the MC1372 were to drive the television directly, Section 15.7 of the FCC specifica­tion must be adhered to.

SIGNAL DESCRIPTION

DISPLAY ADDRESS OUTPUT LINES IDAO-DA121 Thirteen address lines are used by the VDG to scan the

display memory as shown in F1gures 4-7. The starting ad­dress of the display memory is located at the upper left cor­ner of the display screen. As the television sweeps from the left to right and top to bottom, the VDG increments the RAM display address. The timing for two accesses starting at the beginning of the line is shown in Figure 6. These lines are TTL compatible and may be forced into a high­impedance state whenever MS (pin 12) goes low. AO-A3

change during the active display area. A4 changes during the acttve display area in the alphanumerics, semigraphics, CG2, CG3, CG6, and RG6 modes. A5-A 12 do not toggle within the active display area but instead, ripple through the address during border and blanking t1me.

DATA INPUTS IDDO-DD71 Eight TTL compatible data l1nes ;,rP. used to input dat;,

from RAM to be processed by the VDG The data is then in­terpreted and transformed into luminance (Y) and chroma outputs (¢A and ¢S).

POWER INPUTS - Vee requires + 5 volts ± 5% Vss requires zero volts and is normally ground. The tolerance and current requirements of the VDG are specified in the Elec­trical Characteristics.

VIDEO OUTPUTS 1</>A, </>B, Y, CHBI -These four analog outputs are used to transfer luminance and color Information to a standard NTSC color television receiver, either via the MC1372 RF modulator or via drivers directly 1nto Y, cjJA, cps television video inputs (see Figures 10, 11, and 121.

Luminance (Y) - Thts six level analog output contains composite sync, blank1ng and four levels of video luminance.

¢A - This three level analog output is used in combina­tion with cps and Y outputs to specify one of eight colors.

cps - This four level output is used in combination with ¢A and Y outputs to specify one of e1ght colors. Additional­ly, one analog level is used to spec1fy the time of the color burst reference signal.

Chroma Bias (CHB) - This pin is an analog output and provides a DC reference corresponding to the quiescent value of ¢A and I/.! B. CHB is used to guarantee good thermal tracking and minimize the variation between the MC1372 and MC6847. This pin, when pulled low, resets certain registers within the chip In a user's system, this pin should not nor­mally be used as an input. It is used mainly to enhance test capabilitieS within the factory.

FIGURE 15 - COLOR COMPOSITE VIDEO TO COLOR MONITOR

360 560

... I 1 N3064 Adjust for

de Output 14 ~ 113

12 4 3 VI ""'04mAppTyp

I MC137?

~

10 ~ 0 ~-j 8 AdJuSt lor

3 9 k* 750 ac Output

Rat10 Color to V1deo Tr1m

+5V

2N4403

v

"' 33k

~

2N4401 750

470 ""2.0 v

*3.9 kO is MC13

Culu1 ~Composite

T V1dco '=" Out

72 eifect1vr: load, pm 12 voltage doesn't move and IS v1rtual ground

MOTOROLA Semiconductor Products Inc. 12

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MC6847•MC6847Y

SYNCHRONIZING INPUTS (MS, CLKI THREE-STATE CONTROL - IMSI is a TTL compatible

input which, when low, forces the VDG address lines into a high-impedance state, as shown in Figure 9. This may be done to allow other dev1ces (such as an MPUl to address the display memory (RAMI.

CLOCK (CLK) - The V\.JG clock input (CLK) requ1res a 3.579545 MHz (standaro color burst) TV crystal frequency square wave. The duty cycle of this clock must be between 45 and 55% since it controls the width of alternate dots on the television screen. The MC1372 RF modulator may be used to supply the 3.579545 MHz clock and has provisions for a duty cycle adjustment. The VDG will power-up using either the rising or fatltng edge of the clock. The dotted line on the CLK signal tn Figure 4 indicates this characteristic of latching in data on either clock edge.

SYNCHRONIZING OUTPUTS IFS, HS, RPI Three TTL compatible outputs provide circuits, exterior to

the VDG, with ttming references to the following internal VDG states:

FIELD SYNC IFSI - The high-to-low transition of the FS output coincides with the end of active display area (see Figure 8). Dunng this time intervaL an MPU may have total access to the display RAM without causing undesired flicker on the screen. The low-to-high transition of FS coincides with the trailing edge of the vertical synchronization pulse.

HORIZONTAL SYNC IHSI - The HS pulse comcides with the honzontal synchronization pulse furnished to the television receiver by the VDG (see F1gure 7) The high-to­low transition of the HS output coinc1des with the leading edge of the horizontal synchronization pulse and the low-to­high trans1t1on coincides with the trail1ng edge.

ROW PRESET (RP) - If des1red, an external character generator ROM may be used with the VDG. However, an ex­ternal four bit counter must be added to supply row ad­dresses. The counter is clocked by the HS signal and is cleared by the RP signal. RP pulses occur 1n all alphanumeric and semigraphics modes; no pulses are output in the full graphic modes. RP occurs after the first valid 12 lines. Therefore, use an FS clocked prelcadable counter such as a 74LS161 as shown in Figures 7, 1L, and 23

MODE CONTROL LINES INPUT (A/ G, A/S, \NT I EXT, GMO, GM1, GM2, CSS, !NVI

Eight TTL compatible inputs are used to control the operating mode of the VDG. A/S !NT/EXT, CSS, and !NV may be changed on a character-by-character basis. The CSS pin is used to select between two possible alphanumeric col­ors when the VDG is in the alphanumeric mode and between two color sets when the VDG is in the Semigraphics 6 or full graphic modes. Table 1 illustrates the various modes that can be obtained using the mode control lines. There are two dif­ferent types of memory access concerning these modes, they are a short and a long access cycle, which differ by a

FIGURE 16- EXTERNAL CHARACTER GENERATOR ROW COUNTER FOR MC6847

From FS Me6847

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MOTOROLA Semiconductor Products Inc. 1:1

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MC6847•MC6847Y

TABLE 1 - MODE CONTROL LINES (INPUTS)

A/G A/S INTI EXT INV GM2 GM1 GMO

0 0 0 0 X X X 0 0 0 1 X X X 0 0 1 0 X X X 0 0 1 1 X X X

0 1 0 X X X X 0 1 1 X X X X

1 X X X 0 0 0 1 X X X 0 0 1 1 X X X 0 1 0 1 X X X 0 1 1 1 X X X 1 0 0 1 X X X 1 0 1 1 X X X 1 1 0 1 X X X 1 1 1

shift of one full 3.58 MHz cycle. One of the differences be­tween these access times, rn the short access time frame, is a shift of one full 3.58 MHz cycle from the corresponding normal long access time frame, as shown in Figure 6. The modes using short access t1mes read memory twice as often as the long access modes.

OPERATION OF THE VDG

A stmplified block diagram of the VDG is shown in Figure 17a and a detailed block diagram is shown 1n Figure 17b.

The externally generated 3.58 MHz color burst clock drives the VDG. Referring to Figures 11 and 12, note that the horizontal screen span from blanking to blanking is 193.1 clock periods ( = 53.95 fLS). The display window is offset from the left-hand edge by 283 periods and lasts for 128 periods {35.75 p:s) Of the 2421ines on the vertical screen from blank­ing to blanking, 192 lines are used for the display. The display window is offset from the top by 25 lines. Under the constraint of the master clock, the smallest display element possible for the VOG is half period of the 3.58 MHz clock wide by one scan line high. All other display elements are multiples of thts basic size.

DISPLAY MEMORY ADDRESS DRIVERS

The address drivers normally drive the video refresh ad­dress into the display memory so characters may be dtsplayed on the CRT. When the memory select ptn {MSl is pulled low by an external decoder, the dnver outputs go to a h1gh-1mpedance state so external three-state drivers may swttch the M PU produced address onto the dtsplay memory address bus; the MPU may dtrectly manipulate data in the d1splay memory

VIDEO TIMING AND CONTROL

Th1s subsystem of the VOG tnclurles the morle decoding, t1ming generatton, and associated row counter logic, and uses the 3 58 MHz color frequency to generate horizontal and verttcal timing information (vla l1near sh1ft register counters), which the video and chroma encoder uses to generate color v1deo tnformation The horizontal ttmtng for tho3 VOG 1s surnmarized tn F1gure 7. len and one-half cycles of the 3 58 M Hz subcarner are trar1Sm1tted on the back porch

Alpha/ Graphic Mode Select I of Colors

Internal Alphanumerics Internal Alphanumencs Inverted

2 External Alphanumcrrcs External Alphanumencs Inverted

Semigraphrcs 4 (SG41 8 Semigraphics 6 ISG61 8

64 x 64 Color Graphrcs One ICG 1) 4 128x64 Resolution Graphics One (AG11 2 128 x 64 Color Graphics Two ICG2l 4 128x96 Resolutron Graphrcs Two IRG2l 2 128 x 96 Color Graphics Three ICG3) 4 128 x 192 Resolutron Graphrcs Three IRG31 2 128 x 192 Color Graphrcs Six ICG61 4 256 x 192 Resolutron Graphrcs Srx (AG61 2

of every hor1zontal blanking period. This color burst is sup­pressed during vertical sync and equalizing intervals. Color burst is also suppressed in the most dense two color graphic modes. This leads to some interesting rainbow effects on the display which 1s frequency and pattern dependent. The ver­tical timing for the VDG is given in Figure 18. Vertical retrace is initiated by the luminance signal being brought to the blanktng level. The vertical blanking period begins with three lines of equalizing pulses followed by three lines of serrated vertical sync pulses followed by three more lines of equaliz­ing pulses. The remaining vertical blanking period contains the normal horizontal sync pulses. The equalizing and serra­tion pulses are at half line frequency. Nottce the difference in spacmg between the last horizontal sync pulse and the first equalizing pulse in even and odd fields. It is the half line dif terence between fields that produces the ihterlaced ptcture in a frame. Vertical timing between fielcs for the non-interlaced VDG, on the other hand, is identical. The equalizing and ser­ration pulses are, however, at the horizontal frequency.

The 3.58 MHz color frequency is also used to clock the video shift register load counter. This counter and the video shift clock tnhibit ctrcuitry derive the dot-clock for the output of the video shift registers and the load signals for the video shtft registers' input latches. The vertical and horizontal ad­dress counters generate the addresses for the external display memory.

INTERNAL CHARACTER GENERATOR ROM

Since many uses of the VDG will involve the display of alphanumeric data, a character~generator ROM is included on the chip. This ROM will generate 64 standard 5x 7 dot matrix characters from standard 6-bit ASCII input. A stan­dard character set is included in the MC6847 although the ROM is custom programmable.

INTERNAL/EXTERNAL CHARACTER GENERATOR MULTIPLEXER

The internal/external multiplexer allows the use of either the internal ROM or an external character generator. This multiplexer may be switched on a character-by-character basis to allow mixed internal and external characters on the CRT. The external character may be any desired dot-pattern tn the standarU 8x 12 one-character dtsplay matrix, thus allowing the maximum 256 x 192 screen density

MOTOROLA Semiconductor Products Inc. 14

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MC6847•MC6847Y

FIGURE 17a - SIMPLIFIED VDG BLOCK DIAGRAM

+5 ov

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CHB

VIDEO AND COLOR SUBSYSTEM The 8-b1t output of the internal/external multiplexer IS

serialized m an 8-bit sh1ft register clocked at the dot-clock frequency

The lum1nance information from the shift register is sum­med With the horizontal and vert1cal sync signals to produce a compos1te v1deo signal less the chromlll<:mce 1nformat1on,

A/S

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HS

A/G

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GM1

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MOTOROLA Semiconductor Products Inc. 15

FIGURE 17b - DETAILED VDG BLOCK DIAGRAM

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MOTOROLA Semiconductor Products Inc. 17

MC6847•MC6847Y

DISPLAY MODES There are two major display modes in the VDG. Major

mode 1 contains four alphanumeric and two limited graphic modes. Major mode 2 contains eight graphic modes. Of these, four are full color graphic and four restricted color graphic modes. The mode selection for the VDG is sum­marized in Table 2. The mnemonics of these fourteen modes arc explained in the following Sf.!C:tions

In major mode 1 the display w1ndow 1s d1v1ded into 32 col­umns by 16 character eleme'lt rows thus requiring 512 bytes of memory. Each character element is 8 half periods by 12 scan lines in size as shown in F1gure 19. The area outside the display window is black.

The VDG has a built-in character generator ROM contain­ing the 64 ASCII characters 1n a 5x 7 format (see Figure 201.

The 5 x 7 character font is positioned two columns to the nght and three rows down within tre 8 x 12 character ele­ment. S1x bits of the 8-bit data word are typically used for the internal ASCII character generator. The remaining two bits may be used to implement inverse video, color switching, or external character generator ROM selection on a character­by-character basis. For those who wish to display lower case letters, special characters, or even limited-graphics, an exter­nal ROM may be used. If such external ROM is used, all of the 8 x 12 picture elements, or pixels, in the character ele­ment can be utilized. Characters may be either green on a dark green background or orange on a dark orange background, depending on the state of the CSS pin. The In­vert pm can be used to display dark characters on a bnght background

TABLE 2- SUMMARY OF MAJOR MODES Major Mode 1 - Alpha Modes

Title Memory

AlphanumericS 512 X 8 (Internal)

Alphanumencs 512 X 8 (External)

Display Elements Colors Title Memory Display Elements

2-1 H5 2 Sem1graph1c 4 512 X 8

.-------. T EW"-"

I . . 12 7 ..... l_ __L . .

2 "--------"

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Sem,graplliC 6 . . 2 512 X 8 . . 12 . . . . _l . . . . . .

Major Mode 2 - Graphics Modes

Title Memory Colors Comments

i64 x 64 Color Graph1c 1 k X 8 4 Matnx 64 x 64 Elements

128 x 64 Graphics" 1 k X 8 2 Matrix 128 Elements W1de by 128 x 64 Color GraphiC 2kx8 4 64 Elements H1gh

128 x 96 Graphics" 1.5 k X 8 2 Matr1x 128 Elements W1de bv 128 x 96 Color GraphiC 3kx8 4 96 Elements H1gh

128 x 192 Graphics" 3kx8 2 Ma1r1x 128 Elements W1de by 128 x 192 Color Graphic 6kx8 4 192 Clements H1gh

256 x 192 Graph1cs 6kx8 2 Matrix 256 Elements W1de by 192 Elements High

"Graph1cs mode turns on or off each element. The color may be one of two

MOTOROLA Semiconductor Products Inc. 18

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FIGURE 19 ~ ALPHANUMERIC MODE (INTERNAL)

512 Characters 132 x 16) T y[J1cal Character ........

::··::·· •• • •• e-Dot Off 0- Dot Lit H-__ )z"u-''" __ v ','•

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Character Source:

::CUX!ee '..) ... _ . ... ____. ... _).

HluiH Normal Black Background Orange or Green Character ($electable)

Internal - 6 B1t ASCII Generator ROM On Chip or User Definable External - Users ROM

The two limited graphic modes are Semigraphics 4 and Semtgraphtcs 6. In Semigraphics 4, the 8 x 12 dot character block is divided into four pixels (each pixel is four half-clocks by six scan lines). The four low-order bits IDDO-DD3) of each incoming byte of data select one of stxteen possible illumina­tion patterns while the next three bits {DD4-DD6l determine the color of the illuminated elements. The most significant bit is unused. Figure 21 shows the color and pattern selec­t1ons. In Semtgraphics 6 the 8x 12 dot character block is divtded tnto stx pixels, each four half-clocks by four scan ltnes. The six low-order bits of each byte of incoming data select one of 64 possible tllumination patterns while the CSS input and the high-order data btts (DD6-DD7) determine the color of the illuminated elements.

The display window in major mode 2 {full graphics) has a less rigorous format than in major mode 1. The display elements vary from one scan line to three scan lines in height. The length of the display element is either eight or sixteen half-periods wide. Each dtsplay element is divided in­to four or eight pixels. The former corresponds to a full color mode while the latter a restricted color mode, like the semigraphics modes, represents illumination data. When it is high the pixel is illuminated wtth the color chosen by the col­or set select (CSSl pin. When it is low the pixelts black. In the full color modes, pairs of data btts choose one of four colors tn one of two color sets defined by the CSS pin. Dependtng on the state of the CSS pin, the area outside the display wtndow ts either green or buff. The dtsplay formats and color selection for this major mode are summarized in Figure 19.

THE 64x 64 COLOR GRAPHICS ONE (CG1) MODE­The 64 x 64 color graphtcs mode generates a display matrtx of 64 elements wide by 64 elements high. Each element may be one of four colors. A 1 k x 8 dtsplay memory IS requtred The display RAM ts accessed 16 ttmes per horizontal ltne. Each ptxel equals four half-clocks by three scan lines.

THE 128 x 64 RESOLUTION GRAPHICS ONE IRGll MODE - The 128 x 64 graphics mode generates a matrix 128 elements wtde by 64 elements high. Each element may be either ON or OFF However. the entire display may be one of two colors, selected bv usmu the color set select pin A 1 k x 8 d1splay memory IS requ1red The display RAM is ac­cessed 16 t1mes per hor1zontal l1ne. Each pixel equals two half-clocks by three scan l1nes

' '-'-

FIGURE 20 - AVAILABLE ALPHANUMERICS

MD4=1NV=D4 MD7=AS=D7

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. 9 A _B _C D .E _F

A B C 0 G H L M N 0

P Q R S T U V W X

-®ooeeooaoooooooe . oeoooaoooooooooe

eoeoo0ooooeoeoeo eoooooooooeeeoeo

THE 128 x 64 COLOR GRAPHICS TWO (CG21 MODE -The 128 x 64 color graphics mode generates a display matr1x 128 elements wide by 64 elements high. Each element may be one of four colors. A 2k x 8 display memory is required. The display RAM ts accessed 32 times per horizontal ltne. Each pixel equals two half-clocks by three scan lines.

THE 128 x 96 RESOLUTION GRAPHICS TWO IRG21 MODE - The 128 x 96 graphics mode generates a display matrix 128 elements wide by 96 elements high. Each element may be either ON or OFF. However, the entire display may be one of two colors selected by using the color set select pin. A 1.5k x 8 display memory is required. The display RAM is accessed 16 times per horizontal line. Each pixel equals two half-clocks by two scan lines.

THE 128x 96 COLOR GRAPHICS THREE (CG31 MODE The 128x 96 color graphics mode generates a dtsplay 128 elements wide by 96 elements high Each element may be one of four colors. A 3k x 8 display memory is required. The display RAM is accessed 32 times per horizontal line. Each pixel equals two half-clocks by two scan lines.

THE 128 x 192 RESOLUTION GRAPHICS THREE (RG3) MODE - The 128 x 192 graphics mode generates a display matrix 128 elements wide by 192 elements high. Each ele ment may be either ON or OFF, but the ON element may be one of two colors selected with the color set select pin. A 3k x 8 display memory is required. The display RAM is ac­cessed 16 times per horizontal line. Each pixel equals two half-clocks by one scan line

THE 128x 192 COLOR GRAPHICS SIX !CG61 MODE The 128x 192 color graphics mode generates a dtsplay 128 elements Wtde by 192 elements high. Each element may be one of four colors. A 6k x 8 display memory is required. The display RAM is accessed 32 times per horizontal line. Each pixel equals two half-clocks by one scan line

THE 256x 192 RESOLUTION GRAPHICS SIX (RG6) MODE - The 256 x 193 graphtcs mode generates a d1splay 256 elements wide by 192 elements high. Each element may be either ON or OFF, but the ON element may be one of two colors selected with the color set select pin. A 6k x 8 dtsplay memory is required. The d1splay RAM is accessed 32 t1mes per honzontal line. Each ptxel equals one half-clock by one scan ltne

MOTOROLA Semiconductor Products Inc. 20

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07 o5 I os

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FIGURE 21 - SEMIGRAPHIC MODE ENCODING

(a) Data and Display Formats

Luma~ Semigraphics 4

D5

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Chroma

041 03 1 02 01

Luma

41PWcLKI Luma SG4 SG6

Color DN D6 D5 D4 css D7 D6 0 X X X X X X Black

1 0 0 0 0 0 0 Green

1 0 0 1 0 0 1 Yellow

1 0 1 0 0 1 0 Blue

1 0 1 1 0 1 1 Red

1 1 0 0 1 0 0 Buff

1 1 0 1 1 0 1 Cyan

1 1 1 0 1 1 0 Magenta

1 1 1 1 1 1 1 Orange

FIGURE 22 - GRAPHIC MODE ENCODING

Do Jcolor Graphic

I Resolution Do Color Graphic

(b) Display Format

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Resolution Color Mode css Border Color Mode

ON Color DN+ 1 ON Color

0 Green 0 Black 0 0 Green

0 Green 1 Green 0 1 Yellow

0 Green 1 Green 1 0 Blue

0 Green 1 Green 1 1 Red

1 Buff 0 Black 0 0 Buff

1 Buff 1 Buff 0 1 Cyan

1 Buff 1 Bull 1 0 Magenta

1 Buff 1 Buff 1 1 Orange

fiJ0 MOTOROLA Semiconductor Products Inc. 'CY 21

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MC6847•MC6847Y

TYPICAL SYSTEM IMPLEMENTATION The block diagram in Figure 23 shows how the VDG is

related to other funct1onal blocks 1n a typical system {non-6883). A negative row preset s1gnal (f1P) generated by the VDG initializes the row scan counter for the external character generator once every twelve scan lines, whtle the neqative horizontal sync IHS"l acts as clock to this counter The negative field sync {f"S) generates an interrupt to the M PU, signifying that the aisplay memory can be updated Without interference with :he VDG display function. Th1s signal must not be confused with the system vertical sync signal. Field sync is activated by the end of the vertical display window and deactivated by the trailing edge of ver­tical sync. This gives the MPU a total of thirty-two scan lines or 2.03 ms to update the d1splay memory. The MPU acknowledges the interrupt request from the VDG by bring­ing the negative memory select input (MS) to the VDG low. This puts the address bus output from the VOG into high­impedance state, thus relinquishing bus control to the MPU. The timing relationship of horizontal sync, row preset, and field sync are shown in Figures 7, 8, and 13.

The display memory is an element- by-element map of the display window on the screen. The VDG addresses the display memory storage locations in succession and translates their contents 1nto luminance and chrominance levels. The frequency of address update is dependent on the length of the display element. Recall that d1splay elements in major mode 1 are four periods and maJor mode 2 are either four or eight periods of the master clock. Data from the display memory is latched on every address transition. Hence, the data for the f1rst display element must be stable four or eight periods before the horizontal display window depending on the display mode selected. This t1ming require­ment is illustrated in Figure 6.

Examination of Figures 21 and 22 reveal that all display elements within major mode 1 are sim1lar while those within major mode 2 are largely dissimilar. Therefore, mode switch­ing between alphanumeric modes and semigraphic modes can be carried out freely. Care must be taken, however, when performing mode switching in maJOr mode 2. The only compatible modes are between CG1 and RG1, and between CG6 and RG6. Minor mode switching Within the same major mode in a given element row can be ad11eved as long as it IS

between compatible modes. It should be qu1te apparent that maJOr mode switching on an element-by-element basis is im­practical. It can be achieved, however, at the expense of added component count. The element formats 1n the VDG lend themselves to major mode SWitching between element

rows The presence of row preset 1n maJor model serves as il flAg for the beginnmg of a new elemer1\ row. Detection of th1s st~.Jnal can initiate a ma1or mode sw1tr:h from 1 to 2

D1splay memory size is a funct1on of the d1splay dens1ty Quite often a graphic display contains shapes that are several times larger than that of the dtsplay elements in the VDG ThiS is particularly true of certam video games. Much of the display consists of a fixed background. The vertical si?e of a display element can be doubled or quadrupled by simply ig­noring the lowest order or the first two low order verttcal ad­dresses, respectively, from the VDG Reduction of address l1nes naturally leads to reduction in memory size. Another method of memory reduction is to store objects or object fragments in ROM and store their display addresses 1n the RAM portion of display memory. Here, the larger the object fragment, the greater the memory saving.

ASSOCIATED DEVICES

MC6883 - SYNCHRONOUS ADDRESS MULTIPLEXER (SAM I

This device, a linear bipolar comparion to the MC6800 or MC6809E {external clock inputs), is primarily a VDG transparent-access controller. It allows the microprocessor to load and store to VDG display memory ("screen RAM") without waiting for a blank screen interval. Figure 1 shows a typical system using the SAM and t1e MC6809E. The in­herent interleaved direct memory accesses (IDMA) which occur, continuously keep the VOG updated with the proper data (independently of mode), as well as keeping the dynamic memory (used as system memory with the MC6833) refreshed. This is done through a IDMA process as well, dur· ing the time the VDG does not need display data (horizontal and vertical sync times).

In addition to being a transparent memory access and dynamic memory controller, the SAM also functions as an external clock generator for the MC6800/6809E (slight addi­tional circuitry is required for the MC6800l.

MC1372/1373 CHROMA/RF MODULATOR The MC1372 is a chrominance phase-sh1ft modulator with

built in RF up-converter. The part may be used Without the RF modulator for chroma only, or the RF oscillator may be defeated and composite chrominance and luminance can be obtained.

The MC1373 is an RF modulator only (similar to the sec· and half of the MC1372) and can be used to up-modulate separate luma and chroma s1gnals at the receiver for h1gh quality video reception

MOTOROLA Semiconductor Products Inc. )')

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FIGURE 23 - TYPICAL VDG SYSTEM

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loJ " 8

RF -. 1.'' Tank INT/EXT

3.58 MHz HS FS RP A/S :1 \

-~ L XTAL

External

ICLK PE CLR' Character

I Row Generator 0 f-ls /4 A ROM

APPENDIX A CUSTOM MC6847 ORDERING INFORMATION The following tnformation IS requ1red when ordering a

custom MCU. Th1s informatiOn may be transmttted to Motorola 1n the follov ... ilng media

PROM lsi MCM2716s or MCM2708s

MOOS dtsk hie

To 1nit1ate a ROM pattern for the MCU 11 IS necessary to l1rst contact your local f1eld service off1ce, local sales person. or your local Motorola representatiVe

PROMs ·· The MCM2708 or MCM2716 type PROMs, pro­grammed with the customer program (positive logic sense for address and data). may be subrn1tted for pattern genera­tion_ The PROMs must be r.le;:HIV marked to ir1d1cate wh1ch PROM corresponds to wh1ch address space (000-3FF HEX I. (400-?FF) or (000-?FFl. See Figure 24 for recommended marking procedure.

After the PROM(s) are marked they should be placed m conductive IC earners and securely packed Do not use styrofoam

Row Counter Char. Add

I 8

FIGURE 24 - PROM MARKING

-----.....r-

()()() 400

xxx -- C1JS!orr1er ID

VERIFICATION MEDIA

All or1gmal pattern rrH~d1a I PROMs or Floppy D1skl are filed for cor1tractual purposes and CJre not returned A cornputer IIStlf)g of the ROM code will be ~enerated and returned alonq With a IIS\If)g verlf1cat1on form The listing should be thoroughly checked and the verlf1cat10n form completed, s1gned. and returned to Motorola_ The s1gned verifiCatiOn form constitutes the contractual agreement for creat1on of the customer mask If des1red. Motorola w1ll program il blar1k

MOTOROLA Semiconductor Products Inc. 23

MC6847•MC6847Y

2716 Eflf"\()M lsupplu~d lJy the customer) from the cla!d file used to Cif)il\1~ 1\H' custorn rnask to ard tn the verrfrcdtrorr pro

cess

ROM VERIFICATION UNITS

Ten MC684/s contr11nmg the customer's ROM pattcrr1 will be sent lor )Huqr:~rn verl1rca\10n These untb wtll lrilvr: been ll1i-lde lJSrr·rq tire custom mask but are lor the purpuse of f~OM verdtCd\lon only. For expedrerrcy they arc usually un

rnar·ked, packilqed ttl cerarnrc, and tested only at ruom tempr~r<Jturc ilfld b vults These RVUs are rrrcluded rn the

rnilSk chilt~JC and an: rrot productron pcJrtS

FLEXIBLE DISKS

The rk;k rned1<:1 subrrutterl must lw smgle-srded, srnol<? dnnsrty, 8 tnch. MDOS cornpattble tloppres The customer

rnust wnte tlrl-~ hrrrcHy ftle nilrne and comparry r1arne Dn tire

d1sk wrth a lelt-trp pnrr Ttrc llutJIIH;::, <Hr~ IHJ\ tn bt~ rt,lrHrH~d by Motorola as they nrn used lnr <llr:illvi-ll Sl()ri-lqA lire mrnrnrurr1 MOOS systern f1le~; nnJ~;t tw rHr tire~ rk,k .~:-, well ns tlw ab

solute binary object frle (fdenarne 1_0 type of l1lel An obwct file made from a rnernory dump usmq lhr: F-'\OLLOUT com­mand rs also adrnrss<Jllle Cor1srdr~r subrnr\\1nn a source listing as well as the follow1nq 1rlr;c; lilc~ndrTre .I_ X (EXOR­crser® loadable form<Jtl ,1nd frlcrwrne .SA (ASCII Source Code) These files wrll of course be kept confrdentral and are used 11 to speed up the process 1r1 house rf nny problerns <Jrlse, cmd 2) to sreed up our customer to factory rnterf<-Jce 1f a user frnds any software errors ar1d rHc;eds :=JSsrstance qurckly

from the factory representatives

MDOS 1s Motorola's Drsl<. OtWrd\IIIIJ Sv:-,u~rr: ,-JVaiiRblc Drr

dPvelopmcr1t systerns suc!r d~.; I XUHu~;r~r·-; rl! EX OR set~, etc

FIGURE A-2

Customer Name----------------------------------------------------------------------------------------------------

Address

City

Phone ( _____ I ___________________ S tate -------------------------------"-'P ------------------------

Contact Ms/Mr __________________________________________________________________________________________ __

Customer Part Number

Pattern Med1a 2708 PROM 2716 PROM

MOOS Dtsk

(Note 2! ---------------

------ .. ------------ -

Other (NOTE Other med1a requ1res pnor factory approval!

Srgnature

TIt !e ----------------------------· ------------------------------------------------------------------

'-'!! Reg1stered tradernork of Motorolo lrlC

EXORset IS a trademark of Motorola Inc

MOTOROLA Semiconductor Products Inc. 24

'

MC6847•MC6847Y

OUTLINE DIMENSIONS

P SUFFIX PLASTIC PACKAGE

CASE 711-03

~~METERS DIM MIN MAX

+ c f.!'-.

f __ -1

f%-

51.69 52.45 13.72 -14.22 3 94 -5.08 036 0~6

~52

~~-~r~s2c16 0.20 0.38 2 92 3.43

INCHES MIN MAX 2.035 2.065 0.540 0.560 0.155 0.200 0.014 0.022 0.040 0.060

~rrn7:'i F ~-JHL _.jG:~ - ·- f ~·- D K· _' ·- -M

J K L M N

15.24-BSc ()0 150 o s U ___ 1 ,o1_

0.100 BSC 0.065 0.085 0.008 0.01~ 0115 0.135 o.soo sse ao 15o

0.020 0.040

[ D FA-I

_,,_ F

rr -~-~~--·

H . --- D

O[ATING PiAN[

J] ., . r-L--l ~ +ell IN I

r-r 1

,I I

G -- J M-

L SUFFIX CERAMIC PACKAGE

CASE 715-04

NOTES·

NOTES 1 POS!TIONAL TOLERANCE OF LEADS (0),

SHALL BE WITHIN 0.25 mm (0.010) AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLAN£ AND EACH OTHER.

2 DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL

3. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

MILLIMETERS INCHES

1 DIM MIN MAX Ml!"_ MAX ~ 50.29 51.31 1.9-80 2.520

~ ~f~~~~ •;:j~ ~:Wcr--%.~¥o-D 0.38 --~ _ _!!,_0]5 ~ ~- __ 0._7_6 -~~~~30_~

G 254 B_SC 0.10~~

J o~~l----!?~3]- I~ -~~ -K- 2.54 4.19 0.100 0.165 ~ !~~9-9 -i~K~~M ~-

M 100 ~ L_l'!_ -Tg_2 I •5i_LQj4"o -o.oso

1 DIMENSION[&] IS DATUM 2 POSITIONAL TOLERANCE FOR LEADS

[-$_[o_.251Q.010l (MJ] i-J ~ 3 ITJ IS SEATING PLANE 4 DIMENSION "l" TO CENTER OF LEADS

WHEN FORMED PARALLEL

~ DIMENSIONING ANO TOLlRANCING

PER ANSI Y14.5, 1913

MOTOROLA Semiconductor Products Inc. 28

MC6847•MC6847Y

OUTLINE DIMENSIONS ICONTINUEDI

S SUFFIX CERDIP PACKAGE

-INCHE-s-CASE 734 03 ~!!{~_gR~

DIM MIN MAX MIN MAX

f4- ~_u1:·~ 2.020 2 096

"""""""""""""""' ,..,,..,,..,,.., f-! .. 12.70 1~.49 0 500 0.610

" " I ~--4_06 -----s:84 0 i-6o -~~ 0 0.38 0.56 o_oi-s" 0.022

F 1_27 1.65 0.050 0.065

~ 8 r+ r--/-~4f!SC 0.100 BSC 0.20 __ j 0.30 0.008 0.012

j ' 3 18 ..J --~-96 0.125 0.160 l 15.2~ BSC 0.600 BSC

' " M 5" J5U-- !io•o+ Jso

vvvvvvvvvvvvvv vv ~. 0.51 1.27 0.020 J{~

A -·-·· I c [ l =J NOTES

~~-+if~- I DIMENSION-A-IS DATUM 1 POSITIONAL TOLERANCE

FOR LEADS:

.. ~I (· I+ 1 ~0.25(0.010)e 1 T lA e 1

-i Gf• :- -F ~~--0 T -! ~ M 3 [TJ IS SEATING PLANE 4 DIMENSION L TO CENTER

OF LEADS WHEN FORMED PARALLEL

5 DIMENSION A AND B INCLUDES MENISCUS

.--------------------------Mot(1rola rt•servf's the r 1ght 10 makP ch;ln<.J<>'> 10 ilny produc1s here•n to 1mprov•• r•~loabolotv f uncloon or de~llJrl Motorola dm•-; not assume any llablll!y ans1n\-J out ol thP appi 1cat 1on or usc ol any prod1Wt or c•rcu•t rlpscr1ht>d hPrPin. ne1th;•r dm"> <1 UHlV<'V ilf1',' IICI'Jl<.,f' und;;r ,,.., p<ltf'nt r•ghts nor the r1ghts ol ottwrs

MOTOROLA Semiconductor Products Inc. 3501 ED BLUESTEIN BLVD AUSTIN TEXAS 78721 • A SUBSIDIARY OF MOTOROLA INC

(

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