M. Lozano, E. Cabruja, A. Collado Summary of Bump Bonding Techniques for Pixel Systems Centro...
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Transcript of M. Lozano, E. Cabruja, A. Collado Summary of Bump Bonding Techniques for Pixel Systems Centro...
M. Lozano, E. Cabruja, A. Collado
Summary of Bump Bonding Techniques for Pixel Systems
Centro Nacional de Microelectrónica
Barcelona (Spain)
VERTEX 2000 2/31
INDEX
Pixel systems Summary of bump bonding techniques Technology comparison and forecasts Testing issues Thermal issues Conclusions
VERTEX 2000 3/31
Pixels systems
Pixel detector chip Two dimensional diode array Material: Si, diamond, SiC, GaAs, CdTe, CdZnT
Electronics chip Built on a separate substrate Provides: Amplification, data storage, data compression,
communication
Pixel detector bonded to electronics
VERTEX 2000 4/31
Pixel systems
Small pixel size (50 -250 µm) High number of pixels (100 - 10 000) Very low leakage current Low cross talk between pixels Unaffordable with conventional bonding technologies Ideally suited for bump bonding flip chip technology Not commercially available (yet)
Many difficulties to be solved
VERTEX 2000 5/31
Bump bonding flip chip technology
Process steps: Direct bonding Rerouting
» Detector and/or amplifier chips Under Bump Metallisation (UBM) Bumping
» On detector or on amplifier chip, depending on the application
Flip chip Reflow, anneal o adhesive bonding Underfilling
VERTEX 2000 6/31
Rerouting
Rerouting Adapt pad distribution between
detector and electronics chips Material: Al Up to 4 layers High reliability (99.8%) Increase cost Best to adjust pixel and
amplifier size to avoid it
Dielectric choice Inorganic
» Deposited SiO2, Si3N4
» Spin-on glass (SOG) Organic:
» Polyimide Photosensitive polyimide
» Reduce complexity and cost. Another choice for the
detector: no passivation
VERTEX 2000 7/31
Under Bump Metallisation (UBM)
Aluminum not suitable for direct bump bonding Al2O3 passivation layer Au-Al intermetallics
Process steps (mod. 1) Sputter etching metal layers Normal photolithography Metal etching
Process steps (mod. 2) Spin on 5 µm photoresist Sputter etching metal layers Lift off
Metal layers : 1st: Diffusion barrier and adherence 2nd: Soldering 3rd: Passivation for 2nd layer
Examples: Ti/Ni/Au Ti/Au/Cu/Au
VERTEX 2000 8/31
Bumping technologies
Evaporation through mask Evaporation with thick photoresist Screen printing Stud bumping (SBB) Electroplating Electroless plating Conductive Polymer Bumps
VERTEX 2000 9/31
Evaporation through mask (C4)
Process steps Mask alignment Sequential evaporation of
» Thin UBM layer: Cr/Cr-Cu/Cu/Au
» Ball: Pb/Sn Reflow into spheres
Characteristics Proprietary of IBM Need for a metallic mask Pitch 200 µm Bump height 100 - 125 µm Expensive
VERTEX 2000 10/31
Evaporation with thick photoresist
Process steps Spin on thick photoresist (30 - 60 µm) Sequential evaporation of
» Thin UBM layer: Cr/Cr-Cu/Cu/Au
» Ball: Pb/Sn Lift off photoresist Reflow into spheres
Characteristics Variation of previous method Higher pitch
VERTEX 2000 11/31
Screen printing
Process steps Stencil alignment Solder paste deposition with a squeegee Reflow into spheres
Characteristics Minimum pitch: 200 µm Stencil printing thickness: 100 - 50 µm
Same bump height Solder pastes:
» Sn/Pb, Sn/Pb/Ag, Sn/Ag, Sn/Sb» Pb free pastes: In, Pd, Sn/Ag/Cu
Most widespread Very high yield
VERTEX 2000 12/31
Stud bumping (SBB)
Process steps Sequential creation of a ball with a
ball bonder and ball bond Overall planarisation of bumps Optional reflow into spheres
Charactersitics Ball material: Au (Pb free) Min. ball size: 45 µm (3 wire ) Min. pitch: 70 µm No need for UBM in substrate Usable in single chips No self alignment Cheap, but low throughput
Stud Bump BondingSolder Ball BumpingSBB
VERTEX 2000 13/31
Electroplating bump bonding
Process steps Ni/Au sputtering over the
whole wafer Photolithography to delimit
bump areas
(thick photoresist) Electrolytic deposition:
» Cu layer
» Pb/Sn bumps Photoresist elimination Etch wafer metalisation Reflow into spheres
VERTEX 2000 14/31
Electroplating bump bonding
Characteristics Other bump materials:
» Au
» Au/Sn The plating process can induce
wafer stress Equipment compatible with
other microelectronic technologies
Minimum pitch 40 µm Bump height 30 - 75 µm
Difficulties: Bump height highly dependent
in current density Variations in current density
across the wafer gives non uniformity in bump height
Difficult in using thick photoresists
» Deposit
» Align
» Exposure
VERTEX 2000 15/31
Electroless plating
Process steps Pad conditioning Zinkation Bump electroless deposition
Characteristics No need for electrodes Photolithography not required Bump material: Ni/Au Minimum pitch 75 µm Bump diameter 40 µm Bump height 5 - 30 µm
VERTEX 2000 16/31
Conductive Polymer Bumps
Process steps Thick photoresist patterning Conductive polymer filling Selective polymer curing Photoresist removal
Characteristics Very new procedure Minimum bump size 100 µm Pb free Higher contact resistance
» Rc > 100 m
VERTEX 2000 17/31
Flip chip alignment
Special equipment required Pick and place Alignment
Accuracy better than 1/3 bump Alignment State of the art:
Mechanical: 5µm Infrared: 2µm
Self alignment during reflow allows certain degree of tolerance
Industrial equipment requires wafers as substrates, not chips
VERTEX 2000 18/31
CTE (ppm/ºC)
Si 2.6C 1.18SiC 4.6 - 5.9GaAs 6.86CdTe 4.9CdZnTe 4.89
Melt. Point (ºC)
57Bi 43Sn 13962Sn 36Pb 2Ag 17963Sn 37Pb 18390Sn 9.5Bi 0.5Cu 19896.5Sn 3.5Ag 22180Au 20Sn 28095Pb 5Sn 308
Thermal stress: CTE mismatch No problem with silicon detectors Could be an issue with alternative
materials
Reflow Reflow
Soft bumps (PbSn): direct reflow Hard bumps (Au, Ni) : solder paste High temperature step
» Reflow temp. > Melt. Point + 40ºC
Use low reflow temperatures Problems with further soldering
steps of the pixel system
VERTEX 2000 19/31
Adhesive bonding
Isotropic (ICA) or anisotropic (ACA) conductive adhesives
Eliminates reflow Requires hard bumps:
Au, Au/Sn, Ni
There are anisotropic adhesive pastes and films
Advantages Low thermal processing Eliminates solder mask Excellent fine pitch No clean Pb free
Disadvantages Lower mechanical strength No self-alignment
» Higher accuracy of alignment Higher electrical resistance Higher thermal resistance More difficult to rework
VERTEX 2000 20/31
Underfilling
Optional Curing temperature: 140 -
180 ºC Materials:
Silicones Epoxies
In pixel systems it will be necessary to evaluate: Interaction of fillers with
detector surface Radiation resistance of the
materials used
Advantages Improve reliability Reduce thermal stress Increase fatigue resistance Protect from moisture and
contamination Avoid corrosion
Disadvantages Difficults reworking Need of a dispensing machine Increase cost
VERTEX 2000 21/31
Bump technology comparison
Pb alloys can be alfa sources
Min.ball size
Min.Pitch
Bumpmaterial UBM Substrate Comments
Evaporationthrough mask
100 µm 250 µm Pb/Sn Cr-Cu Wafer No fine pitch
Screen printing 100 µm 200 µmPb/Sn
Sn/Ag/CuTi-Ni-Au Wafer
Most widespreadCheap
Stud bumping(SBB)
70 µm 45 µmAu
Pb/SnNo need
WaferChip
Low throughputNo self-alignment
Electroplating 25 µm 40 µmPb/Sn
Cu/Sb/Ag/Sn
Cr-CuTiW-Cu-Au
Ti-Ni-AuWafer
Need for tight control
Electroless plating 40 µm 70 µm Ni/Au ZnWaferChip
Need for pad conditioning
Conductive PolymerBumps
100 µm 150 µm Polymer Cr-Au Wafer Very new
Min.ball size
Min.Pitch
Bumpmaterial UBM Substrate Comments
Evaporationthrough mask
100 µm 250 µm Pb/Sn Cr-Cu Wafer No fine pitch
Screen printing 100 µm 200 µmPb/Sn
Sn/Ag/CuTi-Ni-Au Wafer
Most widespreadCheap
Stud bumping(SBB)
70 µm 45 µmAu
Pb/SnNo need
WaferChip
Low throughputNo self-alignment
Electroplating 25 µm 40 µmPb/Sn
Cu/Sb/Ag/Sn
Cr-CuTiW-Cu-Au
Ti-Ni-AuWafer
Need for tight control
Electroless plating 40 µm 70 µm Ni/Au ZnWaferChip
Need for pad conditioning
Conductive PolymerBumps
100 µm 150 µm Polymer Cr-Au Wafer High RcVery new
VERTEX 2000 22/31
1999 SIA Technology Roadmap Technology roadmap predictions Not technological details High pitch flip chip (< 50 µm) as needed for high resolution pixel
detectors Seems not to be of primary commercial interest in USA It will remain at lab level until 2007 Probably price will not decrease in short term
Flip chip pitch area (µm) 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008
High performance
200 200 200 200 200 200 150 150 150 150
Low cost applications 180 165 150 130 120 110 100 70 50 35
VERTEX 2000 23/31
1999 Japan JISSO Technology Roadmap Similar figures to SIA Roadmap Japan is leading Pb free bumps
For environmental reasons, but good for radiation detectors
Although not listed, electroless should also be considered Pitch target: 50 µm
1999 2000 2005 2010Max number of pads 256 - 2300 560 - 4300 560 - 8400 560 - 14400Chip thickness (µm)Area pad pitch (µm) 250 - 70 120 - 50 100 - 50 50Bump diameter (µm) 150 - 100 100 - 60 60 - 40 50 - 30Bump height (µm) 120 - 80 100 - 60 80 - 40 60 - 30Bump material PbSn, AuBump formation methodBump bonding material SnPb paste
Electroplatting, Stud bumpingSnPb paste, Pb free solder
PbSn, Au, AgSn
650 - 175 650 - 100
VERTEX 2000 24/31
Testing issues
Determine electrical properties of bump bonds Contact resistance Temperature variation
Determine re-routing capacitances
Leakage between bumps Evaluate reliability of bump
bonds
Contact Resistance Very small resistance values (m) Requires the use of special test
structures Contact resistance of:
» Rerouting metal measurement
» UBM
» Bumps
VERTEX 2000 25/31
Rerouting metal contact measurement Test chip with special Kelvin
contact resistance test structures Chip metal with UBM Flip chip to substrate through ball UBM to substrate through ball
VERTEX 2000 26/31
Contact resistance results
0
1
2
3
4
5
-40 -20 0 20 40 60 80 100
Temperature (ºC)
Contact resistance (mW)
Al flip chip with Al substrate (through ball)
Au with Al on substrate
Au flip-chip with substrate (through ball)
VERTEX 2000 27/31
Other testing issues
Leakage between bumps: Final leakage current with the system finished. Difficult to measure Need not only for test chips, but for test system
Bump bonding yield Find for dead channels Separate dead channels at the amplifier or during bonding
System reliability
VERTEX 2000 28/31
Thermal issues
High density of heat generation with difficult evacuation
Bumps can evacuate heat but is not the best way Heatsink needed
In substrate chips In backside of flipped chip With forced convection
» Air cooled
» Liquid cooled
Good thermal design Good material choice for heat evacuation
VERTEX 2000 29/31
Thermal measurements
Using specific test chips with heaters and temperature sensors
Thermal measurements Thermal conductivities Thermal resistances
Thermal modeling Thermal conductivities Heat dissipation
VERTEX 2000 30/31
Example of thermal measurements
CNM MCM-D tecnology Thermal conductivities
» Si: 150 W/mK
» Pb/Sn bump ball: 5 W/mK
» Underfill: 0.3 W/mK
» Polyimide: 0.2 W/mK Thermal resistance
» 1 cm2 Si chip: 0.03 K/W
» 1 ball: 850 K/W
» 1000 ball: 0.85 K/W Thermal model:
» Heating of test flip chip without heatsink
40
50
60
70
80
90
100
0.4 0.6 0.8 1 1.2 1.4 1.6 1.8Power (W)
Flip chip temperature (ºC)
Modelled
Measured
VERTEX 2000 31/31
Conclusions
Flip chip bump bonding is the perfect technology for pixel systems
Still difficulties to be solved Pb alpha emission Thick photoresist manipulation Testing Thermal behavior
Commercial interest 50 µm pitch still not
commercially available Prices will decrease
CNM is involved in different EC projects SUMMIT
» MCM-D technology
» Screen printing
» Finished CIRRµS
» Jan 2000 - Dec 2002
» High volume, low cost, Pitch 40 µm
» Partners: Philips, CNM, CS2, Freudenberg, IMEC, TEMIC, TUB
» Evaluation of different technologies