Modeling of the Impact of Boundary Conditions on AlGaN/GaN HEMT Self Heating

M. Bernardoni, N. Delmonte, R. Menozzi

Department of Information Engineering, University of Parma, V.le G.P. Usberti 181A, 43124 Parma, Italy roberto.menozzi@unipr.it, Tel. +39-0521-905832

Keywords: Gallium nitride, thermal effects, finite-element modeling, reliability, packaging. Abstract

This work shows results of static and dynamic finite-element thermal modeling of AlGaN/GaN HEMTs highlighting the importance of boundary conditions often overlooked in simplified models. These include top-side heat removal, thermal boundary resistance between GaN and substrate, die-attach, and non-isothermal back-side. Both SiC and Si are considered as possible substrates. We also show that careful lumped-element modeling can yield thermal models accurately capturing the static and dynamic behavior without sacrificing the proper treatment of boundary conditions. INTRODUCTION Self-heating is one of the main performance and reliability limiters for power amplifier (PA) devices and MMICs. GaN-based HEMTs, today’s most promising technology for microwave PAs, are a case in point, since exploiting the outstanding properties of the AlGaN/GaN system necessitates that the thermal aspect be carefully addressed in the device design and manufacturing. Finite Element (FE) modeling can be of great help in this respect, given the complexity of the structures, which are wide, three-dimensional, made of different materials (showing significant temperature dependence of the thermal conductivity), and include top- and back-side features and thermal boundary conditions that, if overlooked, end up compromising the modeling results.

In this work we use a FE commercial simulator to solve the heat transport equation, specifically focusing on aspects that are often overlooked: the impact of die-attach and finite backside heat-sinking, the thermal boundary resistance (TBR) [1] between GaN and substrate, and the effect of metal lines and pads. We also use FE simulation to develop lumped-element (LE) models for self-consistent electro-thermal simulations [2], [3].

NUMERICAL SIMULATIONS

We analyze a HEMT made of cells of 12 fingers each; each finger is 150 µm wide, and the separation between

adjacent fingers is 30 µm. The cell’s gate periphery is therefore 1.8 mm, but thanks to symmetry planes (which can be replaced by adiabatic boundary conditions), only half of the fingers and half of the finger width need to be modeled. For the same reasons, a symmetric arrangement of cells allows to limit the study to a single cell. This work considers the two relevant cases of SiC and Si substrate. The simulated 12-finger cell is shown in fig. 1. It has a 2.5 µm-thick GaN layer on top of the substrate; we considered two values for the substrate thickness: 250 µm and 125 µm. We include in our simulations the often neglected TBR between GaN and substrate, as a 50 nm-thick interfacial layer with contact thermal conductivity kC

TBR. The back of the substrate is stuck to a 40 µm-thick Sn(96%)-Ag(4%) die-attach layer with thermal conductivity kDA. Top-side source and drain metals (another often overlooked feature that significantly impacts the thermal budget) are 4 µm-thick gold. Boundary conditions are adiabatic everywhere, except on the back of the die-attach and on the top metal pads, where contact conductivities, kC

BACK and kCTOP, respectively, are varied to

simulate different combinations between isothermal (kC = ∞) and adiabatic (kC = 0) conditions. GaN, SiC, and Si thermal conductivities are temperature-dependent [4].

Fig.1 Simulated AlGaN/GaN HEMT structure. The different shades of gray correspond, from top to bottom, to GaN, substrate (SiC or Si), and die-attach layers. Gold metal lines on top exchange heat through the square pad areas.

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DC SIMULATION RESULTS

Fig. 2 shows the temperature profile along a vertical line originating in the center of the hottest (innermost) finger, for the two SiC thicknesses and for two backside boundary conditions: the ideal isothermal case (kC

BACK = 0), and a realistic case where kC

BACK = 3.6·105 W· K-1·m-2, corresponding to a case-to-ambient thermal resistance of 10 K/W for the 12-finger cell. The dissipated power is 5.4 W for the 1.8 mm cell (i.e., PD = 3 W/mm); there is no heat exchange from the front-side pads (kC

TOP = 0). Note the sharp drop on the TBR (kC

TBR = 3.0·107 W·K-1·m-2 [1]) and the impact of the die-attach (kDA = 45 W·K-1·m-1).

Fig. 2 Temperature profiles under the hottest (innermost) finger, for different SiC substrate thicknesses and for ideal isothermal (300 K, bottom two curves), and non isothermal (kC

BACK = 3.6·105 W· K-1·m-2, top two curves) back-side boundary conditions. PD = 3 W/mm.

The effect of heat removal from the front-side metal pads is illustrated by fig. 3, for both SiC substrate thicknesses, in the case of kC

BACK = 3.6·105 W· K-1·m-2, kCTBR = 3.0·107

W·K-1·m-2, kDA = 45 W·K-1·m-1. Moving from the case of adiabatic top (kC

TOP = 0) to better heat removal from the front-side pads, the peak channel temperature (TMAX) is drastically reduced.

The corresponding simulations for the Si substrate case are shown in fig. 4. Due to the worse thermal conductivity of Si compared with SiC, temperatures are higher than in fig. 2, and the substrate thickness makes a bigger difference.

Finally, fig. 5 shows the impact of the GaN/SiC TBR [1], and the role of the die-attach thermal conductivity kDA.

DYNAMIC SIMULATION RESULTS

Fig. 6 shows the temperature profile along a vertical line originating in the center of the hottest (innermost) finger, for 125 µm-thick SiC substrate, at various times after the application of a power step (PD = 3 W/mm).

Fig. 3 Effect of the front-side pad thermal conductivity on the peak channel temperature. PD = 3 W/mm. The substrate is SiC. The backside is non-isothermal (kC

BACK = 3.6·105 W·K-1·m-2).

Fig. 4 Temperature profiles under the hottest (innermost) finger, for different Si substrate thicknesses and for ideal isothermal (300 K, bottom two curves), and non isothermal (kC

BACK = 3.6·105 W· K-1·m-2, top two curves) back-side boundary conditions. PD = 3 W/mm. A few facts are worth commenting upon. (1) The temperature of the active area starts rising 1 ns after the power step; after 10 ns it has increased by some 10°C; these times can be expected to scale roughly with the gate periphery. (2) 1 µs after the application of the power step, the heat front reaches the SiC substrate; up to this point in time (i.e., for very short-pulsed operation), the substrate material, whether SiC, or Si - or even sapphire for that matter - would not make a difference. (3) The backside temperature starts increasing significantly some 100 µs after the power step; this indicates, for example, that in the case of pulses shorter than 100 µs with small duty cycle, heat removal from the backside is ineffective. (4) Steady-state conditions are reached at about 10 ms.

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Fig. 5 Effect of the GaN/SiC TBR (left curve, kDA = 45 W·K-1·m-1) and die-attach thermal conductivity (right curve, kC

TBR = 3.0·107 W·K-1·m-2) on the peak channel temperature. PD = 3 W/mm. kC

BACK = 3.6·105 W· K-1·m-2, kCTOP = 106

W·K-1·m-2, tSiC = 125 µm.

Fig. 6 Temperature profiles under the hottest (innermost) finger, for 125 µm-thick SiC substrate, at various times after the application of a power step (PD = 3 W/mm). kC

BACK = 3.6·105 W·K-1·m-2; kC

TOP = 0; kCTBR = 3.0·107 W·K-1·m-2;

kDA = 45 W·K-1·m-1.

When heat removal from the top-side is considered (kC

TOP = 106 W·K-1·m-2), the temperature profiles (not shown here) are the same as in fig. 6 up to 100 µs, then deviate significantly toward cooler temperatures from 1 ms on.

The corresponding transient for the case of Si substrate (not shown here) is quite similar, both qualitatively and quantitatively, once the power density has been downscaled so that the steady-state peak temperature is about the same as for the SiC substrate.

LUMPED-ELEMENT THERMAL MODELING

Although FE models are powerful and accurate, they are not amenable to integration in circuit design suites. It is therefore important to develop LE models featuring lumped thermal resistances and capacitances that can be easily treated by tools such as ADS, PSPICE, etc., or by computational tools like MATLAB, where they can be self-consistently coupled with large-signal electrical models [2].

As an example, we model a 2x150 µm HEMT structure, which is made, from top to bottom, of: (1) 2.5 µm-thick top GaN layer; (2) 125 µm-thick SiC substrate; (3) 50 µm-thick Sn(96%)-Ag(4%) die-attach. The model is implemented into Agilent’s ADS. Again, thanks to symmetry, simulation can be restricted to one quarter of the HEMT volume.

The model we present here shows novel features, all of which have significant impact on the overall accuracy:

(a) it gives a realistic 3D representation of heat flow in the whole HEMT structure;

(b) it includes the TBR between GaN and the SiC substrate;

(c) it includes the die-attach layer. The number of gate fingers is at this stage limited to two

for simplicity, but larger numbers of fingers can be modeled. Moreover, top-side heat spreading and sinking elements like metal lines and pads can be included, as well as back-side heat sinking limitations (here we assume perfect back-side heat sinking). Finally, analyzing the case of Si substrate requires only straightforward parameter modification.

Fig. 7 Building blocks of the 3D LE thermal network. The block on the left represents the generic element of volume, while that on the right is used to model surface elements.

The network is made of the building blocks in fig. 7. Each block models the thermal behavior of an element of volume; the resistance element is obtained by multiplying the thermal resistivity (i.e., the inverse of the thermal conductivity) by the length of the associated heat path and dividing it by the path section. The temperature dependence of thermal conductivities introduces a significant non-linearity in the Fourier equation, which is often overlooked in compact models, at the cost of reducing the model accuracy. The thermal conductivities used in the model are again those used in [4]; kDA = 45 W·m-1·K-1, kC

TBR = 3.0·107 W·K-1·m-2. Thermal capacitances are connected between each node and

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thermal ground, and computed multiplying the unit-volume thermal capacitance, i.e., the product of specific heat capacity times the material density of the material, by the element volume. The values of specific heat capacity we used are 470 J/(kg·K) for GaN, 680 J/(kg·K) for SiC, 240 J/(kg·K) for the die-attach, while densities are 6110 kg/m3 for GaN, 3211 kg/m3 for SiC, 7330 kg/m3 for the die-attach.

The dimensions of the elements of volume in which the structure is discretized increase exponentially from the heating area towards the boundaries, which allows simulating large volumes with a relatively small number of elements. A total of 500 blocks was used to model the 165x144x177.5 µm3 structure; 50 additional resistances connecting the GaN with the SiC simulate the TBR. The LE thermal model of the complete structure can thus be built in a totally modular way by instantiating the building block models, the resistance and capacitance values of which are automatically scaled based on the element dimensions, thermal conductance and specific thermal capacitance.

Top contacts along the gate width inject currents equal to the dissipated power densities. With the nodes of the bottom (back of the die-attach) grounded, the value in volts of the voltage at each node gives the local temperature increase over ambient, in Kelvin degrees.

Fig. 8 shows a comparison between the stationary temperature profile along a vertical line passing through the central point of the finger (i.e., the hottest spot) as given by the FE simulation and by the LE thermal network. The match between the two is good, considering that there is no fitting involved. The sharp temperature step at 175 µm is due to the TBR between GaN and SiC.

Fig. 8 Vertical temperature profile for the FE (solid line) and LE (symbols) models. The power is 1 W on the 1x150 µm finger, i.e., 6.67·105 W/cm2, or 6.67 W/mm.

The response to a power step is shown in fig. 9. Again, the match between the FE model and the LE model is good, considering the absence of fitting parameters. It is also worth noting that the presence of various materials in the stack

makes the heating dynamics quite different from that of a single time constant, which nevertheless is commonly used to describe self-heating in large-signal models.

Fig. 9 Self-heating time response to a 6.67 W/mm power step for the LE (solid line) and FE (dashed line) models. CONCLUSIONS

In conclusion, we have shown results of finite-element thermal simulation of AlGaN/GaN HEMT structures highlighting the importance of thermal boundary conditions that are often overlooked in simplified thermal modeling. These include top-side heat removal through metal pads, thermal boundary resistance between the GaN active layer and the substrate, the back-side die attach, and non-isothermal back-side. Both SiC and Si have been considered as substrate materials, and static as well as dynamic conditions have been studied. Finally, we have shown that careful lumped-element modeling can yield efficient thermal models that capture the static and dynamic thermal behavior of the device with good accuracy, without sacrificing the proper treatment of thermal boundary conditions. REFERENCES [1] A. Sarua et al., IEEE Trans. El. Dev., vol. 54, Dec. 2007, pp. 3152-3158. [2] F. Bertoluzza et al., IEEE Trans. Microw. Th. Techn., vol. 57, Dec. 2009, pp. 3163-3170. [3] M. Bernardoni et al., Proc. SPEEDAM 2010, pp. 556-561. [4] F. Bertoluzza et al., Microel. Reliab., vol. 49, 2009, pp. 468-473. ACRONYMS

HEMT: High Electron Mobility Transistor PA: Power Amplifier MMIC: Monolithic Microwave Integrated Circuit FE: Finite Element TBR: Thermal Boundary Resistance LE: Lumped Element 3D: Three-Dimensional

232 CS MANTECH Conference, May 16th-19th, 2011, Palm Springs, California, USA