LTC2058 (Rev 0)...LTC 2058 1 0 Document Feedback For more information TYPICAL APPLICATION FEATURES...
Transcript of LTC2058 (Rev 0)...LTC 2058 1 0 Document Feedback For more information TYPICAL APPLICATION FEATURES...
LTC2058
1Rev 0
For more information www.analog.comDocument Feedback
TYPICAL APPLICATION
FEATURES DESCRIPTION
36V, Low Noise Zero-Drift Operational Amplifier
The LTC®2058 is a dual, low noise, zero-drift operational amplifier that offers precision DC performance over a wide supply range of 4.75V to 36V. Offset voltage and 1/f noise are suppressed, allowing this amplifier to achieve a maximum offset voltage of 5μV and a DC to 10Hz input noise voltage of 200nVP-P (Typ). The LTC2058’s self-calibrating circuitry results in low offset voltage drift with temperature, 0.025μV/°C (Max), and practically zero drift over time. The amplifier also features an excellent power supply rejection ratio (PSRR) of 150dB and a common mode rejection ratio (CMRR) of 150dB (Typ).
The LTC2058 provides rail-to-rail output swing and an input common mode range that includes the V– rail. In addition to low offset and noise, this amplifier features a 2.5MHz (Typ) gain-bandwidth product and a 1.6V/μs (Typ) slew rate.
Wide supply range, combined with low noise, low offset, and excellent PSRR and CMRR make the LTC2058 well suited for high dynamic-range test, measurement, and instrumentation systems.
APPLICATIONS
All registered trademarks and trademarks are the property of their respective owners.
n Supply Voltage Range: 4.75V to 36V n Offset Voltage: 5μV (Maximum) n Offset Voltage Drift: 0.025μV/°C (Maximum, –40°C
to 125°C) n Input Noise Voltage
n 200nVP-P, DC to 10Hz (Typ) n 9nV/√Hz, 1kHz (Typ)
n Input Common Mode Range: V– – 0.1V to V+ – 1.5V n Rail-to-Rail Output n Unity Gain Stable n Gain Bandwidth Product: 2.5MHz (Typ) n Slew Rate: 1.6V/μs (Typ) n AVOL: 150dB (Typ) n PSRR: 150dB (Typ) n CMRR: 150dB (Typ) n Shutdown Mode
n High Resolution Data Acquisition n Reference Buffering n Test and Measurement n Electronic Scales n Thermocouple Amplifiers n Strain Gauges n Low Side Current Sense n Automotive Monitors and Control
150pF
+
–½ LTC2058
–
+½ LTC205818-BIT DAC WITH SPAN SELECT
LTC2756
VOSADJ
RCOMRIN ROFS
REF5V
REF RFB
IOUT1
VOUT IOUT2
GND
VDD
GND
GAINADJUST
GEADJ
20pF
0.1µF
5V
4
2058 TA01a
SPI WITHREADBACK
OFFSETADJUST
18-Bit Voltage Output DAC with Software-Selectable Ranges 20V Step Response of DAC I to V
VS = ±15VDAC SPAN = ±10V
15µs/DIV
V OUT
(5V/
DIV)
2058 TA01b
Output Voltage Noise, ±10V Span, VOUT = 0VMEASUREMENT BANDWIDTH VOUT NOISE10kHz 12μVRMS
100kHz 80μVRMS
LTC2058
2Rev 0
For more information www.analog.com
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
Total Supply Voltage (V+ to V–) ..............................................................40VInput Voltage –IN, +IN ...................................V– – 0.3V to V+ + 0.3V SD, SDCOM .............................V– – 0.3V to V+ + 0.3VInput Current –IN, +IN ........................................................... ±10mA SD, SDCOM ..................................................... ±10mA
(Note 1)
1
2
3
4
8
7
6
5
TOP VIEW
9V–
V+
OUTB
–INB
+INB
OUTA
–INA
+INA
V–
S8E PACKAGE8-LEAD PLASTIC SO
TJMAX = 150°C, θJC = 5°C/W, θJA = 33°C/WEXPOSED PAD (PIN 9) IS V–, MUST BE SOLDERED TO PCB
123456
SDV–
OUTAGUARD
–INA+INA
121110987
SDCOMV+
OUTBGUARD–INB+INB
TOP VIEW
13V–
MSE PACKAGE12-LEAD PLASTIC MSOP
TJMAX = 150°C, θJC = 10°C/W, θJA = 40°C/WEXPOSED PAD (PIN 13) IS V–, MUST BE SOLDERED TO PCB
TUBES TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE
LTC2058IMSE#PBF LTC2058IMSE#TRPBF 2058 12-Lead Plastic MSOP –40°C to 85°C
LTC2058HMSE#PBF LTC2058HMSE#TRPBF 2058 12-Lead Plastic MSOP –40°C to 125°C
LTC2058IS8E#PBF LTC2058IS8E#TRPBF 2058 8-Lead Plastic Small Outline –40°C to 85°C
LTC2058HS8E#PBF LTC2058HS8E#TRPBF 2058 8-Lead Plastic Small Outline –40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Parts ending with PBF are ROHS and WEEE compliant.
For more information on tape and reel specifications, go to: Tape and reel specifications Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
Differential Input Voltage +IN to –IN .............................................................±6V SD – SDCOM ........................................ –0.3V to 5.3VOutput Short-Circuit Duration .......................... IndefiniteOperating Temperature Range (Note 2) LTC2058I .............................................–40°C to 85°C LTC2058H .......................................... –40°C to 125°CStorage Temperature Range .................. –65°C to 150°CLead Temperature (Soldering, 10 sec) ................... 300°C
ORDER INFORMATION
LTC2058
3Rev 0
For more information www.analog.com
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITSVOS Input Offset Voltage (Note 3) 0.5 5 μV
ΔVOSΔT
Average Input Offset Voltage Drift (Note 3) –40°C to 125°C l 0.025 μV/°C
IB Input Bias Current (Notes 4, 5) –40°C to 85°C –40°C to 125°C
l
l
30 100 200 4.5
pA pA nA
IOS Input Offset Current (Notes 4, 5) –40°C to 85°C –40°C to 125°C
l
l
60 200 200 300
pA pA pA
in Input Noise Current Spectral Density (Note 8) 1kHz, CEXT = 0pF 0.5 pA/√Hzen Input Noise Voltage Spectral Density 1kHz 9 nV/√HzenP-P Input Noise Voltage DC to 10Hz 200 nVP-PZIN Differential Input Impedance
Common Mode Input Impedance225k||8 1012||20
Ω||pF Ω||pF
CMRR Common Mode Rejection Ratio (Note 6) VCM = V– – 0.1V to V+ – 1.5V –40°C to 85°C –40°C to 125°C
l
l
123 121 118
150 dB dB dB
PSRR Power Supply Rejection Ratio (Note 6) VS = 4.75V to 36V –40°C to 125°C
l
140 140
150 dB dB
AVOL Open Loop Voltage Gain (Note 6) VOUT = V– +0.5V to V+ – 0.3V, RL =1kΩ –40°C to 125°C
l
124 120
150 dB dB
VOL – V– Output Voltage Swing Low No Load –40°C to 125°C ISINK = 1mA –40°C to 125°C ISINK = 5mA –40°C to 85°C –40°C to 125°C
l
l
l
l
5
55
260
15 20
150 200 470 750 750
mV mV mV mV mV mV mV
V+ – VOH Output Voltage Swing High No Load –40°C to 125°C ISOURCE = 1mA –40°C to 125°C ISOURCE = 5mA –40°C to 85°C –40°C to 125°C
l
l
l
l
5.5
50
235
16 20 75 95
315 365 400
mV mV mV mV mV mV mV
ISC Short-Circuit Current Sourcing/Sinking 20/19 31/30 mASRRISE Rising Slew Rate AV = –1, RL = 10kΩ 1.6 V/μsSRFALL Falling Slew Rate AV = –1, RL = 10kΩ 1.7 V/μsGBW Gain Bandwidth Product 2.5 MHzfC Internal Chopping Frequency 100 kHzIS Supply Current Per Amplifier No Load
–40°C to 85°C –40°C to 125°C
l
l
0.95 1.15 1.4
1.55
mA mA mA
In Shutdown Mode –40°C to 85°C –40°C to 125°C
l
l
3 4.25
5
µA µA µA
VSDL Shutdown Threshold (SD – SDCOM) Low (Note 7) –40°C to 125°C l 0.8 VVSDH Shutdown Threshold (SD – SDCOM) High (Note 7) –40°C to 125°C l 2 V
SDCOM Voltage Range (Note 7) –40°C to 125°C l V– V+ –2V VISD SD Pin Current (Note 7) –40°C to 125°C, VSD – VSDCOM = 0 l –1 –0.5 µAISDCOM SDCOM Pin Current (Note 7) –40°C to 125°C, VSD – VSDCOM = 0 l 0.75 1.5 µA
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. Unless otherwise noted, VS = ±2.5V; VCM = VOUT = 0V.
LTC2058
4Rev 0
For more information www.analog.com
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. Unless otherwise noted, VS = ±15V; VCM = VOUT = 0V.SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VOS Input Offset Voltage (Note 3) 0.5 5 μV
ΔVOSΔT
Average Input Offset Voltage Drift (Note 3) –40°C to 125°C l 0.025 μV/°C
IB Input Bias Current (Note 4, 5) –40°C to 85°C –40°C to 125°C
l
l
30 100 200 4.5
pA pA nA
IOS Input Offset Current (Note 4, 5) –40°C to 85°C –40°C to 125°C
l
l
60 200 200 300
pA pA pA
in Input Noise Current Spectral Density (Note 8) 1kHz, CEXT = 0pF 1kHz, CEXT = 22pF
1 0.5
pA/√Hz pA/√Hz
en Input Noise Voltage Spectral Density 1kHz 9 nV/√Hz
enP-P Input Noise Voltage DC to 10Hz 200 nVP-P
ZIN Differential Input Impedance Common Mode Input Impedance
225k||13 1012||6
Ω||pF Ω||pF
CMRR Common Mode Rejection Ratio (Note 6) VCM = V– – 0.1V to V+ – 1.5V –40°C to 85°C –40°C to 125°C
l
l
138 137 135
150 dB dB dB
PSRR Power Supply Rejection Ratio (Note 6) VS = 4.75V to 36V –40°C to 125°C
l
140 140
150 dB dB
AVOL Open Loop Voltage Gain (Note 6) VOUT = V– +0.4V to V+ –0.25V, RL = 10kΩ –40°C to 125°C
l
137 133
150 dB dB
VOL – V– Output Voltage Swing Low No Load –40°C to 125°C ISINK = 1mA –40°C to 125°C ISINK = 5mA –40°C to 85°C –40°C to 125°C
l
l
l
l
5
55
270
15 20
150 200 470 750 750
mV mV mV mV mV mV mV
V+ – VOH Output Voltage Swing High No Load –40°C to 125°C ISOURCE = 1mA –40°C to 125°C ISOURCE = 5mA –40°C to 85°C –40°C to 125°C
l
l
l
l
7
50
235
18 22 75 90
315 365 400
mV mV mV mV mV mV mV
ISC Short-Circuit Current Sourcing/Sinking 20/25 31/36 mA
SRRISE Rising Slew Rate AV = –1, RL = 10kΩ 1.6 V/μs
SRFALL Falling Slew Rate AV = –1, RL = 10kΩ 1.7 V/μs
GBW Gain Bandwidth Product 2.5 MHz
fC Internal Chopping Frequency 100 kHz
IS Supply Current Per Amplifier No Load –40°C to 85°C –40°C to 125°C
l
l
1 1.2 1.45 1.6
mA mA mA
In Shutdown Mode –40°C to 85°C –40°C to 125°C
l
l
5 7.5 9
µA µA µA
VSDL Shutdown Threshold (SD – SDCOM) Low (Note 7) –40°C to 125°C l 0.8 V
LTC2058
5Rev 0
For more information www.analog.com
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. Unless otherwise noted, VS = ±15V; VCM = VOUT = 0V.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime.Note 2: The LTC2058I is guaranteed to meet specified performance from –40°C to 85°C. The LTC2058H is guaranteed to meet specified performance from –40°C to 125°C.Note 3: These parameters are guaranteed by design. Thermocouple effects preclude measurements of these voltage levels during automated testing. VOS is measured to a limit determined by test equipment capability.Note 4: These specifications are limited by automated test system capability. Leakage currents and thermocouple effects reduce test accuracy. For tighter guaranteed specifications, please contact LTC Marketing.
Note 5: Input BIAS current is measured using an equivalent source impedance of 100MΩ || 51pF.Note 6: Minimum specifications for these parameters are limited by the capabilities of the automated test system, which has an accuracy of approximately 10µV for VOS measurements. For reference, 30V/1µV is 150dB of voltage ratio.Note 7: MSE package only.Note 8: Refer to the Application Information section for more details.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VSDH Shutdown Threshold (SD – SDCOM) High (Note 7) –40°C to 125°C l 2 V
SDCOM Voltage Range (Note 7) –40°C to 125°C l V– V+ –2V V
ISD SD Pin Current (Note 7) –40°C to 125°C, VSD – VSDCOM = 0 l –1 –0.5 µA
ISDCOM SDCOM Pin Current (Note 7) –40°C to 125°C, VSD – VSDCOM = 0 l 0.75 1.5 µA
LTC2058
6Rev 0
For more information www.analog.com
78 TYPICAL CHANNELSVS = ±15V
TIME (HOURS)0 300 600 900 1200 1500 1800 2100
–5
–4
–3
–2
–1
0
1
2
3
4
5
V OS
(µV)
2058 G08
1 TYPICAL UNITVS = ±15VVCM=0V
TEMPERATURE (°C)–50 –25 0 25 50 75 100 125 150
0.01
0.1
1
10
100
I B (n
A)
2058 G09
Input Offset Voltage Distribution Input Offset Voltage DistributionInput Offset Voltage Drift Distribution
Input Offset Voltage Drift Distribution
TYPICAL PERFORMANCE CHARACTERISTICS
Input Offset Voltage vs Input Common Mode Voltage
Input Offset Voltage vs Input Common Mode Voltage
Input Offset Voltage vs Supply Voltage
Long-Term Input Offset Voltage Drift Input Bias Current vs Temperature
6 TYPICAL CHANNELSVS = 5VTA = 25°C
VCM (V)–1 0 1 2 3 4 5
–5
–4
–3
–2
–1
0
1
2
3
4
5
V OS
(µV)
2058 G05
6 TYPICAL CHANNELSVS = 30VTA = 25°C
VCM (V)0 5 10 15 20 25 30
–5
–4
–3
–2
–1
0
1
2
3
4
5
V OS
(µV)
2058 G06
6 TYPICAL CHANNELS VCM = VS/2TA = 25°C
VS (V)0 5 10 15 20 25 30 35 40
–5
–4
–3
–2
–1
0
1
2
3
4
5
V OS
(µV)
2058 G07
N = 160VS = ±2.5Vµ = 0.130µVσ = 0.420µVTA = 25°C
VOS (µV)–3 –2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 2 2.5 3
0
10
20
30
40
50
60
70
80
NUM
BER
OF A
MPL
IFIE
RS
2058 G01
N = 160VS = ±15Vµ = 0.194µVσ = 0.436µVTA = 25°C
VOS (µV)–3 –2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 2 2.5 3
0
10
20
30
40
50
60
70
80
NUM
BER
OF A
MPL
IFIE
RS
2058 G02
N = 160VS = ±2.5Vµ = 3.933nV/°Cσ = 1.318nV/°C
VOS TC (nV/°C)0 2 4 6 8 10 12 14 16 18 20
0
10
20
30
40
50
60
70
80
NUM
BER
OF A
MPL
IFIE
RS
2058 G03
N = 160VS = ±15Vµ = 5.469nV/°Cσ = 1.805nV/°C
VOS TC (nV/°C)0 2 4 6 8 10 12 14 16 18 20
0
10
20
30
40
50
60
70
80
NUM
BER
OF A
MPL
IFIE
RS
2058 G04
LTC2058
7Rev 0
For more information www.analog.com
AVERAGE OF 6 TYPICAL CHANNELSVS = 5VTA=25°C
VCM (V)–1 0 1 2 3 4 5
–100
–80
–60
–40
–20
0
20
40
60
80
100
I B (p
A)
2058 G10
AVERAGE OF 6 TYPICAL CHANNELSVS = 30VTA=25°C
VCM (V)0 5 10 15 20 25 30
–100
–80
–60
–40
–20
0
20
40
60
80
100
I B (p
A)
2058 G11
TYPICAL PERFORMANCE CHARACTERISTICS
DC to 10Hz Voltage Noise DC to 10Hz Voltage Noise Input Voltage Noise Spectrum
Input Bias Current vs Supply Voltage
Input Bias Current vs Input Common Mode Voltage
Input Bias Current vs Input Common Mode Voltage
Input Current Noise SpectrumCommon Mode Rejection Ratio vs Frequency
Power Supply Rejection Ratio vs Frequency
VS = ±2.5V
1s/DIV
INPU
T–RE
FERR
ED V
OLTA
GE N
OISE
(100
nV/D
IV)
2058 G13
VS = ±15V
1s/DIVINPU
T-RE
FERR
ED V
OLTA
GE N
OISE
(100
nV/D
IV)
2058 G14
VS = ±2.5V...±15VAV=+1
FREQUENCY (Hz)0.1 1 10 100 1k 10k 100k 1M 10M
1
10
100
VOLT
AGE
NOIS
E DE
NSIT
Y (n
V/√H
z)IN
PUT-
REFE
RRED
2058 G15
TA = 25°CCEXT = 0 pF
VS= ±15VVS= ±2.5V
FREQUENCY (Hz)0.1 1 10 100 1k 10k 100k
0.1
1
10
CURR
ENT
NOIS
E DE
NSIT
Y (p
A/√H
z)IN
PUT–
REFE
RRED
2058 G16
VS = 30VVCM= VS/2
FREQUENCY (Hz)100 1k 10k 100k 1M 10M
0
20
40
60
80
100
120
CMRR
(dB)
2058 G17
VS = 30VVCM = VS /2
PSRR+
PSRR–
FREQUENCY (Hz)1 10 100 1k 10k 100k 1M 10M
0
20
40
60
80
100
120
140
PSRR
(dB)
2058 G18
AVERAGE OF 6 TYPICAL CHANNELSVCM = VS/2 TA = 25°C
IB(+IN)IB(–IN)
VS (V)0 5 10 15 20 25 30 35 40
–100
–80
–60
–40
–20
0
20
40
60
80
100
I B (p
A)
2058 G12
LTC2058
8Rev 0
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
Closed Loop Gain vs Frequency Open Loop Gain vs Frequency Open Loop Gain vs Frequency
Shutdown Transient with Sinusoid Input
Closed Loop Output Impedance vs Frequency
Output Impedance in Shutdownvs Frequency THD +N vs Amplitude
Shutdown Transient with Sinusoid Input
Closed Loop Output Impedance vs Frequency
VS = ±2.5VRL= 10kΩ
CL= 0pFCL= 50pFCL= 200pF
FREQUENCY (Hz)
PHASE
GAIN
10k 100k 1M 10M –60
–40
–20
0
20
40
60
80
100
–45
0
45
90
135
GAIN
(dB)
PHASE (°C)
2058 G20
VS = ±15VRL= 10kΩ
CL= 0pFCL= 50pFCL= 200pF
FREQUENCY (Hz)10k 100k 1M 10M
–60
–40
–20
0
20
40
60
80
100
–45
0
45
90
135
GAIN
(dB)
PHASE (°C)
2058 G21
PHASE
GAIN
20µs/DIV
SDB–SDCOM2V/DIV
SUPPLYCURRENT2mA/DIV
VIN , VOUT500mV/DIV
2058 G23
VS = ±15V, AV = +1, RL= 2kΩPOWER SUPPLY BYPASS = 10nF
VS = ±2.5V
AV = +1AV = +10AV = +100
FREQUENCY (Hz)100 1k 10k 100k 1M 10M
0.01
0.1
1
10
100
1k
Z OUT
(Ω)
2058 G24
VS = ±15VRL,eff = 10kΩ
FREQUENCY (Hz)1k 10k 100k 1M 10M
–20
–10
0
10
20
30
40
50
60
CLOS
ED L
OOP
GAIN
(dB)
2058 G19
VS = ±2.5V, AV = +1, RL= 2kΩPOWER SUPPLY BYPASS = 10nF
20µs/DIV
SUPPLYCURRENT2mA/DIV
SD–SDCOM2V/DIV
VIN ,VOUT500mV/DIV
2058 G22
VS = ±15V
AV = +1AV = +10AV = +100
FREQUENCY (Hz)100 1k 10k 100k 1M 10M
0.01
0.1
1
10
100
1k
Z OUT
(Ω)
2058 G25
VS = ±15VRL = 10kΩfIN = 1kHzBW = 80kHz
AV = +1AV = –1
OUTPUT AMPLITUDE (VRMS)0.01 0.1 1 10
0.00001
0.0001
0.001
0.01
0.1
–140
–120
–100
–80
–60
THD
+N (%
) THD +N (dB)
2058 G27
VS = ±15V
FREQUENCY (Hz)1 10 100 1k 10k 100k 1M 10M
100
1k
10k
100k
1M
10M
100M
1G
10G
Z OUT
(Ω)
2058 G26
LTC2058
9Rev 0
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
THD +N vs Frequency THD +N vs Frequency
Supply Current vs Supply Voltage
Maximum Undistorted Output Amplitude vs Frequency
Supply Current vs TemperatureShutdown Supply Current vs Supply Voltage
Supply Current vs Shutdown Control Voltage
Supply Current vs Shutdown Control Voltage
Shutdown Pin Current vs Shutdown Pin Voltage
VS = ±15VAV = +1RL = 10kΩBW = 80kHz
VOUT = 3.5VRMSVOUT = 2VRMS
FREQUENCY (Hz)10 100 1k 10k
0.00001
0.0001
0.001
0.01
0.1
–140
–120
–100
–80
–60
THD
+N (%
) THD +N (dB)
2058 G28
±15V
±2.5V
TEMPERATURE (°C)–60 –30 0 30 60 90 120 150
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
I S (m
A)
2058 G32
VS = ±15VSDCOM=0V
ISD –55°CISD 125°CISDCOM –55°CISDCOM 125°C
SD – SDCOM (V)0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
–5
–4
–3
–2
–1
0
1
2
3
4
5
SHUT
DOW
N PI
N CU
RREN
T (µ
A)
2058 G36
VS = ±15VAV = –1RI = RF = 10kΩBW = 80kHz
VOUT = 3.5VRMSVOUT = 2VRMS
FREQUENCY (Hz)10 100 1k 10k
0.00001
0.0001
0.001
0.01
–140
–120
–100
–80
THD
+N (%
) THD +N (dB)
2058 G29
–55°C–40°C0°C
150°C125°C85°C
25°C
VS (V)0 5 10 15 20 25 30 35 40
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
I S (m
A)
2058 G31
SD = SDCOM = VS/2
150°C
–55°C
–40°C
25°C
85°C125°C
VS (V)0 4 8 12 16 20 24 28 32 36 40
0
5
10
15
20
25
I S (µ
A)
2058 G33
VS = ±2.5VSDCOM = –2.5V
–55°C–40°C25°C85°C125°C150°C
SD – SDCOM (V)0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
I S (m
A)
2058 G34
VS = ±15VSDCOM= 0V
–55°C–40°C25°C85°C125°C150°C
SD - SDCOM (V)0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
I S (m
A)
2058 G35
AV = +1RL = 10kΩ
THD+N < 1%VS = ±15V
VS = ±2.5V
FREQUENCY (Hz)1k 10k 100k 1M 10M
0
2.5
5.0
7.5
10.0
12.5
15.0
OUTP
UT A
MPL
ITUD
E (V
P)
2058 G30
LTC2058
10Rev 0
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
Output Voltage Swing High vs Load Current
Output Voltage Swing High vs Load Current
Output Voltage Swing Low vs Load Current
Output Voltage Swing Low vs Load Current
Short-Circuit Current vs Temperature
Short-Circuit Current vs Temperature Large Signal Response Large Signal Response
VS = ±2.5V VIN = ±0.5VAV = +1CL = 200pF
2µs/DIV
V OUT
(200
mV/
DIV)
2058 G44
VS = ±15V VIN = ±5VAV = +1CL = 200pF
10µs/DIV
V OUT
(2V/
DIV)
2058 G45
VS = ±2.5V
–55°C–40°C25°C85°C125°C150°C
ISOURCE (mA)0.001 0.01 0.1 1 10 100
0.001
0.01
0.1
1
10
V+ – V
OUT
2058 G38
VS = ±15V
–55°C–40°C25°C85°C125°C150°C
ISOURCE (mA)0.001 0.01 0.1 1 10 100
0.001
0.01
0.1
1
10
100
V+ - V O
UT (V
)
2058 G39
VS = ±2.5V
–55°C–40°C25°C85°C125°C150°C
ISINK (mA)0.001 0.01 0.1 1 10 100
0.001
0.01
0.1
1
10
V OUT
– V
– (V)
2058 G40
VS = ±15V
–55°C–40°C25°C85°C125°C150°C
ISINK (mA)0.001 0.01 0.1 1 10 100
0.001
0.01
0.1
1
10
100
V OUT
- V- (V
)
2058 G41
VS = ±2.5V
SOURCINGSINKING
TEMPERATURE (°C)–50 –25 0 25 50 75 100 125 150
0
5
10
15
20
25
30
35
40
45
50
I SC
(mA)
2058 G42
VS = ±15V
SOURCINGSINKING
TEMPERATURE (°C)–50 –25 0 25 50 75 100 125 150
0
5
10
15
20
25
30
35
40
45
50
I SC
(mA)
2058 G43
Shutdown Pin Current vs Supply Voltage
SD = SDCOM = VS/2
SDCOM
SDB
–55°C25°C150°C
VS (V)0 5 10 15 20 25 30 35 40
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
SHUT
DOW
N PI
N CU
RREN
T (µ
A)
2058 G37
LTC2058
11Rev 0
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
Small Signal Response Small Signal ResponseSmall Signal Overshoot vs Capacitive Load
Small Signal Overshoot vs Capacitive Load
Output Series Resistance vs CLOAD and Overshoot Large Signal Settling Transient
Large Signal Settling Transient Large Signal Settling Transient Large Signal Settling Transient
VS = ±2.5VVIN = ±50mVAV = +1CL= 200pF
500ns/DIV
V OUT
(25m
V/DI
V)
2058 G46
VS = ±15VVIN = ±50mVAV = +1CL= 200pF
500ns/DIV
V OUT
(25m
V/DI
V)
2058 G47
VS = ± 2.5VAV = +1
CLOAD (F)10p 100p 1n 10n 100n 1µ 10µ 100µ
0
10
20
30
40
50
60
70
80
90
100
OVER
SHOO
T (%
)
2058 G48
OS+
OS–
OS+ RS = 5ΩOS– RS = 5Ω
VS = ± 15VAV = +1
OS+
OS–
OS+ RS = 5ΩOS– RS = 5Ω
CLOAD (F)10p 100p 1n 10n 100n 1µ 10µ 100µ
0
10
20
30
40
50
60
70
80
90
100
OVER
SHOO
T (%
)
2058 G49
VS = ±2.5V...±15VAV= +1TA= 25°C
BETTER STABILITY
< 30% OVERSHOOT< 10% OVERSHOOT
CLOAD (F)100p 1n 10n 100n 1u 10µ 100µ1
10
100
1k
R S (Ω
)
2058 G50
VS = ±15VAV = –1
RF = 10kΩ
–8V
10µs/DIV
VIN8V/DIV
VOUT0.5mV/DIV
2058 G51
VOUT WITHAVERAGING
VOUT
VS = ±15VAV = –1
RF = 10kΩ CF = 22pF
–8V
10µs/DIV
VIN8V/DIV
VOUT0.5mV/DIV
2058 G52
VOUT WITHAVERAGING
VOUT
VS = ±15VAV = –1
RF = 10kΩ CF = 47pF
–8V
10µs/DIV
VIN8V/DIV
VOUT0.5mV/DIV
2058 G53
VOUT
VOUT WITHAVERAGING
VS = ±15VAV = –1
RF = 10kΩ
0V
10µs/DIV
VIN8V/DIV
VOUT0.5mV/DIV
2058 G54
VOUT
VOUT WITHAVERAGING
LTC2058
12Rev 0
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
Output Overload RecoveryEMIRR IN+ vs Frequency
Output Overload Recovery
Output Overload Recovery
Output Overload RecoveryInput Common Mode Capacitance vs Input Common Mode Voltage
Large Signal Settling Transient Crosstalk
VS = ±15VVOUT = 3.5 VRMSAV = +1
RL = 100kΩRL = 1kΩ
FREQUENCY (Hz)10 100 1k 10k 100k
–160
–150
–140
–130
–120
–110
–100
–90
–80
CROS
STAL
K (d
B)
2058 G57
VS = ±2.5VAV = –100RF = 10kΩCL = 100pF
5µs/DIV
VOUT1V/DIV
VIN50mV/DIV
2058 G59
VS = ±2.5VAV = –100RF = 10kΩCL = 100pF
5µs/DIV
VOUT1V/DIV
VIN50mV/DIV
2058 G61
VS = ±15VAV = –100RF = 10kΩCL = 100pF
2µs/DIV
VOUT5V/DIV
VIN250mV/DIV
2058 G62
VS = ±15VAV = –100RF = 10kΩCL = 100pF
2µs/DIV
VOUT5V/DIV
VIN250mV/DIV
2058 G60
VOUT
VOUT WITHAVERAGING
VS = ±15VAV = –1
RF= 10kΩ CF=47pF
0V
10µs/DIV
VIN8V/DIV
VOUT0.5mV/DIV
2058 G56
Large Signal Settling Transient
VS = ±15VAV = –1FRF = 10kΩ C = 22pF
0V
10µs/DIV
VIN8V/DIV
VOUT0.5mV/DIV
2058 G55
VOUT
VOUT WITHAVERAGING
VS = 30VAV=+1VIN=–10dBmVCM= VS/2
EMIRR = 20log(VIN,PEAK/VOUT,DC)
FREQUENCY (Hz)10M 100M 1G 4G
20
40
60
80
100
120
140
EMIR
R (d
B)
2058 G58
VS=5VVS=30V
VCM (V)0 5 10 15 20 25 30
0
5
10
15
20
25
30
C CM
(pF)
2058 G63
LTC2058
13Rev 0
For more information www.analog.com
PIN FUNCTIONSS8E
OUTA (Pin 1): Amplifier A Output.
–INA (Pin 2): Amplifier A Inverting Input.
+INA (Pin 3): Amplifier A Noninverting Input.
V– (Pin 4): Negative Power Supply.
+INB (Pin 5): Amplifier B Noninverting Input.
–INB (Pin 6): Amplifier B Inverting Input.
OUTB (Pin 7): Amplifier B Output.
V+ (Pin 8): Positive Power Supply.
Exposed Pad (Pin 9): Must Be Connected to V–.
MSE12
SD (Pin 1): Shutdown Control Pin.
V– (Pin 2): Negative Power Supply.
OUTA (Pin 3): Amplifier A Output.
GUARD (Pin 4): Guard Ring. No internal connection. (See Applications Information)
–INA (Pin 5): Amplifier A Inverting Input.
+INA (Pin 6): Amplifier A Noninverting Input.
+INB (Pin 7): Amplifier B Noninverting Input.
–INB (Pin 8): Amplifier B Inverting Input.
GUARD/NC (Pin 9): Guard Ring. No internal connection. (See Application Information)
OUTB (Pin 10): Amplifier B Output.
V+ (Pin 11): Positive Power Supply.
SDCOM (Pin 12): Reference Voltage for SD.
Exposed Pad (Pin 13): Must Be Connected to V–.
LTC2058
14Rev 0
For more information www.analog.com
BLOCK DIAGRAMS
V+
V–250Ω
250Ω–IN
+IN2058 BD1
V+
V–V+
V–
+
–OUT
V+
V–
10k
10k
SD
SDCOM
2058 BD2
V+
V–
V+
V–
0.5µA
0.75µA
5.25VVTH ≈ 1.3V
V+
V–
SD
+
–
+–
Amplifier (Each Channel)
Shutdown Circuit (MSE12 Package Only)
LTC2058
15Rev 0
For more information www.analog.com
Input Voltage Noise
Chopper stabilized amplifiers like the LTC2058 achieve low offset and 1/f noise by heterodyning DC and flicker noise to higher frequencies. In a classical chopper sta-bilized amplifier, this process results in idle tones at the chopping frequency and its odd harmonics.
The LTC2058 utilizes circuitry to suppress these spurious artifacts to well below the offset voltage. The typical ripple magnitude at 100kHz is much less than 1µVRMS.
The voltage noise spectrum of the LTC2058 is shown in Figure 1. If lower noise is required, consider the following circuit from the Typical Applications section: Paralleling Choppers to Improve Noise.
APPLICATIONS INFORMATION
chopper and auto-zero amplifiers with switched inputs, the dominant current noise mechanism is not shot noise.
Input Bias Current
The LTC2058's input bias currents are comprised of two very different constituents, diode leakage and charge injec-tion. Leakage currents increase with temperature, while the charge injection from the switching inputs remains rela-tively constant with temperature. The composite of these two currents over temperature is illustrated in Figure 3.
Figure 2. Input Current Noise Spectrum
Figure 3. Input Bias Current vs Temperature
Input Current Noise
For applications with high source impedances, input cur-rent noise can be a significant contributor to total output noise. For this reason, it is important to consider noise current interaction with circuit elements placed at the amplifier’s inputs.
The current noise spectrum of the LTC2058 is shown in Figure 2. The characteristic curve shows no 1/f behavior. As with all zero-drift amplifiers, there is a significant cur- rent noise component at the offset-nulling frequency. This phenomenon is discussed in the Input Bias Current section.
It is important to note that the current noise is not equal to √2qIB A/√Hz. This formula is relevant for base current in bipolar transistors and diode currents; but for most
Figure 1. Input Voltage Noise Spectrum
VS = ±2.5V...±15VAV=+1
FREQUENCY (Hz)0.1 1 10 100 1k 10k 100k 1M 10M
1
10
100
VOLT
AGE
NOIS
E DE
NSIT
Y (n
V/√H
z)IN
PUT–
REFE
RRED
2058 F01
VS = ±15VTA=25°C
CEXT = 0pFCEXT = 22pF
FREQUENCY (Hz)0.1 1 10 100 1k 10k 100k
0.1
1
10
CURR
ENT
NOIS
E DE
NSIT
Y (p
A/√H
z)IN
PUT-
REFE
RRED
2058 F02a
1M
CEXTTEST CIRCUIT
2058 F02b
–
+
1 TYPICAL UNITVS = ±15VVCM = 0V
25°C MAX IB SPEC
TEMPERATURE (°C)–50 –25 0 25 50 75 100 125 150
0.01
0.1
1
10
100
I B (n
A)
2058 F03
LEAKAGE CURRENT
INJE
CTIO
N CU
RREN
T
LTC2058
16Rev 0
For more information www.analog.com
APPLICATIONS INFORMATIONHow the various input bias currents behave and contribute to error depends on the nature of the source impedance. For the input bias currents specified in the electrical tables, the source impedances are high value resistors bypassed with shunt filter capacitance. Figure 4 shows the effec-tive DC error as an input referred current error (output DC voltage error divided by gain and then by the source resistance) as a function of the filter capacitance. Note that the effective DC error decreases as the capacitance increases. The added external capacitance (CEXT) also reduces the input current noise as shown in Figure 2.
Another function of the input capacitance is to reduce the effects of charge injection. The charge injection based current has a frequency component at the chopping fre-quency and its harmonics. In time domain these frequency components appear as current pulses (appearing at regular intervals related to the chopping frequency). When these small current pulses interact with source impedances or gain setting resistors, the resulting voltage spikes are amplified by the closed loop gain. For higher source imped-ances, this may cause the 100kHz chopping frequency to be visible in the output spectrum, which is a phenomenon known as clock feedthrough. To prevent excessive clock
feedthrough, keep gain-setting resistors and source im-pedances as low as possible. When DC highly resistive source impedance is required, the capacitor across the source impedance reduces the AC impedance, reducing the amplitude of the input voltage spikes. Another way to reduce clock injection effects is to bandwidth limit after the op amp output.
Injection currents from the two inputs are of equal magni-tude but opposite direction. Therefore, input bias current effects on offset voltage due to injection currents will not be canceled by placing matched impedances at both inputs.
Above 50°C, leakage of the ESD protection diodes begins to dominate the input bias current and continues to increase exponentially at elevated temperatures. Unlike injection current, leakage currents are in the same direction for both inputs. Therefore, the output error due to leakage currents can be mitigated by matching the source impedances seen by the two inputs. Keep in mind that if the source-impedance-matching technique is employed to cancel the effect of the leakage currents, below 50°C there is an offset voltage error of 2IB x R due to the charge-injection currents. If IB = 100pA and R = 10k, the error is 2µV.
Thermocouple Effects
In order to achieve accuracy on the microvolt level, ther-mocouple effects must be considered. Any connection of dissimilar metals forms a thermoelectric junction and generates a small temperature-dependent voltage. Also known as the Seebeck Effect, these thermal EMFs can be the dominant error source in low drift circuits.
Connectors, switches, relay contacts, sockets, resistors, and solder are all candidates for significant thermal EMF generation. Even junctions of copper wire from different manufacturers can generate thermal EMFs of 200nV/°C, which is 8 times the maximum drift specification of the LTC2058. Figure 5 and Figure 6 illustrate the potential magnitude of these voltages and their sensitivity to tem-perature.
Figure 4. Input Bias Current vs Input Capacitance
VS = ±15V
CEXT (pF)0 50 100 150 200
0
50
100
150
200
EFFE
CTIV
E I B
(pA)
2058 F04a
1M
CEXTTEST CIRCUIT
2058 F04b
–
+
LTC2058
17Rev 0
For more information www.analog.com
Figure 5. Thermal EMF Generated by Two Copper Wires from Different Manufactures
Figure 6. Solder-Copper Thermal EMFs
APPLICATIONS INFORMATION
Figure 7. Techniques for Minimizing Thermocouple-Induced Errors
In order to minimize thermocouple-induced errors, atten-tion must be given to circuit board layout and component selection. It is good practice to minimize the number of junctions in the amplifier’s input signal path and avoid con-nectors, sockets, switches, and relays whenever possible. If such components are required, they should be selected for low thermal EMF characteristics. Furthermore, the number, type, and layout of junctions should be matched for both inputs with respect to thermal gradients on the circuit board. Doing so may involve deliberately introducing dummy junctions to offset unavoidable junctions.
Air currents can also lead to thermal gradients and cause significant noise in measurement systems. It is important to prevent airflow across sensitive circuits. Doing so will often reduce thermocouple noise substantially.
A summary of techniques can be found in Figure 7.
Leakage Effects
Leakage currents into high impedance signal nodes can easily degrade measurement accuracy of sub-nanoamp signals. High voltage and high temperature applications are especially susceptible to these issues. Quality insula-tion materials should be used, and insulating surfaces should be cleaned to remove fluxes and other residues. For humid environments, surface coating may be neces-sary to provide a moisture barrier.
TEMPERATURE (°C)25
MIC
ROVO
LTS
REFE
RRED
TO
25°C
1.8
2.4
3.02.82.6
2.02.2
1.41.6
0.8001.0
0.2000.400
30 40 45
2058 F05
1.2
0.600
035
SOLDER-COPPER JUNCTION DIFFERENTIAL TEMPERATURESOURCE: NEW ELECTRONICS 02-06-77
0THER
MAL
LY P
RODU
CED
VOLT
AGE
IN M
ICRO
VOLT
S
0
50
40
2058 F06
–50
–10010 20 30 50
100
SLOPE ≈ 1.5µV/°CBELOW 25°C
SLOPE ≈ 160nV/°CBELOW 25°C
64% SN/36% Pb
60% Cd/40% SN
LTC2058THERMALGRADIENT
RELAY
MATCHING RELAY NC
* CUT SLOTS IN PCB FOR THERMAL ISOLATION.** INTRODUCE DUMMY JUNCTIONS AND COMPONENTS TO OFFSET UNAVOIDABLE JUNCTIONS OR CANCEL THERMAL EMFs.† ALIGN INPUTS SYMMETRICALLY WITH RESPECT TO THERMAL GRADIENTS.‡ INTRODUCE DUMMY TRACES AND COMPONENTS FOR SYMMETRICAL THERMAL HEAT SINKING.§ LOADS AND FEEDBACK CAN DISSIPATE POWER AND GENERATE THERMAL GRADIENTS. BE AWARE OF THEIR THERMAL EFFECTS.# COVER CIRCUIT TO PREVENT AIR CURRENTS FROM CREATING THERMAL GRADIENTS.
HEAT SOURCE/POWER DISSIPATOR
RL§
–IN
+IN
RF§
RGVIN
*
RG
2057 F07
**
†
‡**
#
+–
+–
VTHERMAL
VTHERMAL
RF
LTC2058
18Rev 0
For more information www.analog.com
APPLICATIONS INFORMATION
Figure 8a. Example Layout of Noninverting Amplifier with Leakage Guard Ring (Channel A Shown)
2058 F08a
+
–
HIGH-Z SENSOR
GUARD RING
† LEAKAGE CURRENT
ALTERNATIVEGUARD RING
DRIVE
ALTERNATIVE GUARD RINGDRIVE CIRCUIT IF RG MUST BE HIGH IMPEDANCE.
†ISENSOR
ZSENSOR
VOUTVBIAS
RG
RF
1/2 LTC2058
R´F
V+
V–
R GRFRG
=R'FR'G
; R'G <<RG
LEAKAGE CURRENT
* MINIMIZE SPACING TO MAXIMIZE THE CLEARANCE BETWEEN THE EXPOSED GUARD RING AND THE EXPOSED PAD
** VERROR = ILEAK RG; RG << ZSENSOR
ALL RESISTORS 0603
HIGH- ZSENSOR GUARD RING
(NO SOLDER MASKOVER GUARD RING)
SD
RG
RF**
V–
V–OUTA
GRD
–INA
+INA *
SDCOM
V+
OUTB
GRD
–INB
+INB
§
§ NO LEAKAGE CURRENT, V+IN = VGRD
Board leakage can be minimized by encircling the input connections with a guard ring operated at a potential very close to that of the inputs. The ring must be tied to a low impedance node. For inverting configurations, the guard ring should be tied to the potential of the positive input (+IN). For noninverting configurations, the guard ring
should be tied to the potential of the negative input (–IN). In order for this technique to be effective, the guard ring must not be covered by solder mask. Ringing both sides of the printed circuit board may be required. See Figure 8a and Figure 8b for examples of proper layout.
LTC2058
19Rev 0
For more information www.analog.com
APPLICATIONS INFORMATION
Figure 8b. Example Layout of Inverting Amplifier with Leakage Guard Ring (Channel A Shown)
2058 F08b
+
–
GUARD RING
1/2 LTC2058LEAKAGECURRENT
LEAKAGE CURRENT IS ABSORBED BY GROUND INSTEAD OFCAUSING A MEASUREMENT ERROR.
VOUT
V+
V–
HIGH-Z SENSOR
RFVBIAS
ALL RESISTORS 0603
HIGH- ZSENSOR
HIGH- Z RF
VBIAS
LEAKAGE CURRENT
LOW IMPEDANCENODE ABSORBS
LEAKAGE CURRENT(GROUND)
GUARD RING(NO SOLDER MASKOVER GUARD RING)
SD
V–
V–OUTA
GRD
–INA *
+INA
SDCOM
V+
OUTB
GRD
–INB
+INB
§ NO LEAKAGE CURRENT, V–IN = VGRD
§
ISENSOR
ZSENSOR
*MINIMIZE SPACING TO MAXIMIZE THE CLEARANCE BETWEEN THE EXPOSED GUARD RING AND THE EXPOSED PAD.
LTC2058
20Rev 0
For more information www.analog.com
APPLICATIONS INFORMATIONFor low leakage applications, the LTC2058 is available in an MSE12 package with a special pinout that facilitates the layout of guard ring structures. The pins adjacent to the inputs have no internal connection, allowing a guard ring to be routed through them.
Power Dissipation
Since the LTC2058 is capable of operating at 36V total supply, care should be taken with respect to power dis-sipation in the amplifier. When driving heavy loads at high voltages, use the θJA of the package to estimate the resulting die-temperature rise and take measures to ensure that the resulting junction temperature does not exceed specified limits. PCB metallization and heat sinking should also be considered when high power dissipation is expected. The LTC2058 is packaged in thermally-enhanced S8E and MSE12 packages. These packages feature lower package thermal resistances compared to their standard counterparts and exposed pads to facilitate heat sinking. The exposed bottom pad must be soldered to the PCB and due to its internal connection to V– it is required to connect the exposed pad to V–. For more efficient heat sinking, it is recommended that the exposed pad have as much PCB metal connected to it as reasonably available. Thermal information for all packages can be found in the Pin Configuration section.
Electrical Overstress and Input Protection
Absolute maximum ratings should not be exceeded. Avoid driving the input and output pins beyond the rails, espe-cially at supply voltages approaching 40V. The inputs of LTC2058 are internally protected by ESD diodes (see Block Diagrams section). The Anode of the bottom side diode is the substrate, so driving an input below the rail can induce undesired parasitic behavior.If overvoltage conditions cannot be prevented, a resistor in series with the threatened pin can be used to limit fault current to below the absolute maximum rating and reduce the possibility of device damage. This technique is shown in Figure 9.
Figure 9. Using a Resistor to Limit Input Current
Figure 10. Differential Input Voltage VS Current
2058 F09
+
–
RIN LIMITS IOVERLOAD TO <10mA FOR VIN < 10V OUTSIDE OF THE SUPPLY RAILS.
OUT½ LTC2058
VIN
V+
V–
RIN1k
IOVERLOAD
The current limiting resistance should not be so high as to add noise and error voltages from interaction with input bias currents. Resistances up to 2k will not significantly impact noise or precision. Use the Figure 10 and Figure 11 (I-V Characteristics of the internal ESD diodes) to help determine the appropriate value of the resistor.
In harsh environments, reliability can be enhanced further with protection circuitry as illustrated in Figure 12. This circuit utilizes low-leakage diodes (Nexperia BAV199) to protect the input. R2 protects the external diodes, and R1 is added to limit the current which would get to the internal diodes. In this circuit R1 can be small as the applied volt-age is already reduced by the external protection diodes.
In high temperature applications where the leakage cur-rents of the internal ESD diodes dominate the input bias current, the circuit may benefit from adding an input bias cancellation resistor in the feedback path (see Typical Application Section: Input Bias Current).
125°C25°C–40°C
DIFFERENTIAL INPUT VOLTAGE (V)–5 –4 –3 –2 –1 0 1 2 3 4 5
–10
–8
–6
–4
–2
0
2
4
6
8
10
INPU
T CU
RREN
T (m
A)
2058 F10
LTC2058
21Rev 0
For more information www.analog.com
APPLICATIONS INFORMATION
Figure 11. ESD Protection Diode Forward Bias Voltage vs Current
Figure 12. Input Protection Circuit Using External Diodes
Shutdown Mode
The LTC2058 in the MSE12 package features a shutdown mode for low power applications. In the OFF state, both amplifiers are shut off and draw less than 9μA of supply current per amplifier. Also in the OFF stage, both outputs present high impedances to external circuitry.
Keep in mind that during the OFF state, even with the amplifier output being high impedance, the output may still be modulated by the input signal through the input differential clamp and the feedback resistor. (Refer to the block diagram for the location of the differential clamp). Also depending on the resistor values, significant current may still be drawn from the input source.
VIN
V+
V–
R1
D1A
BAS199
2058 F12
R2
D1B
+
–½ LTC2058
FORWARD BIASINGESD PROTECTION DIODEBETWEEN INPUT AND V+
FORWARD BIASINGESD PROTECTION DIODEBETWEEN INPUT AND V –
INPUT VOLTAGE BEYOND SUPPLY (V)0 0.2 0.4 0.6 0.8 1
–20
–15
–10
–5
0
5
10
15
20
INPU
T CU
RREN
T (m
A)
2058 F11
125°C25°C–40°C
Shutdown control is accomplished using a separate logic reference input (SDCOM) and a shutdown pin (SD). This method allows for low voltage digital control logic to oper-ate independently of the amplifier’s high voltage supply rails. A summary of control logic and operating ranges is shown in Table 1 and Table 2.
Table 1. Shutdown Control LogicSHUTDOWN PIN CONDITION AMPLIFIER STATE
SD = Float, SDCOM = Float ON
SD – SDCOM ≥ 2V ON
SD – SDCOM ≤ 0.8V OFF
Table 2. Operating Voltage Range for Shutdown PinsMIN MAX
SD – SDCOM –0.2V 5.2V
SDCOM V– V+ –2V
SD V– V+
If the shutdown feature is not required, SD and SDCOM may be left floating. Internal circuitry will automatically keep the amplifier in the ON state.
For operation in noisy environments, a capacitor between SD and SDCOM is recommended to prevent noise from changing the shutdown state.
When there is a danger of SD and SDCOM being pulled beyond the supply rails, resistance in series with the shut- down pins is recommended to limit current.
LTC2058
22Rev 0
For more information www.analog.com
TYPICAL APPLICATIONS
Low Side Current Sense Amplifier
Carbon Monoxide Sensor
Low Side Current Sense Amplifier Transfer Function
2058 TA02a
+
–
10Ω
1k
28V
1N4148 OR EQUIVALENT
OPTIONALSHORT
VOUT
VOUT = 101 • RSENSE • ISENSE
1/2 LTC2058VSENSE
ISENSE
10Ω
RSENSE
+
–
AMPLIFIER OUTPUT SATURATESWITH DIODE SHORTED
DIODE NOT SHORTEDDIODE SHORTEDIDEAL TRANSFERFUNCTION
VSENSE (µV)0 10 20 30 40 50 60 70 80 90 100
0
1
2
3
4
5
6
7
8
9
10
V OUT
(mV)
2058 TA02b
2058 TA03
R41M
PJFETJ177
5V
V+
–5V
C1100nF
SPLIT RAIL SUPPLY REQUIRED
4CM COUNTER ELECTRODE (CE)SELF-BIASES BELOW WE POTENTIALVWE – VCE = –0.3V TO –0.4 TYPICAL
TYPICAL GAIN:2.5mV/ppm COMAX OUTPUT:5V AT 2000ppmCO
4CM CARBON MONOXIDE SENSOR CITY TECHNOLOGY
70nA/ppm CO TYPICAL
R1, 15k R2, 15k
1/2 LTC2058
+
–
CEWE
RE RLOAD, 5Ω
VOUT
5V
–5V
R3, 35.7k
1/2 LTC2058
+
–
C2, 10nF
LTC2058
23Rev 0
For more information www.analog.com
TYPICAL APPLICATIONS
Paralleling Choppers to Improve Noise
–
+R5
R2
R1
R1
8
1/2 LTC2058
VIN
VOUT
2058 TA04
–
+R5
R2
1/2 LTC2058
R1
–
+R5
R2
1/2 LTC2058
R1
DC TO 10Hz NOISE =
WHERE N IS THE NUMBER OF PARALLELED INPUT AMPLIFIERS.
FOR N = 4, DC TO 10Hz NOISE = 100nVP-P , en = 4.5nV/√Hz, in = 2pA/√Hz, IB < 100pA (MAX).
R5 SHOULD BE A FEW HUNDRED OHMS TO ISOLATE AMPLIFIER OUTPUTS WITHOUT CONTRIBUTING SIGNIFICANTLY TO NOISE OR IB-INDUCED ERROR.
, in = √N • 1pA/√Hz, IB < N • 100pA (MAX), en =200nVP-P√N
–
+R5
R2
1/2 LTC2058
R3
–
+
R4
LTC2057
9nV/√Hz√N
AV = • R2R1
+1 R4R3
+1
>> √N FOR OUTPUT AMPLIFIER NOISE TO BE INSIGNIFICANT.R2R1
+1
LTC2058
24Rev 0
For more information www.analog.com
TYPICAL APPLICATIONS
V–
–15V
–15V
15V15V
GND
VINV+ VO
R–
LT1025
2058 TA05
+ (YELLOW)
– (RED)
499k
–
+1/2 LTC2058
LT1991A
VCC
VEE
REFOUT
M9
M3
M1
7
6VOUT = 10mV/°C
VCM
10nF
249k1%
1k1%
22Ω
0.1µF
1k1%
P1
P3
P9
8
9
10
1
2
3
100kCOUPLE THERMALLY
TYPE K
THERMOCOUPLE TEMP OF–200°C TO 1250°CGIVES –2V TO 12.5V VOUTASSUMING 40µV/°C TEMPCO.CHECK ACTUAL TEMPCO TABLE.
VCM = V– + 0.1V TO V+ – 1.5V (SMALL SIGNAL)CMRR = 122dB (0.02°C ERROR PER VOLT)
5
4
Differential Thermocouple Amplifier
LTC2058
25Rev 0
For more information www.analog.com
TYPICAL APPLICATIONS
Photovoltaic Module Sweep Measurement
I–V and P–V Curves
2058 TA06a
PVPANEL
R11M
R2100k
R3, 5Ω2W
R4, 2k
R5, 2k
R6, 1k
R7, 3k
RSENSE
C11pF
C22.5m
D11N4148
R8200Ω
D2D
1Ω, 2W
1/2 LTC2058 1/2 LTC2058
SOPRAY 5WVOC = 21VISC = 0.5A
5V SUPPLY
SW1 SW2
VBR: 2.5V TO 5VVPV IPV
CURRENT
POWER
VOLTAGE (V)1 3 5 7 9 11 13 15 17 19 21
0
35
70
105
140
175
210
245
280
315
350
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
CURR
ENT
(mA) POW
ER (W)
2058 TA06b
LTC2058
26Rev 0
For more information www.analog.com
.016 – .050(0.406 – 1.270)
.010 – .020(0.254 – 0.508)
× 45°
0°– 8° TYP.008 – .010
(0.203 – 0.254)
S8E 1015 REV C
.053 – .069(1.346 – 1.752)
.014 – .019(0.355 – 0.483)
TYP
.004 – .010(0.101 – 0.254)
0.0 – 0.005(0.0 – 0.130)
.080 – .099(2.032 – 2.530)
.118 – .139(2.997 – 3.550)
.050(1.270)
BSC
1 2 3 4
.150 – .157(3.810 – 3.988)
NOTE 3
8 7.005 (0.13) MAX
6 5
.189 – .197(4.801 – 5.004)
NOTE 3
.228 – .244(5.791 – 6.197)
.160 ±.005(4.06 ±0.127)
.118(2.99)REF
RECOMMENDED SOLDER PAD LAYOUT
.045 ±.005(1.143 ±0.127)
.050(1.27)BSC
INCHES(MILLIMETERS)
NOTE:1. DIMENSIONS IN
2. DRAWING NOT TO SCALE3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010" (0.254mm)
4. STANDARD LEAD STANDOFF IS 4mils TO 10mils (DATE CODE BEFORE 542)
5. LOWER LEAD STANDOFF IS 0mils TO 5mils (DATE CODE AFTER 542)
S8E Package8-Lead Plastic SOIC (Narrow .150 Inch) Exposed Pad
(Reference LTC DWG # 05-08-1857 Rev C)
.089(2.26) REF
.030 ±.005(0.76 ±0.127)
TYP
.245(6.22)MIN
4 5
PACKAGE DESCRIPTION
LTC2058
27Rev 0
For more information www.analog.com
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
MSOP (MSE12) 0213 REV G
0.53 ±0.152(.021 ±.006)
SEATINGPLANE
0.18(.007)
1.10(.043)MAX
0.22 – 0.38(.009 – .015)
TYP
0.86(.034)REF
0.650(.0256)
BSC
12
12 11 10 9 8 7
7
DETAIL “B”
1 6
NOTE:1. DIMENSIONS IN MILLIMETER/(INCH)2. DRAWING NOT TO SCALE3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD SHALL NOT EXCEED 0.254mm (.010") PER SIDE.
0.254(.010) 0° – 6° TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
RECOMMENDED SOLDER PAD LAYOUT
BOTTOM VIEW OFEXPOSED PAD OPTION
2.845 ±0.102(.112 ±.004)2.845 ±0.102
(.112 ±.004)
4.039 ±0.102(.159 ±.004)
(NOTE 3)
1.651 ±0.102(.065 ±.004)
1.651 ±0.102(.065 ±.004)
0.1016 ±0.0508(.004 ±.002)
1 2 3 4 5 6
3.00 ±0.102(.118 ±.004)
(NOTE 4)
0.406 ±0.076(.016 ±.003)
REF
4.90 ±0.152(.193 ±.006)
DETAIL “B”CORNER TAIL IS PART OF
THE LEADFRAME FEATURE.FOR REFERENCE ONLY
NO MEASUREMENT PURPOSE
0.12 REF
0.35REF
5.10(.201)MIN
3.20 – 3.45(.126 – .136)
0.889 ±0.127(.035 ±.005)
0.42 ±0.038(.0165 ±.0015)
TYP
0.65(.0256)
BSC
MSE Package12-Lead Plastic MSOP, Exposed Die Pad
(Reference LTC DWG # 05-08-1666 Rev G)
PACKAGE DESCRIPTION
LTC2058
28Rev 0
For more information www.analog.com ANALOG DEVICES, INC. 2018
D16898-0-5/18(0)www.analog.com
TYPICAL APPLICATIONPrecision Filtering Voltage Reference Distribution Buffers
RELATED PARTSPART NUMBER DESCRIPTION COMMENTS
LTC2057/LTC2057HV
High Voltage, Low Noise, Zero Drift Amplifier 4µV VOS, 4.75V to 60V VS, 1mA IS, RR Output
LTC2050HV Zero-Drift Operational Amplifier 3µV VOS, 2.7V to 12V VS, 1.5mA IS, RR Output
LTC2051/LTC2052 Dual/Quad, Zero-Drift Operational Amplifier 3µV VOS, 2.7V to 12V VS, 1.5mA IS, RR Output
LTC2053 Precision, Rail-to-Rail, Zero-Drift, Resistor-Programmable Instrumentation Amplifier
10µV VOS, 2.7V to 11V VS, 1.3mA IS, RRIO
LTC2054/LTC2055 Micropower, Single/Dual, Zero-Drift Operational Amplifier 5µV VOS, 2.7V to 12V VS, 0.2mA IS, RRIO
LTC6652 Precision, Low Drift, Low Noise, Buffered Reference 5ppm/°C, 0.05% Initial Accuracy, 2.1ppmP-P Noise
LT6654 Precision, Wide Supply, High Output Drive, Low Noise Reference 10ppm/°C, 0.05% Initial Accuracy, 1.6ppmP-P Noise
LTC6655 0.25ppm Noise, Low Drift, Precision, Buffered Reference Family 2ppm/°C, 0.025% Initial Accuracy, 0.25ppmP-P Noise
LT6016/LT6017 Dual/Quad, 76V Over-The-Top® Input Operational Amplifier 50µV VOS, 3V to 50V VS, 0.335mA IS, RRIO
LTC6090 140V Operational Amplifier 50pA IB, 1.6mV VOS, 9.5V to 140V VS, 4.5mA IS, RR Output
LT5400 Quad Matched Resistor Network ±0.01%, ±0.2ppm/°C Matching
0.1µF
8V TO 36V
2058 TA07
10k
1/2 LTC2058 LT6202
LTC6655-5
VIN
SHDN
VOUTF
VOUTS
2.7µF 10µF(FILM)
10µF(FILM)
0.1µF
4.7µF8V TO 13.2V
0.1µF
1k
5.62k
8V TO 12.6V
750Ω
–
+
–
+
–
+2Ω
47nF
47µF
1/2 LTC2058
LT6202
0.1µF
4.7µF
1k
5.62k
8V TO 12.6V
750Ω
–
+2Ω
47nF
47µF
VOUT1
VOUT2