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LOW POWER HIGHSPEED MULTIPLIERS

Submitted by:

K.NAVYA 09C81AO456)B.BHANU PRASAD 09C81AO416)B.SUVARNA KUMARI 09C81AO426)

A.GANDHI 09C81A0401)


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INTRODUCTIONBooths multiplication algorithm was invented byANDREW BOOTH in 1951This algorithm is particularly useful for machines thatcan shift bits faster than adding them.

Another improvement in the multiplier is by reducing thenumber of partial products generated.It operates even with signed numbers


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BRAUN ARRAY MULTIPLIER

braun edward louis first proposed the braunmultiplier in 1963.it is a simple parallel multiplier that is commonlyknown as the carry array multiplier.

This is restricted to performing multiplication of twounsigned numbers. It consists of an array of and gates and addersarranged in an iterative structure that does not requirelogic registers. This is also known as the non-additive multipliersince it does not add an additional operand to theresult of the multiplication.


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ARCHITECTURE OF BRAUN MULTIPLIER


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An n*n bit braun multiplier requires n(n-1) addersand n2 and gates . The internal structure of the full adder used in the

braun multiplier makes braun multipliers ideal forvery large scale integration (vlsi) and application

specific integrated circuit (asic) realization. each of the xi y j product bits is generated in

parallel with the and gates.

Each partial product can be added to the previoussum of partial products by using adders.The carry out signals are shifted one bit to the leftand are then added to the sums of the first adderand the new partial product.


7/22GENERAL MULTIPLICATION


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PERFORMANCE :

The braun multiplier performs well forunsigned operands that are less than 16 bits, interms of speed, power and area.Besides, it has a simple and regular structure ascompared to the other multiplier schemes. How ever, the number of components requiredin building the braun multiplier increases

quadratically with the number of bits. This makes the braun multiplier inefficient andso it is rarely employed while handling large

operands.


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SPEED CONSIDERATION: The delay of the braun multiplier i is dependent on thedelay of the full adder cell and also on the final adderin the last row. In the multiplier array, a full adder with balancedcarry and sum delays is desirable because the sum andcarry signals are both in the critical path.

The speed and power of the full adder is veryimportant for large arrays.


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BOOTHS MULTIPLIERA multiplier has two stages. In the first stage, the partial products aregenerated by the booth encoder and the

partial product generator (ppg), and aresummed by compressors.

In the second stage, the two final productsare added to form the final productthrough a final adder.


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BLOCK DIAGRAM


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TRUTH TABLE


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BOOTHS MULTIPLICATION


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OPERATION OF BOOTH

MULTIPLIERThe booth encoder was implemented using two xorgates and the selector using 3muxes and an invertercareful optimization of the partial-product generationcan lead to some substantial delay and hardwarereduction.[8] in the normal 8*8 multiplication 8 partial productsneed to be generated and accumulated.For accumulation seven adders to reduce power arerequired but in the case of booth


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SIMULATION OF BRAUN MULTIPLIER


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SIMULATION OF BOOTH MULTIPLIER


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ADVANTAGESBooth multiplier operates with high speedIt has low complexityLow power consumptionIt has less access time


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APPLICATIONS:It is arithmetic operation for dspapplications.

Such as filtering , and for fouriertransforms.To achieve high execution speed, parallelarray multipliers are widely used .These multipliers tend to consume mostof power in dsp computions


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ARRAY MULTIPLIER BOOTH S MULTIPLIER

1.Total power consumption is267mW.

1.Total power consumption is263mW.

2.Time period is 13.553 nsec. 2.Time period is 2.52 nsec.

3.It has more complexity. 3.It has less complexity.

COMPARISON:


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SUMMARY AND

CONCLUSIONthe braun array multiplier and boothmultiplier was implemented using vhdland the results are verified for the braunand booth multipliers.


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