LowPowerDesignMOSCAP

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Low Power CMOS VLSI Circuit Design (LPVD)

Dr. Veena S Chakravarthi



Goal of the Course

To understand the need for low power fromdevice/technology point of view of VLSI designs,

Basic idea/concepts of low power, estimating powerconsumption and power optimization design

methodology for VLSI chips.



Agenda

UNIT 1Introduction : Need for low power VLSI chips, Sources of

power dissipation on Digital Integrated circuits. Emerging

Low power approaches, Physics of power dissipation in

CMOS devices.

UNIT 2

Device & Technology Impact on Low Power: Dynamic

dissipation in CMOS, Transistor sizing & gate oxide

thickness, Impact of technology Scaling, Technology &

Device innovation

UNIT 3

Power estimation, Simulation Power analysis: SPICE circuit

simulators, gate level logic simulation, capacitive power

estimation, static state power, gate level capacitance

estimation, architecture level analysis, data correlation

analysis in DSP systems, Monte Carlo simulation.



Agenda

UNIT 4

Probabilistic power analysis: Random logic signals,

probability & frequency, probabilistic power analysis

techniques, signal entropy.

UNIT 5

Low Power Design Circuit level: Power consumption in

circuits. Flip Flops & Latches design, high capacitance

nodes, low power digital cells library

UNIT 6Logic level: Gate reorganization, signal gating, logic

encoding, state machine encoding, pre-computation logic



Agenda

UNIT 7

Low power Architecture & Systems: Power & performance

management, switching activity reduction, parallel

architecture with voltage reduction, flow graph

transformation, low power arithmetic components, low

power memory design.

UNIT 8

Low power Clock Distribution: Power dissipation in clock

distribution, single driver Vs distributed buffers, Zero skew

Vs tolerable skew, chip & package co design of clock

network

UNIT 9Algorithm & Architectural Level Methodologies: Introduction,

design flow, Algorithmic level analysis & optimization,

Architectural level estimation & synthesis.



Reference Books

1. Kaushik Roy, Sharat Prasad, “Low-Power CMOS VLSI

Circuit Design” Wiley, 2000

2. Gary K. Yeap, “Practical Low Power Digital VLSI

Design”, KAP, 2002

3. Rabaey, Pedram, “Low Power Design Methodologies”

Kluwer Academic, 19974. Web materials…



Curtosy: Copyright Agrawal & Srivaths, 2007

Low-Power Design and Test,Lecture 1

7

ISSCC, Feb. 2001, Keynote

“Ten years from now,

microprocessors will run at 10GHz to30GHz and be capable of processing1 trillion operations per second –

about the same number ofcalculations that the world's fastestsupercomputer can perform now.

“Unfortunately, if nothing changes

these chips will produce as much

heat, for their proportional size, as a nuclear reactor. . . .”

Patrick P. Gelsinger Senior Vice PresidentGeneral Manager

Digital Enterprise GroupINTEL CORP.



Latest News

Power management, 2011 Jack Ganssle1/30/2011 From Microchip's eXtreme Low Power to TI's OMAP, new

chips contain some interesting and complex power management techniques.

http://www.eetimes.com/discussion/break-points/4212679/Power-management--2011












Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test,Lecture 1 9

VLSI Chip Power Density

4004

8008 8080

8085

8086

286 386

486 Pentium®

P6

1

10

100

1000

10000

1970 1980 1990 2000 2010

Year

P o

w e r D e n s i t y ( W

/ c m 2 )

Hot Plate

Nuclear

Reactor

Rocket

Nozzle

Sun’s Surface

Source: Intel



Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test,Lecture 1 10

SIA Roadmap for Processors (1999)

Year 1999 2002 2005 2008 2011 2014

Feature size (nm) 180 130 100 70 50 35

Logic transistors/cm2 6.2M 18M 39M 84M 180M 390M

Clock (GHz) 1.25 2.1 3.5 6.0 10.0 16.9

Chip size (mm2) 340 430 520 620 750 900

Power supply (V) 1.8 1.5 1.2 0.9 0.6 0.5

High-perf. Power (W) 90 130 160 170 175 183

Source: http://www.semichips.org

http://www.semichips.org/

http://www.semichips.org/



Power values of processors [ISSCC]



Problems found on first spin of silicon in 180/130 nm



Trends in Power conumption



Trends in power components

Component 90nm 65nm 45nm

Dynamic Power

per sq.cm

1X 1.4X 2X

Static Powerper sq. cm

1X 2.5X 6.5X

Total Power persq.cm

1X 2X 4X



Dynamic vs Static power



Sources of Power Consumption

Logic transitions

PD proportional to V, voltage swing, av.Switched capacitance/cycle

n-subnetwork and p-subnetworkconducting simultaneously.

Depends on input-output transitions

When input to and output from arenot changing

Current flow when ip is stable.



Designing for Low power

Reducing supply voltage

Reducing Vt

Frequency of transition or probabilityof transition.



MIS Structure as a tool to study surfaces

Metal

x

y

Insulator

Semiconductor- p-type

d



MOS (Metal-Oxide-Semiconductor)

Assume work function of metal and semiconductor are same.



MOS materials



MOS structure

Shown is the semiconductor substrate with a thin oxide layer and atop metal contact, also referred to as the gate.

A second metal layer forms an Ohmic contact to the back of thesemiconductor, also referred to as the bulk. The structure shown has a p-type substrate. We will refer to this as an n-type MOS capacitor since the

inversion layer contains electrons.

http://ece-www.colorado.edu/~bart/book/book/chapter6/ch6_2.htm



Terminologies

Workfunction: Minimum energy necessary for a metal

electron in metal vacuum system to escape into vacuum from an initialenergy at a fermi level. In metal semiconductor system, still it can beused by replacing free space permittivity ε0 semiconductor permittivityε

s

Electron Affinity: The difference in potential between an

electron at the vacuum level and electron at the bottom of theconduction band. Х

Bandgap: Is the the energy difference between the top of the

valence band and the bottom of the conduction band in thesemicondutor Eg



Energy bandgap (Eg) in semiconductor



Structure and principle of operation

To understand the different bias modes of an MOS we consider 3

different bias voltages.

below the flatband voltage, V FB

between the flatband voltage and the threshold voltage, V T

, and

larger than the threshold voltage.

These bias regimes are called the accumulation, d epletion and

inversion mode of operation.



Structure and principle of operation

Charges in a MOS structure under accumulation,depletion and inversion conditions



Four modes of MOS operation

The four modes of operation of an MOS structure:

Flatband,

Depletion,

Inversion and

Accumulation.

Flatband conditions exist when no charge is present in thesemiconductor so that the Si energy band is flat.

Surface depletion occurs when the holes in the substrate are pushedaway by a positive gate voltage.

A more positive voltage also attracts electrons (the minority carriers) tothe surface, which form the so-called inversion layer.

Under negative gate bias, one attracts holes from the p-type substrateto the surface, yielding accumulation



Effects of Real Surfaces



Charge Distribution



Key Definitions



Potential Definition



Depletion Width



Gate Voltage (depletion case)



MOS capacitor structure



MOS capacitor- accumulation



Accumulation occurs typically for -ve voltages where the -ve charge on

the gate attracts holes from the substrate to the oxide-semiconductor

interface.

Depletion occurs for positive voltages.

The +ve charge on the gate pushes the mobile holes into the substrate.

Therefore, the semiconductor is depleted of mobile carriers at the

interface and a -ve charge, due to the ionized acceptor ions, is left in the

space charge region.

MOS capacitor- accumulation



MOS capacitor- flat band



The voltage separating the accumulation and depletion regime is referred

to as the flatband voltage, V FB.

The flatband voltage is obtained when the applied gate voltage equals

the workfunction difference between the gate metal and the

semiconductor.

If there is a fixed charge in the oxide and/or at the oxide-silicon

interface, the expression for the flatband voltage must be modified

accordingly.

MOS capacitor- flat band



MOS capacitor- depletion



MOS capacitor- inversion



?

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