Low power vlsi design workshop 1

[email protected] www.siliconmentor.com

A workshop on

LOW POWER VLSI DESIGN METHODOLOGIES

All Participants will be Awarded Certification of Merit

Silicon Mentor SF-21,Parsvnath Bibhab Plaza, Alpha-1,Commercial Belt, Greater NOIDA, India Pin: 201310 Tel: 0120-4270185,+91-8130809758, +91-8802846627 Email:[email protected] Web: www.siliconmentor.com


About Silicon Mentor

Silicon Mentor is a Semiconductor Research and Development company with businesses

spread across design services & product development, distribution and training. Head

Quartered in Greater Noida, India Silicon Mentor is a leading provider of VLSI design services

and Intellectual Property. Silicon Mentor a privately held corporation has always strived to

deliver quality solutions & support in all the business areas that it serves. Our Services

offerings include Distribution of Silicon solutions, EDA tools, Engineering Services (Turn Key

Systems Design, Turn Key FPGA Design and), VLSI trainings and industrial training and

Manufacturing. These services are offered to SMEs, Universities and R&D houses in VLSI

Design.

Silicon Mentor University and Industry collaboration

Silicon Mentor University and Industry Collaboration. If we talk about the university relation, Silicon Mentor focusing on University relation to find out the real talent. Silicon Mentor provides a common platform for University and semiconductor industries to research and develop some of the revolutionary products .It comprises of a dedicated team of professionals who possess rich design and application engineering experience in VLSI, Embedded and related areas. It is associating with SMEs and Universities. Under the University collaboration we offer distribution of world class VLSI Development Platforms & EDA tools and technical support to academia community. Some of the service we provides our university partners • EDA Tools expert training to understand each and everything of it. • Domain focus workshop module to enhance the research activity. • Technical support services for academia community in their R & D activities etc.

Objective

This Two day workshop is focused on providing the way and methodologies to reduce the power consumption in VLSI circuits. This program also provides a chance to hands on session of available EDA tool. The use of EDA tool will mainly focus on to implement the simulation of different Low Power VLSI circuit design methodologies.

How to Register • All Engineering Students from EC department can participate in this program

Highlights

Schematic design and Simulation using AMS EDA tool


Concepts of Low power circuit design

MTCMOS and other important low power design methodologies.

Live Verification of circuit behaviour

Requirements The participants should familiar with the following basic concepts: • Basic electric circuit behaviour. • Exposure to current EDA tools. • Basic Concepts of CMOS Analog and Digital design

Schedule Day1: Session I: 8:30 am to 9:00 am • Registration Morning Session: Session I: 9:00 am to 10:45am • An overview of low power VLSI design. • Introduction available EDA tool. Tea Break: 10:45am to 11:00am Session II: 11:00am to 12:00pm • Concepts of Technology scaling • Need of Low power devices Lunch Break: 12pm to 1pm Afternoon Session: Session III: 1:00pm to 3:30pm • Power Reduction methods

Basic threshold reduction technique

Dual Threshold CMOS technique

Variable Threshold CMOS technique

MTCMOS technique

Power gating technique

Tea Break: 03:45pm to 4:00pm Session IV: 4:00pm to 5:30pm • Lab 1: Verification of previous mention technique using available EDA tool. Q/A Session: 5:30pm to 6:00pm


Day 2: Morning Session: Session V: 9:00 am to 10:45am • Parallel and Pipelined Architectures

Parallel Architecture

Pipeline Architecture Tea Break: 10:45am to 11:00am Session VI: 11:00am to 1:00pm

Parallel-Pipelined Architecture

Comparison

Lunch Break: 1pm to 2pm Afternoon Session: Session VII: 2:00pm to 3:45pm • Overview of challenges in low power VLSI circuit design • Major Low power AMS VLSI circuits Design challenges Tea Break: 03:45pm to 4:00pm Session IV: 4:00pm to 5:30pm • Lab 2: Schematic simulation of discussed Low power VLSI design Techniques. Q/A Session: 5:30pm to 6:00pm Course Duration: The duration of this workshop will be two consecutive days, with 7 -8 hours session each day

in a total of 14 -16 Hours.

Certificate Policy:

Certificate of Merit for all the workshop participants from Silicon Mentor

At the end of this workshop, a small competition will be organized among the participating students and winners will be awarded with a 'Certificate of Excellence'

Certificate of Coordination for the coordinators of the campus workshops Fees:

The charges for this workshop are nominal.

This fee includes -

I. Workshop training, study material, certification, government taxes and other

human resource charges.

II. Membership of VLSI Forum, where students can ask questions and discuss

topics with experts, using their registered E-mail ID.


Contact:

We ensure that you will find our training programs extremely beneficial for you. If you have

any queries kindly get back to us.

We are looking forward to a quick and positive response from you and a long term

association with your esteemed organization.

Silicon Mentor

Mob: +91-9999404998, +91-8130809758

Ph: -0120-4270185

Web: www.siliconmentor.com

Email: [email protected]

Low power vlsi design workshop 1

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