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Low Power VLSI Design: Low Power VLSI Design: Challenges and solutionsChallenges and solutions

Dr.S.Saravanan Dr.S.Saravanan M.E.,PhDM.E.,PhD

HOD/EEE(UG)HOD/EEE(UG)

Muthayammal Engineering CollegeMuthayammal Engineering College

RasipuramRasipuram

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AgendaAgenda MotivationMotivation Introduction To VLSI designIntroduction To VLSI design Sources of Power DissipationSources of Power Dissipation Low Power Design MethodologiesLow Power Design Methodologies Low Power Soc DesignsLow Power Soc Designs Low Power Multiplier DesignLow Power Multiplier Design Design of Low Power MACDesign of Low Power MAC ConclusionsConclusions

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MotivationMotivation

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Motivation Motivation

PORTABLE DEVICES …….Note Book PORTABLE DEVICES …….Note Book Computers, PDAs, Laptops, Cell Phones, Computers, PDAs, Laptops, Cell Phones, Pacemaker etc historical drivers of low power Pacemaker etc historical drivers of low power ……..require low power consumption & high ……..require low power consumption & high through putthrough put

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Motivation (Contd..)Motivation (Contd..)

• New portable compute-intensive applicationsNew portable compute-intensive applications* Multi-media* Multi-media* Video display and capture* Video display and capture* Audio reproduction & capture* Audio reproduction & capture* Handwriting recognition* Handwriting recognition* Notebook computer* Notebook computer* Personal data assistant* Personal data assistant* Implantable medical electronics* Implantable medical electronics

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Motivation (contd..)Motivation (contd..) Why so much of stress on Low Power?Why so much of stress on Low Power?

Portable devices run on batteryPortable devices run on battery

Battery life is limitedBattery life is limited

Energy density of Nickel-Metal Energy density of Nickel-Metal Hydride (NiMH) is low@30Wh/lbHydride (NiMH) is low@30Wh/lb

The battery technology is not improving at The battery technology is not improving at the same speed as that of VLSIthe same speed as that of VLSI

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VLSI Chip Power DensityVLSI Chip Power Density

40048008

80808085

8086

286386

486Pentium®

P6

1

10

100

1000

10000

1970 1980 1990 2000 2010

Year

Po

wer

Den

sity

(W

/cm

2 )

Hot Plate

NuclearReacto

r

RocketNozzle

SurfaceSun’s

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Motivation (contd..)Motivation (contd..) Power dissipation increases with the increase in Power dissipation increases with the increase in

clock speedclock speed This will increase the cost This will increase the cost packagingpackaging to remove the to remove the

heatheat Increased Power will generate excessive heat. This Increased Power will generate excessive heat. This

will cause will cause Electro migrationElectro migration Thus Thus ReliabilityReliability becomes an added issue to cost becomes an added issue to cost

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AgendaAgenda

MotivationMotivation Introduction To VLSI DesignIntroduction To VLSI Design Sources Of Power DissipationSources Of Power Dissipation Low Power Design MethodologiesLow Power Design Methodologies Low Power Soc DesignsLow Power Soc Designs Low Power Multiplier DesignLow Power Multiplier Design Design of Low Power MACDesign of Low Power MAC ConclusionConclusion

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What is Micro What is Micro Electronics?Electronics?

• The size of the Electronic Devices in μ- Electronics is in the range of micrometers

• Advantages of such devices…..

• Examples.. ICs……..

• μ- Electronics gave ICs

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Some Land MarksSome Land Marks• 1883 - Thomas Alva Edison , demonstrated the conduction of electrons in vacuum• 1904 - John Fleming invented the vacuum diode

• 1947 – The transistor was developed by BARDEEN, SHOCKLEY and BRATTAIN at Bell Labs.

• 1958 - JACK KILBY developed the first IC

• 1971 – Intel’s 4004 PMOS 4-bit processor @740K

• 1976 – Intel’s first Micro controller

• 1993- Pentium Processor

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BornBorn 23 May23 May 19081908))Madison, WisconsinMadison, Wisconsin, , United StatesUnited States

DiedDied January 30January 30, , 19911991 (aged 82) (aged 82)BostonBoston, , MassachusettsMassachusetts

NationalityNationality United StatesUnited States

FieldsFields PhysicsPhysics

InstitutionsInstitutionsBell LabsBell LabsUniversity of MinnesotaUniversity of MinnesotaUniversity of Illinois at Urbana-ChampaignUniversity of Illinois at Urbana-Champaign

Alma materAlma mater University of Wisconsin-MadisonUniversity of Wisconsin-MadisonPrinceton UniversityPrinceton University

DoctoralDoctoral advisor advisor Eugene WignerEugene Wigner             

Doctoral studentsDoctoral students John SchriefferJohn Schrieffer             Nick HolonyakNick Holonyak

Known forKnown for TransistorTransistorBCS theoryBCS theory

Notable awardsNotable awardsNobel Prize in PhysicsNobel Prize in Physics (1956) (1956)Nobel Prize in PhysicsNobel Prize in Physics (1972) (1972)IEEE Medal of HonorIEEE Medal of Honor (1971) (1971)

John Bardeen

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BornBorn February 10February 10, , 19021902China-AmoyChina-Amoy

DiedDied October 13October 13, , 19871987

NationalityNationality United StatesUnited States

FieldsFields PhysicistPhysicist, , InventorInventor

Known forKnown for TransistorTransistor

Notable awardsNotable awards Nobel Prize in PhysicsNobel Prize in Physics (1956) (1956)

Walter Houser Brattain

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BornBorn 13 February13 February 19101910))London, EnglandLondon, England

DiedDied12 August12 August 1989 (aged 79) 1989 (aged 79)Stanford, CaliforniaStanford, California

InstitutionsInstitutionsBell LabsBell LabsShockley SemiconductorShockley SemiconductorStanfordStanford

Alma materAlma mater CaltechCaltechMITMIT

Doctoral advisorDoctoral advisor John C. SlaterJohn C. Slater

Known forKnown for Co inventor of the Co inventor of the transistortransistor

Notable awardsNotable awards         Nobel Prize in Physics (1956)Nobel Prize in Physics (1956)

Religious stanceReligious stance None, atheistNone, atheist

William Shockley

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What is VLSI?What is VLSI?• Classification of ICs….. Based on no. of transistors

• In VLSI… Transistor count is in excess of 40 thousand

• A state of art of VLSI has more than 100 million transistors

• VLSI Chip…. Only CMOS transistors

• CAD tools are a must to design , verify and test the VLSI chips

• SOC- System On Chip

• ASP-Application Specific Product using IP CORES

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GORDON MOORE

Moore's Law: The number of transistor is doubled in every 18 months—Gordon E. Moore

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P6Pentium ® proc

486

3862868086

80858080

80084004

0.1

1

10

100

1971 1974 1978 1985 1992 2000Year

Po

wer

(W

atts

)Lead Microprocessors power continues to increaseLead Microprocessors power continues to increase

Power delivery and dissipation will be prohibitivePower delivery and dissipation will be prohibitive

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Lead microprocessors frequency doubles every 2 yearsLead microprocessors frequency doubles every 2 years

P6

Pentium ® proc486

38628680868085

8080

80084004

0.1

1

10

100

1000

10000

1970 1980 1990 2000 2010Year

Fre

qu

ency

(M

Hz)

2X every 2 years

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40048008

80808085 8086

286386

486Pentium® proc

P6

0.001

0.01

0.1

1

10

100

1000

1970 1980 1990 2000 2010

Year

Tra

nsi

sto

rs (

M)

2X growth in 1.96 years!

Transistors on lead microprocessors double every 2 yearsTransistors on lead microprocessors double every 2 years

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VLSI Design FlowVLSI Design Flow

VLSI DESIGN STYLES

Full Custom Semi custom FPGA Based

Standard cell Based

Gate ArrayBased

XilinxAlteraActel…………

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System Idea

Sub Blocks Identification

Bottom – Up(Full custom) Top Down

(Standard Cell)

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Sub BlockSchematic

Transistor levelSimulation

(Spice)

Layout

Extraction

LVS

Post LayoutSimulation

Full Custom Flow

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RTL Code

Logic Synthesis& Target Library

Mapping

TargetLibrary

Gate level Net list

DigitalSimulation

Placement & Routing

(Std.Cells)

Post layoutSimulation

Standard Cell Flow

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Placement & Routing(Top level)

Top levelVerification

Tape-out

Prototyping

Testing

Fabrication

Back End Flow

Full custom Standard cell

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CAD in VLSI

E (Engg) CADT (Technology) CAD

CONCEPT

VLSICkt.

Design

VLSI Chip

CONCEPT- Defines the final Product Specification ( the Product May be a Intel μP, Texas DSP or Motorola’s μC or it could be an ASIC)

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VLSI ProcessingVLSI Processing

OxidationOxidation Diffusion/Ion ImplantationDiffusion/Ion Implantation Poly DepositionPoly Deposition EtchingEtching Metallisation(vacuum/Sputtering)Metallisation(vacuum/Sputtering) TestingTesting SCRIBING And PACKAGINGSCRIBING And PACKAGING Testing…..Release To MarketTesting…..Release To Market

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AgendaAgenda

MotivationMotivation Introduction To VLSI DesignIntroduction To VLSI Design Sources Of Power DissipationSources Of Power Dissipation Low Power Design MethodologiesLow Power Design Methodologies Low Power Soc DesignsLow Power Soc Designs Low Power Multiplier DesignLow Power Multiplier Design Design of Low Power MACDesign of Low Power MAC ConclusionConclusion

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Power Equations in CMOSPower Equations in CMOS

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Techniques For Low PowerTechniques For Low Power

Supply voltageSupply voltage

Physical capacitancePhysical capacitance

Switching ActivitySwitching Activity

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Dynamic power (Switching )Dynamic power (Switching )

I charge

I discharge

0

1

Vdd

Vss

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Sources of Power DissipationSources of Power Dissipation

2. 2. Static PowerStatic Power = Leakage Power = Leakage Power

= I= ILL .V .VDDDD

N+ N+

I Rev

VDD

P-Sub

Gate Tunneling current is a major leakage power source in DSM ICs

IT

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Sources of Power DissipationSources of Power Dissipation

3. 3. Short Circuit PowerShort Circuit Power

P P short short = I= IDD ShortShort . V . VDDDD

IIDD Short Short

VDDVDD

VGND VGND

VDD/2

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AgendaAgenda

MotivationMotivation Introduction To VLSI DesignIntroduction To VLSI Design Sources Of Power DissipationSources Of Power Dissipation Low Power Design MethodologiesLow Power Design Methodologies Low Power Soc DesignsLow Power Soc Designs Low Power Multiplier DesignLow Power Multiplier Design Design of Low Power MACDesign of Low Power MAC ConclusionConclusion

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Levels of Levels of OptimizationOptimization

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Reduction of switching activity

• By proper choice of logic topology• By circuit level optimization

• The representation of data can have significant impact on switching activity at the system levelEx: Use of Gray coding instead of binary coding in applications where data bits change sequentially such as address bits

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Glitch ReductionGlitch Reduction

ABC

DE

ABCDE

Glitch

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Glitch ReductionGlitch Reduction

• Delay balanced• No glitch• Same function

Ex-or gates

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Gated Clock SignalsGated Clock Signals

Reg

Reg

Reg

EX-OR

MSBComparator

(N-1) bitComp-arator

Clk Gated clock

A(N-1)

B(N-1)

In conventional approachAll bits are first latched into2 N-bit Regs, and Subsequently applied to thecomparator

Clk

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Reduction of Switched CapsReduction of Switched CapsSystem level Measures

Large bus Caps due to:i) Large no.of drivers & receivers sharing the same busii) The parasitic Cap.of the long bus

Global bus structure is partitioned into a number of smaller Dedicated local buses to handle data transmission

C bus

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Circuit- Level Measures

• Cap is a function of the no. of transistors in a Logic circuit• Use Pass-transistor (transmission gates) logic

• Using Xn gates one can construct 2:1 mux And a XOR gate with 6 Transistors against 12 and 14 transistors

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Leakage current/powerLeakage current/power Dynamic Power is Dynamic Power is αα V V22

dddd

Static power is proportional to VStatic power is proportional to Vdddd

So power reduces with the reduction of VSo power reduces with the reduction of Vdddd

With the scaling down of voltage and With the scaling down of voltage and dimensions Vdimensions Vthth of the transistor is also scaled of the transistor is also scaled

downdown But leakage current increases exponentially But leakage current increases exponentially

in sub-threshold region . So reduce leakagein sub-threshold region . So reduce leakage

currentcurrent

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Variable Threshold CMOSVariable Threshold CMOS

Leakage is reduced by turning OFF Leakage is reduced by turning OFF transistors not in usetransistors not in use

Use High Vt transistor for low I -leak and Use High Vt transistor for low I -leak and use Low Vt transistor in critical pathuse Low Vt transistor in critical path

So one should use transistors of differentSo one should use transistors of different

threshold voltagesthreshold voltages

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Software Design For Low PowerSoftware Design For Low Power

Most efforts….focused on hardware designMost efforts….focused on hardware design It is because HW is the physical means by It is because HW is the physical means by

which power is converted into useful which power is converted into useful computationcomputation

It would be unwise to ignore the influence of It would be unwise to ignore the influence of SW on power dissipationSW on power dissipation

In systems based on digital processors or In systems based on digital processors or controllers, it is SW that directs much of the controllers, it is SW that directs much of the activity of the HWactivity of the HW

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So , the manner in which SW uses the HW So , the manner in which SW uses the HW can have a substantial impact on the power can have a substantial impact on the power dissipation of a systemdissipation of a system

Can draw an analogy from automobilesCan draw an analogy from automobiles The manner in which one drives his/her The manner in which one drives his/her

automobile can have a significant effect on automobile can have a significant effect on total fuel consumptiontotal fuel consumption

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AgendaAgenda MotivationMotivation Introduction To VLSI DesignIntroduction To VLSI Design Sources Of Power DissipationSources Of Power Dissipation Low Power Design MethodologiesLow Power Design Methodologies Low Power Soc DesignsLow Power Soc Designs Low Power Multiplier DesignLow Power Multiplier Design Design of Low Power MACDesign of Low Power MAC ConclusionConclusion

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IntroductionIntroduction Power is a serious concern in today's Power is a serious concern in today's

SoC design.SoC design. Core based SoC design is common to Core based SoC design is common to

get time to market advantage.get time to market advantage. Cores are designed to be generic and Cores are designed to be generic and

reusable with configurability.reusable with configurability. Need For Core customization.Need For Core customization. Core evaluation for PowerCore evaluation for Power

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SoC CompositionSoC Composition

SOC

Digital core

Analog FrontEnd

Serdes

PLL1

PLL2

Phy

Memory

Hard Macros

Spares

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AgendaAgenda MotivationMotivation Introduction To VLSI DesignIntroduction To VLSI Design Sources Of Power DissipationSources Of Power Dissipation Low Power Design MethodologiesLow Power Design Methodologies Low Power Soc DesignsLow Power Soc Designs Low Power Multiplier DesignLow Power Multiplier Design Design of Low Power MACDesign of Low Power MAC ConclusionConclusion

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VLSI Signal Processing Building VLSI Signal Processing Building BlocksBlocks

Adder Adder

MultiplierMultiplier

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Existing Low-power TechniquesExisting Low-power Techniques

Partially Guarded Computation (PGC).Partially Guarded Computation (PGC).

Dynamic-range Determination (DRD).Dynamic-range Determination (DRD).

Glitching Power Minimization (GPM).Glitching Power Minimization (GPM).

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Partially Guarded ComputationPartially Guarded Computation

MSPMSP LSPLSP

Detection logic Reg. 2Reg. 1

Latch

latch

clock

inputs

Out puts

Dynamic Range DeterminationDynamic Range Determination

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Add to Match the required word lengthAdd to Match the

required word length

Dynamic range determination

Dynamic range determination

Dynamic range determination

Dynamic range determination

Large eff. Dynamic range

Large eff. Dynamic range

Addition on the eff. bit

Addition on the eff. bit

Glitching Power MinimizationGlitching Power Minimization

By replacing some existing gates with By replacing some existing gates with functionally equivalent ones that can be functionally equivalent ones that can be “frozen” by asserting a control signal. “frozen” by asserting a control signal.

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Main Functions in MultiplierMain Functions in Multiplier

Partial products generationPartial products generation

Partial product compressionPartial product compression

Partial product additionPartial product addition

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Array MultiplierArray Multiplier

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Modified Booth MultiplierModified Booth Multiplier

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Booth Multiplier With Spurious Booth Multiplier With Spurious Power Suppression TechniquePower Suppression Technique

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Proposed Multiplier-DemonstrationProposed Multiplier-Demonstration

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AgendaAgenda MotivationMotivation Introduction To VLSI DesignIntroduction To VLSI Design Sources Of Power DissipationSources Of Power Dissipation Low Power Design MethodologiesLow Power Design Methodologies Low Power Soc DesignsLow Power Soc Designs Low Power Multiplier DesignLow Power Multiplier Design Design of Low Power MACDesign of Low Power MAC ConclusionConclusion

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Design of Low Power MACDesign of Low Power MAC

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Input Image And Its Pixel ValuesInput Image And Its Pixel Values

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1/9 1/9 1/9

1/9 1/9 1/9

1/9 1/9 1/9Input image of the filter Input image of the filter

Pixel value matrix of input image

Output Image And Its Pixel ValuesOutput Image And Its Pixel Values

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Output image of the filter

Pixel value matrix of output image

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ConclusionsConclusions

State of art VLSI chip ( SOC) contains State of art VLSI chip ( SOC) contains hundres of million transistorshundres of million transistors

So it dissipates lot of powerSo it dissipates lot of power To keep the packaging cost low….low To keep the packaging cost low….low

power technology power technology For portable devices low power ICs …a For portable devices low power ICs …a

mustmust There are different low power design There are different low power design

techniquestechniques

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ReferencesReferences Principles of CMOS VLSI Design---Neil weste Principles of CMOS VLSI Design---Neil weste

and K.Eshraghianand K.Eshraghian ASICs -------M.J.SmithASICs -------M.J.Smith CMOS Design, layout and simulation CMOS Design, layout and simulation

R.Jacob BakerR.Jacob Baker Introduction to VLSI circuits & systems Introduction to VLSI circuits & systems

-----John Uvemura-----John Uvemura Digital systems design using VHDL----Jr.RothDigital systems design using VHDL----Jr.Roth VHDL Primer----Jayaram BhaskarVHDL Primer----Jayaram Bhaskar Low-Power CMOS VLSI Circuit Design------Low-Power CMOS VLSI Circuit Design------

Kaushik Roy, Sharat PrasadKaushik Roy, Sharat Prasad

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THANK YOU

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