Low-Power VLSI Circuits -...
Transcript of Low-Power VLSI Circuits -...
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Power-Aware Testing for
Low-Power VLSI Circuits
Test
Power
Xiaoqing Wen Kyushu Institute of Technology
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High Performance
Call Cam
Web Mail
Function-Mode
Low Functional Power (Wide Use of PMS)
Successful LSI
Product Low Power
Call Cam
Web Mail
Test-Mode
High Test Power (Needs to Handle PMS)
Function
Test
Growing Power Gap
Test Power Related Crisis (Damage / Low Yield / High Cost)
Excessive Heat � Timing Failures
Low Power
Design
Power Aware
Test
Background
Higher Test Complexity due to PMS
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Outline
➊ Test Power Problems
➋ Power Analysis for Power-Aware Test
➌ Power Management for Power-Aware Test
➍ Future Research Topics
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Outline
➊ Test Power Problems
➋ Power Analysis for Power-Aware Test
➌ Power Management for Power-Aware Test
➍ Future Research Topics
![Page 5: Low-Power VLSI Circuits - 九州工業大学aries3a.cse.kyutech.ac.jp/~wen/ICSICT_Wen_2016-10-26.pdf2016/10/26 · Clock Stretch. Instantaneous Delay Increase on Clock Path. © X.](https://reader036.fdocuments.in/reader036/viewer/2022090810/611c4304dd806d6afa5b4ea2/html5/thumbnails/5.jpg)
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Shift Failure
Capture Power
(IR-Drop / L di/dt) – Induced Delay Increase and/or Clock Skew
Excessive Heat
Capture Failure
Launch Capture
C2 C1
Response Capture
Fast Test Cycle
Capture
Shift Power
CLK S1 SL
SE
Test Vector Load Completed
Shift
Test Vector Load Started
Many Shift Pulses
Clock Skew in Clock Tree
Excessive Delay Increase on Long Sensitized Path
Impact of Test Power in At-Speed Scan Testing (LOC)
Accumulative Instantaneous Instantaneous Clock
Stretch
Instantaneous
Delay Increase on Clock Path
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Chip Damage Reduced Reliability
High Test Cost
False-Test-Induced Yield Loss
Low Test Quality Low Reliability
Test Power Problems: P1 ~ P4
Excessive Heat
Shift Failure
Clock Stretch
Captuere Failure
P1
P2 P3
P4
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Functional Power
Test Power before
Function -Test Power Gap
Power-Aware Test
Test Power Analysis Test Power Management
Test Power after
Avoid Over-Kill
Avoid Under-Kill
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Outline
➊ Test Power Problems
➋ Power Analysis for Power-Aware Test
➌ Power Management for Power-Aware Test
➍ Future Research Topics
![Page 9: Low-Power VLSI Circuits - 九州工業大学aries3a.cse.kyutech.ac.jp/~wen/ICSICT_Wen_2016-10-26.pdf2016/10/26 · Clock Stretch. Instantaneous Delay Increase on Clock Path. © X.](https://reader036.fdocuments.in/reader036/viewer/2022090810/611c4304dd806d6afa5b4ea2/html5/thumbnails/9.jpg)
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Temp. Analysis
Sensitization Analysis
Excessive Heat Excessive Delay along Sensitized / Clock Paths
Delay Analysis
IR-Drop Analysis +
Ideal vs. Reality
Switching Activity
� Accurate but costly. � OK for sign-off but too expensive for use in DFT / ATPG.
� Fast and accurate-enough approximation needed. � Layout / PDN aware gate-level metric preferred.
Ideal Reality
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Excessive Heat for the Whole Circuit
Power Estimation Metrics
Whole-Circuit-Based Analysis
Power Estimation Metrics
P1: Excessive Heat
Path-Based Analysis
P2: Shift Failure P3: Capture Failure P3: Clock Stretch
Excessive Delay along Sensitized / Clock Paths
Local Global
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SFF2 SFF4 SFF1 SFF3 SI SO
Global Shift Power Analysis for Excessive Heat (P1)
Estimating Accumulative Impact of Shift Power
Weighted_Transitions = ∑ (Scan_Chain_Length - Transition_Position)
(R. Sankaralingam, et al., Proc. VTS, pp. 35-40, 2000)
0 1 1 0
0 - - -
1 0 - - 1 1 0 - 0 1 1 0
4 3 2 1 T1
T2
T3
T4
Switching at FFs
Switching in the CUT
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Local Shift Power Analysis for Shift Failures (P2)
Estimating Inst. Impact of Shift Power on Clock
FF1 FF2… …
SCK
WSA1 WSA2ΔWSA
exce
ssiv
e Timing failure
(Y. Yamato, et al., Proc. ITC, Paper 12.1, 2011)
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Aggressor Region of Gate G�
On-Path Gate G�
Long Sensitized Path P�
Impact Area of Path P
WSA of the Impact Area of P
FFs FFe �
Local Capture Power Analysis for Capture Failures (P3)
(X. Wen, et al., Proc. VTS, pp. 166-171, 2011)
G
N1 N2 N3
N5
N4
N6 N7 N8
N10 N11
N14 N15
N9 N12
N13 N16
N17 N18 N19
VDD
VSSP is risky Large
P is safe Small
Estimating Impact of Capture Power on LSP
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Local Capture Power Analysis for Clock Stretch (P4)
Estimating Impact of Capture Power on Clock
FFi …
SCK
WSA
exce
ssiv
e Clock Stretch
…
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Outline
➊ Test Power Problems
➋ Power Analysis for Power-Aware Test
➌ Power Management for Power-Aware Test
➍ Future Research Topics
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Temperature-Safety
Shift-Failure-Safety
Capture-Failure-Safety
Clock-Stretch-Safety
Requirements of Power-Aware Test
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Capture-Failure-Safety
ATPG Technique for Capture-Failure-Safety
Rescue &
Mask
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0
X
X X
1
0
1
X
0
Risky
Risky
Impact Areas
C2
Impa
ct X
-Bits�
Path Classification
Detection- Oriented
Test Cube Generation
0
X
X X
X
X
1
X
0
C1
X-Restoration for Risky Paths
Detection- Oriented X-Filling
(Random- Fill, etc.)
0
1
0 1
1
0
1
0
0
V1
Conventional X-Filling
for Reducing Capture WSA
Remaining Risky Path
Masking
0
0
0 0
1
0
1
1
0
N
V2
Rescue Mask
Impact Areas
Safe
Risky
(X. Wen, et al., Proc. ITC, Paper 13.1, 2012)
For Capture-Failure-Safety: Example
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19 © X. WEN 2016. All Rights Reserved. (X. Wen, et al., Proc. ITC, Paper 13.1, 2012)
For Capture-Failure-Safety: Results (Commercial ATPG)
82.8
78.0 76.0 80.9 83.1 81.4
1,568 2,592 3,776 1,280 1,330 1,444
39.3 46.6 45.6 43.1 42.9 44.2
1358.4
1292.8 3329.1 282.3 187.8 255.7
3.8 1.9 0.2 2.2 3.9
13.0
491 1,869 2,196
264 224 533
b17 b18 b19 b20 b21 b22
FC (%) SDQL BCE
(%) # of
Vectors Circuit CPU (Sec.)
% Risky Vectors
Ä Risky test vectors (i.e., vectors with risky paths) do exist. Ä Metrics for assessing test quality: FC: Fault Coverage BCE: Bridge Coverage Estimate SDQL: Small Delay Quality Level
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20 © X. WEN 2016. All Rights Reserved. (X. Wen, et al., Proc. ITC, Paper 13.1, 2012)
For Capture-Failure-Safety: Results (Proposed ATPG)
ΔFC (%)
ΔSDQL (%)
ΔBCE (%)
Δ# of Vectors
(%)
0.14 0.06 0.03 0.08 0.05 0.11
0.20 1.45 0.15 0.21 0.17 0.30
-0.45 -0.41 -0.07 +1.86 -1.10 -0.68
-2.02
-0.17 -0.65 +0.63 -0.98 -2.03
0 0 0 0 0 0
Circuit CPU (Sec.)
683 2,931 3,229
532 394
1,150
% Risky Vectors
b17 b18 b19 b20 b21 b22
Ä Capture-failure-safety is guaranteed. Ä Impact on and test data volume is insignificant. Ä Impact on test quality (FC, BCE, SDQL) is negligible.
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Capture-Failure-Safety
ATPG for Capture-Failure-Safety & Clock-Stretch-Safety
Rescue &
Mask &
Reduction
Clock-Stretch-Safety
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22 © X. WEN 2016. All Rights Reserved. (X. Wen, et al., Proc. ATS, 2015)
ATPG for Capture-Failure-Safety and Clock-Stretch-Safety Example (1/2)
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23 © X. WEN 2016. All Rights Reserved. (X. Wen, et al., Proc. ATS, 2015)
ATPG for Capture-Failure-Safety and Clock-Stretch-Safety Example (2/2)
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ATPG for Capture-Failure-Safety and Clock-Stretch-Safety
(X. Wen, et al., Proc. ATS, 2015)
Results (Commercial ATPG)
Ä Test data inflation is large. Ä Risks of capture failures remain even with LCP-ATPG vectors.
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ATPG for Capture-Failure-Safety and Clock-Stretch-Safety
(X. Wen, et al., Proc. ATS, 2015)
Results (Proposed ATPG)
Ä Test data inflation is very small. Ä Impact on test quality (FC, BCE, SDQL) is negligible. Ä Capture-failure-safety is guaranteed. Ä Clock stretch is significantly reduced.
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Outline
➊ Test Power Problems
➋ Power Analysis for Power-Aware Test
➌ Power Management for Power-Aware Test
➍ Future Research Topics
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Topic #1: GPU-Based Electrical-Level Test Power Analysis
Full-Timing Electrical-Level Test Power Analysis Needed
Ä Which test vector is test-power-risky ? Ä What is the problem (P1~P4) ? Ä Where is the problem ?
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Topic #2: Advanced Test Power Management
Excessive Heat
Shift Failure
Clock Stretch
Captuere Failure
P1 P2 P3 P4
Test Power Problems
◎ △ 〇 △
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Topic #3: Right-Power Test
Low-Power Test reduce only
Power-Safe Test reduce + mask
Right-Power Test reduce + mask + increase
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Right-Capture-Power Test Generation: Concept
Pinpoint Capture Power
Management
Long Sensitized Path
Sensitized Path
Non-Sensitized Path
FFs V F (V)
Capture
High Local Switching Activity
Low Local Switching Activity
Cold
Hot
Dead
No need to consider dead areas. Hot areas must be removed by reducing local switching. Cold areas may be made “warm” by increasing local switching.
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High Performance
Call Cam
Web Mail
Function-Mode
Low Functional Power (Wide Use of PMS)
Successful LSI
Product Low Power
Call Cam
Web Mail
Test-Mode
High Test Power (Needs to Handle PMS)
Function
Test
Growing Power Gap
Test Crisis (Damage / Low Yield / High Cost)
Excessive Heat � Timing Failures
Low Power
Design
Power Aware
Test
Summary
Higher Test Complexity due to PMS
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