Low Power Design Approach in VLSI

Introduction

• In this electronic era of miniaturization of circuitry,there is a need of devices with less power consumptionand short delay.

• But in actual these both these parameters arecontradictory to each other. If we improve the one,other one gets deteriorated because power delayproduct remains constant.

• This suggests that there must be a different approachto achieve desired level of power with delay in limitswhich can be tolerated in circuit.

Why to reduce Power Consumption ?

• To optimise battery Back-Up in mobile Devices.

• To ensure stable and Optimum working of circuit.

• Implementation of integrated circuitry in a chipresults in very high power consumption anddissipation.

• For longer device life.

Basic Concept Behind Power Reduction.....!

• The power reduction approach can be implemented byreducing the sub-threshold current which in-turn is responsiblefor lower static power consumption in circuit.

• Power consumption is proportional to the sub thresholdcurrent, if we decrease the current we can decrease the powerconsumption and this current is decreased if we increase thethreshold voltage.

• So, basically to ensure less power dissipation, thresholdvoltage level can be increased.

Low Power Strategies

• Reverse Body Biasing

• Dual Threshold CMOS

• Multi Threshold CMOS

• Sleep transistor

• Sleepy Stack

Reverse Body Biasing technique:

In this technique we provide voltage to the Body (Substrate) terminal ofMOSFET so that there is an increase in the threshold voltage whichfurther decreases the sub threshold current that ultimately helps inreduction of the power dissipation because power is proportional to thecurrent.

Dual Threshold CMOS:

This approach is implemented by using different CMOS with differentthreshold voltage to decrease the power consumption.

It mainly decreases the sub threshold leakage current.

But at the same time there is certain increase in the number of MOSFETswhich altogether increases the delay in circuit.

Multi Threshold CMOS:

Multiple threshold CMOS technique makes use of both high and lowthreshold MOS in the same circuit. The main concern is to selectivelychange the threshold voltages in order to improve the power consumptionwith improved the circuit speed.

Simple method of making MOS with multiple threshold voltages is toapply different bias voltages (VB) to the body or substrate terminal of thetransistors. Other methods include changing the thickness of gate oxideor dopant concentration in the MOS channel.

This approach overcomes the speed limitation which is present in DTCMOS

Sleep Transistor:

• In this technique, the sleeptransistors having high thresholdvalue is inserted between the Vddand the pull up network andanother transistor is insertedbetween the pull down networkand ground.

• These transistors switch ON whencircuit is ON and switch off whencircuit is idle. By cutting off thepower supply, this can reduce theleakage power.

• But when it is in cut off state, itdoes not hold states, it destruct thestates.

Sleepy Stack approach:

• This technique divides the single transistor into two half-sizetransistors. In this approach every half-transistor is added in seriesso that there is small leakage current.

• It also adds sleepy transistors to disconnect the power supplyand ground from the network so that there is no powerconsumption in off mode.

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