Low Power Circuits and Systems - Nptel · Q5. Distinguish between energy and power dissipation of...

Review Questions/AnswersReview Questions/AnswersLow Power Circuits and SystemsLow Power Circuits and SystemsReview Questions/AnswersReview Questions/AnswersLow Power Circuits and SystemsLow Power Circuits and Systems

Ajit PalAjit Pal

ProfessorProfessorDepartment of Computer Science and EngineeringDepartment of Computer Science and Engineering

Indian Institute of Technology KharagpurIndian Institute of Technology Kharagpur

INDIAINDIA--721302721302

Review Questions of LecReview Questions of Lec--11

Q1. Why low power has become an important issue in Q1. Why low power has become an important issue in

the present day VLSI circuit realization?the present day VLSI circuit realization?

Q2. How reliability of a VLSI circuit is related to its Q2. How reliability of a VLSI circuit is related to its

power dissipation?power dissipation?

Q3. How environment is affected by the power Q3. How environment is affected by the power

Ajit Pal, IIT KharagpurAjit Pal, IIT Kharagpur

dissipation of VLSI circuits?dissipation of VLSI circuits?

Q4. Why leakage power dissipation has become an Q4. Why leakage power dissipation has become an

important issue in deep submicron technology?important issue in deep submicron technology?

Q5. Distinguish between energy and power dissipatio n Q5. Distinguish between energy and power dissipatio n

of VLSI circuits. Which one is more important for of VLSI circuits. Which one is more important for

portable systems?portable systems?

2

Answer to Questions of LecAnswer to Questions of Lec--11

Q1. Why low power has become an important issue in the present Q1. Why low power has become an important issue in the present

day VLSI circuit realization?day VLSI circuit realization?

�� AnsAns: In deep submicron technology the power has bec ome as : In deep submicron technology the power has become as

one of the most important issue because of:one of the most important issue because of:

�� Increasing transistor count; the number of transist ors is Increasing transistor count; the number of transist ors is getting doubled in every 18 months based on getting doubled in every 18 months based on Moore,sMoore,s LawLaw

�� Higher speed of operation; the power dissipation is Higher speed of operation; the power dissipation is


�� Higher speed of operation; the power dissipation is Higher speed of operation; the power dissipation is proportional to the clock frequencyproportional to the clock frequency

�� Greater device leakage currents; In nanometer techn ology Greater device leakage currents; In nanometer techn ology the leakage component becomes a significant percent age of the leakage component becomes a significant percent age of the total power and the leakage current increases a t a faster the total power and the leakage current increases a t a faster rate than dynamic power in technology generationsrate than dynamic power in technology generations

3


Q2. How reliability of a VLSI circuit is related to its power Q2. How reliability of a VLSI circuit is related to its power

dissipationdissipation??

AnsAns: It has been observed that : It has been observed that eevery very 1010ºC rise in temperature ºC rise in temperature

roughly doubles the failure roughly doubles the failure rate because various farate because various faiilure mechanism lure mechanism

such as silicon interconnect fatigue, such as silicon interconnect fatigue, electromigrat ionelectromigration diffusion, diffusion,

junction diffusion and thermal runaway starts occur ring as junction diffusion and thermal runaway starts occur ring as

temperature increases.temperature increases.


temperature increases.temperature increases.

Q3. How environment is affected by the power dissip ation of VLSI Q3. How environment is affected by the power dissip ation of VLSI

circuitscircuits??

�� AnsAns: : According to an estimate of the U.S. Environmental According to an estimate of the U.S. Environmental Protection Agency (EPA), 80% of the power consumpti on by Protection Agency (EPA), 80% of the power consumpti on by office equipment are due to computing equipment and a large office equipment are due to computing equipment and a large part from unused part from unused equipment. Moreover, the power equipment. Moreover, the power is dissipated is dissipated mostly in the form of heat. The cooling techniques, such as AC mostly in the form of heat. The cooling techniques, such as AC transfers the heat to the environment.transfers the heat to the environment.


Q4. Why leakage power dissipation has become an imp ortant issue Q4. Why leakage power dissipation has become an imp ortant issue

in deep submicron technologyin deep submicron technology??

AnsAns: : In In deep submicron technology deep submicron technology the leakage component the leakage component

becomes a significant percentage of the total power and the becomes a significant percentage of the total power and the

leakage current increases at a faster rate than dyn amic power leakage current increases at a faster rate than dyn amic power in in

new new technology technology generations. That is why the leakage pow er has generations. That is why the leakage power has

become an important issue.become an important issue.


become an important issue.become an important issue.

Q5. Distinguish between energy and power dissipatio n of VLSI Q5. Distinguish between energy and power dissipatio n of VLSI

circuits. Which one is more important for portable systemscircuits. Which one is more important for portable systems??

AnsAns: Power (P) is the power dissipation in Watts at different : Power (P) is the power dissipation in Watts at di fferent

instances of time. On the other has energy (E) ref ers to the energy instances of time. On the other has energy (E) ref ers to the energy

consumed in Joule over a period of time (E = P*t).consumed in Joule over a period of time (E = P*t).


Q1. What are the commonly used conducting layers Q1. What are the commonly used conducting layers

used in IC fabrication?used in IC fabrication?

Q2. Show the basic structure of a MOS transistor.Q2. Show the basic structure of a MOS transistor.

Q3. What is the latch up problem that arises in bul k Q3. What is the latch up problem that arises in bul k

CMOS technology? How is it overcome?CMOS technology? How is it overcome?


Q3. Distinguish between the bulk CMOS technology wi th Q3. Distinguish between the bulk CMOS technology wi th

the the SoISoI technology fabrications. technology fabrications.

Q4. What are the benefits of SOI technology relativ e to Q4. What are the benefits of SOI technology relativ e to

conventional bulk CMOS technology?conventional bulk CMOS technology?


Q1. What are the commonly used conducting layers us ed in IC Q1. What are the commonly used conducting layers us ed in IC

fabrication?fabrication?

AnsAns: : Fabrication involves fabrication of Fabrication involves fabrication of ppatterned laye rs of the atterned layers of the

three conducting materials: three conducting materials: metalmetal , , polypoly--siliconsilicon and and diffusion by diffusion by

using using a series of photolithographic techniques and chemic al a series of photolithographic techniques and chemic al

processes involving oxidation of silicon, diffusion of impurities processes involving oxidation of silicon, diffusion of impurities

into the silicon and deposition and etching of alum inum or into the silicon and deposition and etching of alum inum or


into the silicon and deposition and etching of alum inum or into the silicon and deposition and etching of alum inum or

polysiliconpolysilicon on the silicon to provide interconnectio n.on the silicon to provide interconnection.


Q2. Show the basic structure of a MOS transistor.

�Ans: The basic structure of a MOS transistor is giv en below. On a lightly doped substrate of silicon two islands of d iffusion regions called as source and drain , of opposite polarity of that of the substrate, are created. Between these two regions, a thin insulating layer of silicon dioxide is formed and on top of this a conducting material made of poly-silicon or metal called gate is deposited.

Ajit Pal, IIT KharagpurAjit Pal, IIT Kharagpur 8

substrate

Source DrainGate

MetalPolysiliconOxideDiffusionDepletion

Answer to Questions of LecAnswer to Questions of Lec--22Q3Q3. What is the latch up problem that arises in bulk CMOS . What is the latch up problem that arises in bulk CMOS

technology? technology?

AnsAns: The latch: The latch--up is an inherent problem in both nup is an inherent problem in both n--well as well a s pwell as well as p--

well based CMOS circuits. The phenomenon is caused by the well based CMOS circuits. The phenomenon is caused by the

parasitic bipolar transistors formed in the bulk of silicon as shown parasitic bipolar transistors formed in the bulk of silicon as shown

in the figure for the nin the figure for the n--well process. well process. LatchLatch--upup can be defined as the can be defined as the

formation of a lowformation of a low --impedance path between the power supply and impedance path between the power supply and


formation of a lowformation of a low --impedance path between the power supply and impedance path between the power supply and

ground rails through the parasitic ground rails through the parasitic npnnpn and and pnppnp bipolar transistors. bipolar transistors.

As shown the BJTs are crossAs shown the BJTs are cross--coupled to form the st ructure of a coupled to form the structure of a

siliconsilicon--controlledcontrolled--rectifier (SCR) providing a shortrectifier (SCR) providing a short--circuit path circuit path

between the power rail and ground. Leakage current through the between the power rail and ground. Leakage current through the

parasitic resistors can cause one transistor to tur n on, which in parasitic resistors can cause one transistor to tur n on, which in

turn turns on the other transistor due to positive feedback and turn turns on the other transistor due to positive feedback and

leading to heavy current flow and consequent device failure. leading to heavy current flow and consequent device failure.

9


Q4. How the latch up problem can be overcome? Q4. How the latch up problem can be overcome?

AnsAns: There are several approaches to reduce the ten dency : There are several approaches to reduce the tenden cy

of Latchof Latch--up. Some of the important techniques are up. Some of the important techniques are

mentioned below:mentioned below:

�� Use guard ring around pUse guard ring around p-- and/or nand/or n--well with frequent well with frequent

contacts to the ringscontacts to the rings


contacts to the ringscontacts to the rings

�� To reduce the gain product B1XB2To reduce the gain product B1XB2

�� Moving the nMoving the n--well and the n+ source/drain further apartwell and the n+ source/drain further apart

�� Buried n+ layer in well to reduce gain of Q1Buried n+ layer in well to reduce gain of Q1

�� Higher substrate doping level to reduce RHigher substrate doping level to reduce R--subsub

�� Reduce RReduce R--well by making low resistance contact to GNDwell by making low resistance contact to GND

10


Q5. Distinguish between the bulk CMOS technology wi th Q5. Distinguish between the bulk CMOS technology wi th

the the SoISoI technology fabrications. technology fabrications.

AnsAns: In bulk CMOS technology, a lightly doped p: In bulk CMOS technology, a lightly doped p--type or type or

nn--type substrate is used to fabricate MOS transis tors. type substrate is used to fabricate MOS transistors .

On the other hand, an insulator can be used as a On the other hand, an insulator can be used as a

substrate to fabricate MOS transistorssubstrate to fabricate MOS transistors


substrate to fabricate MOS transistorssubstrate to fabricate MOS transistors

11


Q6. What are the benefits of SOI technology relativ e to conventional Q6. What are the benefits of SOI technology relativ e to conventional

bulk CMOS technology?bulk CMOS technology?

�� AnsAns: Benefits of SOI technology relative to convent ional silicon : Benefits of SOI technology relative to convention al silicon (bulk CMOS):(bulk CMOS):

�� Lowers parasitic capacitance due to isolation from the bulk Lowers parasitic capacitance due to isolation from the bulk silicon, which improves power consumption and thus high speed silicon, which improves power consumption and thus high speed performance.performance.

�� Reduced short channel effectsReduced short channel effects


�� Reduced short channel effectsReduced short channel effects

�� Better subBetter sub--threshold slope.threshold slope.

�� No Latch up due to BOX (buried oxide).No Latch up due to BOX (buried oxide).

�� Lower Threshold voltage.Lower Threshold voltage.

�� Reduction in junction depth leads to low leakage cu rrent.Reduction in junction depth leads to low leakage cu rrent.

�� Higher Device density.Higher Device density.

12

Review Questions Review Questions of Lecof Lec--33

Q1. What are the basic assumptions of the fluid mod el?Q1. What are the basic assumptions of the fluid mod el?

Q2. Explain the function of a MOS transistor in the Q2. Explain the function of a MOS transistor in the

saturation mode using fluid model.saturation mode using fluid model.

Q3. Explain the function of a MOS transistor in the Q3. Explain the function of a MOS transistor in the

nonsaturationnonsaturation mode using the fluid model.mode using the fluid model.


Q4. Explain the three modes of operation of a MOS Q4. Explain the three modes of operation of a MOS

transistors.transistors.

Q5. Explain the linear region of the IQ5. Explain the linear region of the I--V characte ristic of V characteristic of

an an nMOSnMOS transistor using the fluid model.transistor using the fluid model.

13

Answer to the Questions of LecAnswer to the Questions of Lec--3 3

Q1. What are the basic assumptions of the fluid mod el?Q1. What are the basic assumptions of the fluid mod el?

AnsAns: There are two basic assumptions as follows:: There are two basic assumptions as follows:

(a) Electrical charge is considered as fluid, which can move from (a) Electrical charge is considered as fluid, which can move from

one place to another depending on the difference in their level, of one place to another depending on the difference in their level, of

one from the other, just like a fluid.one from the other, just like a fluid.

(b) Electrical potentials can be mapped into the ge ometry of a (b) Electrical potentials can be mapped into the ge ometry of a


container, in which the fluid can move around.container, in which the fluid can move around.

Q2. Q2. Explain the function of a MOS transistor in the Explain the function of a MOS transistor in the non saturationnonsaturation

mode using the fluid modelmode using the fluid model..

AnsAns: Gate voltage higher than the threshold voltage and the drain : Gate voltage higher than the threshold voltage an d the drain

voltage is slightly higher than source voltage. In such a situation, voltage is slightly higher than source voltage. In such a situation,

as the drain voltage is increased the slope of the fluid flowing out as the drain voltage is increased the slope of the fluid flowing out

increases indicating linear increase in the flow of current. increases indicating linear increase in the flow of current.

14


Q3. Explain the function of a MOS transistor in the saturation mode Q3. Explain the function of a MOS transistor in the saturation mode

using fluid model.using fluid model.

AnsAns: : The saturation mode corresponds to the drain voltage is much The saturation mode corresponds to the drain voltag e is much

higher than source voltage. higher than source voltage. In such a situation the slope of the In such a situation the slope of the

fluid cannot increase representing constant flow of fluid.fluid cannot increase representing constant flow of fluid.

Q4. Explain the three modes of operation of a MOS t ransistorsQ4. Explain the three modes of operation of a MOS t ransistors..


AnsAns: The three modes are:: The three modes are:

(a)(a) Accumulation mode when Accumulation mode when VgsVgs is much less than is much less than VtVt

(b)(b) Depletion Depletion mode when mode when VgsVgs is equal to is equal to VtVt

(c)(c) Inversion Inversion mode when mode when VgsVgs is greater than is greater than VtVt

15


Q5. What are the three regions of operation of a MO S transistor?Q5. What are the three regions of operation of a MO S transistor?

AnsAns: The three regions are:: The three regions are:

CutCut--off off regionregion : This is essentially the accumulation mode, where : This is essentially the accumulation mode, where

there is no effective flow of current between the s ource and drain.there is no effective flow of current between the s ource and drain.

NonNon--saturated regionsaturated region : : This is the This is the active,active, linearlinear or or week inversionweek inversion

region, where the drain current is dependent on bot h the gate and region, where the drain current is dependent on bot h the gate and


drain voltages.drain voltages.

Saturated region:Saturated region: This is the This is the strong inversionstrong inversion region, where the region, where the

drain current is independent of the draindrain current is independent of the drain--toto--so urce voltage but source voltage but

depends on the gate voltage.depends on the gate voltage.

16


Q1. What is the threshold voltage of a MOS transis tor? How it

varies with the body bias?

Q2. The following parameters are given for an nMOS p rocess: t ox

500Å, NA = 1x1016cm -3, ND = 1x1020cm -3, NOX = 2x1010cm -1. (i)

Calculate Vt for an unimplanted transistor, (ii) what type and what

concentration must be implanted to achieve Vt = +1.5 V and Vt = -

2.0V?


2.0V?

Q3. What is channel length modulation effect? How t he voltage

current characteristics are affected because of thi s effect?

Q4. What is body effect? How does it influences the threshold

voltage of a MOS transistor?

Q5. What is transconductance of a MOS transistor? Ex plain its role

in the operation of the transistor.

17

Answer to the Questions of LecAnswer to the Questions of Lec--44

Q1. What is the threshold voltage of a MOS transis tor? How it

varies with the body bias?

Ans: One of the parameters that characterizes the s witching

behavior of a MOS transistor is its threshold voltag e Vt. This can be

defined as the gate voltage at which a MOS transist or begins to

conduct.

Q2. The following parameters are given for an nMOS process: t


Q2. The following parameters are given for an nMOS process: tox

500Å, NA = 1x1016cm -3, ND = 1x1020cm -3, NOX = 2x1010cm -1. (i)

Calculate Vt for an unimplanted transistor, (ii) what type and what

concentration must be implanted to achieve Vt = +1.5 V and Vt = -

2.0V?

18

Q3. What is channel length modulation effect? How t he voltage

current characteristics are affected because of thi s effect?

Ans: It is assumed that channel length remains cons tant as the

drain voltage is increased appreciably beyond the o n set of

saturation. As a consequence, the drain current rem ains constant

in the saturation region. In practice, however the channel length

shortens as the drain voltage is increased. For lon g channel



shortens as the drain voltage is increased. For lon g channel

lengths, say more than 5 µm, this variation of length is relatively

very small compared to the total length and is of l ittle consequence.

However, as the device sizes are scaled down, the v ariation of

length becomes more and more predominant and should be taken

into consideration. As a consequence, the drain cu rrent increases

with the increase in drain voltage even in the satu ration region.

19

Q4. What is body effect? How does it influences the

threshold voltage of a MOS transistor?

Ans: All MOS transistors are usually fabricated on a common

substrate and substrate (body) voltage of all devic es is normally

constant. However, as we shall see in subsequent ch apters, when

circuits are realized using a number of MOS devices , several



devices are connected in series. This results in di fferent source

potentials for different devices. It may be noted t hat the threshold

voltage V t is not constant with respect to the voltage differe nce

between the substrate and the source of the MOS tra nsistor. This is

known as the substrate-bias effect or body effect . Increasing the

Vsb causes the channel to be depleted of charge carries and this

leads to increase in the threshold voltage.

20

Q5. What is transconductance of a MOS transistor?

Explain its role in the operation of the transistor .

Ans: Trans-conductance is represented by the change in

drain current for change in gate voltage for consta nt value

of drain voltage. This parameter is somewhat simila r to β,

the current gain of bipolar junction transistors. The



the current gain of bipolar junction transistors. The

following equation shows the dependence of on vario us

parameters. As MOS transistors are voltage controll ed

devices, this parameter plays an important role in

identifying the efficiency of the MOS transistor.

21


Q1. Explain the behaviour of a nMOS transistor as a s witch.

Q2. Explain the behaviour of a pMOS transistor as a s witch.

Q3. How one nMOS and one pMOS transistor are combined to

behave like an ideal switch.

Q4. The input of a lightly loaded transmission gate is slowly


changes from HIGH level to LOW level. How the curre nts through

the two transistors vary?

Q5. How its ON-resistance of a transmission gate ch anges as the

input varies from 0 V to Vdd, when the output has a light capacitive

load.

22

Q3. How one nMOS and one pMOS transistor are

combined to behave like an ideal switch.


Vdd

0/Vdd0/Vdd

0


Ans: To overcome the limitation of either of the tr ansistors, one

pMOS and one nMOS transistor can be connected in parall el with

complementary inputs at their gates. In this case w e can get both

LOW and HIGH levels of good quality at the output. The low level

passes through the nMOS switch and HIGH level passes through

the pMOS switch without any degradation as shown in the figure.

23


Q4. The input of a lightly loaded transmission gate is slowly

changes from HIGH level to LOW level. How the curre nts through

the two transistors vary?

Ans: Another situation is the operation of the tran smission gate

when the output is lightly loaded (smaller load cap acitance). In this

case, the output closely follows the input. In this case the

transistors operate in three regions depending on t he input voltage


transistors operate in three regions depending on t he input voltage

as follows:

Region I: nMOS non-saturated, pMOS cut-OFF

Region II: nMOS non-saturated, pMOS non-saturated

Region III: nMOS cut off, pMOS non-saturated

24

Q5. How its ON-resistance of a transmission gate

changes as the input varies from 0 V to Vdd, when t he

output has a light capacitive load.

Ans: The variation of ON resistance is shown in the

figure. The parallel resistance remains more or les s

constant.



constant.

25

Vtp| Vtn| Vdd

RON

Vdd

- Vtn

Reqp || Reqn

Reqp

Reqn

CL

Vdd

0Vout=Vin - V

Idsn+Idsp

IdspIdsn

Vout

Id

Vout

Vtp| |


Q1. Draw the ideal characteristics of a CMOS invert er Q1. Draw the ideal characteristics of a CMOS invert er

and compare it with the actual characteristics.and compare it with the actual characteristics.

Q2. What is noise margin? Find out the noise margin Q2. What is noise margin? Find out the noise margin

from the actual characteristics of the inverter.from the actual characteristics of the inverter.

Q3. Compare the characteristics of the different t ypes Q3. Compare the characteristics of the different t ypes


of MOS inverters in terms of noise margin and power of MOS inverters in terms of noise margin and power

dissipation.dissipation.

26


Q1. Draw the ideal characteristics of a CMOS invert er Q1. Draw the ideal characteristics of a CMOS invert er

and compare it with the actual characteristics.and compare it with the actual characteristics.

AnsAns: The ideal and actual characteristics are given : The ideal and actual characteristics are given

below. In the ideal characteristics, the output vol tage is below. In the ideal characteristics, the output vol tage is

VddVdd for input voltage from o to for input voltage from o to VddVdd/2 and 0 for input /2 and 0 for input

voltage from voltage from VddVdd/2 to /2 to VddVdd. This is not true in case of the . This is not true in case of the


voltage from voltage from VddVdd/2 to /2 to VddVdd. This is not true in case of the . This is not true in case of the

actual characteristics as shown below.actual characteristics as shown below.

27

Vout

Vin

2

Vdd

Vdd

Vdd

Vdd

VOH

VOL

VIH

VIL

Vout

VinVT

VIN

= VOUT

Q2. What is noise margin? Find out the noise margin from the Q2. What is noise margin? Find out the noise margin from the

actual characteristics of the inverteractual characteristics of the inverter..

AnsAns: : An important parameter called noise margin is associated with

the input-output voltage characteristics of a gate. It is defined as

the allowable noise voltage on the input of a gate so that the output

is not affected. The deviations in logic levels fro m the ideal values,

which are restored as the signal propagates to the output, can be



which are restored as the signal propagates to the output, can be

obtained from the DC characteristic curves. The log ic levels at the

input and output are given by

The noise margins are:

28

Q3. Compare the characteristics of the different t ypes of MOS Q3. Compare the characteristics of the different t ypes of MOS

inverters in terms of noise margin and power dissip ationinverters in terms of noise margin and power dissip ation..

AnsAns: Various characteristic parameters are compared in the : Various characteristic parameters are compared in the

following table:following table:




Q1. What is the inversion voltage of an inverter? F ind Q1. What is the inversion voltage of an inverter? F ind

out the inversion voltage of a CMOS inverter.out the inversion voltage of a CMOS inverter.

Q2. How the inversion voltage is affected by the re lative Q2. How the inversion voltage is affected by the re lative

sizes of the sizes of the nMOSnMOS and and pMOSpMOS transistors of the CMOS transistors of the CMOS

inverter?inverter?


Q3. Find out the noise margin of a CMOS inverter.Q3. Find out the noise margin of a CMOS inverter.

Q4. How the noise margin is affected by voltage Q4. How the noise margin is affected by voltage

scaling?scaling?

Q5. What is the lower limit of supply voltage of a CMOS Q5. What is the lower limit of supply voltage of a CMOS

inverter. What happens if the supply voltage is inverter. What happens if the supply voltage is fur ther further

reduced?reduced?

30


Q1. What is the inversion voltage of an inverter? F ind out the Q1. What is the inversion voltage of an inverter? F ind out the

inversion voltage of a CMOS inverter.inversion voltage of a CMOS inverter.

AnsAns: The inversion voltage : The inversion voltage VinvVinv is defined as the voltage at which is defined as the voltage at which

the output voltage Vo is equal to the input voltage Vin. For a CMOS the output voltage Vo is equal to the input voltage Vin. For a CMOS

inverter it can be expressed in terms of the thres hold voltages of inverter it can be expressed in terms of the thres hold voltages of

the MOS transistors and other parameters. the MOS transistors and other parameters.


ForFor

31

Q2. How the inversion voltage is affected by the re lative Q2. How the inversion voltage is affected by the re lative

sizes of the sizes of the nMOSnMOS and and pMOSpMOS transistors of the CMOS transistors of the CMOS

inverterinverter??

AnsAns: : In a CMOS process



To make one may choose

to get to get VinvVinv = = VddVdd/2/2

32

Q3. Find out the noise margin of a CMOS inverterQ3. Find out the noise margin of a CMOS inverter..

AnsAns: : For a symmetric inverter

Noise Margin

and





scaling?scaling?

AnsAns: As the supply voltage is : As the supply voltage is

reduced, the margin also decreasesreduced, the margin also decreases

as shown in the figure.as shown in the figure.

33

Vdd = 5V

Vdd = 4V

Vdd = 3V

Vdd = 2V

Vtn = 1V

Vtp = -1V

1 2 3 4 5

1

2

3

4

5

Input Voltage

Out

put V

olta

ge

Q5. What is the lower limit of supply voltage of a CMOS Q5. What is the lower limit of supply voltage of a CMOS

inverter. What happens if the supply voltage is fur ther inverter. What happens if the supply voltage is fur ther

reducedreduced??

AnsAns: The lower limit of the supply voltage depends on : The lower limit of the supply voltage depends on

the sum of the thresholdthe sum of the threshold

voltages of the voltages of the nMOSnMOS andandVdd



voltages of the voltages of the nMOSnMOS andand

the the pMOSpMOS transistors.transistors.

VddVdd = = VtnVtn +|+|VtpVtp|. As the supply |. As the supply

voltage is reduced further, voltage is reduced further,

it leads to hysteresis in the it leads to hysteresis in the

ttransfer characteristics.ransfer characteristics.34

Input Voltage

Out

put V

olta

ge

VddVtnVdd - IVtpI


Q1. What is sheet resistance? Find out the expressi on Q1. What is sheet resistance? Find out the expressi on

of the resistance of rectangular sheet in terms of sheet of the resistance of rectangular sheet in terms of sheet

resistance.resistance.

Q2. Find out the capacitance of a MOS capacitor.Q2. Find out the capacitance of a MOS capacitor.

Q3. Find out the expression of delay time of a CMOS Q3. Find out the expression of delay time of a CMOS


inverter.inverter.

Q4. What are the various ways to reduce the delay t ime Q4. What are the various ways to reduce the delay t ime

of a CMOS inverter?of a CMOS inverter?

Q5. Explain the commonly used technique to estimate Q5. Explain the commonly used technique to estimate

the delay time of a CMOS inverter.the delay time of a CMOS inverter.

35

Answer to the Questions of LecAnswer to the Questions of Lec--88�� Q1. What is sheet resistance? Find out the expressi on Q1. What is sheet resistance? Find out the expressi on

of the resistance of rectangular sheet in terms of sheet of the resistance of rectangular sheet in terms of sheet

resistance.resistance.AnsAns: The sheet resistance is defined as the resista nce per unit area : The sheet resistance is defined as the resistance per unit area of a sheet of material.of a sheet of material. Consider a rectangular sheet of material with Consider a rectangular sheet of material with Resistivity = ρρρρ, Width = W, Thickness = t and Length = L.Then, the resistance between the two ends is


ohmA

L

Wt

LR AB

ρρ ==.

ohmRt

RS == ρFor L = W

Where, RS is defined as the sheet resistance

Then, the resistance between the two ends is

Q2. Find out the capacitance of a MOS capacitor.Q2. Find out the capacitance of a MOS capacitor.

AnsAns: The capacitance of a parallel plate capacitor is given : The capacitance of a parallel plate capacitor is given

by by

Farads 0

D

ACo insεε=



Where A is the area of the plates and D is the thic kness of Where A is the area of the plates and D is the thic kness of

the insulator between the plates. the insulator between the plates.

37

Q3. Find out the expression of delay time of a CMOS Q3. Find out the expression of delay time of a CMOS

inverterinverter..

AnsAns: The delay time td is given by the expression: The delay time td is given by the expression

2

1

−

+=

t

L

pp

p

nn

nd

VV

C

WK

L

WK

Lt



Where C is the load capacitance, Where C is the load capacitance, VddVdd is the supply is the supply

voltage and voltage and VtVt is the threshold voltages of the MO S is the threshold voltages of the MOS


38

1

−

dd

tdd

ppnn

V

VV

WKWK

Q4. What are the various ways to reduce the delay t ime Q4. What are the various ways to reduce the delay t ime

of a CMOS inverterof a CMOS inverter??

AnsAns: Various ways for reducing the delay time are g iven below:: Various ways for reducing the delay time are give n below:

(a) The (a) The width of the MOS transistors can be increas ed to reduce the width of the MOS transistors can be increased to re duce the

delay. This is known as gate sizing, which will be discussed later in delay. This is known as gate sizing, which will be discussed later in

more details.more details.



more details.more details.

(b) The (b) The load capacitance can be reduced to reduce d elay. This is load capacitance can be reduced to reduce delay. Th is is

achieved by using transistors of smaller and smalle r dimensions as achieved by using transistors of smaller and smalle r dimensions as

provided by future generation technologies. provided by future generation technologies.

(c) Delay (c) Delay can also be reduced by increasing the sup ply voltage can also be reduced by increasing the supply voltag e VddVdd

and/or reducing the threshold voltage and/or reducing the threshold voltage VtVt of the MO S transistors. of the MOS transistors.

39


Q5. Explain the commonly used technique to estimate Q5. Explain the commonly used technique to estimate

the delay time of a CMOS inverter.the delay time of a CMOS inverter.

AnsAns: As the delay time of an inverter is very small , it : As the delay time of an inverter is very small, i t

cannot be measured accurately using conventional cannot be measured accurately using conventional

method with the help of an oscilloscope. Delay is method with the help of an oscilloscope. Delay is

usually measured by realizing a ring oscillator usin g a usually measured by realizing a ring oscillator usin g a


usually measured by realizing a ring oscillator usin g a usually measured by realizing a ring oscillator usin g a

large number of inverters, say 101. Then the freque ncy large number of inverters, say 101. Then the freque ncy

of oscillation is measured using the expressionof oscillation is measured using the expression

wwhere n is the number of inverters and td is the here n is the number of inverters and td is the

ddelay time.elay time.

40

dntf

2

1=


Q1. Justify the reason for not recommending more th an 4 pass transistors to use in series in realizing logic cir cuits.Q2. Draw the schematic diagram of an inverting supe r-buffer and explain its operation.Q3. Give the schematic diagram of a Bi-CMOS inverte r. Explain its operation. . Compare the switching characteristics o f a BiCMOSinverter with respect to that for static CMOS for d ifferent fan out conditions.


conditions.Q4. Prove that the delay of a series of pass transi stors can be reduced from quardratic dependence to linear depende nce on the number of transistors in series by inserting buffer s at suitable intervals.Q5. Design a scaled chain of inverters such that th e delay time between the logic gate (C g = 100 fF) and a load capacitance 2 pF in minimized. Find out the number of stages and stage ratio.

41


Q1. Explain the basic concept of super buffer.

Ans: There are situations when a large load capacit ance such as, There are situations when a large load capacitance such as,

long buffers, offlong buffers, off--chip capacitive load, or I/O buf fer are to be chip capacitive load, or I/O buffer are to be

driven by a driven by a gate. In gate. In such cases, the delay can be very high if such cases, the delay can be very high if

driven by a standard driven by a standard gate. gate. Limitations Limitations of driving by a simple of driving by a simple

nMOSnMOS inverter inverter is the ais the a symmetric symmetric drive capability of pulldrive capability of pull --up and up and


nMOSnMOS inverter inverter is the ais the a symmetric symmetric drive capability of pulldrive capability of pull --up and up and

pullpull--down devices (down devices (ratioedratioed logiclogic). Moreover, when ). Moreover, when the pullthe pull--down down

transistor is ON, the pulltransistor is ON, the pull--up transistor also rema ins up transistor also remains ON. So, the ON. So, the

pullpull--down transistor should also sink the current of the pulldown transistor should also sink the current of the pull--up up

device. Although this limitation is overcome in CMO S circuits, device. Although this limitation is overcome in CMO S circuits,

there is asymmetry in drive there is asymmetry in drive capability of pullcapability of pull--up and pullup and pull--down down

devices having the same minimum size.devices having the same minimum size.

42

Q2. Draw the schematic diagram of an inverting and non-inverting

super-buffers and explain its operation.

Ans: The schematic diagrams of the super buffers a re given below. The average of the saturation currents for Vds = 5V and linear current for Vds = 2.5V is approximately 4.4 βpu for the standard inverter. On the other hand the, for the super-buff er, the average current is 19.06 βpu, which is 4 times that of standard inverter. Thus, the pull -up device is capable of sourcing about four times



Thus, the pull -up device is capable of sourcing about four times the current of the standard nMOS inverter..

43

Vin

Vout

Vin

Vout

VddVddVdd2/1

1/2

2/1

1/2

2/1

1/2

Q3. Give the schematic diagram of a Bi-CMOS inverte r. Explain its operation. . Compare the switching characteristics o f a BiCMOSinverter with respect to that for static CMOS for d ifferent fan out conditions.Ans: The schematic diagram of a BiCMOS inverter is g iven below. Higher current drive capability of bipolar NPN tran sistors is used in Higher current drive capability of bipolar NPN tran sistors is used in realizing birealizing bi--CMOS inverters. The delays of CMOS an d CMOS inverters. The delays of CMOS and BiCMOSBiCMOSinverters are compared for different faninverters are compared for different fan--outs. It may be noted that outs. It may be noted that for fanfor fan --out of 1 or 2, CMOS provides smaller delay compared to out of 1 or 2, CMOS provides smaller delay compared to



for fanfor fan --out of 1 or 2, CMOS provides smaller delay compared to out of 1 or 2, CMOS provides smaller delay compared to BiCMOSBiCMOS. However, as fan. However, as fan--out increases further, out increases further, BiCMOSBiCMOS performs performs better and better.better and better.

44

Vdd

P1

N1

N2

N3

Q1

Q2

Vout

CL

Vin

Vin

t

BiCMOS

CMOSVout

t

Q4. Design a scaled chain of inverters such that th e delay time between the logic gate (C g = 100 fF) and a load capacitance 2 pF in minimized. Find out the number of stages and stage ratio.

Ans: It may be It may be noted noted that a MOS transistor of unit length (2 λ)that a MOS transistor of unit length (2 λ) has has gate capacitance proportional to its width (W), whi chgate capacitance proportional to its width (W), whi ch may be may be multiple multiple of λ. With the increase of the width,of λ. With the increase of the width, the current drivin g the current driving capability capability is increased. is increased. But, this But, this in turn, also increases the in turn, also increases the gategate capacitance. As a consequence the delay in driving a load capacitance. As a consequence the delay in driving a load



gategate capacitance. As a consequence the delay in driving a load capacitance. As a consequence the delay in driving a load capacitance capacitance CC LL by by a transistor of gate capacitance Cg is given by the a transistor of gate capacitance Cg is given by the relationship relationship тт.C.CLL // Cg . So, delay in driving by a single stage is Cg . So, delay in driving by a single stage is 2000/100 2000/100 тт = 200 = 200 тт. With n stages, where n dependent on the stage . With n stages, where n dependent on the stage ratio, the delay is ratio, the delay is

45

min ln L

g

ct nf e

cτ τ

= =

or ln n ln

ln or n

ln

y f

y

f

=

=


Q1. How the transfer characteristic of a CMOS NAND gate is affected Q1. How the transfer characteristic of a CMOS NAND gate is affected

with increase in fanwith increase in fan--in?in?

Q2. How the transfer characteristic of a CMOS NOR g ate is affected Q2. How the transfer characteristic of a CMOS NOR g ate is affected


Q3 How switching characteristic of a CMOS NAND gate is affected Q3 How switching characteristic of a CMOS NAND gate is affected



Q4. How switching characteristic of a CMOS NOR gate is affected Q4. How switching characteristic of a CMOS NOR gate is affected


Q5. How noise margin of a CMOS NAND/NOR gate is af fected with Q5. How noise margin of a CMOS NAND/NOR gate is af fected with

increase in fanincrease in fan--in?in?

46


Q1. How the transfer characteristic of a CMOS NAND gate is affected Q1. How the transfer characteristic of a CMOS NAND gate is affected


AnsAns: Transfer characteristic does not remain symmet ric with : Transfer characteristic does not remain symmetric with

increase in fanincrease in fan--in of the NAND gate. The inversio n voltage moves in of the NAND gate. The inversion voltage moves

towards right with the increase in fantowards right with the increase in fan--in.in.

Q2. How the transfer characteristic of a CMOS NOR g ate is affected Q2. How the transfer characteristic of a CMOS NOR g ate is affected

with increase in fanwith increase in fan --in?in?



AnsAns: In case of NOR gate the transfer characteristi c also does not : In case of NOR gate the transfer characteristic a lso does not

remain symmetric and the inversion voltage moves t owards left remain symmetric and the inversion voltage moves t owards left

with the increase in fanwith the increase in fan--in.in.

47

Q3 How switching characteristic of a CMOS NAND gate is affected Q3 How switching characteristic of a CMOS NAND gate is affected


AnsAns: When the load capacitance is relatively large, the fall time : When the load capacitance is relatively large, th e fall time

increases linearly with the increase in fanincreases linearly with the increase in fan--in and the rise time is in and the rise time is

not affected much.not affected much.

Q4. How switching characteristic of a CMOS NOR gate is affected Q4. How switching characteristic of a CMOS NOR gate is affected





AnsAns: When the load capacitance is relatively large, the rise time : When the load capacitance is relatively large, th e rise time

increases linearly with the increase in fanincreases linearly with the increase in fan--in and the fall time is in and the fall time is

not affected much.not affected much. For the same area, NAND gates are superior For the same area, NAND gates are superior

to NOR gates in switching characteristics because o f higher to NOR gates in switching characteristics because o f higher

mobility of electrons compared holes.mobility of electrons compared holes. For the same d elay, NAND For the same delay, NAND

gates require smaller area than NOR gatesgates require smaller area than NOR gates

48

Q5. How noise margin of a CMOS NAND/NOR gate is af fected with Q5. How noise margin of a CMOS NAND/NOR gate is af fected with

increase in fanincrease in fan--in?in?

AnsAns: Because of the change in the inversion voltage , the noise : Because of the change in the inversion voltage, t he noise

margin is affected with the increase in fanmargin is affected with the increase in fan--in. in. For equal fanFor equal fan--in, in,

noise margin is better for NAND gates compared to N OR gates.noise margin is better for NAND gates compared to N OR gates.

We may conclude that for equal area design NAND gat es are We may conclude that for equal area design NAND gat es are

faster and better alternative to NOR gatesfaster and better alternative to NOR gates



faster and better alternative to NOR gatesfaster and better alternative to NOR gates

49


Q1. For a complex/compound CMOS logic gate, how do you realize Q1. For a complex/compound CMOS logic gate, how do you realize

the pullthe pull--up and the pullup and the pull--down networks?down networks?

Q2. Give the two possible topologies ANDQ2. Give the two possible topologies AND--OROR--INV ERT ANDINVERT AND--OROR--

INVERT (AOI) and ORINVERT (AOI) and OR--ANDAND--INVERT (OAI) to realize CMOS logic INVERT (OAI) to realize CMOS logic

gate. Explain with an example.gate. Explain with an example.

Q3. Give the AOI and OAI realizations for the sum a nd carry Q3. Give the AOI and OAI realizations for the sum a nd carry

functions of a full adder.functions of a full adder.


functions of a full adder.functions of a full adder.

Q4. How do you realize pseudo Q4. How do you realize pseudo nMOSnMOS logic circuits. Compare its logic circuits. Compare its

advantage and disadvantages with respect to standar d static advantage and disadvantages with respect to standar d static

CMOS circuits.CMOS circuits.

50


Q1. For a complex/compound CMOS logic gate, how do you realize Q1. For a complex/compound CMOS logic gate, how do you realize

the pullthe pull--up and the pullup and the pull--down networks?down networks?

�� AnsAns: A CMOS logic gate consists of a : A CMOS logic gate consists of a nMOSnMOS pullpull--down network down network

and a and a pMOSpMOS pullpull--up network. The up network. The nMOSnMOS network is connected network is connected

between the output and the ground, whereas the pullbetween the output and the ground, whereas the pull --up network up network

is connected between the output and the power suppl y.is connected between the output and the power suppl y. The The

nMOSnMOS network corresponds to the complement of the functi on network corresponds to the complement of the functi on


nMOSnMOS network corresponds to the complement of the functi on network corresponds to the complement of the functi on

either in sumeither in sum--ofof--product or productproduct or product--ofof--sum forms sum forms and and the the pMOSpMOS

network is dual of the network is dual of the nMOSnMOS networknetwork ..

51


Q2. Give the two possible topologies ANDQ2. Give the two possible topologies AND--OROR--INV ERT INVERT ANDAND--OROR--

INVERTINVERT ((AOI) and ORAOI) and OR--ANDAND--INVERT INVERT ((OAI) to realize CMOS logic OAI) to realize CMOS logic

gate. Explain with an examplegate. Explain with an example..

AnsAns: : The The ANDAND--OROR--INVERT network corresponds to the realiz ation INVERT network corresponds to the realization

of the of the nMOSnMOS network network in in sumsum--ofof--product product form. Where as the ORform. Where as the OR--

ANDAND--INVERT network corresponds to the realization of the INVERT network corresponds to the realization of th e

nMOSnMOS network in productnetwork in product --ofof --sum form. sum form. In both the cases, In both the cases, the the


nMOSnMOS network in productnetwork in product --ofof --sum form. sum form. In both the cases, In both the cases, the the

pMOSpMOS network is dual of the network is dual of the nMOSnMOS networknetwork ..

52


Q3. Give the AOI and OAI realizations for the sum a nd carry Q3. Give the AOI and OAI realizations for the sum a nd carry

functions of a full adderfunctions of a full adder..

AnsAns: AOI form of realization is: AOI form of realization is

sshown in the figure.hown in the figure. A

A

B

B

Cin

VddVdd

B

Cin

A B Cin


A AB

B

Cin

Cin

Co

Co

B

AA B

Cin

AS


Q4. How do you realize pseudo Q4. How do you realize pseudo nMOSnMOS logic circuits. Compare its logic circuits. Compare its

advantage and disadvantages with respect to standar d static advantage and disadvantages with respect to standar d static

CMOS circuitsCMOS circuits..

AnsAns: In the pseudo: In the pseudo--nMOSnMOS realization, the realization, the pMOSpMOS network of the network of the

static CMOS realization is replaced by a single static CMOS realization is replaced by a single pMO SpMOS transistor transistor

with its gate connected to GND. with its gate connected to GND. An nAn n--input pseudo input pseudo nMOSnMOS requires requires

n+1 transistors compared to 2n transistors of the c orresponding n+1 transistors compared to 2n transistors of the c orresponding


n+1 transistors compared to 2n transistors of the c orresponding n+1 transistors compared to 2n transistors of the c orresponding

static CMOS static CMOS gates.gates. This leads to substantial This leads to substantial reduction in area and reduction in area and

delay in pseudo delay in pseudo nMOSnMOS realization. realization. As the As the pMOSpMOS transistor is always transistor is always

ON, it leads to ON, it leads to static static power dissipation power dissipation when the output is LOW.when the output is LOW.

54


Q1. In what way relay logic circuits differ from pa ss transistor logic

circuits? Why the output of a pass transistor circu it is not used as a

control signal for the next stage?

Q2. What are the advantages and limitations of pass transistor logic

circuits? How the limitations are overcome?

Q3. Why is it necessary to insert a buffer after no t more than four

pass transistors in cascade?



Q4. Why is it necessary to have swing restoration l ogic in pass

transistor logic circuits? Explain its operation.

Q5. What is the ‘sneak path’ problem of pass transi stor logic

circuits? How sneak path is avoided in Universal Lo gic Module

(ULM) based realization of pass transistor network. Illustrate with

an example.

55


Q1. In what way relay logic circuits differ from pa ss transistor logic

circuits? Why the output of a pass transistor circu it is not used as a

control signal for the next stage?

Ans: Logic functions can be realized using pass tra nsistors in a

manner similar to relay contact networks. However, there are some

basic differences as mentioned below:

(a) In relay logic, output is considered to be ‘1’ when there is some


(a) In relay logic, output is considered to be ‘1’ when there is some

voltage passing through the relay logic. Absence of voltage is

considered to be ‘0’. On the other hand, is case of pass

transistor logic it it is essential to provide both charging and is essential to provide both charging and

discharging path for the discharging path for the output load capacitance. output load capacitance.

(b)(b) There is no voltage drop in the relay logic, but there is some There is no voltage drop in the relay logic, but th ere is some

voltage drop across the pass transistor network.voltage drop across the pass transistor network.

(c)(c) Pass transistor logic is faster than relay lo gic.Pass transistor logic is faster than relay logic.56

Q2. What are the advantages and limitations of pass transistor logic

circuits? How the limitations are overcome?

Ans: Pass transistor realization is Pass transistor realization is ratiolessratioless, i.e. there is no need to , i.e. there is no need to

have L:W ration in the realization. All the transis tors can be of have L:W ration in the realization. All the transis tors can be of

minimum dimension. Lower minimum dimension. Lower area due to smaller number of area due to smaller number of

transistors in pass transistor realization compared to static CMOS transistors in pass transistor realization compared to static CMOS

realization. Pass transistor realization also has l esser realization. Pass transistor realization also has l esser power power



realization. Pass transistor realization also has l esser realization. Pass transistor realization also has l esser power power

dissipation because there is no dissipation because there is no static power and sh ortstatic power and short--circuit power circuit power

dissipation in pass transistor circuits. The limita tions aredissipation in pass transistor circuits. The limita tions are (a) Higher (a) Higher

delay in long chain of pass delay in long chain of pass transistors (b) Multitransistors (b) Multi--thresholdthreshold Voltage Voltage

drop (drop (VoutVout = = VddVdd –– VtnVtn) (c) Complementary ) (c) Complementary control control signals and (d) signals and (d)

Possibility of sneak path because of the presence o f path to Possibility of sneak path because of the presence o f path to VddVdd and and

GND.GND.

57

Q3. Why is it necessary to insert a buffer after no t more than four


AnsAns: : When a signal is steered through several sta ges of pass When a signal is steered through several stages of pass

transistors, the delay can be transistors, the delay can be considerable. For n s tages of pass considerable. For n stages of pass

transistors, the delay is given by the relationship .transistors, the delay is given by the relationship .


( )2

1+= nnCReqτ


To overcome the problem of long delay, buffers shou ld be inserted To overcome the problem of long delay, buffers shou ld be inserted

after every three or four pass transistor after every three or four pass transistor stages.stages.

58

Q4. Why is it necessary to have swing restoration l ogic in pass

transistor logic circuits? Explain its operation.

Ans: In order to avoid the voltage drop at the outp ut (In order to avoid the voltage drop at the output (V outVout = = VddVdd ––

VtnVtn) , it is necessary to use additional hardware k nown swing ) , it is necessary to use additional hardware know n swing

restoration logic at the gate outputrestoration logic at the gate output. At the output of the swing . At the output of the swing

restoration logic there is rail to rail voltage swi ng. The swing restoration logic there is rail to rail voltage swi ng. The swing

restoration can be done using a restoration can be done using a pMOSpMOS transistor with its gate transistor with its gate



restoration can be done using a restoration can be done using a pMOSpMOS transistor with its gate transistor with its gate

connected to GND. connected to GND.

59

Q5. What is the ‘sneak path’ problem of pass transi stor logic

circuits? How sneak path is avoided in Universal Lo gic Module

(ULM) based realization of pass transistor network. Illustrate with

an example.

AnsAns: As shown in the figure, the output : As shown in the figure, the output

iis connected to both ‘1’ (s connected to both ‘1’ (VddVdd) and ‘0’ ) and ‘0’


CB

f


(GND). The output attains some intermediate (GND). The output attains some intermediate

Value between Value between VddVdd and GND. The MUX basedand GND. The MUX based

rrealization allows connection of the output toealization allows connection of the output to

oonly one input, which can be either 0 or 1. nly one input, which can be either 0 or 1.

Multiplexer realization of

Is shown in the figure.

60

1 0

A D

babaf ′+′=

0

0

Vdd

Vdd

a′

b′

ba′

b′

a

ba

V0

Review Questions LecReview Questions Lec--1313

Q1. What is Shanon’s Expansion Theorem? How can be u sed realize

pass transistor circuit for a given Boolean functio n?

Q2. Obtain an ROBDD for the Boolean function F = Obtain an ROBDD for the Boolean function F = ∑∑(3, 7, 9, 11, 12, 13, (3, 7, 9, 11, 12, 13,

14,15). Realize the function using a CPL circuit. 14,15). Realize the function using a CPL circuit.

Q3. Compare the area, in terms of the number of tra nsistors, for the

three different implementations of a full adder usi ng (i) static CMOS,

(ii) domino CMOS, and (iii) complementary pass tran sistor logic


(ii) domino CMOS, and (iii) complementary pass tran sistor logic

(CPL).

61


Q1. What is Shanon’s Expansion Theorem? How can be u sed realize

pass transistor circuit for a given Boolean functio n?

Ans: According to According to Shanon’sShanon’s expansion theorem, a Boolean function expansion theorem, a Boolean function

can be expanded around a variable xcan be expanded around a variable x i i to represent the function as to represent the function as

f = f = xx ii ff xxii + + xx ii ’f’f xi’ ,xi’ , where where ff xxii and and ff xixi’ ’ are the positive and negative are the positive and negative

cofactors of f, respectively.cofactors of f, respectively. A positive Shannon cof actor of A positive Shannon cofactor of

function f with respect to variable xfunction f with respect to variable x is defined as that function is defined as that function


function f with respect to variable xfunction f with respect to variable x ii is defined as that function is defined as that function

with all instances of xwith all instances of x i i replaced by 1. A negative Shannon replaced by 1. A negative Shannon

cofactor is the same, but replaces all instances of xcofactor is the same, but replaces all instances of x i i by 0.by 0.

This is illustrated by the following example:This is illustrated by the following example:

62

0

cb′′′′

a

a′′′′b

1

f( )cbbaaf .0.1. ′+′+=

Q2. Obtain an ROBDD for the Boolean function F = Q2. Obtain an ROBDD for the Boolean function F = ∑∑∑∑∑∑∑∑(3, 7, 9, 11, 12, (3, 7, 9, 11, 12,

13, 14,15). Realize the function using a CPL circui t. 13, 14,15). Realize the function using a CPL circui t.

a

b b

a

b b



Step1 Step 210

b

c

b

c c c

d d d d d d d d

10

c c c

d d d d

AnsAns 2:2:

a

b

c

b

c c

a

b

c



Step 3 Step 4

10

c c c

d

10

c

d

Passtransistor

logic

Vdd

VO’


Ans 2:Ans 2:


logic

Passtransistor

logic

Vdd

O

b’

b

c

c’

Vdd

F’

1

d

0

d

a’

a


Ans 2:Ans 2:


V dd

F

0

b’

b

c

c’

0

d'

1

d'

a’

a

Q3. Compare the area, in terms of the number of tra nsistors, for the

three different implementations of a full adder usi ng (i) static

CMOS, (ii) domino CMOS, and (iii) complementary pas s

transistor logic (CPL).

Ans: The full adder block diagram is given below:



FULLADDER

S

Co

A

B

Cin

The full adder The full adder

Realization using Realization using

Static CMOS is Static CMOS is

A

A

B

B

Cin

Co

VddVdd

A

B

Cin

A B Cin

S



Static CMOS is Static CMOS is

given here.given here.

It requires 28 It requires 28


68

A AB

B

Cin

Cin

Co

B

AA B

Cin

The realization using The realization using

NORA dynamic CMOSNORA dynamic CMOS

requires 20 transistors.requires 20 transistors.


clk

B

Cin

A B Cin

Coclk


S

clk

Co

A

B

clk

B

AA B

Cin

S

The pass transistor realization of the full adder i s given below. It The pass transistor realization of the full adder i s given below. It

requires 16 (8+8) transistors.requires 16 (8+8) transistors.


C

Co

C CC

S


Cin Cin

AAAA

0 1

CinCin

A

B B B B

AA A

BB


Q1. What are the key characteristics of MOS dynamic circuits?Q1. What are the key characteristics of MOS dynamic circuits?

Q2. Explain the basic operation of a 2Q2. Explain the basic operation of a 2--phase dynam ic circuit?phase dynamic circuit?

Q3. Q3. How 2-phase clocks can be generated using inver ters?

Q4. What makes dynamic CMOS circuits faster than st atic CMOS

circuits?

Q5. Compare the sources of power dissipation betwee n static CMOS


Q5. Compare the sources of power dissipation betwee n static CMOS

and dynamic CMOS circuits?

71


Q1. What are the key characteristics of MOS dynamic circuits?Q1. What are the key characteristics of MOS dynamic circuits?

AnsAns: : The advantage of low power of static CMOS ci rcuits and The advantage of low power of static CMOS circuits and

smaller chip area of smaller chip area of nMOSnMOS circuits are combined in dynamic circuits are combined in dynamic

circuits leading to circuits of smaller area and lo wer power circuits leading to circuits of smaller area and lo wer power

dissipation. Smaller area due to lesser number of t ransistors (n+2) dissipation. Smaller area due to lesser number of t ransistors (n+2)

compared to static CMOS realization requiring 2n tr ansistors to compared to static CMOS realization requiring 2n tr ansistors to

realize a nrealize a n --variable function. Dynamic CMOS circuits have Lowe r variable function. Dynamic CMOS circuits have Lowe r


realize a nrealize a n --variable function. Dynamic CMOS circuits have Lowe r variable function. Dynamic CMOS circuits have Lowe r

static power static power dissipation because of smaller capacit ance. There is dissipation because of smaller capacitance. There i s

no no short circuit power dissipation short circuit power dissipation and no and no glitchingglitching power power

dissipation. Dynamic CMOS circuits are also faster because the dissipation. Dynamic CMOS circuits are also faster because the

capacitance is about half that of the static CMOS circuits.capacitance is about half that of the static CMOS circuits.

72

Q2. Explain the basic operation of a 2Q2. Explain the basic operation of a 2--phase dynam ic circuit?phase dynamic circuit?

AnsAns: The operation of the circuit can be explained using : The operation of the circuit can be explained usi ng prechargeprecharge

logic in which the output is logic in which the output is prechargedprecharged to HIGH level during to HIGH level during φφφφφφφφ2 2

clock and the clock and the output is evaluated during output is evaluated during φφφφφφφφ1 clock1 clock..

Q3Q3. . How 2-phase clocks can be generated using i nverters?

Ans: As shown below, two phase clock can generated using



inverters. The timing diagram is given in the next slide.

73

Clk

φ2

φ1

Timing diagram of the two-phase clock generated fro m a single-phase clock.

Clk

Answer to Questions of Answer to Questions of LecLec--1414


.φ1

φ2

5 3 4 3

Q4. What makes dynamic CMOS circuits faster than st atic CMOS

circuits?

Ans: As MOS dynamic circuits require lesser number of transistors

and lesser capacitance is to be driven by it. This makes MOS

dynamic circuits faster.

Q5. Compare the sources of power dissipation betwee n static

CMOS and dynamic CMOS circuits?



CMOS and dynamic CMOS circuits?

Ans: In both the cases there is switching power and leakage power

dissipations. However, the short circuit and glitch ing power

dissipations, which are present in static CMOS circ uits, are not

present in dynamic CMOS circuits.

75


Q1. What is charge leakage problem of dynamic CMOS circuits? Q1. What is charge leakage problem of dynamic CMOS circuits?

How is it overcome?How is it overcome?

Q2. What is charge sharing problem? How can it be o vercome?Q2. What is charge sharing problem? How can it be o vercome?

Q3. Explain the clock skew problem of dynamic CMOS circuits?Q3. Explain the clock skew problem of dynamic CMOS circuits?

Q4. How clock skew problem is overcome in in domino CMOS Q4. How clock skew problem is overcome in in domino CMOS

circuits?circuits?


Q5. How clock skew problem is overcome in in NORA C MOS Q5. How clock skew problem is overcome in in NORA C MOS

circuits?circuits?

76

Q1. What is charge leakage problem of dynamic CMOS circuits? Q1. What is charge leakage problem of dynamic CMOS circuits?

How is it overcome?How is it overcome?

AnsAns: The source: The source--drain diffusions form parasitic diode s with the drain diffusions form parasitic diodes with the

substrate. There is reverse bias leakage current .T he current is substrate. There is reverse bias leakage current .T he current is

in the range 0.1nA to 0.5nA per device at room temp erature and in the range 0.1nA to 0.5nA per device at room temp erature and

the current doubles for every 10the current doubles for every 10 °°C increase in temperature . This C increase in temperature . This



the current doubles for every 10the current doubles for every 10 °°C increase in temperature . This C increase in temperature . This

leads to slow but steady discharge of the charge on the leads to slow but steady discharge of the charge on the

capacitor, which represent information. This needs to be capacitor, which represent information. This needs to be

compensated by refreshing the charge at regular int erval.compensated by refreshing the charge at regular int erval.

77

Before the switches are closed, the charge on C L is given by QA = V dd CL and charges at node B and C are

CLS1

C1

S2C2

A

B C

Vdd

1

A

C1B

CL

1

Clk


Q2. What is charge sharing problem of dynamic CMOS circuits?

Ans: The charge sharing problem is illustrated in the following diagram


charges at node B and C are QB = 0 and QC = 0

After the switches are closed, there will be redist ribution of charges based of charge conservation principle, and the voltage V A at node A is given by VA, which is less than Vdd.

( ) .21 ALddL VCCCVC ++=dd

L

LA V

CCC

CV

)( 21 ++=

2

0

Clk=1

1

C2C

1


Q3. Explain the clock skew problem of dynamic CMOS circuits?Q3. Explain the clock skew problem of dynamic CMOS circuits?

AnsAns: Clock skew problem arises because of delay du e to : Clock skew problem arises because of delay due t o

resistance and parasitic capacitances associated wi th the wire that resistance and parasitic capacitances associated wi th the wire that

carry the clock pulse and this delay is approximate ly proportional carry the clock pulse and this delay is approximate ly proportional

to the square of the length of the wire. When the c lock signal to the square of the length of the wire. When the c lock signal

reaches a later stage before its preceding stage, t he reaches a later stage before its preceding stage, t he prechargeprecharge

phase of the preceding stage overlaps with the eval uation phase of phase of the preceding stage overlaps with the eval uation phase of


phase of the preceding stage overlaps with the eval uation phase of phase of the preceding stage overlaps with the eval uation phase of

the later stage, which may lead to premature discha rge of the load the later stage, which may lead to premature discha rge of the load

capacitor and incorrect output during evaluation ph ase. capacitor and incorrect output during evaluation ph ase.

79

AnsAns: In domino CMOS circuits the : In domino CMOS circuits the problem is overcome by adding an problem is overcome by adding an inverter as shown in the diagram. It inverter as shown in the diagram. It consists of two distinct components: consists of two distinct components: The first component is a conventional The first component is a conventional dynamic CMOS gate and the second dynamic CMOS gate and the second

N-block

Clk

To next

Vdd

Answer to Questions of LecAnswer to Questions of Lec--1515Q4. How clock skew problem is overcome in in domino CMOS circuits?


dynamic CMOS gate and the second dynamic CMOS gate and the second component is a static inverting CMOS component is a static inverting CMOS buffer . During buffer . During prechargeprecharge phase, the phase, the output of the dynamic gate is high, but output of the dynamic gate is high, but the output of the inverter is LOW. As the output of the inverter is LOW. As a consequence it cannot drive an a consequence it cannot drive an nMOSnMOS transistor ON. So, the clock transistor ON. So, the clock skew problem is overcome.skew problem is overcome.

N-block

Clk

To nextstage

n- p-

clk′′′′clk clk

n-

Ans: The problem can be overcome using NORA logic, nMOS and pMOS transistor networks are alternatively used. The output of an nMOS block is HIGH during precharge,

Q5. How clock skew problem is overcome in in NORA C MOS circuits?



n-block

p-block

′′′′clkclk clk

n-block

HIGH during precharge, which cannot turn a pMOS transistor ON. Similarly, the output of an pMOS block is LOW during precharge, which cannot turn a nMOS transistor ON.

Review Questions of LecReview Questions of Lec--1616Q1. Distinguish between Mealy and Moore machines.Q1. Distinguish between Mealy and Moore machines.

Q2. A sequence detector produces a ’1’ for each occ urrence of the Q2. A sequence detector produces a ’1’ for each occ urrence of the

input sequence ‘1001’ at its input.input sequence ‘1001’ at its input.

(a) Draw the state(a) Draw the state--transition diagram of the FSM r ealizing the transition diagram of the FSM realizing the

sequence detector.sequence detector.

(b) Obtain state table from the state transition di agram.(b) Obtain state table from the state transition di agram.


(c) Realize the FSM using D FFs and a PLA. (c) Realize the FSM using D FFs and a PLA.

Q3. How can you realize a set of Boolean functions using a ROM. Q3. How can you realize a set of Boolean functions using a ROM.

Q4. How the limitations of a ROMQ4. How the limitations of a ROM--based realization is overcome in a based realization is overcome in a

PLAPLA--based realization.based realization.

82

Q1. Distinguish between Mealy Q1. Distinguish between Mealy

and Moore machines.and Moore machines.

AnsAns: In a Mealy machine the : In a Mealy machine the

outputs are dependent on the outputs are dependent on the

inputs and present state. The inputs and present state. The

Output transition function is

represented by Z = λλλλ(S,X).CLK

PI POCombinational logicto compute outputs

and next states

Latches

NSPS



represented by Z = λλλλ(S,X).

Where as in a Moore machine Moore machine

the outputs are dependent the outputs are dependent

only on present state. The only on present state. The

output transition function is

represented by Z = λλλλ(S)

CLK

CLK

PI

POCombinational logicto compute outputs

Combinational logic tocompute next states

Latches

NS

PS

Q2. A sequence detector produces a ’1’ Q2. A sequence detector produces a ’1’ for each for each

occurrence of the input sequence ‘1001’ at its inpu t.occurrence of the input sequence ‘1001’ at its inpu t.

(a) Draw the state(a) Draw the state--transition diagram of the FSM transition diagram of the FSM

realizing the sequence detector.realizing the sequence detector.




(c) Realize the FSM using D FFs and a PLA. (c) Realize the FSM using D FFs and a PLA.

s1 s2 s3 s4

1/0 0/00/0

0/0

1/1

0/0

1/01/0

Ans: 2(a)

AnsAns: 2(b) The state : 2(b) The state

table from the table from the

state transition state transition

diagram is given diagram is given

below:below:

s1 s2 s3 s4

1/0 0/00/0

0/0

1/1

0/0

1/01/0



Y2Y1, zPS y2y1 x =0 X = 1S1 0 0 00,0 01,0S2 01 10,0 01,0S3 1 0 11,0 01,0S4 1 1 00,0 01,1

0/0

AnsAns: 2(c) : 2(c)

Realization of Realization of

the FSM using the FSM using

D FFs and a D FFs and a

PLA is shown PLA is shown

in the diagram. in the diagram.



Y2 = x’(y2y1’ + y2’y1)Y1 = x + x’y2y1’z = xy2y1

xy1 y2

Y2 Y1 z

CLK

DQ

DQ

y3

y2

y1

Y3

Y2

Y1

PI PO

NSPS

ROMx z

DQ

DQ

DQ

Q3. How can you realize a set of Boolean functions using a ROM?Ans: ROMs can be used to realize a set of Boolean functions as show In the diagram. Encoder part of the ROM is realized according to the functions.

ENCODER



CLK

DQ

y3

DECODERENCODER

z

y2

y1

x

Y1Y2 Y3

Q4. How the limitations of a ROMQ4. How the limitations of a ROM--based realization is overcome in a based realization is overcome in a

PLAPLA--based realizationbased realization..

AnsAns: In a ROM, the encoder part is only programmabl e and use : In a ROM, the encoder part is only programmable a nd use of of

ROMs to realize Boolean functions is wasteful in ma ny ROMs to realize Boolean functions is wasteful in ma ny

situations because there is no crosssituations because there is no cross--connect for a significant connect for a significant

part . This wastage can be overcome by using Progra mmable part . This wastage can be overcome by using Progra mmable

Logic array (PLA), which requires much lesser chip area.Logic array (PLA), which requires much lesser chip area.



Logic array (PLA), which requires much lesser chip area.Logic array (PLA), which requires much lesser chip area.

88


Q1. Sketch the schematic diagram of a SRAM memory c ell along Q1. Sketch the schematic diagram of a SRAM memory c ell along

with sense amplifier and data write circuitry. with sense amplifier and data write circuitry.

Q2. Explain how read and write operations are perfo rmed in a Q2. Explain how read and write operations are perfo rmed in a

SRAM. SRAM.

Q3. In what way the DRAMs differ from SRAMs?Q3. In what way the DRAMs differ from SRAMs?

Q4. Explain the read and write operations for a oneQ4. Explain the read and write operations for a one --transistor transistor


DRAM cell.DRAM cell.

89

Q1. Sketch the schematic Q1. Sketch the schematic diagram of a SRAM memory diagram of a SRAM memory cell along with sense cell along with sense amplifier and data write amplifier and data write circuitry. circuitry.

Answer to Questions of LecAnswer to Questions of Lec--1717Answer to Questions of LecAnswer to Questions of Lec--1717

VssVssVssVss

T1T1T1T1 T2T2T2T2

T3T3T3T3 T4T4T4T4

T5T5T5T5 T6T6T6T6

VddVddVddVdd

VddVddVddVddBit line CBit line CBit line CBit line C Bit line C'Bit line C'Bit line C'Bit line C'


AnsAns: The schematic diagram of : The schematic diagram of a SRAM memory along with a SRAM memory along with the sense amplifier and data the sense amplifier and data

write circuitrywrite circuitry

VssVssVssVss

VssVssVssVss

Cross-coupledCross-coupledCross-coupledCross-coupled

sense amplifiersense amplifiersense amplifiersense amplifier

CLKCLKCLKCLK

WBWBWBWB WB'WB'WB'WB'

ColumnColumnColumnColumn

selectselectselectselect

Row selectRow selectRow selectRow select Word lineWord lineWord lineWord line

Q2. Explain Q2. Explain how read and write operations are perfo rmed.how read and write operations are performed.

AnsAns: Steps of READ operation: : Steps of READ operation:

1.1. PrechargePrecharge and equalization circuit is activated to and equalization circuit is activated to prechargeprecharge the the bus lines to bus lines to VddVdd/2 /2

2.2. The word line is activated connecting the cell to B and B’ lines. The word line is activated connecting the cell to B and B’ lines. As a consequence, a voltage is developed between B and B’.As a consequence, a voltage is developed between B and B’.



3.3. Once adequate voltage is developed between B an d B’, the Once adequate voltage is developed between B and B’ , the sense amplifier amplifies the signals to rail to ra il using sense amplifier amplifies the signals to rail to ra il using regenerative action. The output is then directed to the chip I/O regenerative action. The output is then directed to the chip I/O pin by the column decoder.pin by the column decoder.

Steps of write operation:Steps of write operation:

1. The data available on the chip I/O pin re direct ed to the B and B’ 1. The data available on the chip I/O pin re direct ed to the B and B’ lines. By activating the word line signal, the data is transferred lines. By activating the word line signal, the data is transferred to the memory cellto the memory cell

Q3. In what way the DRAMs differ from SRAMs?Q3. In what way the DRAMs differ from SRAMs?

AnsAns: Both SRAMS and DRAMs are volatile in nature, i .e. : Both SRAMS and DRAMs are volatile in nature, i.e.

information is lost if power line is removed. Howev er, SRAMs information is lost if power line is removed. Howev er, SRAMs

provide high provide high switching switching speed, good speed, good noise noise margin but require margin but require

larger larger chip chip area than DRAMs.area than DRAMs.

Q4. Explain the read and write operations for a oneQ4. Explain the read and write operations for a one --transistor transistor





AnsAns: : A significant improvement in the DRAM evolut ion was to A significant improvement in the DRAM evolution was to

realize 1realize 1--T T DRAM DRAM cell. One cell. One additional capacitor is explicitly additional capacitor is explicitly

fabricated for storage fabricated for storage purpose. To purpose. To store ‘1’, it is charged to store ‘1’, it is charged to VddVdd--

VtVt and to store ‘0’ it is discharged to and to store ‘0’ it is discharged to 0V. Read 0V. Read operation is operation is

destructive. Sense destructive. Sense amplifier is needed for amplifier is needed for reading. Read reading. Read

operation is followed by restoration operation is followed by restoration operation.operation.

92

Review Questions Review Questions of Lecof Lec--1818

Q1. Q1. How charge sharing leads to power dissipation?How charge sharing leads to power dissipation?

Q2. Q2. What is short circuit power dissipation? On wha t parameters What is short circuit power dissipation? On what pa rameters

does it depend?does it depend?

Q3. Q3. Justify the statement; “there is no short circu it power Justify the statement; “there is no short circuit p ower

dissipation in a static CMOS circuit if dissipation in a static CMOS circuit if VddVdd < (< (VtnVtn + !+ !VtpVtp!)”!)”

Q4. What is Q4. What is glitchingglitching power dissipation? How can it be minimized ? power dissipation? How can it be minimized?


Q1. How charge sharing leads to power Q1. How charge sharing leads to power

dissipation?dissipation?

AnsAns: : In case of dynamic gates, power In case of dynamic gates, power

dissipation takes place due to the dissipation takes place due to the

phenomenon of charge sharing phenomenon of charge sharing

even when the output is not 0 at the even when the output is not 0 at the

time evaluation. At the time of time evaluation. At the time of

B=1

A=1

C=0

C1

C2

CL



time evaluation. At the time of time evaluation. At the time of

prechargeprecharge, the output is charged to , the output is charged to

VddVdd, but at the time of evaluation, , but at the time of evaluation,

the output decreases because of the the output decreases because of the

of the sharing of charge by the two of the sharing of charge by the two

capacitors C1 and C2. In the next capacitors C1 and C2. In the next

prechargeprecharge phase a power phase a power

dissipation equal to P takes place.dissipation equal to P takes place.

Clk

After charge sharing, the new voltage level After charge sharing, the new voltage level is is V newVnew. Because of the . Because of the

conservation of charge, we get conservation of charge, we get

CCC

VCV ddL

new ++=

LddnewL CVVCCC =++ ).( 21



321 CCCnew ++

ddL

Ldd V

CCC

CVV .

21 ++−=∆

ddL

VCCC

CC.

21

21

+++

2

21

21

)(

).(.. dd

L

LddL V

CCC

CCCVVCP

+++

=∆=


Q2. What is short circuit power dissipation? On wha t parameters Q2. What is short circuit power dissipation? On wha t parameters

does does iit depend?t depend?

AnsAns: : As input changes slowly, power dissipation takes pl ace even As input changes slowly, power dissipation takes pl ace even

when there is no load or parasitic capacitor. when there is no load or parasitic capacitor. When the input is When the input is

greater than greater than VtnVtn and less than (and less than (VddVdd –– VtpVtp), both the ), both the nMOSnMOS and and

pMOSpMOS transistors are ON. The supply voltage is now s horted to transistors are ON. The supply voltage is now short ed to

GND through the two transistors. This leads to the short GND through the two transistors. This leads to the short circuit circuit


GND through the two transistors. This leads to the short GND through the two transistors. This leads to the short circuit circuit

power dissipation.power dissipation.

96

Q3. Justify the statement; “there is no short circu it power Q3. Justify the statement; “there is no short circu it power

dissipation in a static CMOS circuit if dissipation in a static CMOS circuit if VddVdd < (< (VtnVtn + !+ !VtpVtp!)”.!)”.

AnsAns: When : When VddVdd < (< (VtnVtn + !+ !VtpVtp!), only one !), only one thansistorthansistor can turn on at a can turn on at a

time. Since time. Since bothebothe transistors cannot turn on simultaneously, transistors cannot turn on simultaneously,

there is no short circuit power dissipation.there is no short circuit power dissipation.

Q4. What is Q4. What is glitchingglitching power dissipation? How can it be minimizedpower dissipation? How can it be minimized??



AnsAns: Because of finite delay of the gates used to r ealize Boolean : Because of finite delay of the gates used to real ize Boolean

functions, different signals cannot reach the input s of a gate functions, different signals cannot reach the input s of a gate

simultaneously. This leads to spurious transitions at the output simultaneously. This leads to spurious transitions at the output

before it settles down to its final value. The spur ious transitions before it settles down to its final value. The spur ious transitions

leads to charging and discharging of the outputs ca using leads to charging and discharging of the outputs ca using

glitchingglitching power dissipation. It can be minimized by having power dissipation. It can be minimized by having

balanced realization having same delay at the input s. balanced realization having same delay at the input s.

97


Q1. List various sources of leakage currents. .

Q2. Why leakage power is an important issue in deep submicron Q2. Why leakage power is an important issue in deep submicron technology?technology?

Q3. What is band-to-band tunneling current?

Q4. What is body effect?

Q5. What is subthreshold leakage current? Briefly di scuss various mechanisms responsible for this leakage current?



Q1. List various sources of leakage currents. . AnsAns: Various sources of leakage currents are listed : Various sources of leakage currents are listed below:below:

•• II11= Reverse= Reverse--bias pbias p--n junction diode leakage current n junction diode leakage current

•• II22 == BandBand--toto--band tunneling current band tunneling current

•• II == SubthresholdSubthreshold leakage current leakage current


•• II3 3 == SubthresholdSubthreshold leakage current leakage current

•• II44 = Gate Oxide tunneling current= Gate Oxide tunneling current

•• II55 == Gate current due to hotGate current due to hot--carrier injectioncarrier injection

•• II6 6 == Channel punchChannel punch--through through

•• II77 == Gate induced drainGate induced drain--leakage current leakage current

99

Q2. Why leakage power is an important issue in deep submicron technology?Ans: In deep submicron technology, the leakage comp onent is a significant %

of total power as shown in the diagram. Moreover, t he leakage current is increasing at a faster rate than dynamic power. As a consequence, it has become an important issue in DSM.

10

10

10

0

1

2

Active Power



10

10

10

10

10

10

10

-6

-5

-4

-3

-2

-1

Pow

er (

W)

1.0 0.8 0.6 0.5 0.35 0.25 0.18

Technology Generation (µm)

Stand by Power

Q3. What is band-to-band tunneling current?

Ans: When both n regions and p regions are heavily doped, a When both n regions and p regions are heavily doped , a high electric field across a reverse biased phigh electric field across a reverse biased p--n ju nction causes n junction causes significant current to flow through the junction du e to tunneling significant current to flow through the junction du e to tunneling of electrons from the valence bond of the pof electrons from the valence bond of the p--region to the region to the conduction band of nconduction band of n--region. This is known as bandregion. This is known as band--toto--band band tunneling.tunneling.





AnsAns: As a negative voltage is applied to the substr ate with : As a negative voltage is applied to the substrate with respect to the source, the wellrespect to the source, the well--toto--source junct ion the device is source junction the device is reverse biased and bulk depletion region is widened . This leads reverse biased and bulk depletion region is widened . This leads to increase the threshold voltage. This effect is k nown as body to increase the threshold voltage. This effect is k nown as body effect. effect.

101

Q5. What is subthreshold leakage current? Briefly di scuss various mechanisms responsible for this leakage cur rent?

AnsAns: The : The subthresholdsubthreshold leakage current in CMOS circuits is due to leakage current in CMOS circuits is due to

carrier diffusion between the source and the drain regions of the carrier diffusion between the source and the drain regions of the

transistor in weak inversion, when the gate voltage is below Vtransistor in weak inversion, when the gate voltage is below V tt. .

The behavior of an MOS transistor in the The behavior of an MOS transistor in the subthresholdsubthreshold operating operating



The behavior of an MOS transistor in the The behavior of an MOS transistor in the subthresholdsubthreshold operating operating

region is similar to a bipolar device, and the region is similar to a bipolar device, and the subt hresholdsubthreshold

current exhibits an exponential dependence on the g ate voltage. current exhibits an exponential dependence on the g ate voltage.

The amount of the The amount of the subthresholdsubthreshold current may become significant current may become significant

when the gatewhen the gate--toto--source voltage is smaller than , but very close source voltage is smaller than, but very close

to the threshold voltage of the device. to the threshold voltage of the device.

102


Q1. Explain the basic concepts of supply voltage scaling.

Q2. As you move to a new process technology with a scaling fact or S = 1.4,how the drain current, power density, delay and energy requi rementchanges for the constant field scaling?

Q3. Distinguish between constant field and constant voltag e feature sizescaling? Compare their advantages and disadvantages.

Q4. Compare the constant field and constant voltage scaling approaches in


Q4. Compare the constant field and constant voltage scaling approaches interms of area, delay, energy and power density parameters.

Q5. Explain how parallelism can be used to achieve low power instead ofhigh performance in realizing digital circuits.

Q6.Explain how multicore architecture provides low power c ompared to thesingle core architecture of the same performance.

Q1. Explain the basic concepts of supply voltage scaling.Ans: Power dissipation is proportional the square of the sup ply voltage. So,a factor of two reduction in supply voltage yields a factor of four decrease inenergy. But, as the supply voltage is reduced, delay increas es as shown inthe diagram. So, the challenge is to scale down the supply vol tage withoutcompromise in performance.

1.0 1.0



0 1 2 3 4 5 0 1 2 3 4 50.0

0.2

0.0

0.2

0.4 0.4

0.6

0.8 0.8

0.6

1.0

Nor

mal

ized

Ene

rgy

Nor

mal

ized

Del

ay

VddVdd

Q2. As you move to a new process technology with a scaling factor Q2. As you move to a new process technology with a scaling factor S = 1.4, how the drain current, power dissipation, power density, S = 1.4, how the drain current, power dissipation, power density, delay and energy requirement changes for the consta nt field delay and energy requirement changes for the consta nt field scaling?scaling?AnsAns: : Drain current reduces by a factor of S. Alth ough power Drain current reduces by a factor of S. Although po wer dissipation decreases by a factor of Sdissipation decreases by a factor of S 22 , the power density remains , the power density remains the same. The delay decreases by a factor of S and the energy the same. The delay decreases by a factor of S and the energy decreases by a factor of Sdecreases by a factor of S 3 .3 .



Q3. Distinguish between constant field and constant voltage Q3. Distinguish between constant field and constant voltage

feature size scaling? Compare their advantages and feature size scaling? Compare their advantages and

disadvantages.disadvantages.

AnsAns: In this approach the magnitude of all the inte rnal electric fields : In this approach the magnitude of all the interna l electric fields

within the device are preserved, while the dimensio ns are scaled within the device are preserved, while the dimensio ns are scaled

down by a factor of S. This requires that all poten tials must be down by a factor of S. This requires that all poten tials must be

scaled down by the same factor. Accordingly, supply as well as scaled down by the same factor. Accordingly, supply as well as



scaled down by the same factor. Accordingly, supply as well as scaled down by the same factor. Accordingly, supply as well as

threshold voltages are scaled down proportionately. But, in threshold voltages are scaled down proportionately. But, in

constantconstant--voltage scaling, all the device dimension s are scaled voltage scaling, all the device dimensions are scal ed

down by a factor of S just like constantdown by a factor of S just like constant--voltage s caling, supply voltage scaling, supply

voltage and threshold voltages are not scaled. voltage and threshold voltages are not scaled.

106

QQ44.. CompareCompare thethe constantconstant fieldfield andand constantconstant voltagevoltage scalingscaling

approachesapproaches inin termsterms ofof area,area, delay,delay, energyenergy andand powerpower densitydensity

parametersparameters..

Quality Cons field Scaling Constant Voltage Scaling

Gate Capacitance /g gC C S′ = /g gC C S′ =



Gate Capacitance

Drain Current

Power Dissipation

Power Density

Delay

Energy

/g gC C S′ =

SII DD /=′2/ SPP =′

/ ( / )P Area P Area′ ′ =' /d dt t S=

2 3 3

. 1' d dt P tP

E ES S S S

= × = =

/g gC C S′ =

SII DD .=′

SPP .=′3/ /P Area S P Area′ ′ =

' 2/d dt t S=

SEE /'=

Q5. Explain how parallelism can be used to achieve low power

instead of high performance in realizing digital ci rcuits.

Ans: Traditionally, parallelism is used to improve performance at

the expense of larger power dissipation. But, inste ad of trying to

improve performance, the power dissipation can be r educed by

scaling down the supply voltage such that the perfo rmance

remains unaltered.



remains unaltered.

108

Q6.Explain how multicore architecture provides low power c ompared to thesingle core architecture of the same performance.

Ans: The idea behind the parallelism for low-power can be ext ended tomulti-core architecture. The clock frequency can be reduce d withcommensurate scaling of the supply voltage as the number of c ores isincreased from one to more than one while maintaining the sam ethroughput.


Q1. In what situation pipelining can be implemented ?

Q2. Explain how pipelining can be used to achieve l ow power instead

of high performance in realizing digital circuits.

Q3. How clock frequency, speed up, throughput and p ower

dissipation changes for a pipelined implementation with k stages with

respect to non -pipelined implementation?


respect to non -pipelined implementation?

Q4. How can you combine sizing and supply voltage s caling to realize

low power circuits?

Q5. Explain with an example how pipelining and par allelism can be

combined to realize low power circuits?to realize low power circuits?

109


Q1. In what situation pipelining can be implemented ?

Ans: A task can be pipelined when it can be divided into more than

one independent subtasks, which can be executed in a overlapped

manner.

Q2. Explain how pipelining can be used to achieve l ow power instead

of high performance in realizing digital circuits.


Ans: In a conventional pipelined implementation, th e subtasks are

executed in a overlapped manner at a faster rate. I nstead of that, the

subtasks can be executed at the same rate as the or iginal task but

with reduced supply voltage. This is how the pipeli ned the

implementation will require lower power.

110

Q3. How clock frequency, speed up, throughput and p ower

dissipation changes for a pipelined implementation with k stages

with respect to non-pipelined implementation?

Ans: Clock frequency = kf, speedup =

where n is the number of tasks executed using k-sta ge pipeline,

and power dissipation = 1/k 2.

)1(

.

−+=

nk

knSk



Q4. How can you combine sizing and supply voltage s caling to

realize low power circuits?

Ans: It can be done in three steps (a) Upsize gates on the critical

path to reduce delay of the circuit (b) Scale down t he supply

voltage to equalize with the original delay (c) Ups ize gates on

non-critical paths selectively without exceeding th e critical path

delay.

111

Q5. Explain with an example how pipelining and par allelism can be

combined to realize low power circuits?to realize low power circuits?

AnsAns: Here, more than one parallel structure is used and each : Here, more than one parallel structure is used an d each

structure is pipelined. Both power supply and frequ ency of structure is pipelined. Both power supply and frequ ency of

operation are reduced to achieve substantial overal l reduction in operation are reduced to achieve substantial overal l reduction in

power dissipation. power dissipation.




Q1. Explain the basic concept of multi level voltag e scaling.

Q2. What is the impact of multiple supply voltages on the

distribution of path delays of a circuit with respe ct to that for single

supply voltage?

Q3. List and explain three important issues in the context of

multiple supply voltage scaling?


Q4. What problem arises when a signal passes from l ow voltage

domain to high voltage domain? How this problem is overcome?

Q5. Explain the design decision for the placement o f converters in

the voltage scaling interfaces.

113


Q1. Explain the basic concept of multi level voltag e scaling.

Ans: This is an extension of SVS where two or few f ixed voltage

domains are used in different parts of a circuit,. As we know,

high igh VddVdd gates have less delay, but higher dynamic and st atic gates have less delay, but higher dynamic and stati c

power dissipation and low power dissipation and low VddVdd gates have larger delay but gates have larger delay but

lesser power dissipation. Voltage islands can be ge nerated at lesser power dissipation. Voltage islands can be ge nerated at


lesser power dissipation. Voltage islands can be ge nerated at lesser power dissipation. Voltage islands can be ge nerated at

different levels of granularity, such as macro leve l and standard different levels of granularity, such as macro leve l and standard

cell level. The slack of the offcell level. The slack of the off--critical path can be utilized for critical path can be utilized for

allocation of macro modules of lowallocation of macro modules of low--VddVdd to offto off--criticalcritical--path path

macro modules. Total power dissipation can be reduc ed without macro modules. Total power dissipation can be reduc ed without

degrading the overall circuit performance.degrading the overall circuit performance.

114

Q2. What is the impact of multiple supply voltages on the

distribution of path delays of a circuit with respe ct to that for

single supply voltage?

Ans: Path delay for different paths in a circuit f or single supply

voltage is shown. The graph of a Gaussian is a characteristic The graph of a Gaussian is a characteristic

symmetric "bell curve" shape that quickly falls off towards plus/minus symmetric "bell curve" shape that quickly falls off towards plus/minus

infinity plus/minus infinity. However, when multiple supply voltages infinity plus/minus infinity. However, when multiple supply voltages



infinity plus/minus infinity. However, when multiple supply voltages infinity plus/minus infinity. However, when multiple supply voltages

are used, the path delay distribution is not Gaussian because are used, the path delay distribution is not Gaussian because

modules having smaller delays are assigned with smaller supply modules having smaller delays are assigned with smaller supply

voltage and their delay increases.voltage and their delay increases.

115


Q3. List and explain the important issues in the co ntext of multiple

supply voltage scaling?

Ans: Important issues in the context of MVS are lis ted below: (a) Voltage Scaling Interfaces (b) Converter Placement (c) Floor planning, Routing and Placement (d) Multiple Supply Voltages


(d) Multiple Supply Voltages (e) Static Timing Analysis (f) Power up and Power down Sequencing (g) Clock distribution

116


Q4. What problem arises when a signal passes from l ow voltage

domain to high voltage domain? How this problem is overcome?

Ans: A highA high--level output from the lowlevel output from the low--VddVdd domain has output domain has output

VddLVddL, which may turn on both , which may turn on both nMOSnMOS and and pMOSpMOS transistors of the transistors of the

highhigh --VddVdd domain inverter resulting in short circuit between domain inverter resulting in short circuit between VddHVddH to to


highhigh --VddVdd domain inverter resulting in short circuit between domain inverter resulting in short circuit between VddHVddH to to

GND. A level converter needs to be inserted to avo id this static GND. A level converter needs to be inserted to avo id this static

power consumptionpower consumption

117


Q5. Explain the design decision for the placement o f

converters in the voltage scaling interfaces.

AnsAns: One important design decision in the voltage : One important design decision in the voltage scaling interfaces is the placement of converters . As scaling interfaces is the placement of converters . As the highthe high--toto--low level converters use lowlow level converters use low--VddVdd voltage voltage rail, it is a appropriate to place them in the rece iving rail, it is a appropriate to place them in the rece iving or destination domain. It is also recommended to or destination domain. It is also recommended to


or destination domain. It is also recommended to or destination domain. It is also recommended to place the lowplace the low--toto--high level converters in the r eceiving high level converters in the receiving domain. As the lowdomain. As the low--toto--high level converters req uire high level converters require both low and highboth low and high--VddVdd supply rails, at least one of the supply rails, at least one of the supply rails needs to be routed from one domain to supply rails needs to be routed from one domain to the other.the other.

118


Q1. For a workload of 50%, explain how reduction in

power dissipation takes place for DVS and DVFS?

Q2. With the help of a schematic diagram, explain h ow

the dynamic voltage and frequency scaling technique is

used to achieve low power dissipation of a processo r.


Q3. In what way adaptive voltage scaling differs fr om

dynamic voltage scaling?

Q4. Show various building blocks required for the

implementation of adaptive voltage scaling system.

119


Q1. For a workload of 50%, explain how reduction in

power dissipation takes place for DVS and DVFS?

Q2. With the help of a schematic diagram, explain h ow

the dynamic voltage and frequency scaling technique is

used to achieve low power dissipation of a processo r.




Q4. Show various building blocks required for the

implementation of adaptive voltage scaling system.

120

Rel

ativ

eP

ower

P1WORKLOAD 50%

No voltage orfrequency

scaling

0

1

Q1. For a workload of 50%,

explain how reduction in power

dissipation takes place for DFS

and DVFS?

Ans: The adjacent diagrams

show how reduction in power

dissipation take in the two



Time T20

(b)

Time

P2

T1

WORKLOAD 50%

Frequency Scaling 50%

No voltage scaling

Rel

ativ

eP

ower

0

0.5

(c)

Time

P3

T1

WORKLOAD 50%

Frequency Scaling 50%With voltage scaling

Rel

ativ

eP

ower

0.25

(d)

dissipation take in the two

situations.

DC / DC

Converter

Workload

MonitorV fixed

r FrequencyGenerator

r

Q2. With the help of a schematic diagram, explain h ow the dynamic voltage and frequency scaling technique is used to achieve low power dissipation of a processor. Ans: The diagram shows how both voltage and frequen cy are controlled for different predicted workload.



Variable VoltageProcessor )( rµµµµ

V (r) W f ( r )

MMMM

Task

Queue

1λλλλ

2λλλλ

nλλλλ

λλλλ



Ans: The DVFS approach is The DVFS approach is openopen--loop in nature. loop in nature. VoltageVoltage--frequency pairs are determined at design t ime frequency pairs are determined at design time keeping sufficient margin for guaranteed operation keeping sufficient margin for guaranteed operation across the entire range of best and worst case proc ess, across the entire range of best and worst case proc ess, voltage and temperature (PVT) voltage and temperature (PVT) conditions. As conditions. As the the



voltage and temperature (PVT) voltage and temperature (PVT) conditions. As conditions. As the the design needs to be very conservative for successful design needs to be very conservative for successful operation, the actual benefit obtained is lesser th an operation, the actual benefit obtained is lesser th an actually actually possible. A possible. A better alternative that can overcome better alternative that can overcome this limitation is the Adaptive Voltage Scaling (AV S) this limitation is the Adaptive Voltage Scaling (AV S) where a closewhere a close--loop feedback system is implemented loop feedback system is implemented between the voltage scaling power supply and delay between the voltage scaling power supply and delay sensing performance monitor at execution sensing performance monitor at execution time. time.

123

Q4. Show various building blocks required for the i mplementation of adaptive voltage scaling system.

AnsAns: The schematic diagram is given below. The oper ation of : The schematic diagram is given below. The operati on of different building blocks are as follows:different building blocks are as follows:



The onThe on--chip monitor not only checks the actual vol tage developed, chip monitor not only checks the actual voltage dev eloped,

but also detects whether the silicon is slow, typic al or fast and the but also detects whether the silicon is slow, typic al or fast and the

effect of temperature on the surrounding silicon. effect of temperature on the surrounding silicon. T he DVC emulates The DVC emulates

the critical path characteristic of the system by u sing a delay the critical path characteristic of the system by u sing a delay

synthesizer and controls the dynamic supply voltage (0.9 to 1.6V at synthesizer and controls the dynamic supply voltage (0.9 to 1.6V at

5mV step in real 5mV step in real time). The time). The DFC adjusts the clock frequency at the DFC adjusts the clock frequency at the



5mV step in real 5mV step in real time). The time). The DFC adjusts the clock frequency at the DFC adjusts the clock frequency at the

required minimum value by monitoring the system act ivity (20MHz required minimum value by monitoring the system act ivity (20MHz

to to 120MHz). The 120MHz). The voltage and frequency are predicted ac cording to voltage and frequency are predicted according to

the performance monitoring of the the performance monitoring of the system. The system. The DVFM system can DVFM system can

track the required performance with a high level of accuracy over track the required performance with a high level of accuracy over

the full range of temperature and process the full range of temperature and process deviation s.deviations.

125


Q1. Explain the basic concept of hardwareQ1. Explain the basic concept of hardware--software software

tradeoff with an example for low power .tradeoff with an example for low power .

Q2. Distinguish between superscalar and VLIW Q2. Distinguish between superscalar and VLIW

architecturearchitecture

Q3. Discuss why VLIW architecture allows lower powe r Q3. Discuss why VLIW architecture allows lower powe r


dissipation compared to Superscalar architecture.dissipation compared to Superscalar architecture.

Q4. In the context of Q4. In the context of Transmeta’sTransmeta’s Crusoe processor Crusoe processor

explain the role of Code Morphing Software.explain the role of Code Morphing Software.

Q5. How caching can be used to achieve lower power Q5. How caching can be used to achieve lower power

dissipation in VLIW architecture?dissipation in VLIW architecture?

126


Q1. Explain the basic concept of hardwareQ1. Explain the basic concept of hardware--software tradeoff with software tradeoff with

an example for low power .an example for low power .

AnsAns: It is well known that the same : It is well known that the same functionality can be either functionality can be either realized by hardware or by software or by a combina tion of realized by hardware or by software or by a combina tion of both. both. The hardwareThe hardware--based approach has the following char acteristic:based approach has the following characteristic:

•• FasterFaster•• CostlierCostlier•• Consumes more powerConsumes more power


•• Consumes more powerConsumes more powerOn the other hand the softwareOn the other hand the software--based based approachhasapproachhas the following the following characteristics:characteristics:

•• CheaperCheaper•• SlowerSlower•• Consumes lesser Consumes lesser powerpower

127

Q2. Distinguish between superscalar and VLIW Q2. Distinguish between superscalar and VLIW archit ecture.architecture.

AnsAns: Both superscalar and VLIW architectures implem ent : Both superscalar and VLIW architectures implement a form of a form of

parallelism called instructionparallelism called instruction--level parallelism w ithin a single level parallelism within a single

processor. A processor. A superscalar processor executes more th an one superscalar processor executes more than one

instructions during a clock cycle by simultaneously dispatching instructions during a clock cycle by simultaneously dispatching

multiple instructions to more than one functional u nits on the multiple instructions to more than one functional u nits on the

processor. In processor. In a superscalar CPU the a superscalar CPU the dispatcher dispatcher reads instructions reads instructions



processor. In processor. In a superscalar CPU the a superscalar CPU the dispatcher dispatcher reads instructions reads instructions

from memory and decides which ones can be run in pa rallel, from memory and decides which ones can be run in pa rallel,

dispatching them to two or more functional units co ntained inside a dispatching them to two or more functional units co ntained inside a

single single CPU. So, in this case ILP is implemented by hardware. CPU. So, in this case ILP is implemented by hardwar e.

On the other hand, a On the other hand, a compiler compiler identifies that can be identifies that can be

executed in parallel and generates executed in parallel and generates long instructio ns having long instructions having

multiple operations meant for different functional multiple operations meant for different functional units. Therefore, units. Therefore,

in this case ILP is implemented by in this case ILP is implemented by software.software.

128

Q3Q3. Discuss why VLIW architecture allows lower po wer dissipation . Discuss why VLIW architecture allows lower power dissipation compared to Superscalar architecturecompared to Superscalar architecture..

AnsAns: As parallelism is identified by software at co mpile time, the : As parallelism is identified by software at compi le time, the VLIW incurs lower power dissipation.VLIW incurs lower power dissipation.

Q4. In the context of Q4. In the context of Transmeta’sTransmeta’s Crusoe processor explain the role Crusoe processor explain the role of Code Morphing Softwareof Code Morphing Software..AnsAns : : The Code Morphing software mediates between x86 sof tware The Code Morphing software mediates between x86 sof tware



AnsAns : : The Code Morphing software mediates between x86 sof tware The Code Morphing software mediates between x86 sof tware and the VLIW and the VLIW engine. It engine. It is fundamentally a dynamic translation is fundamentally a dynamic translation system. A system. A program that program that translates instructions from one translates instructions from one instruction instruction set architecture set architecture to another instruction set archite cture. to another instruction set architecture. Here, x86 Here, x86 code is compiled into VLIW code is compiled into VLIW code of the code of the CruosoeCruosoe processor. processor. Code Code Morphing software insulates x86 programs from the h ardware Morphing software insulates x86 programs from the h ardware engine’s native instruction engine’s native instruction set. The set. The code morphing software is the code morphing software is the only program that is written directly for the VLIW only program that is written directly for the VLIW processor.processor.

129


Q5. How caching can be used to achieve lower power dissipation Q5. How caching can be used to achieve lower power dissipation in VLIW architecture?in VLIW architecture?

AnsAns: : In realIn real--life applications it is very common to exe cute a block of life applications it is very common to execute a bl ock of code many times over and over after it has been tra nslated code many times over and over after it has been tra nslated once. A once. A separate memory space is used to store the translat ion cache and separate memory space is used to store the translat ion cache and the code morphing the code morphing software. software. It allows reuse the translated code by It allows reuse the translated code by making use of locality of reference making use of locality of reference property. Cachi ng property. Caching translations translations provide excellent opportunity of reuse in many realprovide excellent opportunity of reuse in many real --life life


applications.applications.

130


Q1. Explain the basic concept of bus encoding to re duce switched Q1. Explain the basic concept of bus encoding to re duce switched

capacitance.capacitance.

Q2. Q2. Find out the switching activity of a moduloFind out the switching activity of a modulo--7 coun ter using 7 counter using

binary and Gray codes for state encodingbinary and Gray codes for state encoding

Q3. How gray coding helps to reduce power dissipati on for fetching Q3. How gray coding helps to reduce power dissipati on for fetching

instructions from main memory?instructions from main memory?


Q4. How reduction in power dissipation is achieved by dividing a Q4. How reduction in power dissipation is achieved by dividing a

6464--bit bus into eight 8bit bus into eight 8--bit buses.bit buses.

Q5. How T0 encoding achieves almost zero transition on a bus.Q5. How T0 encoding achieves almost zero transition on a bus.

131


Q1. Explain the basic concept of bus encoding to re duce switched Q1. Explain the basic concept of bus encoding to re duce switched

capacitance.capacitance.

AnsAns: Switching activity can be reduced by coding th e address bit : Switching activity can be reduced by coding the a ddress bit

before sending over the bus. This is done before sending over the bus. This is done introduci ng sample introducing sample to to

sample correlation such that total number of bit tr ansitions is sample correlation such that total number of bit tr ansitions is

reduced. Similarly, reduced. Similarly, ccommunicating ommunicating data bits in an appropriately data bits in an appropriately

coded form can reduce the switching coded form can reduce the switching activity.activity.


coded form can reduce the switching coded form can reduce the switching activity.activity.

132

Q2. Find out the switching activity of a moduloQ2. Find out the switching activity of a modulo--7 counter using binary 7 counter using binary and Gray codes for state encodingand Gray codes for state encoding ..

AnsAns: The reduction in the number of bit transitions for the two types of : The reduction in the number of bit transitions fo r the two types of coding is given below:coding is given below:

Binary code Transitions Gray code Transitions

000 000

001 1 001 1



001 1 001 1

010 2 011 1011 1 010 1

100 3 110 1

101 1 111 1

110 2 101 1

2 2

Total 12 8

Q3. How gray coding helps to reduce Q3. How gray coding helps to reduce

power dissipation for fetching power dissipation for fetching

instructions from main memoryinstructions from main memory??

AnsAns: : A A gray code sequence is a set of gray code sequence is a set of

numbers in which adjacent numbers numbers in which adjacent numbers

have only one bit have only one bit difference. On the difference. On the

other hand, the number of transitions other hand, the number of transitions



other hand, the number of transitions other hand, the number of transitions

vary from 1 to n (n/2 on the average) as vary from 1 to n (n/2 on the average) as

shown in the adjacent table. The power shown in the adjacent table. The power

dissipations of the bus driver decreases dissipations of the bus driver decreases

because of the reduction of switching because of the reduction of switching

activity.activity.

134

Q4Q4. How T0 encoding achieves almost zero transiti on on a bus. How T0 encoding achieves almost zero transition o n a bus..

AnsAns: In T0 encoding, after sending the first addres s, the same : In T0 encoding, after sending the first address, the same

address is sent address is sent for for infinite streams of consecutive addresses. infinite streams of consecutive addresses. The The

receiver side is informed about it by sending an ad ditional bit receiver side is informed about it by sending an ad ditional bit

known as increment (INC) bit. However, if the addre ss is not known as increment (INC) bit. However, if the addre ss is not

consecutive, then the actual address is sent. The consecutive, then the actual address is sent. The T 0 code provides, T0 code provides,

zero transition property zero transition property for for infinite streams of consecutive infinite streams of consecutive



zero transition property zero transition property for for infinite streams of consecutive infinite streams of consecutive

addresses.addresses.

135


1. Explain the basic concept of clock gating to red uce power 1. Explain the basic concept of clock gating to red uce power

dissipation in a digital circuit.dissipation in a digital circuit.

2. What are the three levels of clock gating granul arity? Compare 2. What are the three levels of clock gating granul arity? Compare

their pros and cons.their pros and cons.

3. Explain the important issues related to clock ga ting in the clock 3. Explain the important issues related to clock ga ting in the clock

tree.tree.


4. Explain with an example, how power dissipation i n a 4. Explain with an example, how power dissipation i n a

combinational circuit can be reduced by using opera nd combinational circuit can be reduced by using opera nd

isolation.isolation.

136


1.1. Explain the basic concept of clock gating to reduce power Explain the basic concept of clock gating to reduce power

dissipation in a digital circuit.dissipation in a digital circuit.

Ans: It has been observed that a major component of processor power is the clock power (50% of the total power). So, there is scope for large reduction of power dissipation by u sing suitable technique to remove a large number of unnecessary t ransitions. Such transitions can be suppressed without affectin g functionality. One of the most successful and commonly used low po wer


One of the most successful and commonly used low po wer technique is clock gating.

137

2. What are the three levels of clock gating granul arity? Compare 2. What are the three levels of clock gating granul arity? Compare

their pros and cons.their pros and cons.

Ans: There are three levels of granularity:• Module-level clock gating: Large reduction in power but there

is limited opportunity.• Register-level clock gating: There is more opportun ity

compared to module level clock gating, but lesser r eduction



compared to module level clock gating, but lesser r eduction of power.

• Cell-level clock gating: Provides many more opportu nities and it lends itself to automated insertion and can result in massively clock gated designs.

138

3. Explain the important issues related to clock ga ting in the clock 3. Explain the important issues related to clock ga ting in the clock

treetree..

AnsAns: : Clock tree amounts to a significant portion of the total

dynamic power consumption. It leads to a tradeoff b etween the

physical capacitance that is prevented from switch ing and the

number of unnecessary transitions. Disabling at hig her up in the

tree prevents larger capacitance from switching, bu t the gating



tree prevents larger capacitance from switching, bu t the gating

condition is satisfied fewer times. Having multiple gating points

along a path may be beneficial.

4. Explain with an example, how power dissipation i n a 4. Explain with an example, how power dissipation i n a

combinational circuit can be reduced by using opera nd combinational circuit can be reduced by using opera nd

isolationisolation..

139

Ans: Operand isolation is a technique for power red uction in the

combinational part of the circuit. Here the basic c oncept is to ‘shut-

off’ logic blocks when they do not perform any usef ul computation.

Shutting-off is done by not allowing the inputs to toggle in clock

cycles when the output of the block is not used. In the following

example, the output of the adder is loaded into the latch only when

S_1 is 1 and S_2 is 0. So, input lines of the adder may be gated



S_1 is 1 and S_2 is 0. So, input lines of the adder may be gated

based on this condition, as shown in the diagram.

140

D

CLK

00

11

S_1S_2

+

A

B

D

CLK

00

11

S_1S_2

+

A

B

AS


Q1. What is the basic concept of clock gated FSM. Q1. What is the basic concept of clock gated FSM.

Q2. How state encoding can be used to reduce power dissipation in Q2. How state encoding can be used to reduce power dissipation in

an FSM? Explain with an example.an FSM? Explain with an example.

Q3. How power dissipation is reduced by partitionin g an FSM> Q3. How power dissipation is reduced by partitionin g an FSM>

Explain with an example.Explain with an example.

Q4. A sequence detector produces a ’1’ Q4. A sequence detector produces a ’1’ for each occ urrence for each occurrence


of the input sequence ‘1001’ at its input.of the input sequence ‘1001’ at its input.




(c) Realize the FSM using D FFs and a PLA.(c) Realize the FSM using D FFs and a PLA.

141


Q1. What is the basic concept of clock gated FSM. Q1. What is the basic concept of clock gated FSM.

AnsAns: : There are conditions when the next state and output values do There are conditions when the next state and output values do

not change (idle not change (idle condition). Clocking condition). Clocking the circuit during the circuit during this idle this idle

condition leads to unnecessary wastage of condition leads to unnecessary wastage of power. Th e power. The clock can be clock can be

stopped, stopped, if the idle conditions can be if the idle conditions can be detected. This detected. This saves power saves power

both in the combinational circuit as well as the both in the combinational circuit as well as the re gisters/latches. registers/latches.


Q2. How state encoding can be used to reduce power dissipation in Q2. How state encoding can be used to reduce power dissipation in

an FSM? Explain with an examplean FSM? Explain with an example..

AnsAns: In : In the state assignment the state assignment phase of an FSM, phase of an FSM, each state is given a each state is given a

unique unique code. It has been observed that states code. It has been observed that states assignment assignment

strongly influences the complexity of its combinati onal logic strongly influences the complexity of its combinati onal logic

part used to realize the FSM. Traditionally part used to realize the FSM. Traditionally state a ssignment has state assignment has

been used to optimize the area and delay of the been used to optimize the area and delay of the circuit. It circuit. It can can



been used to optimize the area and delay of the been used to optimize the area and delay of the circuit. It circuit. It can can

also be used to reduce switching activity for the r eduction of the also be used to reduce switching activity for the r eduction of the

dynamic dynamic power. This is illustrated with the help of the following power. This is illustrated with the help of the fol lowing

example:example:

143

S1 S2 S3 S4

1/0 1/0 1/0 1/0

0/0 0/0 0/00/0,1/1

0/0S5

Transitions Assignment-1 Assignment-2

S1→→→→S1 0.0 0.0

S1→→→→S2 1.5 0.5

S2→→→→S1 1.5 0.5

S1 S2 S3 S4

1/01/0 1/0 1/0

0/0 0/00/0

0/0,1/1

0/0S5State Encoding

S1 000

S2 111

S3 001

S4 110

S5 101



S2→→→→S1 1.5 0.5

S2→→→→S3 1.0 0.5

S3→→→→S1 0.5 1.0

S3→→→→S4 1.5 0.5

S4→→→→S1 1.0 0.5

S4→→→→S5 1.0 1.0

S5→→→→S1 2.0 1.0

Total 10.0 5.5

S5 101

State Encoding

S1 000

S2 001

S3 011

S4 010

S5 100

Q3. How power dissipation is reduced by partitionin g an Q3. How power dissipation is reduced by partitionin g an FSM. FSM.

Explain with an exampleExplain with an example..

AnsAns: : The idea is to decompose a large FSM into a several smaller FSMs with smaller number of state registers and com binational blocks. Out of all the FSMs, only the active FSMs r eceive clock and switching inputs, and the others are idle and consu me no dynamic power. This is the basic concept of reducing dynami c power by



partitioning an FSM.

Q4Q4. A sequence detector produces a ’1’ . A sequence detector produces a ’1’ for for each occurrence of the each occurrence of the

input sequence ‘1001’ at its input.input sequence ‘1001’ at its input.




(c) Realize the FSM using D FFs and a PLA.(c) Realize the FSM using D FFs and a PLA.

145

AnsAns: 4(a) The state transition diagram is given bel ow:: 4(a) The state transition diagram is given below:

s1 s2 s3 s4

1/0 0/00/0

1/1

0/0

1/01/0



Y2Y1, zPS y2y1 x =0 X = 1S1 0 0 00,0 01,0S2 01 10,0 01,0S3 1 0 11,0 01,0S4 1 1 00,0 01,1

0/0

1/1

AnsAns: 4(b) The state : 4(b) The state

table is given in the table is given in the

adjacent diagramadjacent diagram

AnsAns: 4(c) The FSM using D FFs and a PLA to realize the : 4(c) The FSM using D FFs and a PLA to realize the

combinational circuit is given below:. combinational circuit is given below:.



Y2 = x’(y2y1’ + y2’y1)Y1 = x + x’y2y1’z = xy2y1

xy1 y2

Y2 Y1 z

CLK

DQ

DQ


Q1. In what situation the use of signQ1. In what situation the use of sign--magnitude fo rm of number magnitude form of number

representation instead of 2’s complement form is be neficial in representation instead of 2’s complement form is be neficial in

terms of power dissipation? Illustrate with an exam pleterms of power dissipation? Illustrate with an exam ple..

Q2. Explain how the ordering of input signal does a ffect the Q2. Explain how the ordering of input signal does a ffect the

dynamic power dissipation on a bus? Illustrate with an example.dynamic power dissipation on a bus? Illustrate with an example.

Q3. What is Q3. What is glitchingglitching power dissipation? How can it be minimized ?power dissipation? How can it be minimized?


Q4. How is it possible to reduce power dissipation by duplicating a Q4. How is it possible to reduce power dissipation by duplicating a

resource rather than using it twice?resource rather than using it twice?

148


Q1. In what situation the use of signQ1. In what situation the use of sign--magnitude fo rm of number magnitude form of number

representation instead of 2’s complement form is be neficial in representation instead of 2’s complement form is be neficial in

terms of power dissipation? terms of power dissipation?

AnsAns: In most of the signal processing applications, 2’s complement : In most of the signal processing applications, 2’ s complement

is typically chosen to represent numbers. Sign exte nsion causes is typically chosen to represent numbers. Sign exte nsion causes

MSB signMSB sign --bits to switch when a signal transitions from +bits to switch when a signal transitions from + veve to to ––


MSB signMSB sign --bits to switch when a signal transitions from +bits to switch when a signal transitions from + veve to to ––

veve or vice versa. 2’s complement can result in sig nificant or vice versa. 2’s complement can result in signifi cant

switching activity when the signals being processed switch switching activity when the signals being processed switch

frequently around zero. Switching in MSBs can be mi nimized by frequently around zero. Switching in MSBs can be mi nimized by

using signusing sign--magnitude (Smagnitude (S--M) representation.M) representation.

149

Q2. Explain how the ordering of input signal does a ffect the Q2. Explain how the ordering of input signal does a ffect the

dynamic power dissipation on a bus? Illustrate with an dynamic power dissipation on a bus? Illustrate with an

example.example.

AnsAns: Let us consider two alternative : Let us consider two alternative topologies to imp lement topologies to implement

the required 2 additionsthe required 2 additionsTopology #1Topology #1

�� SUM1 = IN + (IN>>7)SUM1 = IN + (IN>>7)



�� SUM1 = IN + (IN>>7)SUM1 = IN + (IN>>7)�� SUM2 = SUM1 + (IN>>8)SUM2 = SUM1 + (IN>>8)

Topology #2Topology #2�� SUM1 = (IN>>7) + (IN>>8)SUM1 = (IN>>7) + (IN>>8)�� SUM2 = SUM1 + INSUM2 = SUM1 + IN

Topology 1 Topology 2



Shift operation represent a scaling operation, whic h has the effect Shift operation represent a scaling operation, whic h has the effect of reducing the dynamic range of the signalof reducing the dynamic range of the signal



•Transition Probability for 3 signals – IN, IN>>7, IN >>8

ABC

1O

A B C0 1 0 1 1 1

O

2

Q3. What is glitching power dissipation? How can it be minimized?

Ans : In digital circuits glitch is an undesired transition that occurs before the signal settles to its intended value. In other words, glitch is an electrical pulse of short duration that is usually the result of a fault or design error. As shown in the adjacent diagram, there is some delay at



O

O

t = 0

2

1adjacent diagram, there is some delay at the output O 1, which results in a glitch at output O 2. As there is some capacitance associated with the output O 2, it leads to switching power dissipation. This switching power dissipation arising out of a glitch is known as glitching power dissipation.

AO1

O2AB

These “Extra” transitions can be minimized by�Balancing all signal paths�Reducing logic depth



Realization of A.B.C.D in cascaded form where there is possibility of glitch.

Balanced realization of the same function with lesser possibility of glitch

BCD

O2 O3BCD

AnsAns: Potential Logic Styles are:: Potential Logic Styles are:�� Static CMOS LogicStatic CMOS Logic�� Dynamic CMOS LogicDynamic CMOS Logic�� PassPass--Transistor Logic (PTL)Transistor Logic (PTL)

Q4. What are the potential logic styles for the rea lization of low power Q4. What are the potential logic styles for the rea lization of low power high performance CMOS circuits?high performance CMOS circuits?



�� PassPass--Transistor Logic (PTL)Transistor Logic (PTL)

Ref: D. Samanta, Ajit Pal, Logic Styles for High Performance and LowPower, Proceedings of the 12th International Worksh op on Logic and Synthesis, 2003 (IWLS-2003), pp. 355-362, May 2003

Static CMOS Logic� Advantages� Ease of fabrication� Good noise margin� Robust� Lower switching activity� Good input/output decoupling� No charge sharing problem� Availability of matured logic

synthesis tools and techniques

� Disadvantages� Larger number of transistors

(larger chip area and delay)� Spurious transitions (glitch)



synthesis tools and techniques � Spurious transitions (glitch) due to finite propagation delays leading to extra power dissipation and incorrect operation

� Short circuit power dissipation� Weak output driving capability� Large number of standard cells

requiring substantial engineering effort for technology mapping

pullup

network

pulldown

network

CL

INPUT f

VDD

VSS

Dynamic CMOS Logic

� Advantages� Combines the advantages

of low power of static CMOS and low chip area of pseudo-nMOS

� Reduced number of � Disadvantages

pulldown

network

VDD

INPUT

φ

φ

VSS

CL

f evaluationprecharge

φ = 0

φ = 1

f H

f H|H L



� Reduced number of transistors compared to static CMOS (n+2 versus 2n)

� Faster than static CMOS logic

� No short circuit power dissipation

� No spurious transition and glitching power dissipation

� Disadvantages� Higher switching activity� Not as robust as static CMOS

logic� Clock skew problem in

cascaded realization� Suffers from charge sharing

problem� Mature synthesis tool not

available

Pass-Transistor Logic

� Advantages� Lower area due to smaller

number of transistors and smaller input loads

� Ratio-less PTL allows minimum dimension transistors and hence

� Disadvantages� Increased delay due to long

chain pf pass-transistors� Multi-threshold voltage

drop� Dual-rail logic to provide all

signals in complementary



transistors and hence makes area efficient circuit realization

� No short circuit current leading to lower power dissipation

signals in complementary form

� There is possibility of sneak path


Q1. Q1. Why leakage power is an important in the deep s ub micron

technology?

Q2. What challenges we face in using threshold volt age scaling to Q2. What challenges we face in using threshold volt age scaling to

minimize leakage power dissipation?minimize leakage power dissipation?

Q3. Explain how transistor staking can be used to r educe leakage Q3. Explain how transistor staking can be used to r educe leakage

power dissipation.power dissipation.


Q4. Distinguish between standby and runtime leakage power. Why Q4. Distinguish between standby and runtime leakage power. Why

runtime leakage power is becoming important in the present day runtime leakage power is becoming important in the present day

context?context?

Q5. Compare between VTCMOS and MTCMOS for leakage p ower Q5. Compare between VTCMOS and MTCMOS for leakage p ower

reduction.reduction.

Q6. Give the advantages and limitations of MTCMOS a pproach.Q6. Give the advantages and limitations of MTCMOS a pproach.

159

Q1. Why leakage power is an important in the deep s ub micron technology?Q1. Why leakage power is an important in the deep s ub micron technology?

AnsAns: As shown in the diagram, the leakage power com ponent is increasing : As shown in the diagram, the leakage power compon ent is increasing

at a higher rate compared to dynamic power as we mo ve towards deep sub at a higher rate compared to dynamic power as we mo ve towards deep sub

micron technology. So, it has become an important i ssue.micron technology. So, it has become an important i ssue.



Q2. What challenges we face in using threshold volt age scaling to minimize Q2. What challenges we face in using threshold volt age scaling to minimize leakage power dissipation?leakage power dissipation?

AnsAns: : As supply voltage is scaled down to reduce p ower dissipation, the threshold voltage is also scaled down to maintain p erformance. As we do so, the subthreshold leakage current increases leading t o high power dissipation. So, the challenge is to maintain perfo rmance with lower power dissipation.


Ajit Pal, IIT KharagpurAjit Pal, IIT Kharagpur161

Ans: When more than one transistor is in series in a CMOS circuit, the leakage current has strong dependence on 0V 2.3V

Q3. Explain how transistor staking can be used to reduce leakage power Q3. Explain how transistor staking can be used to reduce leakage power dissipation.dissipation.



strong dependence on the number of turned off transistor. This is known as stacking effect. The highest leakage current is 99 times that of the

lowest leakage current

0V

0V

0V 14mV

34mV

89mV

State (ABC)

Leakage Current ( nA )

Leaking Transistors

000 0.095 Q1, Q2, Q3

001 0.195 Q1,Q2 010 0.195 Q1,Q3 011 1.874 Q1 100 0.184 Q2,Q3 101 1.220 Q2 110 1.140 Q3 111 9.410 Q4,Q5,Q6



111 9.410 Q4,Q5,Q6

A suitable input combination is A suitable input combination is used such that the reduction in used such that the reduction in leakage current due to stacking leakage current due to stacking effect is maximized. effect is maximized.


Q4. Distinguish between standby and runtime leakage power. Why Q4. Distinguish between standby and runtime leakage power. Why

runtime leakage power is becoming important in the present day runtime leakage power is becoming important in the present day

context?context?

AnsAns: Standby leakage power dissipation takes place when the : Standby leakage power dissipation takes place whe n the

circuit is not in use, i.e. inputs do not change an d clock is not circuit is not in use, i.e. inputs do not change an d clock is not

applied. On the other hand, runtime leakage power d issipation applied. On the other hand, runtime leakage power d issipation

takes place when the circuit is being used.takes place when the circuit is being used.


takes place when the circuit is being used.takes place when the circuit is being used.

164

Q5. Compare between VTCMOS and MTCMOS for leakage p ower Q5. Compare between VTCMOS and MTCMOS for leakage p ower

reduction.reduction.

AnsAns: In case of VTCMOS, basic principle is to adjus t threshold : In case of VTCMOS, basic principle is to adjust t hreshold voltage by changing substrate bias. Transistors ini tially have voltage by changing substrate bias. Transistors ini tially have low low VV thth during normal operation and substrate bias is alter ed during normal operation and substrate bias is alter ed using substrate bias control circuit. The threshold is increased using substrate bias control circuit. The threshold is increased by using reverse body bias when the circuit is not in use. by using reverse body bias when the circuit is not in use. Effective in reducing leakage power dissipation in standby mode Effective in reducing leakage power dissipation in standby mode and it involved additional area and higher circuit complexity. So, and it involved additional area and higher circuit complexity. So,



and it involved additional area and higher circuit complexity. So, and it involved additional area and higher circuit complexity. So, it is a postit is a post--silicon approach.silicon approach.

On the other hand, in case of MTCMOS approach MOS On the other hand, in case of MTCMOS approach MOS transistors of multiple threshold voltages are fabr icated in which transistors of multiple threshold voltages are fabr icated in which a power gating transistor is inserted in the stack between the a power gating transistor is inserted in the stack between the logic transistors and either power or ground, thus creating a logic transistors and either power or ground, thus creating a virtual supply rail or a virtual ground rail, respe ctively. The logic virtual supply rail or a virtual ground rail, respe ctively. The logic block contains all lowblock contains all low--VthVth transistors for fastest switching transistors for fastest switching speeds while the switch transistors, header and foo ter, are built speeds while the switch transistors, header and foo ter, are built using highusing high--VthVth transistors to minimize the leakage power transistors to minimize the leakage power dissipation. So, it is a predissipation. So, it is a pre--silicon approach.silicon approach.

165

Review Questions Review Questions of Lecof Lec--3030Q1. Explain how standby power is reduced in MTCMOS technique. Q1. Explain how standby power is reduced in MTCMOS technique.

Discuss its advantage and disadvantages.Discuss its advantage and disadvantages.

Q2. Explain how multiple threshold voltage transist ors can be used to Q2. Explain how multiple threshold voltage transist ors can be used to

realize low voltage high performance circuits requi ring low power realize low voltage high performance circuits requi ring low power

((ii) only in the standby mode, (ii) both in standb y and active mode.) only in the standby mode, (ii) both in standby an d active mode.

Q3. Compare the advantage and disadvantages of fineQ3. Compare the advantage and disadvantages of fine --grained and grained and

coarsecoarse --grained power gating approaches. grained power gating approaches.


coarsecoarse --grained power gating approaches. grained power gating approaches.

Q4. Distinguish between local and global power gati ng and compare Q4. Distinguish between local and global power gati ng and compare

their advantage and disadvantages.their advantage and disadvantages.

Q5. Why is it necessary to isolate a signal as it g oes from one voltage Q5. Why is it necessary to isolate a signal as it g oes from one voltage

domain to another voltage domain? Explain how is it domain to another voltage domain? Explain how is it

implemented?implemented?

Q6. Explain different approaches of state retention . Q6. Explain different approaches of state retention .

166


Q1. Compare and contrast clock gating versus power gating Q1. Compare and contrast clock gating versus power gating approaches.approaches.AnsAns: Clock gating minimizes dynamic power by stoppi ng : Clock gating minimizes dynamic power by stopping unnecessary transitions, but power gating minimizes leakage power unnecessary transitions, but power gating minimizes leakage power by inserting a highby inserting a high--VtVt transistor in series with the lowtransistor in series with the low--vtvt logic blocks .logic blocks.

Q2. Compare the advantage and disadvantages of fineQ2. Compare the advantage and disadvantages of fine --grained and grained and coarsecoarse--grained power gating approaches. grained power gating approaches.


AnsAns: In case of fine: In case of fine--grained approach the switch is p laced locally grained approach the switch is placed locally inside each standard cell and the switch must be de signed to supply inside each standard cell and the switch must be de signed to supply worst case current so that it does not impact perfo rmance. In this worst case current so that it does not impact perfo rmance. In this approach, the area overhead of each cell is signifi cant (2Xapproach, the area overhead of each cell is signifi cant (2X--4X). On the 4X). On the other hand, in case of coarseother hand, in case of coarse--grained approach, a block of gates has grained approach, a block of gates has its power switched by a collection of switched cell s. In this case the its power switched by a collection of switched cell s. In this case the sizing is very difficult, but it has significantly less area overhead than sizing is very difficult, but it has significantly less area overhead than that of fine grain approach. It is a preferred appr oach because of that of fine grain approach. It is a preferred appr oach because of lesser area overhead.lesser area overhead.

167


Q3. Distinguish between local and global power gati ng and Q3. Distinguish between local and global power gati ng and compare their advantage and disadvantages.compare their advantage and disadvantages.

AnsAns: Global power gating refers to a logical topolo gy in which : Global power gating refers to a logical topology in which multiple switches are connected to one or more bloc ks of logic, and multiple switches are connected to one or more bloc ks of logic, and a single virtual ground is shared in common among a ll the power a single virtual ground is shared in common among a ll the power gated logic blocks. This topology is effective for large blocks gated logic blocks. This topology is effective for large blocks (coarse(coarse--grained) in which all the logic is power g ated, but is less grained) in which all the logic is power gated, but is less effective for physical design reasons, when the log ic blocks are effective for physical design reasons, when the log ic blocks are


effective for physical design reasons, when the log ic blocks are effective for physical design reasons, when the log ic blocks are small. It does not apply when there are many differ ent power gated small. It does not apply when there are many differ ent power gated blocks, each controlled by different sleep enable s ignals.blocks, each controlled by different sleep enable s ignals.

On the other hand, local power gating refers to a l ogical On the other hand, local power gating refers to a l ogical topology in which each switch singularly gates its own virtual topology in which each switch singularly gates its own virtual ground connected to its own group of logic. This ar rangement ground connected to its own group of logic. This ar rangement results in multiple segmented virtual grounds for a single sleep results in multiple segmented virtual grounds for a single sleep domain.domain.

168


Q4. Why is it necessary to isolate a signal as it g oes from one Q4. Why is it necessary to isolate a signal as it g oes from one voltage domain to another voltage domain? Explain h ow is it voltage domain to another voltage domain? Explain h ow is it implemented?implemented?

AnsAns: There is no guarantee that the power gated blo cks will fully : There is no guarantee that the power gated blocks will fully

charge or discharge. As a consequence, the outputs of powered charge or discharge. As a consequence, the outputs of powered


charge or discharge. As a consequence, the outputs of powered charge or discharge. As a consequence, the outputs of powered

down blocks may result in crowbar currents in the powered up down blocks may result in crowbar currents in the powered up

blocks. To overcome this problem, it is necessary t o isolate a blocks. To overcome this problem, it is necessary t o isolate a

power gated block from a non power gated block.power gated block from a non power gated block.

169


Q5. Explain different approaches of state retention . Q5. Explain different approaches of state retention .

AnsAns: Given a power switching fabric and an isolatio n strategy, it is : Given a power switching fabric and an isolation s trategy, it is

possible to power gate a block of logic, but unless a retention possible to power gate a block of logic, but unless a retention

strategy is employed, all state information is lost when the block strategy is employed, all state information is lost when the block

is powered down. To resume its operation on power u p, the is powered down. To resume its operation on power u p, the

block must either have its state restored from an e xternal source block must either have its state restored from an e xternal source

or build up its state from the reset condition. In either case, the or build up its state from the reset condition. In either case, the


or build up its state from the reset condition. In either case, the or build up its state from the reset condition. In either case, the

time and power required can be significant. The fol lowing three time and power required can be significant. The fol lowing three

approached can be usedapproached can be used�� A software approach based on reading and writing re gistersA software approach based on reading and writing re gisters�� A scanA scan--based approach based on the rebased approach based on the re--use of scan chains use of scan chains

to store state off chip to store state off chip �� A registerA register--based approach that uses retention regi stersbased approach that uses retention registers

170


Q1. How supply voltage scaling leads to run time le akage power Q1. How supply voltage scaling leads to run time le akage power

reduction?reduction?

Q2. How can you combine power gating with dynamic voltage Q2. How can you combine power gating with dynamic voltage

scaling to reduce power dissipation?scaling to reduce power dissipation?

Q3. Explain the basic concept of dual Q3. Explain the basic concept of dual VtVt assignme nt for reduction assignment for reduction

of leakage power.of leakage power.


Q4. Distinguish between delayQ4. Distinguish between delay--constrained and ener gyconstrained and energy--constrained constrained

dual dual VtVt assignment approaches.assignment approaches.

Q5. Explain how the threshold voltage can be dynami cally adjusted Q5. Explain how the threshold voltage can be dynami cally adjusted

to reduce leakage power dissipation.to reduce leakage power dissipation.

171


Q1. How supply voltage scaling leads to run time le akage power

reduction.

Ans: Supply voltage reduction not only leads to the reduction of

dynamic power, it also leads to the reduction of le akage power.

The subthreshold leakage due to GIDL and DIBL decre ases as

supply voltage is scaled down. It has also been dem onstrated

that the supply voltage scaling impacts in the orde rs of V 3 and V4


that the supply voltage scaling impacts in the orde rs of V 3 and V4

on subthreshold leakage and gate leakage, respectiv ely.

172

Ans: As the supply voltage along the

frequency is lowered using the DVFS,

the supply voltage hits the lower limit

and the curve flattens out and the

supply voltage cannot be further


1 . 0

0 . 75

ower

(W) Traditional power

management

Q2. How can you combine power gating with dynamic voltage scaling to reduce power dissipation?


lowered. At this point it is more efficient

to switch over to traditional power

management, i.e. the supply voltage is

turned on and off depending on the

performance requirement. This is how

one can combine the DVFS and

traditional power management approach

as shown in the diagram.

173

0 . 5

0

NormalActivity level

0 . 2 5

1 . 0 0 . 75 0 . 5 0 . 2 5 0P

o

DVFS

DVFS with traditionalpower managent


Q3. Explain the basic concept of dual Vt assignment for the

reduction of leakage power.

Ans: This is based on the observation that all gate s are not on the

critical path when the circuit is represented with the help of a

directed acyclic graph (DAG). So, gates on the crit ical path can

be realized using Low-V th transistors for high performance and

the gates on the noncritical path are realized usin g high -V


the gates on the noncritical path are realized usin g high -Vth

transistors to reduce leakage power. This is the ba sic concept of

dualVt assignment.

174

Q4. Distinguish between delay-constrained and energ y-constrained

dual Vt assignment approaches.

Ans: In delay-constrained approach, no compromise i s made on

performance. So, dual-Vt assignment is done such tha t there is

no performance degradation. On the other hand, in e nergy

constrained approach some compromise in performance is

made, say 10% to 15%, to achieve larger reduction i n the leakage



made, say 10% to 15%, to achieve larger reduction i n the leakage

power.

175

Q5. Explain how the threshold voltage can be dynami cally adjusted Q5. Explain how the threshold voltage can be dynami cally adjusted

to reduce leakage power dissipation.to reduce leakage power dissipation.Ans: Just like dynamic the Vdd scaling scheme, a dyn amic Vth

scheme (DVTS) can be used to reduce runtime leakage power in sub-100-nm generations, where leakage power is sign ificant portion of the total power at runtime. When the wor kload is less than the maximum, the processor is operated at lowe r clock frequency. Instead of reducing the supply voltage, the DVTS



frequency. Instead of reducing the supply voltage, the DVTS hardware raises the threshold voltage using reverse body biasing to reduce runtime leakage power. Just enoug h throughput is delivered for the current workload b y dynamically adjusting the Vth in an optimal manner to maximize l eakage power reduction.

A simpler scheme is called Vth-hopping which dynami cally switches between only two threshold voltages; Low-V t and High-Vt as the frequency controller generates either FCLK or FCLK/2, respectively

176


Q1. Distinguish between conventional charging (used in static CMOS

circuits) and adiabatic charging of a load capacita nce.

Q2. Explain how dynamic power dissipation is minimi zed using

adiabatic switching?

Q3. Prove that the charging of a capacitor C in n steps to a voltage

Vdd instead of a conventional single -step charging reduces the


Vdd instead of a conventional single -step charging reduces the

power dissipation by a factor of n.

Q4. Realize a 2-input OR/NOR gate using positive fe edback adiabatic

logic (PFAL) circuit. Explain its operation.

177

Answer to Questions of LecAnswer to Questions of Lec--3232Q1. Distinguish between conventional charging (used in static CMOS

circuits) and adiabatic charging of a load capacita nce.

Ans: Switching power dissipation in static CMOS cir cuit with

capacitive load C L has a lower limit of C LVdd2/2. On the other hand,

charge moves efficiently from power supply to the l oad

capacitance by using slow, constant-current chargin g. Reversing

the current source will cause the energy to flow fr om the load


the current source will cause the energy to flow fr om the load

capacitance back into the power supply. The power s upply must

be so designed to retrieve the energy fed back to i t. Adiabatic-

switching circuits require non-constant, non-standa rd power

supply with time-varying voltage. This supply is ca lled “Pulsed-

power supplies”.

178

Q2. Explain how dynamic power dissipation is minimi zed using

adiabatic switching?

Ans: In adiabatic switching, a time-dependent curre nt source, I(t) is

used to charge the capacitance C through a resistor R. For

T>2RC, the dissipated energy is smaller than the co nventional

lower limit C LVdd2/2. The dissipation can be made arbitrarily

small by extending the charging time T. As the diss ipated energy



small by extending the charging time T. As the diss ipated energy

is proportional to R, a smaller R results in a low er dissipation

unlike conventional case.

179

Q3. Prove that the charging of a capacitor C in n steps to a voltage

Vdd instead of a conventional single-step charging r educes the

power dissipation by a factor of n.

Ans: Energy dissipation for single step charging E = CLV2 / 2.

Energy dissipation in each of n step charging is eq ual to Estep = C LV2 / 2n2

.The total energy dissipation in N step charging eq ual to N.Estep = N. (C LV2 /



2n2)= CLV2 / 2n. Therefore, Estep / E = 1/n. Therefore, the po wer dissipation

reduces by a factor of n.

Q4. Realize a 2-input OR/NOR gate using positive fe edback

adiabatic logic (PFAL) circuit. Explain its operati on.

Ans: Perform the following steps:

1. Replace each of the PMOS and NMOS devices in the pull-up and pull-down networks with T-gates.

2. Use expanded pull-up network to drive the true ou tput. Use



expanded pull-down network to drive the complementa ry output.

3. Both networks in the transformed circuit are used to charge and discharge the load capacitance.

4. Replace DC Vdd by a pulsed power supply with varyi ng voltage to allow adiabatic operation.

The realization is shown in the next slide

VVAA XX

NORNOR

YY

XX

X

OROR



NORNORXX

YY

YY

OROR

X YY


Q1. Write a short note on “Battery-driven system de sign”.

Q2. Explain rate capacity effect for rechargeable batteries.

Q3 Explain recovery effect for rechargeable batteries.

Q3. What is the ‘non-increasing profile effect’ of a battery?


Q4. Explain the basic steps of battery aware task s cheduling. How

does it improves the lifetime of a Battery?

Q5. Why is the reverse body biasing important to ex tend the battery

life in the present day context?

183


Q1. Write a short note on “Battery-driven system de sign”.

Ans: In recent years there large proliferation of p ortable computing and communication equipment, such as laptops, palmt ops, cell-phones, etc. and the growth rate of these portable equipment is very high. The complexity of these devices is also incre asing with time, leading to larger energy consumption. As these devi ces are battery operated, battery life is of primary concern. Unfor tunately, the battery technology has not kept up with the energy requirem ent of the


technology has not kept up with the energy requirem ent of the portable equipment. Moreover, the commercial succes s of these products depend on weight, cost and battery life. L ow power design methodology is very important to make these battery -operated devices commercially viable.

184

Q2. Explain rate capacity effect for rechargeable batteries.

Ans: Dependency between the actual capacity and the magnitude of

the discharge current depends on the availability o f active region.

When discharge rate is high, surface of the cathode gets coated with

insoluble compound. This prevents access to many ac tive areas and

consequent reduction of actual capacity of the batt ery. As a result, a

higher rate of discharge leads to a lower available capacity. This is



higher rate of discharge leads to a lower available capacity. This is

known as Rate Capacity effect.

Q3 Explain recovery effect for rechargeable batteries.

Ans: Availability of charge carriers D\depends of t he concentration of positively charged ions near the cathode. When heav y current is drawn, rate at which positively charged ions consum ed at the cathode is more than supplied. This improves as the battery is kept idle for some duration. As a consequence, the batte ry voltage recovers in idle periods.

185

Q3. What is the ‘non-increasing profile effect’ of a battery?

Ans: It has been experimentally verified that if th e tasks consuming

higher power are scheduled first followed by tasks with decreasing

power consumption, then energy available in the bat tery is larger

compared to other schedules. This is known as non-i ncreasing

profile effect.



profile effect.

186

Q4. Explain the basic steps of battery aware task s cheduling. How

does it improves the lifetime of a Battery?

Ans: There are three steps. In the first step, an e arly deadline first

(EDF) based schedule is made, provided the task dep endencies are

not violated. In the second step, the task schedule is modified by

scheduling the tasks in the non increasing order of the current

loads provided the deadlines and the task dependenc ies are not



loads provided the deadlines and the task dependenc ies are not

violated. In the third step, starting from the last task, the slack

obtained at the end of the task is utilized to get the optimal pair of

supply voltage and the body bias voltage. This proc edure is

followed until either there is no more slack, or fu rther scaling down

not possible.

187

Q5. Why is the reverse body biasing important to ex tend the battery

life in the present day context?

Ans: With the advancement of technology, as the process

technology further gets lower, the energy due to st atic power

becomes more significant, and the algorithm using R BB to reduce

the leakage current provides larger saving in power dissipation.




Q1. What is the limitation of contemporary CAD tool s?

Q2. Give a summary of the benefits and impacts of t he different low

power techniques.

Q3. What is provided by UPF?

Q4. What are the key features of Eclypse, the low-p ower CAD tool

of Synopsis?



Q1. What is the limitation of contemporary CAD tool s?Q1. What is the limitation of contemporary CAD tool s?

AnsAns: In RTL coding there is no provision to use Mul ti: In RTL coding there is no provision to use Multi- -VtVt , Multi, Multi--VddVdd, ,

Body biasing and power gating in RTL synthesis. So , the static Body biasing and power gating in RTL synthesis. So , the static

power reduction techniques cannot be used. As suppl y voltage power reduction techniques cannot be used. As suppl y voltage

and the operating frequency are also not handled at the RTL and the operating frequency are also not handled at the RTL

level, the dynamic power can be reduced primarily b y reducing level, the dynamic power can be reduced primarily b y reducing

the switching activity the switching activity αα. Commonly used techniques in RTL . Commonly used techniques in RTL


the switching activity the switching activity αα. Commonly used techniques in RTL . Commonly used techniques in RTL

synthesis to reduce synthesis to reduce αα are:are:�� Bus encodingBus encoding�� Clock gatingClock gating�� FSM state assignmentFSM state assignment

190

Q2. Give a summary of the benefits and impacts of t he different low power techniques.

Technique DynamicPower

StaticPower

DesignImpact

VerificationImpact

ImplementationImpact

Ans: The benefits and impacts of different low power techniq ues issummarized in the following table. These techniques can sign ificantly reducepower consumption in deep submicron chips. However, these t echniquestraditionally require ad-hoc, time-consuming, risk-pron e, and manualverification and implementation approaches, unless autom ated using CADtools.



PowerBenefit

PowerBenefit

Impact Impact Impact

ClockGating

Large Small Small Small Small

Multi-Vdd Large Small Little Low Medium

DVFS Large Small Medium Large Medium

Multi-Vt Small Large Medium Small Medium

PowerGating

Small Very Large

Medium Large Medium

Q3. What is provided by UPF?Q3. What is provided by UPF?

AnsAns: : UPF provides the ability for electronic syst ems to be designed with power as a key consideration early in the proc ess. It accomplishes this through the ability to allow the specification of implementation-relevant power information early in the design process — RTL (register transfer level) or earlier. UPF provides a consistent format to specify power -aware design information



consistent format to specify power -aware design information that cannot be specified in HDL code or when it is undesirable to directly specify within the HDL logic, as doing so would tie the logic specification directly to a constrained power implementation.

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Q4. What are the key features of Eclypse, the low-p ower CAD tool

of Synopsis?

Ans: Eclypse provides a comprehensive approach – powe r-aware

tools at all levels of design hierarchy starting fr om early

architectural and system-level analysis to verifica tion, RTL

synthesis, test, physical implementation and sign-o ff. This

supports the Accellera Unified Power format – an open industry



supports the Accellera Unified Power format – an open industry

standard to specify power intent and it is backed b y the popular

“Low Power Methodology Manual” (LPMM).

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Q1. How parameter variations impact on circuits and

microarchitecture of present day VLSI circuits?

Q2. Why current or future technologies result in two- sided

constraints?

Q3. What are the basic approaches for variation tol erant design?

Q4. Explain how you can achieve low power single-Vt circuits using


judicious use of sizing?

Q5. Explain how you can use adaptive body biasing t o improve

yield.

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Q1. How parameter variations impact on yield of pre sent day VLSI

circuits?

� Ans: Fluctuations are attributed to the manufacturi ng process

(e.g., drifts in Leff, Tox, Vt, or Ncheff ), which affect circuit yield. For

example, with in die variation in Leff can be as high as 50%. 30%

delay variation and 20X leakage variation between f ast and slow

dies have been reported for 0.18µ CMOS process. Low leakage


dies have been reported for 0.18µ CMOS process. Low leakage

chips with too low frequency must be discarded and high

frequency chips with too high leakage must also be discarded.

This lwads to reduction in yield.

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Q2. Why current or future technologies result in two -sided

constraints?

Ans: Lower channel length leads to smaller threshol d voltage and

larger power dissipation and higher channel length leads to higher

threshold voltage and longer delay. This leads to t wo-sided

constraints for current and future technologies.





Ans: Basic approaches are:

(a) To reduce the sources of variations, (b) Reduce the effects of

variation at the time of design and (c) Reduce effe cts of variation

after fabrication (post-silicon) such as reverse bo dy biasing.

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Q4. Explain how you can achieve low power single-Vt circuits using

judicious use of sizing?

Ans: This can be done in three steps:

Step-I: Upsize gates on the critical path to reduce delay of the entire

circuit.

Step II: Increase threshold voltage of the MOSFETs of the entire



circuit to minimize leakage power

Step III: Downsize gates on the non critical path t o reduce area and

dynamic power

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Q5. Explain how you can use adaptive body biasing t o improve

yield.

Ans: Starting with Vt lower than the target voltage, adaptive body

biasing can be used to match the mean Vt of all the die samples.

The die samples that require larger body bias to ma tch its mean Vt

to the target Vt end with higher within -die variation.



to the target Vt end with higher within -die variation.

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Thanks!Thanks!


Thanks!Thanks!

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