Low Latency Clock Domain Transfer for Simultaneously Mesochronous, Plesiochronous and Heterochronous...
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Transcript of Low Latency Clock Domain Transfer for Simultaneously Mesochronous, Plesiochronous and Heterochronous...
Low Latency Clock Domain Transfer for Simultaneously Mesochronous,
Plesiochronous and Heterochronous Interfaces
Wade WilliamsPhilip Madrid, Scott C. Johnson
March 14, 2007
Low Latency Clock Domain Transfer2 March 14, 2007
Presentation Overview
Introduction
Clock Domain Characteristics
Design Constraints
Solution
System Response Time
Additional Benefits
Enhancements
Questions
Low Latency Clock Domain Transfer3 March 14, 2007
Introduction
Increasing Levels of Integration
Mixed designs: System-On-A-Chip (SOC)
Independently clocked domains
Independently powered domains
Faster External Interfaces
Interface clock frequencies are starting to exceed the internal logic clock rates
Clock frequencies exceeding 2 GHz
Low Latency Clock Domain Transfer4 March 14, 2007
Clock Domain Characteristics
Reference clock source mismatches (plesiochronous)
PLL reference clock distribution
PLL accumulated phase error
Grid clock insertion delay
Spread-Spectrum
Temperature
Voltage
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D
D
Clock Domain (cont.)
PLL
D PLLD
D
D D Clock A
Clock B
D
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Design Constraints
Minimized Latency, Maximized Throughput
Unknown Phase Relationship Between Domains
Controlled Frequency Mismatches (1% - 2%)
Predictable Scheduling for Pipelining
Manufacturability
Deterministic
Small design footprint
Simple design for quick productization
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Solution
This problem can be solved by building a system comprised of 3 major blocks
Circular FIFO
– Performs the basic clock domain transfer
Pointer Tracking Logic
– Maintains a consistent pointer separation and provides predictable latency across the interface
Digital Filter
– Ensures system stability by filtering out errors due to sampling uncertainties
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FIFO
Basic clock domain transfer is achieved using a circular First-In First-Out (FIFO) queue.
Example
8 entry FIFO
Write Pointer on Clock A (Frequency = 2)
Read Pointer on Clock B (Frequency = 3)
Clock B Frequency > Clock A Frequency
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FIFO (cont.)
7
6
5
4
3
1
2
0
Clock A(Freq = 2)
WrPtr
Clock B(Freq = 3)
RdPtr
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FIFO (cont.)
Slow Domain (Clock A) free-runs
Fast Domain (Clock B) is gated to create the RdPtr Clock
Average frequency matches Clock A
Duty cycle and clock periods can vary
Clock A (2)[WrPtr Clock]
Clock B (3)
RdPtr Clock
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Pointer Tracking Logic
This logic maintains a constant separation between the read and write pointers.
Operates exclusively in the faster clock domain
Leverages the fact that any changes in the pointer separation occur very slowly.
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Pointer Tracking (cont.)
76543
12
0
Clock A(Freq = 2)
WrPtr[2:0]
Clock B(Freq = 3)
RdPtr[2:0]
WrPtr[2]FF#0
FF#6
FF#7
Evaluate
RdPtr Clock
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Pointer Tracking (cont.)
The synchronization chain runs at the FIFO data rate
Information about the pointer location is preserved across the synchronization interface.
Evaluate is a falling edge pulse generated by the MSB of the WrPtr[2:0]. It represents the WrPtr going to 0.
When Evaluate pulses, we compare the RdPtr against the desired location.
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Digital Filter
This averages out the sample data and prevents false pointer corrections
Sampling errors are introduce by:
Variations in the clock period of the RdPtr Clock
Metastability on the first sampling flop
High speed clock phase variations due to oscillations on the power supplies
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Digital Filter (cont.)
Variations in the RdPtr Clock period and duty cycle are intrinsic to this solution.
Irregularities created by throttling the faster clock necessitate the use of a digital filter
The effects of the clock period and duty cycle variations can be exacerbated by the sample rate of the final design.
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Digital Filter (cont.)
The sample rate and the RdPtr Clock can create ratios which inadvertently bias the data. This can not be completely solved with the digital filter.
Additional refinements:
Allow hysterersis in the system
Alter the sample rate
Clock A
RdPtr Clk (I)
RdPtr Clk (II)
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Digital Filter (cont.)
Metastability occurs when the data fails to satisfy the setup and hold requirements for the first synchronizing flop.
It is expected that there will be periods of time when the front of the synchronization flop chain is operating in a metastable region.
The digital filter can help reduce some of the sampling errors (noise) due to metastability.
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Digital Filter (cont.)
This design is not intended to track high speed phase variations between the two clock domains.
Frequency oscillations on the power supplies are a primary contributor to this phenomenon.
The digital filter can help average out the spurious samples and provide more accurate tracking.
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System Response Time
Using the eight entry FIFO example and a digital filter requiring 3 samples, a correction is possible every 3x8=24 slow clocks.
In practice, the system will incur a full FIFO iteration before evaluating the first sample. This reduces the corrections to 1 in 32 clocks, allowing it to track a 3.1% clock difference.
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Additional Benefits
This design carries several beneficial properties
The desired pointer separation can be programmable
Initial pointer placement can be conservative
The tracking logic can be disabled
FIFO data traffic is quickly supported
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Enhancements
There are a few enhancements which are immediately feasible with this design
The logic can be mirrored
Pointer correction events can be pipelined
The tracking logic can operate off slightly earlier versions of their respective clock domains
The digital filter can be customized to the application
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Trademark Attribution
AMD, the AMD Arrow logo and combinations thereof are trademarks of Advanced Micro Devices, Inc. in the United States and/or other jurisdictions. Other names used in this presentation are for identification purposes only and may be trademarks of their respective owners.
©2006 Advanced Micro Devices, Inc. All rights reserved.