IEICE TRANS. FUNDAMENTALS, VOL.E94–A, NO.3 MARCH 2011937

PAPER

Low Complexity Filter Architecture for ATSC TerrestrialBroadcasting DTV Systems

Yong-Kyu KIM†, Chang-Seok CHOI†, Nonmembers, and Hanho LEE†a), Member

SUMMARY This paper presents a low complexity partially folded ar-chitecture of transposed FIR filter and cubic B-spline interpolator for ATSCterrestrial broadcasting systems. By using the multiplexer, the proposedFIR filter and interpolator can provide high clock frequency and low hard-ware complexity. A binary representation method was used for designingthe high order FIR filter. Also, in order to compensate the truncation errorof FIR filter outputs, a fixed-point range detection method was used. Theproposed partially folded architecture was designed and implemented with90-nm CMOS technology that had a supply voltage of 1.1 V. The imple-mentation results show that the proposed architectures have 12% and 16%less hardware complexity than the other kinds of architecture. Also, boththe filter and the interpolator operate at a clock frequency of 200 MHz and385 MHz, respectively.key words: digital signal processing (DSP), FIR, filter, architecture, cubicspline, interpolation, digital TV (DTV)

1. Introduction

In order to administer limited frequency resources and offerhigher quality service, the existing analog TVs have beenreplaced with digital TVs (DTVs) in many countries. Forthis transition, the Advanced Television Standard Commit-tee (ATSC) standards [1] have been proposed. The DTV re-ceiver for the ATSC cable broadcasting system is required.This receiver has been used in many fields such as High-Definition TV (HDTV), set-top boxes, VCR/DVDs, andPDAs. In particular, the DTV tuner is an important blockin the DTV receivers and is a major power expender. There-fore, low-cost DTV tuner Integrated Circuits (ICs) for theDTV systems are required to select the desired frequencyand down-converting for the intermediate frequency. Thedigital FIR filter and interpolator are the most fundamentalDigital Signal Processing (DSP) components for the CMOSDTV tuner.

The FIR filter has the advantages of stability and easyimplementation, but the large number of filter taps can leadto excessive hardware complexity. Therefore, folding tech-niques [2], [3] have been proposed as a means of reducingthe hardware complexity. A significant advantage of thefolded FIR filter architecture is that it can lead to reducethe hardware complexity compared to the corresponding un-folded one. The sampling frequency of the FIR filter outputis generally increased by the interpolator. The interpola-

Manuscript received April 19, 2010.Manuscript revised September 14, 2010.†The authors are with School of Information and Communica-

tion Engineering, Inha University, Incheon, 402-751, Republic ofKorea.

a) E-mail: hhlee@inha.ac.krDOI: 10.1587/transfun.E94.A.937

tor is generally used to calculate new samples at arbitrarytime instants in between existing discrete-time samples. Apolynomial-based interpolation filter can be efficiently im-plemented by using Farrow architecture [4]. The interpola-tion methods using polynomials have been investigated in[5], [6]. Among others, spline interpolations are very usefulmethods for smoothing out noisy data [7]. This is becausethey offer a good tradeoff between simplicity and efficiencyin controlling the degree of smoothing.

In this paper, we present a low-complexity FIR filterand interpolator for ATSC DTV tuner. Also, a novel archi-tecture of the FIR filter and interpolator are proposed withthe aim of reducing hardware complexity and improving in-terpolation efficiency. This design has a lower number ofgate counts and a shorter critical path delay in comparisonto the conventional architectures.

In Sect. 2, a comprehensive introduction of the ATSC8-VSB system is given. The proposed FIR filter and inter-polator are presented in Sect. 3. In Sect. 4, the results andperformance comparisons are given. Finally, conclusionsare presented in Sect. 5.

2. ATSC-8VSB System

2.1 ATSC 8-VSB Transmitter

The 8-VSB (Vestigial Side Band) is the modulation schemeused for USA’s digital television broadcasting. It supportsdata transmission rates of 19.39 Mbps with 6 MHz. Thetransmitter of the ATSC 8-VSB is shown in Fig. 1(a), inwhich the MPEG-2 Transport Stream (TS) comprised of 188bytes, is received with data rates of 19.39 Mbps. After thetransport streams of 187 bytes, except for sync bytes, aredispersed as energy, Reed-Solomon (RS) codes are used toencode the TSs. After interleaving the data encoded with theRS codes, the convolution encode is carried out. The con-volution encoded bit is modulated with a symbol composedof eight levels, and then transmission symbols are generated.The transmission symbol is a transmitted 8-VSB signal witha bandwidth of 6 MHz after being filtered at the VSB mod-ulator.

2.2 ATSC 8-VSB Receiver

The 8-VSB receiver is composed of a phase tracker, equal-izer, Intermediate Frequency (IF) filter, and synchronousdetector. Also, it includes a convolution and RS decoder

Copyright c© 2011 The Institute of Electronics, Information and Communication Engineers

938IEICE TRANS. FUNDAMENTALS, VOL.E94–A, NO.3 MARCH 2011

for error compensation. The 8-VSB receiver is shown inFig. 1(b). After the tuner selects a desired channel and fil-ters an intermediate bandwidth from the IF filter, the tunersearches a carrier wave frequency. After the synchronousdetector searches for a synchronous signal and clock, theequalizer eliminates any multi-path interference. Next, thephase tracker compensates for any phase error left behindafter a signal passes through the equalizer.

2.3 Specification of ATSC 8-VSB Tuner

According to the ATSC DTV standards, DTV informationincluding video and audio must first be compressed intoMPEG-2 format. Then, the digital data are also modu-lated with 8-VSB and up-converted to the desired Radio Fre-quency (RF) channel for transmission. The system specifi-cation for the 8-VSB tuner is shown in Table 1. The channelbandwidth is 6 MHz, which is the frequency, when the zero-IF signal is up-converted to a low-IF signal.

For practical communication systems, the desiredchannel usually receives multiple interferences. The inter-ferences generate distortion components in the desired chan-nel due to the unavoidable nonlinear characteristics of thedevices used during the implementation of the TV tuner. As

Fig. 1 Block diagram of ATSC 8-VSB systems. (a) transmitter, (b)receiver.

Table 1 System specification for 8-VSB tuner.

a result, the power level of those interferences channels canbe 40 dB higher than the desired channel. In addition to thelinearity requirement, a sharp selection ratio is necessary toattenuate the interference channel enough at the output ofthe tuner so that the analog-to-digital converter (ADC) in thedemodulator is not saturated. In the worst case scenario, thetuner has to provide over 50 dB attenuation for the adjacentchannel. Another important specification listed in Table 1is the image rejection ratio. Because the final intermediatefrequency is 44 MHz in this specific application, the imagechannel is 88 MHz away from the desired channel. There-fore, the required image rejection ratio is usually over 60 dB.This image rejection requirement is an important factor forthe design of the DTV tuner.

3. FIR Filter and Interpolator Design for DTV Tuner

As shown in Fig. 2, the DTV tuner consists of a digital FIRfilter, interpolator, up-converter, and analog circuits. In thissection, we present the methods for designing the digital FIRfilter and interpolator.

3.1 Modeling of FIR Filter System

The digital FIR filter is a system in which each output sam-ple is the sum of a finite number of weighted samples ofthe input sequence. The effect of the Linear Time Invari-ance (LTI) system on the magnitude and phase of the inputcomplex exponential signal is determined by the frequencyresponse H(e jω). If the input is x[n] = Aejϕe jωn, then byusing the polar form of H(e jω), the result below is given:

y[n] = |H(e jω)|e j∠H(e jω) · Aejϕe jωn

= (|H(e jω)A|) · e j(∠H(e jω)+ϕ)e jωn (1)

The notation |H(e jω)| is referred to as the gain of thesystem. In order to design the FIR filter, the type of filter andcoefficients of the transfer function have to be determined.

Next, it is required that an in-out bit of the FIR filteris considered and implemented by analyzing the quantiza-tion of the coefficients. That is, the fixed-point simulationfor the FIR filter is required. For the fixed-point simulation,

Fig. 2 Block diagram of DTV tuner.

KIM et al.: LOW COMPLEXITY FILTER ARCHITECTURE FOR ATSC TERRESTRIAL BROADCASTING DTV SYSTEMS939

Table 2 Digital FIR filter specifications.

Fig. 3 Magnitude frequency responses of the FIR filter.

Table 3 Coefficients of FIR filter lookup table.

it is necessary to extract the coefficients that meet the spec-ification of the FIR filter by using a MATLAB FDA (Fil-ter Design Analysis) tool as shown in Table 2. Since thebit width of the defined filter output is 12-bits, the coeffi-cients extracted by using the FDA tool need to be convertedto proper values in order to set the output bit of the filter

to 12-bits. Figure 3 shows the frequency response that usesproper coefficients. The converted filter coefficients havebeen selected with the lowest quantization error. Table 3shows the coefficients lookup table of the proposed FIR fil-ter, in which the index k and coefficient h(k) represent thecoefficient number and coefficients generated using MAT-LAB FDA tool. hbinary(k) is binary coefficients which wasconverted from the decimal coefficients h(k). hf ixed−point(k)is 16-bit coefficients which has been obtained using fixed-point simulation and meet the specification of digital FIRfilter in Table 2. To get the hf ixed−point(k), hbinary(k) was usedas parameters in the fixed-point simulator.

3.2 Low Complexity FIR Filter Design

With respect to the FIR filter in the DTV tuner, low com-plexity is the primary goal for minimizing the hardware sizeand power consumption. Therefore, various low area re-duction strategies have been applied. To reduce hardwarecomplexity, several techniques such as the filter design withnon-multiplier, Canonical Signed Digit (CSD) representa-tion of coefficients, and folding techniques are used.

The FIR filter with non-multiplier can be implementedby using the shift and add operator. For example, a multi-plied B with A=0.11011 can be expressed as B � 1 + B �2 + B � 4 + B � 5, where � is the right bit shift opera-tor. After the filter coefficients are obtained, it is possible tofind the correct activated bit. Therefore, effective arithmeticcan be carried out by using the required quantity of shift andadding operators for coefficients.

It is generally well known that Common Sub-expression Elimination (CSE) methods based on CSD co-efficients can reduce the number of adders required for themultipliers of FIR filters. CSD methods have been used tominimize the non-zero bits. However, CSD methods are notappropriate for the high order FIR filter design. As shown inTable 2, the desired number of FIR filter taps is 138. In [8],a CSE algorithm using binary representation of coefficientsis presented for the implementation of a higher order FIR.The FIR filter using this algorithm has a lower number ofadders than that of the CSD-based CSE method. The CSEmethod, which is also called Binary Sub-expression Elimi-nation (BSE), is used to eliminate a redundant binary Com-mon Sub-expression (CS) that occurs within a coefficient.In Fig. 4, a binary number can be formed with three terms,which are [101], [1101], and [100001]. It is assumed that x1

is an input signal. These CSs can be expressed as

[101] = x2 = x1 + 2−2x1 (2)

[1101] = x3 = x1 + 2−2x1 + 2−3x1 (3)

[100001] = x3 = x1 + 2−5x1. (4)

If more than one CS occurs between a coefficient pair,the CSs can be grouped together to reduce the redundantarithmetic. As shown in Fig. 4, the number of same CS istwo and these terms are composed of same portions namedD, E, and F, respectively.

940IEICE TRANS. FUNDAMENTALS, VOL.E94–A, NO.3 MARCH 2011

Fig. 4 Representation of filter coefficients using BSE.

Table 4 Number of grouped common sub-expressions of FIR filter (138taps).

In Table 4, the occurrence frequency of a CS is definedas the number of the same CS being reused or repeated forthe filter coefficients. The number of grouped CSs for a bi-nary representation of coefficients is smaller than the CSDrepresentation of coefficients. Therefore, the binary repre-sentation of coefficients is more favorable for reducing theadders in the filter.

Overall, the FIR filter architecture is a transposed formrealized from using thirteen CSs, which are [101], [10101],[101001], [1011], [110], [1101], [11001], [111], [1111],[1001], [10011], [10001], and [100001] inside the circleshown in Fig. 5. The input signal x0, output signal y, thirteenCSs (x1 to x13), and convolution computation parts (h0 ∗ xto h69 ∗ x) with a filter coefficient are placed. The accumu-lation part is composed of a symmetrical structure becausethe filter has linear phase characteristics. In the commonsub-expression part, the CS [101] can be expressed as mark� 2. This expression is meant to be shifted two bits to theright. Similarly, the CS [10101] can also be expressed asmark� 4 because it is shifted four bits to the right from theCS [101]. Each CS is connected to other filter coefficientsfor convolution computation. Finally, the processed CSs areaccumulated and delayed at the accumulation block. Thisarchitecture can be designed without any extra multiplier.

Fig. 5 BSE realization of FIR filter with coefficients.

Fig. 6 Interpolation using Cubic spline function.

3.3 Interpolation Filter Design Using Spline Function

Spline-based interpolation is a convolution-based interpola-tion where the interpolation kernel is a piecewise polyno-mial generated by a B-spline. It is composed of two oper-ations: a preliminary iterative filtering to get the spline co-efficients and a mixed discrete-continuous convolution thatgenerates reconstructed samples at the interpolation range.Usually, B-splines of three degree (cubic) are preferred, asthey provide a sufficient quality and acceptable computa-tional load. As shown in Fig. 6, the cubic spline interpola-tion is a piecewise continuous curve with continuous firstand second order derivatives. A third degree polynomial isconstructed between each point. In Fig. 2, it is assumed thatthe samples passed through the FIR filter are y(nTs). Af-ter the FIR filter, samples y(nTs) are taken at uniform in-

KIM et al.: LOW COMPLEXITY FILTER ARCHITECTURE FOR ATSC TERRESTRIAL BROADCASTING DTV SYSTEMS941

tervals, Ts. The samples at correct symbol timing, t = kT ,is interpolated from the samples y(nTs) by using an inter-polator. Based on the interpolation theory, the value of areconstructed signal yrecon(t) can be expressed as

yrecon(kT ) =∞∑

n=−∞y(nTs)h(t − nTs) (5)

where h(t) is the interpolation function. In cubic B-spline,Eq. (6) can be substituted for Eq. (5). That is, Eq. (6) can bechanged into

yrecon(kT ) =1∑

l=−2

c((nk − l)Ts)β3((l + μk)Ts) (6)

where β3 is the cubic B-spline function, c(nTs) are B-splinecoefficients, and μk is the fractional interval [9]. Assumingμk = 0, coefficients can be determined by using Eq. (6)

y(nTs) =1∑

l=−2

c((n − 1)Ts)β3(lTs)

=16

(c((n + 1)Ts) + 4c(nTs) + c((n − 1)Ts))

= (c ∗ hd)nTs (7)

With the aid of the z-transform, the equation can beexpressed as [9]:

c(z) =Y(z)Hd(z)

(8)

where Hd(z) = 16 (z + 4 + z−1).

In Fig. 9, there are two parts, which are the IIR filterand approximate FIR filter [10]. In the IIR filter, the B-spline coefficients are determined by using input samplesy(nTs). In the Farrow interpolation filter, the reconstructedsamples yrecon(t) are calculated. The Farrow polynomial ap-proximations [10]. According to the piecewise polynomialmodel, the generation of reconstructed samples at an arbi-trary position is possible. The cubic polynomial degree inthe Farrow structure is represented by a 4 × 4 matrix. Inthe case of cubic B-spline interpolation kernel, the recon-structed samples are generated by the following equation[11]:

S (x) =16

[1 μ μ2 μ3] ·

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎣−1 3 −3 13 −6 3 0−3 0 3 01 4 1 0

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎦ ·⎡⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎣ck−1

ck

ck+1

ck+2

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎦ (9)

An IIR filter has two poles at p1 = −2 +√

3 and p2 =1p1

. A preliminary iterative filter is divided into two filters asfollows [12]:

Hiter(z) =−6p1

1 − p21

(1

1 − p1z−1

)+

6p1

1 − p21

⎛⎜⎜⎜⎜⎝ z

z − p−11

⎞⎟⎟⎟⎟⎠= H1(z) + H2(z) (10)

H1 is a 1 tap IIR filter and H2 is an approximate FIR

filter, respectively.

4. Proposed Partially Folded FIR Filter and Spline In-terpolator Using Sub-Filter

4.1 Proposed Partially Folded FIR Filter Architecture

Folding techniques have been proposed as a means of re-ducing the hardware complexity. The FIR filters are idealcandidates for folding since they are a repetition of multi-plication. A significant advantage of the folded FIR filterarchitecture is that they lead to reduced hardware complex-ity compared to the corresponding unfolded schemes and theclock skew problem does not exist. Also, combined foldedand unfolded filters are much more efficient compared tothe full folded filters. The partially folded filter is an inter-mediate form between the folded and unfolded form of thefilter featuring higher throughput than the fully folded, andrequiring less hardware than the unfolded.

In this paper, a partially folded FIR filter design in atransposed form is considered by using 6-to-1 multiplexer(MUX) instead of a delay register. By using 6-to-1 MUX inthe multiplier block as shown in Fig. 7, it is expected that thetotal area of the FIR filter can be reduced than the structureusing the delay register [12]. This architecture is composedof 23 stages including 23 MUXes, which select filter coeffi-cients according to the control signal, because the number of

Fig. 7 Proposed partially transposed folded FIR filter architecture.

Table 5 Scheduling order of filter output at stage 1.

942IEICE TRANS. FUNDAMENTALS, VOL.E94–A, NO.3 MARCH 2011

Fig. 8 Interpolation after moving random value from input y0.

unfolded filter taps and folding factors is 138 and 6, respec-tively. The advantage of this architecture is that it can selectcoefficients without any extra delay operation compared tothe conventional folded architectures. Therefore, it can leadto a much reduced hardware complexity. The data flow ofstage 1 is shown in Table 5. The initial values at the registersare d5, d4, d3, d2, d1, and d0. The computed parts with filtercoefficients and input data are fed into the registers sequen-tially (D0 to D5) during six clock cycles. At the first clock,the processed value (y0+ d1) in the multiplier block is fedto D5, where y0 becomes h0*x(n). When the next processedvalue (y1 + d2) is fed to D5, the previous processed value(y0+d1) moves to D4. These processes progress until all theprocessed values in the multiplier block are fed to the entireregister. At this time, the control signal of 2-to-1 MUX be-comes “1” and the value of d6 at stage 2 is fed to the adderat stage 1. From this process, the first clock cycle to obtainthe output is finished. However, the processing to obtain theother outputs, six clock cycles are required.

4.2 Proposed Cubic B-Spline Interpolator Using Sub-Filter

In this section, Cubic B-spline interpolator architecture us-ing sub-filter is presented. The disadvantage of the conven-tional cubic-B spline is the increase of errors at a rapid slant.This leads to a deteriorated performance of the filter. Asshown in Fig. 8, it is possible to estimate the samples by us-ing the spline polynomial after going by t. At this time, thedashed line placed on high is more deteriorated in compari-son to the original signal that indicates a solid line. In orderto decrease the errors, it is necessary that the sample closedto the original curved line should be obtained if a sampleat y0 can be moved to a position that has a sample value ofy0 + α. By moving α up or down, the performance of inter-polation can be improved. A movement α can be expressedas a form of the sub-filter, as shown in Fig. 9(a). Also, theoverall spline interpolation architecture can be divided intothree parts by Eq. (10): a composed IIR filter, an approx-imate FIR filter, and a cubic B-spline reconstruction filter.In general, the Farrow architecture of the continuous delaycontrol has been widely used in designing the interpolationfilter [4]. This structure has the disadvantage of increasingthe constant multiplier and delay according to the filter coef-ficient. However, the cubic B-spline interpolation architec-ture has six constant multipliers, twelve adders, and three

Fig. 9 Proposed block diagram of (a) spline interpolation filter usingsub-filter before reconstructing samples, (b) IIR filter H1(z), (c) partiallyfolded approximate FIR filter H2(z).

delay devices. Figure 13 shows the frequency characteris-tics and phase delay of spline interpolation filter using sub-filter, in which the approximate FIR filter system is modeledaccording to the specifications in Table 6. The fixed-pointsimulation is carried out for the approximate FIR filter de-sign. Figure 11 shows the magnitude response of approxi-mate FIR filter. To verify the efficiency of the cubic B-splinefilter, a sub-filter can be modeled. First, the step size knownto affect the steady state error is considered. A minimumstep size is set to 0.0035 because it is a moment that has aoptimal state error.

After deciding the minimum step size, the initial valuesare set to 0 and added or subtracted by 1 of initial step sizevalue. The results generated by doing this are applied to sub-filter shown in Fig. 9(a). The c(nTs) generated from Fig. 9(a)

KIM et al.: LOW COMPLEXITY FILTER ARCHITECTURE FOR ATSC TERRESTRIAL BROADCASTING DTV SYSTEMS943

Table 6 Specifications of approximate FIR filter.

Fig. 10 Cubic B-spline interpolation Farrow architecture forreconstructed samples.

is connected to the Cubic B-spline interpolation Farrow ar-chitecture for reconstructed samples as shown in Fig. 10. Iffinal pass-band ripple error generated after passing throughthe architecture in Fig. 10 is reduced, the step size is set tohalf and the previous processes are repeated. These pro-cesses are continued until the pass-band ripple error has thesmallest value. The processes to determine the sub-filter canbe described as follows.

1. First, define the sub-filter applied to the previous partof the reconstruction filter. α = ck x(n + k) + ck+1x(n +k − 1) · · · + c1x(n − l)

2. Set the interval carried out an interpolation. (k = 1, l =1, c−1 = 0, δ = 1, where δ is step size.)

3. Generate initial coefficients. {c−k + δ, c−k+1 + δ, cl + δ},{c−k − δ, c−k − δ, cl − δ}

4. For each coefficient, set the interpolation interval to 0to 1. Calculate the ripple error of the pass-band widthby increasing its gap by 0.1.

5. Find the coefficients that have a minimum ripple errorin Stage 4.

6. If the ripple error of the pass-bandwidth doesn’t de-crease, shorten the interpolation interval by half andthen, start the Stage 3.

7. If this does not satisfy the desired specification of thefilter, carry out the Stage 3 again with the increased

Fig. 11 Magnitude response of approximate FIR filter.

Fig. 12 Frequency characteristics and phase delay of continuous delaycontrol interpolation filter.

filter length.

A sub-filter obtained by the above method can be ex-pressed as Eq. (11).

α = −0.054x(n + 3) + 0.0031x(n + 2) − 0.075x(n + 1)

+ 0.68x(n) + 0.041x(n − 1) + 0.094x(n − 2) (11)

Figures 12 and 13 compare the ripple error and phasedelay for the continuous delay control architecture and pro-posed architecture. The phase delay can be a importantmeasure for fulfilling the interpolation. If the phase delayis increased by the sample rate conversion, then it is im-portant that the synchronization between the input and out-put should be adjusted. Because of this, calculating the de-gree of ripple error and phase delay after interpolating cantell us whether the synchronization is carried out well ornot. The responses corresponding to the delay values d =0.1, 0.2, · · · , 0.5 are shown in Figs. 12 and 13.

They show that d (= 0.1) is equal to that of d (=0.9) forthe even-length (L=4) filter, and the corresponding phase de-lay responses are symmetric with respect to the curve of d(=0.5). At the low frequency, the phase delay curves arenearly constant, but at the high frequency they approachthe integer delay, which is in the case of ‘2’ as shown in

944IEICE TRANS. FUNDAMENTALS, VOL.E94–A, NO.3 MARCH 2011

Fig. 13 Frequency characteristics and phase delay of spline interpolationfilter using sub-filter.

Table 7 Implementation results of several FIR filter architectures.

Fig. 12, and ‘3’ as shown in Fig. 13. For Figs. 12 and 13, theripple error of the pass-bandwidth and phase delay valuesover continuous delay control architecture are 0.0262 and0.00612, respectively. However, the ripple error and phasedelay of the proposed architecture are 0.0115 and 0.00383,respectively. This shows that the proposed architecture has amore advantageous position in ripple error and phase delaythan the continuous delay control structure.

5. Results and Comparison

The proposed partially folded FIR filter and overall interpo-lation filter were designed in Verilog HDL and simulated toverify its functionality by using MATLAB and ModelSim6.0 SE. The proposed architectures were synthesized usingappropriate time and area constraints. The synthesis stepswere carried out by using SYNOPSYS design tools and 90-nm CMOS technology optimized for a 1.1 V supply voltage.

Table 7 shows the implementation results of the pro-

Table 8 Implementation results of the proposed Cubic B-spline structureusing sub-filter and continuous delay control architecture.

posed partially folded FIR architecture, unfolded architec-ture, and conventional folded architecture. The proposedpartially folded FIR filter architecture operates approxi-mately at a clock frequency of 200 MHz, and requires ap-proximately 60% and 12% fewer gate counts than the un-folded and conventional folded architectures, respectively.The latency of the proposed architecture is six times longerthan that of the unfolded architecture, because the folded ar-chitecture has a folding factor of six. In the unfolded part,the architecture using coefficients expressed as binary rep-resentation has 6% less hardware complexity than the archi-tecture using coefficients expressed as CSD representation.

Table 8 shows the implementation results of the over-all interpolation filter architectures. The proposed cubic B-spline interpolation filter architecture using the sub-filter has16% less hardware complexity than the conventional con-tinuous delay control architecture. It also operates approx-imately at the clock frequency of 385 MHz. Because theproposed interpolation filter has a folding factor of six, itslatency has six times longer than that of the unfolded archi-tecture.

6. Conclusion

This paper presents the design and implementation of thepartially folded FIR filter and cubic B-spline interpolationfilter using sub-filter for ATSC broadcasting DTV systems.To implement a low complexity FIR filter, the optimiza-tion of filter coefficients was needed. To do this, a com-mon sub-expression elimination method, which shares coef-ficients expressed as binary representation, is used. Insteadof using a delay unit, a control method of the filter coeffi-cients using a multiplexer is proposed. As a result, the pro-posed architecture has 60% less hardware complexity thanthe unfolded architecture. Also, it has 12% less hardwarecomplexity than the other folded architecture.

The overall interpolation filter architecture using sub-filter and cubic B-spline has a more efficient interpolationperformance. Also, it has 16% less hardware complexitythan the conventional continuous delay control architecture.The proposed FIR filter and interpolator has potential appli-cations in DTV tuner for ATSC broadcasting DTV systems.

Acknowledgments

This research was supported by the MKE/KEIT, Korea

KIM et al.: LOW COMPLEXITY FILTER ARCHITECTURE FOR ATSC TERRESTRIAL BROADCASTING DTV SYSTEMS945

(KI002145).

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Yong-Kyu Kim received B.S. degree andM.S. degrees, both in information & commu-nication engineering from Inha University, In-heon, Korea in 2008 and 2010 respectively. Hisresearch interests are digital VLSI circuits andsystems for digital signal processing (DSP) in-cluding design and implementation of efficientfilter architectures.

Chang-Seok Choi received B.S. degree ininformation & communication engineering fromHanshin University in 2005 and M.S. degree ininformation & communication engineering fromInha University, Incheon, Korea, in 2007, re-spectively. He is currently working toward thePh.D. degree in Inha University. His researchinterests are digital VLSI circuits and systemsfor digital signal processing (DSP) including de-sign and implementation of efficient filter archi-tectures.

Hanho Lee received the Ph.D. and M.S.degrees, both in Electrical & Computer En-gineering, from the University of Minnesota,Minneapolis, in 2000 and 1996 respectively,and the B.S. degree in Electronics Engineer-ing from Chungbuk National University, S. Ko-rea, in 1993. In 1999, he was a Member ofTechnical-Staff-1 at Lucent Technologies, BellLabs, Holmdel, NJ. From April 2000 to Au-gust 2002, he was a Member of Technical Staffat the Lucent Technologies (Bell Labs Innova-

tions), Allentown, where he was responsible for the development of VLSIarchitectures and implementation of high-performance DSP multiproces-sor SoC for wireless infrastructure systems. From August 2002 to August2004, he was an assistant professor at the Department of Electrical & Com-puter Engineering, University of Connecticut. Since August 2004, he hasbeen with the School of Information and Communication Engineering, InhaUniversity, where he is presently an Associate Professor. His research in-terests include design of VLSI circuits and systems for communications,System-on-a-Chip (SoC) design, reconfigurable architecture, and forwarderror correction coding.