Lord of the Board Amps

8/12/2019 Lord of the Board Amps

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e o r ea er n g er ormance g na r ocess ng o u ons

High-Speed Printed Circuit

John Ardizzoni Dennis Falls

Analog Devices Avnet Electronics Marketing


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A enda

Overview

SchematicLocation, location, location

Power supply bypassing

ParasiticsGround and power planes

Packaging

RF Si nal routin and shieldin

Checking the layout

Summary

2


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Overview

PCB la out is one of the last ste s in the desi n rocess and

often one of the most criticalHigh-speed circuit performance is heavily dependant on

la out

A high-performance design can be rendered useless due to apoor or sloppy layout

Improve the layout process

Ensure expected circuit performance is achieved

Lower cost

Lower stress for you and the PCB designer

3


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Schematic


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Schematic

The stren th of an structure includin PCBs is onl as

good as the foundation on which it built upon!A good layout starts with a good Schematic!

Include as much information as you can

What should you include?

5


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Items to Include on a Schematic

Notes

Component tolerances and case sizes

Part numbers (internal/external/alternative)

Board stack up

es s or a gnmen proce ures

Power dissipation

Controlled impedance and line matching -

Thermal requirements

Keep outs

Critical component placement

Warning flags

What ever else ou can think of!

6


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Schematic40 MHz

C1

0.1uF

U1

+5V

R6301

S1C4

2.2uF

+5V

40 MHz

OSC Out

Must be right atop amp supply

pins

Put C4 and C7 onback of board

right under thepower supply pin.

Run 40MHz traces on bottom

Place this cap right at pin 14 to digital ground

+

R3

562 ADA4860-1

-

+

R4

210

C5

0.01uF

R5562

C2 C3

C60.01uF

U2

VIN

VOUT

R2

R7

50

of the board ensure signal

trace is the same length

40 MHzOSC Out

R1

1K

Linear Regulator

-5V

SAT SAT2.2uF

U3

U4D11N4148

Must be right at

op amp supplypins

+5V

+5V

FREQUENCY ADJUST1.0 C2=C3, use these 2 capacitors to adjust the -3dB BW

i l

+

See critical component placement

drawing for location

AD590

ADP667

Sensor+12V +5

V

VOUT

Linear Regulator

-12V -5V

+ +

U5

D21N4148

C810uF

Casesize

1210C9

0.01uF

C110.1uF

C12

10uFCase

size1210

C13 C16

-5V

+5V

R81K

1K

erating able

R1

R2

R3

C1

C2

C3

U1

U2

VALUE

1

2

3

4

5

6

7

8

62mW 10mW

ITEM REF DES ACTUALRATING

++

Casesize1210 C14

0.1uF

C150.1uF

10u

Case size1210

2.0 All Resistors in ohms unless noted otherwise.3.0 All capacitors in pF unless noted otherwise.

6 0 U1SOIC-14 U2SOT-23-6 U3 SOIC-8 U4SOIC-80.062"

Signal 1

Analog Ground 1

Digital GroundPower plane

l

BOARD STACK UP1.0 All resistors and capacitors are 0603 case size unless noted otherwise.

4.0 Run analog traces on Signal 1 layer, run digital traces on Signal 2 layer

NOTES:

5.0 Remove ground plane on all layers under the mounting pins of U2

7

. , , , ,nalog roun

Signal 2


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Location, location, location!


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Location Location Location

Input/output and power connections are typicallydefinedEverything else is undefined

Crit ical component placement

Signal routing

9


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Trust No One


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Trust No One

If oure doin our ownlayout, thats one thing.

If youre not .

11


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Trust No One


If youre not .

Dont assume the CAD rou isgoing to read your mind and getit right!

12


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Trust No One


If youre not .


In the end youre responsiblefor making it work!

13


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Trust No One


If youre not .


Youre responsible for making itwork!

When working with the CADGroup

14


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Trust No One


If youre not .




Make sure you and the designerare on the same page

15


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Trust No One


If youre not .





Brief circuit explanation

16


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Trust No One


If youre not .






17



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Trust No One

If youre doing your ownlayout, thats one thing.

If youre not .Dont assume the CAD group is

it right!


When working with the CADGroupMake sure you and the designer



18


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Trust No One

If youre doing your own layout,a s one ng.

If youre not . Dont assume the CAD group is

oin to read our mind and et itright!


Group Make sure you and the designer

are on the same page


Input/Output connections

Board outline drawing and stack up

19


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Trust No One

If youre doing your own layout,.

If youre not . Dont assume the CAD group is

going to read your mind and get itr g


When working with the CAD Group Make sure you and the designer

are on the same page


Critical com onent lacement

Input/Output connections Board outline, stack up

Tell them to call you if they have a

20


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Power Supply Bypassing


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Power Su l B assin

B assin is essential tohigh speed circuitperformance

22


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Power Su l B assin


Ca acitors ri ht at owersupply pins

23


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Power Su l B assin



Capacitors provide low AC

impedance to groundProvide local charge storage

for fast rising/falling edges

24


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Power Su l B assin


Ca acitors ri ht at owerIC

+VSL1

1H

supply pins


impedance to ground

C1

0.1F

Provide local charge storagefor fast rising/falling edges

Keep trace lengths short

EQUIVALENT DECOUPLED POWER

LINE CIRCUIT RESONATES AT:

f =1

2 LC

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Power Su l B assin







26


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Power Su l B assin

B assin is essential tohigh speed circuit

performance






Close to load returnHelps minimize transient

currents in the ground plane

27


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Power Su l B assin

Bypassing is essential tohigh speed circuit

performanceCapacitors right at power

Capacitors provide low ACimpedance to ground

Provide local char e stora efor fast rising/falling edges


Close to load return

Helps minimize transientcurrents in the ground plane

Values

28


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Power Su l B assin

Bypassing is essential tohigh speed circuit

performanceCapacitors right at power

Capacitors provide low ACimpedance to ground

Provide local charge storage for


Close to load return

in the ground planeValues Individual circuit performance

29

Maintains low AC impedance


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Power Su l B assin

Bypassing is essential tog spee c rcu

performanceCapacitors right at powersupply pins Capacitors provide low AC

impedance to ground Provide local charge storage for

fast rising/falling edges

Close to load return Helps minimize transient currents

in the ground plane

Values Individual circuit performance Maintains low AC impedance Multi le resonances

30


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Power Su l B assin

Bypassing is essential to highspee c rcu per ormance

Capacitors right at powersupply pins

impedance AC return

Provide local charge storage forfast rising/falling edges

Close to load return Helps minimize transient currents

in the ground plane

a ues Individual circuit performance Maintains low AC impedance

31

Ferrite beads


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Parasitics


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Parasitics

Parasite An or anism that rows feeds and is sheltered onor in a different organism while contributing nothing to the

survival of its host.

Parasit ics in high-speed PCBs, can destroy circuitperformance!

33


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Parasitics

PCB parasites take the form of undesired capacitors,

Parasitics are extremely difficult to remove from a PCBPrevention is the best method to minimize parasitics

34


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Trace/Pad Ca acitance

dA

kA=d3.11

A = area in cm2

d = spacing between plates in cm

35


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dA Example: Pad of SOIC

L = 0.2cm W = 0.063cm

K= 4.7

A = 0.0126cm2

dC

3.11= d = 0.073cm

C = 0.072pF

A = area in cm2


36


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Example: Pad of SOIC

dA

. .

K= 4.7

= 2

d = 0.073cm

C = 0.072pF

dC

3.11=

A = area in cm2


Reduce Capacitance

1) Increase board thickness or layers

2) Reduce trace/pad area

3) Remove ground plane

37


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A roximate Trace Inductance

38

All dimensions are in mm


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Example


L= 25.4mm

W = .25mm

H = .035mm (1oz copper)Strip Inductance = 28.8nH

39

z L = . a . errorin a 50 system


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Example


Minimize InductanceL= 2.54cm =25.4mm

W = .25mm1) Use Ground plane

2) Keep length short (halving

H = .035mm (1oz copper)Strip Inductance = 28.8nH

inductance by 44%)

3) Doubling width only

40

z L = . a . errorin a 50 system

11%


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Via Parasitics

Via Inductance Via Capacitance

155.0 TD

r

L = inductance of the via, nH

D2 = diameter of clearance hole in theground plane, cm

nH

+

1ln2d

hL12

DD

H = length of via, cm

D = diameter of via, cm

1 = ame er o pa surroun ng v a, cm

T = thickness of printed circuit board, cm

= relative electric permeability of circuitboard material

C = arasitic via ca acitance F

r

Given:

H= 0.157 cm thick board,

D= 0.041 cmGiven:

T = 0.157cm,

L ~ 1.2nh 1= . cm

D2 = 0.127

C ~ 0.51pf

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Via Cross Section

2

D1

42


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Ca acitor Parasitic Model

LRP

RS

r

C

C = Capacitor

RDA

CDA

RP = insulation resistanceRS = equivalent series resistance (ESR)

L = series inductance of the leads and plates

43

DA

CDA = dielectric absorption


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Resistor Parasitic Model

P

R = ResistorCP = Parallel capacitance

44


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Low Fre uenc O Am Schematic

45


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Hi h S eed O AmSchematic

46


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Hi h S eed O AmSchematic

Parasitic Capacitance

47


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48

http://www.analog.com/en/design-tools/dt-multisim-spice-program-download/design-center/index.html


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Stra Ca acitance Simulation Schematic

49


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Frequency Response with 2pF Stray Capacitance

1.8dB peaking

50


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Stra Inductance

Parasitic Inductance

51


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Parasitic Inductance Simulation Schematic

AD8055 24.5mm x .25mm =29nH

52


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Pulse Res onse With and Without GroundPlane

0.6dB overshoot

53


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Transient Res onse AD80091GHz Current Feedback Amplifier

RF402

+5V

10uF

402

RG

0.1uF

150

0.1uF

-5V

u

54


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Small Chan es Can Make a Bi Difference!

55

Circuit BCircuit A


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Im ro er Use of Sco e Probe Ground Cli

56


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Effect of Cli Lead Inductance

57


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Pro er Groundin for Sco e Probe in Hi h-

Speed Measurments

58


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Small Chan es Make Bi Differences

Circuit BCircuit A

21ns 17ns

59

25% reduction in ringing duration and amplitude


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Ground and Power Planes

G d d P Pl P id


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Ground and Power Planes Provide

A common reference oint

Shielding

Lower noise

Lower impedance

Reduces parasitics

Heat sink

Power distribution

61

G d Pl


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Ground Plane

I

62


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DigitalAnalog Resistor

ClockWrong Way

Input Connector

Sensitive Analog

Circuitry Disrupted by

ID

ANALOG

CIRCUITS

DIGITAL

CIRCUITSVD VA

+ +

IA

INCORRECT

63 IDIA + IDGND

REF


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DigitalAnalog Resistor

ClockWrong Way

Sensitive Analog

Circuitry Disrupted by

ID

ANALOG

CIRCUITS

DIGITAL

CIRCUITSVD VA

+ +

IA

INCORRECT

64ID

IA

+ ID

GND

REF


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Digital

Analog

CircuitryResistor

Right Way

Clock

Circuitry

Sensitive Analog

Circuitry Safe from

Digital Supply Noise

ID

IA CORRECT

ANALOGCIRCUITS

DIGITALCIRCUITS

VD VA

+ +

VIN

65 ID

IAGND

REF


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Digital

Analog

CircuitryResistor

Right Way

Clock

Circuitry

Sensitive Analog

Circuitry Safe from

Digital Supply Noise

ID

IA CORRECT

ANALOGCIRCUITS

DIGITALCIRCUITS

VD VA

+ +

VIN

66 ID

IAGND

REF


67/107

Grounding Example:

To la er is solid round.

Res

istor

Signal

Input Termination

Bottom has a trace/transmission lineconnecting the RF connector to theload.

Top Side

Resistor

e urn curren ows n e op ayerground plane directly above the traceon the opposite side.

Bottom side

67


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Grounding Example: DC Current vs. ACCurrent:

AC currentfollows the

path of least

impedance

In a split or broken ground, the returncurrents follow the path of least

Resistor

mpe ance

At DC, the current follows the path ofleast resistance

curren

follows the

path of least

resistance

,current follows the path of leastinductance

Since there is now a loop theinductance can be quite high and the

circuit can now propagate EMI/RFI

68

Groundin Mixed Si nal ICs: Sin le PC Board


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Groundin Mixed Si nal ICs: Sin le PC Board

VA VD

MIXEDVA VD

CIRCUITS CIRCUITS

AGND DGND

SIGNAL

DEVICESYSTEM

STAR

A A D D

ANALOG

GROUND PLANE

DIGITAL

GROUND PLANE

DA

DIGITALANALOG

69

SUPPLYSUPPLY

Ground Plane Recommendations


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Ground Plane Recommendations

There is no single grounding method which is guaranteed to work100% of the time!

emove groun p ane un er op amps o re uce paras ccapacitance

At least one layer on each PC board MUST be dedicated to groundlane!

Provide as much ground plane as possible especially under tracesthat operate at high frequency

Use thickest metal as feasible (reduces resistance and provides

Use multiple vias to connect same ground planes together

Do initial layout with split analog and digital ground planes

Keep bypass capacitors and load returns close to reduce distortionConnect analog, digital and RF grounds at one point

70


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Packaging and Pinout

O Am Packa in and Pinout


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O Am Packa in and Pinout

Packa in la s a lar e role in hi h-s eed a lications

Smaller packages

Better at higher speeds

Compact layout

Intuitively makes more sense

Compact layout

Lower distortion

72

O Am SOIC Packa in


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Traditional SOIC-8 layout

Feedback routed around or underneath amplifier

73

O Am SOIC Packa in


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Traditional SOIC-8 layout

Feedback routed around or underneath amplifier

74

Analo Devices Low Distortion Pinout


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Pinout enables com actOriginal Pin-Out

layout DisableFB 1

2

8

7IN +VS

+

-

NC

4 5VS

OUT

NC

1 8NC +VS

2

5

6

7FEEDBACK

IN

+IN

OUTPUT

NC

VS

3

4

4-0-001

75

0481

LFCSP



76/107


layout

Lower distortion

DisableFB 1

2

8

7IN +VS

+

-

4 5VS

OUT

NC

1 8NC +VS

2

5

6

7FEEDBACK

IN

+IN

OUTPUT

NC

VS

3

4

4-0-001

76

0481

LFCSP



77/107


layout

Lower distortion

DisableFB 1

2

8

7IN +VS

+

-

performance

4 5VS

OUT

NC

1 8NC +VS

2

5

6

7FEEDBACK

IN

+IN

OUTPUT

NC

VS

3

4

4-0-001

77

0481

LFCSP



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layout

Lower distortion

DisableFB 1

2

8

7IN +VS

+

-

performance

LFCSP4 5VS

OUT

NC

, , ,ADA4899, ADA4857, ADA4817

1 8NC +VS

2

5

6

7FEEDBACK

IN

+IN

OUTPUT

NC

VS

3

4

4-0-001

78

0481

LFCSP

Low distortion inout enables com act


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and streamline layout

79

Low distortion inout enable com act and


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streamline layout

Tantalum

CF

C

RL

AD80XX

RT

RG

00

Tantalum

80


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RF Components from Analog Devices


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htt ://www.analo .com/en/rfif-com onents/ roducts/index.html

83


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PC Board Circuit Material Type and Minimizing


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Losses

performance

Select PC board dielectric material to have the lowest loss tangent

GHz

PTFE(Teflon) dielectric material is usually used for the lowest loss

at the hi her RF and microwave fre uenc ran es but at a muchhigher price

Be sure that the correct impedance transmission line is used for theinterconnection of the RF devices

Use as wide of a transmission line as possible for the correct

impedance, and try to keep it short to reduce Skin Effect lossesUse high Q, or low loss passive components for all RF matching,

85

,

Microstri and Stri line Transmission Lines


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50 ohm interfaces are most often used between most integratedRF devices

Interconnects less than 1/20 of a wavelength long can usually be

made without a matched transmission lineAvoid lon microstri lines as the could become

antennas(microstrip) and radiate RF

To minimize coupling to the transmission line, DO NOT place othertraces or ground plane closer than three times of the dielectric

e gUse proper technique for making bends in microstrip lines

Locate the microstrip lines on the component side of the board if

86

Microstri Transmission Lines


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MicrostripControlled Impedance Line

ross ec on

Advantages:

Transmission line on outside layerof board

Easy to attach components to trace

Components can be placed atdifferent locations along the line toaid in tuning

Aid in RF testing as you are able tomeasure levels along the line

Disadvanta es: Slightly higher loss

Not shielded and could radiate RFsignal

TWZ

r

O

8.0

ln

41.1

87

Stripline Transmission Lines


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StriplineControlled Impedance Line

Cross Section

Advantages:

Lower loss at higher microwave

Shielded transmission line, no RFradiation from board

Disavantages:

Requires vias to connect to line

No ability to connect tuning or

No access to line to makeadjustments or connections to linefor RF testing TW

BZ

O

8.0

)(9.1ln

60)(

88

Higher PCB cost r

Microstri and Stri line Transmission Lines


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Bends in Microstrip and Stripline

In order to preserve a constantimpedance around a bend, some

followed

DO NOT make a right angle bend asshown

r g ang e en can e ma e wa swept bend, or a Mitered bend

Bends in a transmission line that areless than 90 degrees can also bemitered as shown

89

Ground Plane La out Considerations


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Do NOT have breaks or voids in the RF ground plane under, or overRF transmission lines

Ground plane Vias around the RF circuits should be spaced closer

than 1/20 of a wavelength as a minimum, or closer if possible at thehigher frequencies

Use as large size vias as practical to minimize inductance

Stitch the top and bottom ground planes together with as manyvias as possible

Signal and bias lines can be placed below RF ground plane layerfollowed by another power ground plane layer for the DC anddigital returns

,

plane with many closely spaced vias to transfer heat to all groundplane layers

90

Ground Plane La out Considerations


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Closel s aced vias under

Vias placed in ground

plane at each end ofthe DC bias bypass

components requiring heat

sinking

transmission line

Proper spacing of ground plane

Closely spaced Proper layout pattern for

away from transmission line(gap= 3 times dielectric height)

roun p ane v as

along transmission

line

Stitch ground

RF connector to PC board

91

p anes toget er

with multiple vias

on top and bottom sides of PC board

Developing a RF Printed Circuit oard


92/107

Draw Schematic of circuit to be placed on the PC board

Have data sheets on components to indicate pkg size, pinouts, etc

Determine location and orientation of active devices to optimize RFinterfaces

Place RF matching/terminating components around the device to

Use as small of mounting pad as possible with discrete RFcomponents to keep stray capacitance to a minimum

Observe proper orientation of discrete components if placed next to

eac o er o avo coup ng e ec sSeparate inductors from each other in the layout, or place

perpendicular to each other to prevent coupling of their magneticfields

Make sure that components that are connected to the ground plane

have a via(s) as close to the end of the component as possibleUse wide power traces if possible to lower DC losses and provide

92

Designing a RF Printed Circuit oard Draw Schematic of circuit


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Draw Schematic of circuit

Draw layout of components to optimize parts placement and interconnections

ADL5523 AD5350

LNA Mixer IF AMP

93

Designing a RF Printed Circuit oard


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Matching

components placed

close to RF device

Place bias line bypassing

components close to RF

device

Large number of vias under devices

to provide good RF grounds and

thermal conductivity

Ground vias at end

of RF and bypass

components

Ground plane

Is not close to

transmission

coupling

ADL5523 AD5350 AD8353

LNA Mixer IF AMP

IF

Output

LO Input

Inductors placed at rightangles to reduce coupling

of their magnetic fields

RF devices placed in a straightline to aid in overall circuit

stability

Short interstage RFtransmission lines

between stages

Very short groundleads from device

to ground plane

RF attenuatorplaced close to

board connector

94

Shieldin on RF Circuit Boards

On multilayer circuit boards, use Stripline transmission lines if possible


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On multilayer circuit boards, use Stripline transmission lines if possible Route DC bias and signal traces on inner layers between the ground planes

If re uired lace shielded enclosures around the RF sta es on the board

Be careful as to the physical size of the shielded enclosures, as it couldbecome a resonate cavity at the higher frequencies

Traces going to or from shielded sections should be routed on inner layers

Shield enclosure outlinesDC bias line on inner layer

ADL5523 AD5350 AD8353

LNA Mixer IF AMP

D C BiasRF Input

IF Output

L O Input

95

plated through to provide good RF

grounds to the external housing

transmission lines to provide

shielding



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Checking the Layout

Checkin the La out


97/107

Desi n review

Colleague review

97

Checkin the La out


98/107

Desi n review

Colleague

Colored pencils

Helps trace signal path onschematic and PCB

98

Checkin the La out


99/107

Desi n review

Colleague

Colored pencils

Helps trace signal path onschematic and PCB

board corrections are made

Trust no one

board could inadvertentlychange another part of theboard

99

N e x t S t e p s


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Order Boards

Build and test

Evaluate performance

Successful High Speed/RF PCB design is a combination ofeducation and experience

100



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Summary

Summar

High speed PCB design requires deliberate thought and attention to detail!


102/107

High speed PCB design requires deliberate thought and attention to detail!

Load the schematic with as much information as possible

Where you put individual components on the board is just as important asto where you put entire circuits

Take the lead when laying out your board, dont leave anything to chance

Parasitics must be considered and dealt with

Ground and Power planes play a key role in reducing noise and parasitics

more compact layouts

There are many options for signal distribution, make sure you choose theright one for your application

ec e ayou an c ec aga n

Successful High Speed PCB design is a combination of education andexperience and sometimes a little luck!

102

Summar

Work directly with PC board designer as they most likely will not


103/107

Work directly with PC board designer as they most likely will notunderstand proper RF layout techniques

rov e es gner w a raw ng o e oca on o e cr ca gfrequency components and transmission lines

Instruct the board designer that transmission line widths andlen ths are ver critical and must be exactl as calculated

Place the components to minimize the length of RFinterconnections

Generally try to place components in a straight line to avoid

Place circuit blocks such as oscillators, mixers, amplifiers inseparate sections on the board if possible

Do NOT mix di ital, low level analo , or bias traces with RFinterconnects to avoid unwanted coupling

Locate the components operating at the highest frequencies closeto board interconnects

103

, ,sending out for fabrication

References

Ardizzoni, John A Practical Guide to High-Speed Printed-Circuit-Board La o t


104/107

Board Layout Ardizzoni John Kee Hi h-S eed Circuit-Board La out on Track

EE Times, May 23, 2005.Brokaw, Paul, An IC Amplifier Users Guide to Decoupling,

Grounding, and Making Things Go Right for a Change, AnalogDevices Application Note AN-202.Brokaw, Paul and Jeff Barrow, Grounding for Low- and High-

Frequency Circuits, Analog Devices Application Note AN-345.Buxton, Joe, Careful Design Tames High-Speed Op Amps, Analog

Devices Application Note AN-257.DiSanto, Greg, Proper PC-Board Layout Improves Dynamic

Range, EDN, November 11, 2004.Grant, Doug and Scott Wurcer, Avoiding Passive-Component

Pitfalls, Analog Devices Application Note AN-348 Johnson, Howard W., and Martin Graham, High-Speed Digital

Design, a Handbook of Black Magic , Prentice Hall, 1993. Jung, Walt, ed., Op Amp Applications Handbook, Elsevier-Newnes,2005 available on Amazon.com

104

Kester, Walt, The Data Conversion Handbook, Elsevier-Newnes,2005 available on Amazon.com

References


105/107

Hartley, Rick, RF / Microwave PC Board Design and Layout

Reed, Dale, RF and Microwave Basics Impact PCB Design

Mercer, Sean, Minimizing RF PCB Electromagnetic Emissions, RFDesign, January 1999.

Fabian Kung Wai Lee, Open notes on High-Speed Printed CircuitBoard (PCB) Design (August 2008) Available athttp://persona.mmu.edu.my/~wlkung/ADS/ads.htm

owe, ar an, r p ne rcu es gnRogers Corporation, A Low cost Laminate for Wireless

Applications, Microwave Journal, Sept 1996

, .

105

Contact Information


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John Ardizzoni Dennis Falls

Analog Devices, Inc.

804 Woburn Street

Avnet Electronics Marketing

9200 Indian Creek Parkway, -

Email:

Overland Park, Kansas 66210

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Lord of the Board Amps

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