PowerPoint PresentationMarkus Loose
Rockwell Scientific
Vyshnavi Suntharalingam
Monolithic CMOS
Hybrid CMOS
Emerging Technologies
Vertical Integration
Markus Loose
Alan Hoffman
Vyshi Suntharalingam
HgCdTe 4K x 4K mosaic, 18 µm pixels
InSb 2K x 2K,
3D stacked CMOS wafer sandbox
Monolithic CMOS 4K x 4K, 5 µm pixels
CMOS - *
+
Multiplexing of pixel voltages: Successively connect amplifiers to common bus
Sensor Output
Various options possible:
add. amplifiers (analog output)
A/D conversion (digital output)
Pixel Array
Control &
Timing
Many foundries available worldwide
No mechanical shutter required
CMOS process enables integration of many additional features
Various pixel circuits from 3 transistors up to many 100 transistors per pixel
Random pixel access, windowing, subsampling and binning
Bias generation (DACs)
A/D conversion
Low power consumption
CMOS - *
Special Scanning Techniques Supported by CMOS
Different scanning methods are available to reduce the number of pixels being read:
Allows for higher frame rate or lower pixel rate (reduction in noise)
Can reduce power consumption due to reduced data
Random Read
Selective reset of saturated pixels
Fast reads of selected pixels
Subsampling
Used to obtain higher frame rates on full-field images
Windowing
Used to achieve higher frame rates (e.g. AO, guiding)
Binning*
Used to achieve lower noise and higher frame rates
* Binning is typically less efficient
in CMOS than in CCDs.
CMOS - *
Astronomy Application: Guiding
Special windowing can be used to perform full-field science integration in parallel with fast window reads.
Simultaneous guide operation and science data capture within the same detector.
Two methods possible:
Overhead reduces full-field frame rate
Parallel reading of full-field and window
Requires additional output channel
Full field row
Snapshot Shutter
Row 1
Row 2
Row 3
Row 4
Row 5
start integrating
stop integrating
start 2nd integration if pixel supports “integrate while read”
integration time
integration time
integration time
integration time
integration time
Row 1
integration time
Rolling Shutter (Ripple Read)
Each row starts and stops integrating at a different time (progressively).
Typically less transistors per pixel and lower noise.
integr
stop integrating
Stitching Enables Large Sensor Arrays
The small feature size of modern CMOS processes limits the maximum area that can be exposed in one step (so-called reticle) to about 22 mm.
However, larger chips can produced by breaking up the design into smaller sub-blocks that fit into the reticle.
Sub-blocks are exposed one after another
Some blocks are used multiple times
Ultimate limit is given by wafer size
Reticle
Acquisition System
Detector Array
Digital data
Single Chip
Small, low system power
Acquisition System
Detector Array
Analog output
Large, higher power
Acquisition System
Analog output
Dual Chip
Small, low system power
CMOS - *
Monolithic CMOS
A monolithic CMOS image sensor combines the photodiode and the readout circuitry in one piece of silicon
Photodiode and transistors share the area => less than 100% fill factor
Small pixels and large arrays can be produced at low cost => consumer
3T Pixel
4T Pixel
photodiode
transistors
Reset
Select
SF
PD
Monolithic CMOS technology has enabled highly integrated, complete imaging systems-on-a-chip:
Single chip cameras for video and digital still photography
Performance has significantly improved over last decade and is better or comparable to CCDs for many applications.
Especially suited for high frame rate sensors (> Gigapixel/s) or other special features (windowing, high dynamic range, etc.)
However, monolithic CMOS is still limited with respect to quantum efficiency:
Photodiode is relatively shallow => low red response
Metal and dielectric layers on top of the diode absorb or reflect light => low overall QE
Backside illumination possible, but requires modification of CMOS process
2 Mpixel HDTV CMOS Sensor
Quantum Efficiency of a CMOS sensor
Si PIN
Monolithic CMOS
Hybrid CMOS
Emerging Technologies
Vertical Integration
Markus Loose
Alan Hoffman
Vyshi Suntharalingam
MOS w/surface channel CCD
PMOS or NMOS
CMOS - *
Hybrid of Detector Array and ROIC Connected by Indium Bumps
Mature interconnect technique:
99.9% interconnect yield
Also called a Focal Plane Array (FPA) or Hybrid Array
Indium bump
Detector Array
Large CMOS hybrids revolutionized infrared astronomy
Growth in size has followed "Moore's Law" for over 20 years
18 month doubling time
predicted
289.4559149431
459.4834875358
1024
729.3859424483
1157.8301886198
1837.9443140615
3596
2917.5602215192
4631.3468700152
7351.8187121536
16384
11670.3066933516
18525.4919427944
65536
29407.440673179
46681.4900039895
74102.3856244678
117630.425994715
186727.012944229
1048576
296411.213920457
470524.35720182
746912.263513745
1185651.54140987
1882108.04175896
2987665.90109731
4742632.90870247
7528474.61908191
4194304
11950730.9929385
18970638.6076649
16777216
30114068.2854696
47803193.5274712
75882982.3244931
120456952.382276
100000000
191213852.338834
303533640.882956
Sheet1
predicted
1980
289
1981
459
1982
1024
729
1983
1158
1984
1838
1985
3596
2918
1986
4631
1987
7352
1988
16384
11670
1989
18525
1990
65536
29407
1991
46681
1992
74102
1993
117630
1994
186727
1995
1048576
296411
1996
470524
1997
746912
1998
1185652
1999
1882108
2000
2987666
2001
4742633
2002
7528475
2003
4194304
11950731
2004
18970639
16777216
2005
30114068
2006
47803194
2007
75882982
2008
120456952
predicted
CMOS - *
for CMOS ROICs
detector bias remains constant
detector bias remains constant
detector bias changes during integration
some nonlinearity
Comments
Very high gains demonstrated
CMOS - *
Si:As IBC
Si PIN
Detector
Material
* Long wave cutoff is defined as 50% QE point
** Spectral range can be extended into visible range by removing substrate
*** Approximate detector temperatures for dark currents << 1 e-/sec
Operating
ROICs are interchangeable among detectors (except Si:As)
HgCdTe and InGaAs require special packaging due to CTE mismatch between detector and ROIC
CMOS - *
Fixed pattern noise
Caused by residual non-uniformity after calibration
Can be reduced (eliminated?) by calibrating at multiple points in the dynamic range
Random Telegraph Signal (RTS)
Personal experience: have not seen this
CMOS - *
Periodic sampling of detector signal possible during a long integration
Two general methods of white noise reduction by multiple sampling
Fowler sampling: average 1st N samples and last N samples; then subtract
Sample up the ramp (SUTR): fit line (or polynomial) to all samples
Reset begins integration
Voltage ramp for
a single pixel
Data courtesy of Dr. Craig McMurtry, University of Rochester
2 e-
Sampling in Uncorrelated (White) Noise Limit
Peak at Fowler N/3
"System on a chip" is possible
Clocks & biases
A/D & DAC
SCAs
CMOS - *
Outline
Monolithic CMOS
Hybrid CMOS
Emerging Technologies
Vertical Integration
Markus Loose
Alan Hoffman
Vyshi Suntharalingam
Economics of scale accelerate progress Lower fabrication cost, Foundry access
High resistivity (deep depletion) substrates Controlled temperature ramps & stress control
Epi doping optimized for digital CMOS Scalable to 300mm
Buried channel Multiple oxidation cycles
Complex implant engineering Rapid Thermal Processing (RTP)
Single gate dielectric thickness
Multiple gate dielectric thicknesses
Doped polysilicon (single type)
Highly nonplanar surfaces Conservative design rules
Fine-line patterning Multiple metal layers (dense routing)
Vulnerable to space-radiation-induced traps
CMOS - *
STI, salicides, RTP can generate and propagate crystalline defects, thus increasing dark current
Composite dielectric materials degrade sensitivity and create interference effects which impact transmission, especially in the blue
Silicide blocks are typically used for image sensor pixel regions
Shallow junctions can be a problem for leakage
CMOS - *
Silicide is blocked from the photosensitive regions of the pixel
CMOS - *
0.3um
Silicide blocks are incorporated at 0.15um and 0.13um technology nodes
Lining oxide modifications are also made to manage stress
According to TSMC, there are problems with manufacturing non-silicided regions at the 90-nm node.
CMOS - *
Fill factor tradeoff
PD from Drain-Substrate or Well-Substrate diode
Low photoresponsivity
Surface recombination at Si/SiO2 interface
QE*FF > 60% is good, many < 20%
High leakage
LOCOS/STI, salicide
Pixel Layout
Field inversion causing complete failure of the imager
Layout-related mitigation techniques limit pixel fill factor
CMOS - *
Fill factor loss
Conventional Monolithic APS
Local image processing
pixel
CMOS - *
Two-layer stack with insulated vias through thinned bulk Si
Photo Courtesy of RTI
10 mm
10 mm
10 mm
Slide showing “to scale” several different approaches to 3D circuit integration. Including (on the left) traditional bump bonds which are used to interconnect two circuit layers. (middle) A bulk-silicon-based through wafer via approach being pursued by several research organizations. (right) Lincoln’s approach based on SOI layer transfer. Note the much smaller size and 3-layer integration demonstrated by the MIT-LL approach.
Lincoln’s approach :
CMOS - *
Foundry fabricated daughter chip bump bonded to non-imaging side
Tiled Array
mechanical mockup
Tile with
Daughter Chip
8 mm
Overview physical description of this 3D stacked imager demonstration.
(Elements of this slide were cleared for ISSCC 2005 - slide #7)
CMOS - *
SOI-CMOS
Pixel
Cross sectional SEM micrograph through functional active pixel imager. Each 8x8-um pixel contains three SOI-CMOS transistors in Tier-2 and one 3-D via to contact the Tier-1 photodiode.
(This slide previously cleared for this meeting)
CMOS - *
Silicon photodetector tier
Per-pixel 3D interconnections
100% fill factor
Presented at 2005 ISSCC
Front Illuminated
Back Illuminated
The largest-area imager we have built using our 3-D stacking technology was this 1024x1024 pixel imager described here.
The vertical integration permitted very small (8umx8um) pixels with a vertical interconnection in every pixel
The device has been successfully processed for backside illumination and continues to operate as an image sensor.
(This slide previously cleared for ISSCC 2005 as slides #7 and #33)
CMOS - *
Objective: single flash, non-scanned 3D area imager
Pixel stores range, not intensity, information
3-D imaging provides
Robust object recognition
Active intensity image
Npe= 105
3-D images enable easy image segmentation based on range, object recognition signatures that are robust to lighting or reflectivity variations, and object recognition through camoflage. 3D images can also be used to align intensity images from multiple sensors in different locations.
Here is an example comparing an intensity image of two vehicles with a 3-D image of the same scene. One vehicle is obscured by a camoflage net. The 3-D image, when rotated using rendering software, reveals the camoflaged vehicle clearly. It is not possible to make out the camoflaged vehicle at all in the intensity image, even with over 250 times as many photoelectrons per pixel.
CMOS - *
16-channel CMOS readout
32x32 CMOS readout
This chart summarizes the development of these sensors over the past 5 years.
-we developed our own design of a silicon APD, ans are currently developing sensors for 1.06 and 1.55 micron wavelength radiation.
-The early brassboard system which produced the images shown on the last slide used an external readout circuit.
-We next productd an integrated 4x4 array which had integrated CMOS readout circuits and wire bonded the small APD array to it.
-Last year I reported on first operation of a 32x32 pixel APD array integrated with a CMOS readout circuit with one circuit for each pixel. Work this year has focused on improving this first circuit.
CMOS - *
Laser radar focal plane based on single-photon-sensitive Geiger-mode avalanche photodiodes
64 x 64 demonstration circuit (scalable)
Pixel size reduction from 100 mm to 30 mm
Timing resolution reduction from 1 ns to 0.1 ns
100x reduction in voxel volume
3D-Integrated Tier-1/Tier-2 wafer pair electrical test vehicle
150 mm
VISA APD Pixel Circuit (~250 transistors/pixel)
Third application area, a 3-tier Geiger-mode avalanche photodiode (APD) 3D LIDAR array, using an APD tier, a 3.3 volt CMOS tier, and a 1.5 volt CMOS tier.
CMOS - *
Outline
Monolithic CMOS
Hybrid CMOS
Emerging Technologies
Vertical Integration
Markus Loose
Alan Hoffman
Vyshi Suntharalingam
Comparison CMOS vs. CCD for Astronomy
Silicon PIN hybrid detectors have become a serious alternative to CCDs providing a number of significant advantages, specifically for large mosaic focal plane arrays.
Property
CCD
Pixel pitch
Typ. wavelength coverage
400 – 1000 nm
400 – 1000 nm with Si PIN 400 – 5000 nm with InSb or HgCdTe
Noise
Shutter
Mechanical
Radiation
Sensitive
Control Electronics
Low voltage only, can be integrated into single chip
Special Modes
Orthogonal Transfer, Binning, Adaptive Optics
Windowing, Guide Mode, Random Access, Reference Pixels, Large dynamic range (up the ramp)
CMOS - *
Conclusion
MWIR arrays
predicted
6
8
10
12
1020304050