Logic Synthesis for Low Power(CHAPTER 6)

6.1 Introduction6.1 Introduction

6.2 Power Estimation Techniques6.2 Power Estimation Techniques

6.3 Power Minimization Techniques6.3 Power Minimization Techniques

6.4 Summary6.4 Summary

6.1 Introduction[1]

• Low power, yet high-throughput and computationally intensive Low power, yet high-throughput and computationally intensive circuits are becoming a critical application domaincircuits are becoming a critical application domain

1) One driving factor1) One driving factor

- Growing class of personal computing devices and wireless - Growing class of personal computing devices and wireless

communications systemscommunications systems

-> demand high-speed computations and comlex -> demand high-speed computations and comlex functionaliliesfunctionalilies

with low power comsumptionwith low power comsumption

2) Another crucial driving factor2) Another crucial driving factor

- Excessive power consumption in intergrating more - Excessive power consumption in intergrating more transistorstransistors

on a single chip or on a multiple-chip moduleon a single chip or on a multiple-chip module

6.1 Introduction[2]

- Unless power consumption is dramatically - Unless power consumption is dramatically reduced, thereduced, the

resulting heat limits the feasible packing and resulting heat limits the feasible packing and performanceperformance

of VLSI circuits and systemsof VLSI circuits and systems

- Circuits synthesized for low power are less - Circuits synthesized for low power are less susceptible tosusceptible to

run time failuresrun time failures

6.1 Introduction[3]

• Multifaceted approach attaking the problem on four frontsMultifaceted approach attaking the problem on four fronts

1) Reducing chip and package capacitance1) Reducing chip and package capacitance

- Process development such as SOI(Silicon On Insulator) with- Process development such as SOI(Silicon On Insulator) with

fully depleted wells, process scaling to submicron devicefully depleted wells, process scaling to submicron device

sizes, and advanced inerconnect substrates such as Multi-sizes, and advanced inerconnect substrates such as Multi-ChipChip

modulemodule

2) Scaling the supply voltage2) Scaling the supply voltage

- Require new IC fabrication processing- Require new IC fabrication processing

- Require support circuitry for low-voltage operation - Require support circuitry for low-voltage operation includingincluding

level-converters and DC/DC converters level-converters and DC/DC converters

6.1 Introduction[4 ]

3) Using power management strategies 3) Using power management strategies

- Various static and dynamic power management - Various static and dynamic power management techniquestechniques

- Very application dependent- Very application dependent

4) Employing better design techniques4) Employing better design techniques

- Investment to reduce power by design is - Investment to reduce power by design is relatively small inrelatively small in

comparision to the other two approaches comparision to the other two approaches

6.1 Introduction[5 ]

• System LevelSystem Level

- Inactive hardware module may be automatically turned - Inactive hardware module may be automatically turned offoff

- Module provided with the optimum supply voltage and - Module provided with the optimum supply voltage and interfacedinterfaced

by means of level convertersby means of level converters

- Some of energy cycled back to the power supply- Some of energy cycled back to the power supply

- Task partitioned between various hardware modules or - Task partitioned between various hardware modules or programmableprogrammable

processorsprocessors

6.1 Introduction[6]

• Architectural(behavioral) design levelArchitectural(behavioral) design level

- Concurrency increasing transformation- Concurrency increasing transformation

-> loop unrolling, pipeling, control flow optimization-> loop unrolling, pipeling, control flow optimization

- Critical path reducing transformation- Critical path reducing transformation

-> height minimization, retiming, pipeling-> height minimization, retiming, pipeling

- Algorithm-specific instruction set may be utilized- Algorithm-specific instruction set may be utilized

-> boost code density and minimize switching-> boost code density and minimize switching

- Gray code addressing scheme- Gray code addressing scheme

-> reduce the number of bit change-> reduce the number of bit change

- On-chip cache -> minimize external memory references- On-chip cache -> minimize external memory references

- Locality -> avoid accessing global resources - Locality -> avoid accessing global resources

6.1 Introduction[7]

• Register-transfer and logic levelRegister-transfer and logic level

- Symbolic states of a FSM can be assigned binary codes - Symbolic states of a FSM can be assigned binary codes to to

minimize the number of bit changes minimize the number of bit changes

- Latches in a piplined design can be repositioned- Latches in a piplined design can be repositioned

-> eliminate hazardous activity in the circuit-> eliminate hazardous activity in the circuit

- Output logic values of a circuit precomputed one cycle - Output logic values of a circuit precomputed one cycle beforebefore

- Common sub-expressions with low transition extracted- Common sub-expressions with low transition extracted

- Nodes with high switching activity hidden inside CMOS- Nodes with high switching activity hidden inside CMOS

- Gate resizing, signal-to-pin assignment, I/O encoding- Gate resizing, signal-to-pin assignment, I/O encoding

6.1 Introduction[8]

• Physical design levelPhysical design level

- Use appropriate net weights during- Use appropriate net weights during

-> netlist partitioning, floorplanning, placement, -> netlist partitioning, floorplanning, placement, routingrouting

- Individual transistors sized down- Individual transistors sized down

- Use optimally sized inverter chains- Use optimally sized inverter chains

-> buffer large capacitive loads-> buffer large capacitive loads

- Combine wire and driver sizing- Combine wire and driver sizing

-> reduce the interconnect delay -> reduce the interconnect delay

-> small increase in the power dissipation-> small increase in the power dissipation

- Clock tree- Clock tree

-> minimize the load on the clock drivers-> minimize the load on the clock drivers

6.1 Introduction[9]

• Circuit levelCircuit level

- Recycle the signal energies using the adiabatic - Recycle the signal energies using the adiabatic switchingswitching

principles principles

- Conbine self-timed circuits with a mechanism for - Conbine self-timed circuits with a mechanism for selective selective

adjustment of the supply voltageadjustment of the supply voltage

- Transfer of the energy stored on a capacitance to some - Transfer of the energy stored on a capacitance to some chargecharge

sharing capacitancessharing capacitances

- Design energy efficient level-converters - Design energy efficient level-converters

- DC/DC converters- DC/DC converters

6.1 Introduction[10]

• Design for low power problem can be achieved withDesign for low power problem can be achieved with

- Accurate power prediction and optimization tools- Accurate power prediction and optimization tools

- Power efficient gate and module libraries- Power efficient gate and module libraries

• Critical need for CAD toolsCritical need for CAD tools

1) to estimate power dissipation during design process to 1) to estimate power dissipation during design process to meet meet

the power budget the power budget

2) to enable efficient design and characterization of the 2) to enable efficient design and characterization of the designdesign

librarieslibraries

3) to reduce the power dissipation using various 3) to reduce the power dissipation using various transformationtransformation

and optimizatonsand optimizatons

6.2 Power Estimation Techniques

• Multifaceted approach attaking the problem on four frontsMultifaceted approach attaking the problem on four fronts

1) Reducing chip and package capacitance1) Reducing chip and package capacitance

- Process development such as SOI(Silicon On Insulator) with- Process development such as SOI(Silicon On Insulator) with

fully depleted wells, process scaling to submicron devicefully depleted wells, process scaling to submicron device

sizes, and advanced inerconnect substrates such as Multi-sizes, and advanced inerconnect substrates such as Multi-ChipChip

modulemodule

2) Scaling the supply voltage2) Scaling the supply voltage

- Require new IC fabrication processing- Require new IC fabrication processing

- Require support circuitry for low-voltage operation - Require support circuitry for low-voltage operation includingincluding

level-converters and DC/DC converters level-converters and DC/DC converters