Logic Circuits II ECE 2411 Thursday 4:45pm-7:20pm Nathan ... 2016/ECE2411/Lecture1.pdf ·...

Logic Circuits II ECE 2411

Thursday 4:45pm-7:20pm

Nathan Pihlstrom

B.S.E.E. from Colorado State University M.S.E.E. from Colorado State University M.B.A. from UCCS Ford Microelectronics, Inc./Visteon 1985 - 2000 Intel Corp. 2000-2006 Marvell 2006-2009 Hittite Microwave 2009-2011 Covidien 2011 - 2013 LSI/Avago/Broadcom 2013 - present UCCS ECE4280/5280, ECE4211/5211, ECE4200, ECE4242/5242, ECE1411, ECE2411

My Background

Chapter 1 Review

Binary Numbers

• Floating Point Representation:

– 11010.112 = 26.7510

– 1x24 + 1x23 + 0x22 + 1x21 + 0x20 + 1x2-1 + 1x2-2 = 26.75

2-1 = 0.5

2-2 = 0.25

2-3 = 0.125

2-4 = 0.0625

2-5 = 0.03125

One’s Complement

• Obtained by subtracting each digit from 1

or

• Invert any 1 to 0, any 0 to 1 1 – 0 = 1

1 – 1 = 0

• Examples 1011000 -> 0100111

0101101 -> 1010010

Two’s Complement

• Formed by: – Taking the 1’s complement and adding 1. or – Leaving all least significant 0s and the first 1

unchanged – Replacing 1s with 0s and 0s with 1s in all other higher

significant digits.

• Examples: 110_1100 -> 001_0100 010_1101 -> 101_0011

Subtraction with 2’s Complements

• Given X = 1010100 and Y = 1000011

• X – Y: X = 1010100

Y’= 0111101 (2’s Complement)

Sum = 1 0010001

• Y – X: Y = 1000011

X’= 0101100 (2’s Complement)

Sum = 1101111

Subtraction with 1’s Complement • Given X = 1010100 and Y = 1000011

• X – Y: X = 1010100

Y’= 0111100 (1’s Complement)

Sum = 10010000

Carry 1

Sum = 0010001

• Y – X: Y = 1000011

X’ = 0101011 (1’s Complement)

Sum = 1101110

Signed Binary Numbers

• Signed Magnitude Representation: – Left most bit indicates sign: 0 for +, 1 for –

• Signed 1’s Complement Representation: – 1’s Complement (invert) all bits including the sign bit

• Signed 2’s Complement Representation: – 2’s Complement all bits including the sign bit

• Book example of -9 using eight bits: – Signed Magnitude: 00001001 -> 10001001 – Signed 1’s Complement: 00001001 -> 11110110 – Signed 2’s Complement: 00001001 -> 11110111

Signed Binary Numbers

• Signed 2’s Complement has only one positive representation for zero.

– See table 1.3

• 1’s Complement is seldom used for arithmetic operations though easily generated.

Arithmetic Addition

• Represent positive numbers using binary

• Represent negative numbers using 2’s complement

• Discard carry out of sign bit. +6 0000_0110 -6 1111_1010

-13 1111_0011 -13 1111_0011

-7 1111_1001 (000_0111) -19 1110_1101 (0001_0011)

Arithmetic Subtraction

• Generate the 2’s complement of the subtrahend and add to minuend. Discard sign bit carry out

(+A) – (+B) = (+A) + (-B)

(+A) – (-B) = (+A) + (+B)

Book Example: -6 – (-13) = -6 + 13 = +7

-6 1111_1010 -> 1111_1010

-(-13) 1111_0011 -> 0000_1101

+7 1_ 0000_0111

Offset Binary • Value stored is offset from the actual value by the

offset value.

• Coding technique where all zeros corresponds to the minimal negative value and all ones to the maximal positive value.

• Converted to 2’s complement by inverting MSB.

• Allows high speed comparison.

Offset Binary Decimal 2’s Complement Offset Binary

7 0111 1111

6 0110 1110

5 0101 1101

4 0100 1100

3 0011 1011

2 0010 1010

1 0001 1001

0 0000 1000

-1 1111 0111

-2 1110 0101

-3 1101 0101

-4 1100 0100

-5 1011 0011

-6 1010 0010

-7 1001 0001

-8 1000 0000

Real Numbers in Binary • Defined by IEEE754 specification

• Format

Single Precision Example: 1234.5678 is normalized to 1.2345678 x 103

with Exponent = 3, Mantissa = 12345678 Signed Exponents are biased by adding 127 (ranges from -127 to 128)

S 1 bit

Exponent 8/11 bits

Mantissa 23/52 bits

Level Bits Range Precision

Single precision 32 +1.18x10-38 to +3.4x1038 ~ 7 digits

Double precision 64 +2.23x10-308 to +1.80x10308 ~ 15 digits

Real Numbers in Binary • Example:

– Convert -14.09375 to IEEE754 single precision format: • First bit is 1 as value is negative • Convert 0.09375 to binary:

0.09375 x 2 = 0.1875 0 0.1875 x 2 = 0.375 0 0.375 x 2 = 0.75 0 0.75 x 2 = 1.5 1 0.50 x 2 = 1.00 1 So 14.0937510 = 1110.000112

• Next rewrite binary number in scientific form by moving binary point to right three places:

1.11000011 x 23

All binary number in scientific form will have a 1 on left side of binary point, so ignore (don’t store).

• Next convert Exponent to excess 127 form: 127 + 3 = 13010 = 100000102

• Thus -14.09375:

S Exponent Mantissa

1 1 0 0 0 0 0 1 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Gray Code

• Only one bit changes when going from one number to the next

• Useful for optical rotary encoders:

Error Detecting Code

• Additional bit added to bus, RAM, etc. to indicate parity. – Even parity:

• Set to one if number of ones in value is odd • Set to zero if number of ones in value is even

– Odd parity: • Set to one if number of ones in value is even • Set to zero if number of ones in value is odd

• Note: detects errors only. Error Correcting Code invented by Hamming in 1950s which can detect up to two errors and correct one (more on this later).

Chapter 2

• “+” = OR Function

• “·” = AND Function

• Theorems important to remember for post place and route edits as only have defined gates to work with.

• DeMorgan’s Theorem (bubble pushing):

Axiomatic Definition of Boolean Algebra

• In this work, Shannon proved that Boolean algebra and binary arithmetic could be

used to simplify the arrangement of the electromechanical relays that were used then in telephone call routing switches. He next expanded this concept, and he also proved that it would be possible to use arrangements of relays to solve problems in Boolean algebra.

Chap 1-2 Copyright 2012 G. Tumbush v1.5 20

• In 1904, E.V. Huntington formulated the postulates that formally define Boolean algebra.

• In 1937, Claude Shannon founded both digital computer and digital circuit design theory when, as a 21-year-old master's degree student at the Massachusetts Institute of Technology (MIT), he wrote his thesis demonstrating that electrical applications of Boolean algebra could construct and resolve any logical, numerical relationship.

• His thesis was published in the 1938 issue of the Transactions of the American Institute of Electrical Engineers , and proved that a two-valued Boolean algebra (whose members are most commonly denoted 0 and 1, or false and true) can describe the operation of two-valued electrical switching circuits.

Claude Shannon


• Would certainly want to minimize the number of mechanical relays used!


• Two –Valued Boolean Algebra

– Defined on a set of two elements, B = {0, 1} with rules for the two binary operators + and⋅as shown in the following operator tables:

x y x ∙ y

0 0 0

0 1 0

1 0 0

1 1 1

AND

x y x+y

0 0 0

0 1 1

1 0 1

1 1 1

OR

x x’

0 1

1 0

NOT

Axiomatic Definition of Boolean Algebra • Show that the Huntington postulates are valid for the set B = {0,

1} and the two binary operators + and ⋅ – Closed: From binary operator tables, the result of AND, OR, and NOT

result in 0 or 1 and 0 ∈ B – Identity Elements: From tables, we see that:

0 + 0 = 0 0 + 1 = 1 + 0 = 1 1 ⋅ 1 = 1 1 ⋅ 0 = 0 ⋅ 1 = 0

which establishes the two identity elements, 0 for + and 1 for ⋅ per postulate 2 (x + 0 = x, x ⋅ 1 =x)

– Identity Commutative Law: (x + y = y + x, xy = yx) • obvious from the binary operator tables

x y x ∙ y

0 0 0

0 1 0

1 0 0

1 1 1

AND

x y x+y

0 0 0

0 1 1

1 0 1

1 1 1

OR

x x’

0 1

1 0

NOT


– Distributive Law: x⋅(y+z) = (x⋅y)+(x⋅z)

x y z y+z x⋅(y+z) x⋅y x⋅z (x⋅y)+(x⋅z)

0 0 0 0 0 0 0 0

0 0 1 1 0 0 0 0

0 1 0 1 0 0 0 0

0 1 1 1 0 0 0 0

1 0 0 0 0 0 0 0

1 0 1 1 1 0 1 1

1 1 0 1 1 1 0 1

1 1 1 1 1 1 1 1

values are the same


– Distributive Law: x+(y ⋅ z) = (x+y) ⋅ (x+z)

x y z y⋅z x+(y⋅z) x+y x+z (x+y) ⋅(x+z)

0 0 0 0 0 0 0 0

0 0 1 0 0 0 1 0

0 1 0 0 0 1 0 0

0 1 1 1 1 1 1 1

1 0 0 0 1 1 1 1

1 0 1 0 1 1 1 1

1 1 0 0 1 1 1 1

1 1 1 1 1 1 1 1

values are the same

Basic Theorems and Properties of Boolean Algebra

• Basic Postulates and Theorems

– The postulates are basic axioms of the algebraic structure and need no proof

– The theorems must be proven from the postulates

2.4 Basic Theorems and Properties of Boolean Algebra

2.5 Boolean Functions • Complement of a Function

– The complement of function F is F’ and is obtained by the interchange of 0’s with 1’s and 1’s with 0’s in the value of F

– The complement of a function may be derived algebraically using DeMorgan’s theorem

(A + B)’ = A’B’ theorem 5a (DeMorgan’s)

– Extended to three variables (A + B + C)’ = (A + x)’ where x = B + C = A’x’ theorem 5a (DeMorgan’s) = A’(B + C)’ substitute B + C = x = A’(B’C’) theorem 5a (DeMorgan’s) = A’B’C’ theorem 4b (associative)

– In General (A + B + C + D + … + F)’ = A’B’C’D’ … F’ (ABCD … F)’ = A’ + B’ + C’ +D’ + … + F’

2.4 Basic Theorems and Properties of Boolean Algebra

• Operator Precedence

1. Parentheses

2. NOT

3. AND

4. OR

2.5 Boolean Functions

• Algebraic Manipulation – Term: A gate is required for each term and each

variable within the term is an input to the gate – Literal: A single variable within a term, in

complemented or un-complemented form – Reducing the number of terms, number of literals, or

both may result in a simpler circuit F2 = x’y’z + x’yz + xy’ has three terms and eight literals F2 = x’z + xy’ has two terms and four literal

2.5 Boolean Functions • Example 2.3

– Find the complement of the previous functions F1 and F2 • F1 = x + y’z F1’ = (x + y’z)’ = x’ ⋅ (y’z)’ = x’ ⋅ y + z’ • F2 = x’y’z + x’yz + xy’ F2’ = (x’y’z + x’yz + xy’)’ = ((x’y’z)’ ⋅ (x’yz)’ ⋅ (xy’))’ = (x + y + z’) ⋅ (x + y’ + z’) ⋅ (x’ + y) let x + z’ = a = (a + y)(a + y’) ⋅ (x’ +y) = (aa + a(y’ + y) + yy’) ⋅ (x’ + y) recall xx = x, xx’ = 0, x + x’ = 1 = (a + a + 0) ⋅ (x’ + y) recall x + x = x = a + (x’ + y) = (x + z’) ⋅ (x’ + y) • F2 = x’z + xy’ F2’ = (x’z + xy’)’ = (x’z)’ ⋅ (xy’)’ = (x + z’) ⋅ (x’ + y)

Canonical and Standard Forms

• Canonical Form: Simplest or Standard form of an expression

• minterm or standard product – A product term in which each of the variables appears

once (complemented or uncomplemented) – AND operation

• maxterm or standard sum – A sum term in which each of the variables appears once

(complemented or uncomplemented) – OR operation

• Boolean functions expressed as a sum of minterms or a product of maxterms are said to be in canonical form

Sum of Minterms and Product of Maxterms

• Sum of Minterms

– Recall that for n variable, there are 2n Miterms and any Boolean function can be expressed as a sum of minterms or sum or product (SoP)

– The minterms whose sum results in 1’s of the 22n functions in the Truth table

• Product of Maxterms

– Each of the 22n functions of n binary variable can also be expressed as a product of maxterms

2.6 Canonical and Standard Forms

• Minterms and Maxterms

– n variables can be combined to form 2n minterms

– n variables can be combined to form 2n maxterms

2.6 Canonical and Standard Forms • A Boolean function can be expressed algebraically from a

given truth table by forming a minterm for each combination of the variables that produce a 1 in the function and then taking the OR of all the terms

• Consider:

f1 = x’y’z + xy’z’ + xyz

f2 = x’yz + xy’z + xyz’ + xyz

2.6 Canonical and Standard Forms • The complement of a Boolean function may be read from the

truth table by forming a minterm for each combination that produces a 0 in the function and then Oring those terms.

• Consider:

f1’ = x’y’z’ + x’yz’ + x’yz + xy’z + xyz’

f2’ = x’y’z’ + x’y’z + xy’z + xy’z’

2.6 Canonical and Standard Forms • If we take the complement of f1’, we obtain the function f1 as

a product of sums:

f1’ = x’y’z’ + x’yz’ + x’yz + xy’z + xyz’

f1 = (x + y + z)(x + y’ + z)(x+ y’ + z’)(x’ + y + z’)(x’ + y’ + z)

= M0M2M3M5M6

• Similarly: f2’ = x’y’z’ + x’y’z + xy’z + xy’z’

f2 = (x + y + z)( x + y + z’)( x + ’y + z’)( x’ + y + z)

= M0M1M2M4

2.6 Canonical and Standard Forms • In general:

– To convert from one canonical form to another, interchange the symbols Σ and Π and list those numbers missing from the original form

– Consider: F = xy + x’z

F(x, y, z) = Σ (1, 3, 6, 7)

As there are 2n = 8 minterms

And maxterms, the missing

terms are 0, 2, 4, and 5

F(x, y, z) = Π (0, 2, 4, 5)

2.6 Canonical and Standard Forms • Standard Forms

– By definition, for the two canonical forms of Boolean algebra, each minterm or maxterm must contain all the variables, either complemented or uncomplemented

– The standard form of Boolean function however, the terms can contain one, two, or any number of literals

F1 = y’ + xy + x’yz’

has three product terms with one, two, and three literals

Standard Forms

Sum of Products F1 = y’ + xy + x’yz’

Product of Sums F2 = x(y’ + z)(x’ + y + z’)

Non-Standard Form F3 = AB + C(D + E)

Sum of Products F3 = AB + CD + CE

2.7 Other Logic Operations

2.8 Digital Logic Gates

2.9 Integrated Circuits • Levels of Integration

– Small Scale Integration (SSI) • Several independent gates in a single package

– Medium Scale Integration (MSI) • 10 to 1,000 gates in a single package • Digital functions such as decoders, adders, muxes, etc.

– Large Scale Integration (LSI) • Thousands of gates in a single package • Processors, memories

– Very Large Scale Integration (VLSI) • Millions of gates within a single package • Complex microprocessors, large memories arrays

– System on a Chip (SoC) • Integrates all components of a computer or

other electronic system into a single chip. It may contain digital, analog, mixed-signal, and often radio-frequency functions—all on a single chip substrate.

2.9 Integrated Circuits • Moore’s Law:

– Observation by Gordon Moore that, over the history of computing hardware, the number of transistors in a dense integrated circuit doubles approximately

every two years.

Chapter 3

• Karnaugh Maps (K-maps) used for manual gate level minimization

• Recall that any Boolean function can be expressed as a sum of minterms

• The resulting expression is always on of the two standard forms

Two Variable K-map

F = xy = (x’+y)(x+y)(y’+x)

Minterm Maxterms

F = x + y = (x+ y)

Minterms Maxterm

Four Variable K-map

F = BD + B’D’ + CD +AD

F = BD + B’D’ + CD +AB’

F = BD + B’D’ + B’C + AD

F = BD + B’D’ + B’C AB’

Four Variable K-Map

Don’t Care Conditions

Without Don’t Cares: F = yz + w’x’z

NAND and NOR

Out Out

Inverter Switching

NAND Circuits

• Must be Sum of Products form

F = AB + CD = ((AB)’((CD)’)’

NOR Circuits

• Must be in Product of Sums form

Exclusive OR

• Useful for Parity Generation

P = x + y + z

Bubble Pushing • Bubble Pushing Rules

– Begin at the output and work back to inputs

– Working backwards, draw each gate in a form so that bubbles cancel.

Source: Digital Logic Design Slides, James E. Stine, Jr.

NAND-NOR Structures

• NANDs, NORs , and inverters are the basic circuit used to create combinatorial logic in CMOS. • DeMorgan’s theorem provides equivalent structures for NAND and NOR gates

y

bay

a

b

a

b

a

b

a

b

y y

y

bay

equivalent

bay bay

equivalent

Implementing SOP with NAND gates

Implement equation

CDDBAEFGY

E

F

A

BD

C

D

Y

G

E

F

A

BD

C

D

Y

GE

F

A

BD

C

D

Y

G

Implementing POS with NOR gates

Implement equation

))()(( GAFEACBDY

B

C

A

F

E

A

G

Y

D

B

C

A

F

E

A

G

Y

D

B

C

A

F

E

A

G

Y

D

3.9 Hardware Description Language

• Hardware Description Language (HDL) is a computer based language used to describe the hardware of a digital system in textual form. – Specifically oriented to describing hardware

structures and behavior of logic circuits

• Documented and codified – Standardized by governing body

– Read by both humans and computers

3.9 Hardware Description Language • HDLs are used in several step in the integrated

circuit design flow: – Design entry creates a HDL based description of the

functionality to be implemented in hardware – The description can be in a variety of forms:

• Boolean logic equations • Truth tables • Netlist of interconnected gates • Abstract behavior model

– Documentation • Allows a form that can be read by compiler

– Ideally, compiler and synthesis tool independent

• Read by humans – Still need header, notes, etc. to allow for efficient information

exchange between designers

3.9 Hardware Description Language • Logic Synthesis

– Process of generating a list of physical components and interconnects (netlist) from the model of a digital system described in HDL

• The synthesis tool extracts the desired logic function from the HDL and maps it to a target component library

3.9 Hardware Description Language • Timing Verification

– Confirms that the design will operate at the specified speed, temperature, voltage, and over process variation using the target library components

– Done during/after synthesis

• Allows accurate load on outputs – Tools smart enough to up size output drives based on loads

• If after place and route allows interconnect effects modelling

3.9 Hardware Description Language • Verilog Background

– Verilog created at Gateway Design Automation in 1983/1984

– Cadence Design Systems, a major Electronic Design Automation (EDA) vendor purchased Gateway in 1990 • Originally intended for simulation, synthesis support added later

– Cadence transferred Verilog to public domain • Verilog becomes IEEE Standard 1364-1995 and is known as

Verilog-95

– Extensions to Verilog-95 submitted to IEEE • IEEE Standard 1364-2001, a.k.a. Verilog-2001

– Minor corrected submitted to IEEE in 2005 • IEEE Standard 1364-2005, a.k.a. Verilog-2005

3.9 Hardware Description Language • The Verilog Language Reference Manual (LRM) specifies a

syntax that precisely describes the allowed constructs. – Verilog composed of approximately 100 keywords – Verilog is case sensitive

• All keywords are lowercase

– Variables and module names cannot start with numerals and cannot contain or start with special characters, with the exception of “_” • The “_” allowed within numbers for ease of reading

– Text between two forward slashes (//) and end of line are considered comments and ignored by simulator • Specific comments are active for synthesis

– Multiline comments begin with /* and terminate with */ – Blank spaces are ignored

• Cannot appear within keyword text, a user defined an operator, or number

– Declarations, assignments, and statements end with a semicolon

Comments

• Two types of comments:

– One line comments

• Start with // and end at end of line (eol)

– Multi-line comments:

• Start with /* and end with */

• Blank spaces are ignored • Cannot appear within keyword text, a user defined

operator, or number

• A “\” is used for line multi-line continuation character

3.9 Hardware Description Language • Modules

– Modules is the basic unit of hierarchy in a design • Designs would be flat w/o modules

– Unwieldy for larger designs – Need a way to separate design from test bench

– Module consists of: • Boundaries (module, endmodule) • Inputs and Outputs (can also pass parameter values into module • Behavioral code

– A module should be contained within one file • Multiple files can reside with file but should be avoided • File name should have “.v” suffix

– Can be a single element (i.e. behavioral code) or collection of lower level modules with interconnect.

– Module name should match file name – Declaration: A Verilog module is declared – Instantiation: Once a Verilog module is declared it may be instantiated

within a design (other modules)


• Modules

– Hello world example:

// Example of "Hello World" program in Verilog module hello_world; initial begin $display(“Hello World”); end endmodule

3.9 Hardware Description Language • Modules

– Port list: • The interface between the module and its environment

module #(parameters) module_name (port list);

…. endmodule

• All but top level module in a hierarchy have ports module top_tb(); … endmodule

• Ports consists of a combination of (direction relative to module): Inputs – keyword input Outputs – keyword output Inout – keyword inout (bi-directional port)

• Scalar port: input clk;

• Vector port: output [7:0] data;


• Gate level description (system primitives): – not – buf – and – nand – or – nor – xor – xnor

• Syntax (for our purposes) gateType #delay optName(output, input1, input2, …);

3.9 Hardware Description Language `timescale 1ns/10ps // HDL Example 3.1 // Verilog model of circuit of Figure 3.35 // IEEE 1364-1995 Syntax module simpleCircuit(A, B, C, D, E); // Notice upper/lower case output D, E; input A, B, C; // Declare internal wires wire w1; /* Instantiate Gates Format is: type optName(output, input1, input2, …) */ and G1(w1, A, B); // Optional gate instance name not (E, C); // w/o opt. gate instance name or G3(D, w1, E); endmodule


• Verilog Port Definition – Can specify port connections implicitly or explicitly

when instantiating modules • Implicit

• Explicit

• Safer to use explicit

module module_name(port_name, port_name, …) …

endmodule

module module_name(.port_name1(signal_nam1e), .port_name2(signal_name2), …); … endmodule


• Verilog wire: – “wire” is combinational and evaluates continuously

– Cannot store a value

– No properties (delay, etc.) associated with wires • Just interconnect between elements

• Verilog reg – “reg” is sequential and evaluates on event

– Can store a value

– More in Chapter 5


• Modules

– Need to provide

stimulus to module

to verify functionality

using test bench

`timescale 1ns/10ps // HDL Example 3.1 test bench // Verilog model of circuit of Figure 3.35 // IEEE 1364-1995 Syntax module simpleCircuit_tb(); // Notice, no ports wire D, E; reg A, B, C; // Instantiate simpleCircuit // Implicit ports simpleCircuit u1(A, B, C, D, E); // Stimulus per table 3.5 initial begin A = 0; B = 0; C = 0; #100; A = 1; B = 1; C = 1; #100 $stop; // $finish will exit simulator end endmodule


• Modules simpleCircuit_tb

simpleCircuit

reg A

reg B

reg C

3.9 Hardware Description Language • timescale

– A “`” (grave accent) indicates a compiler directive – `timescale 1ns/1ps

• Specifies the time unit and time precision – time unit

» 1ns indicates a time unit of 1ns » #10 will have a delay of 10nS

– time precision » Indicates the degree of accuracy, i.e. how delay values are rounded

– Valid time units are s, ms, us, ns, ps, fs – Only 1, 10 , or 100 are valid integers for specifying unit and precision

• Must be specified before and outside module definition – The first line of a module is the ‘timescale compiler directive if required,

otherwise an optional comment as the book indicates

• Module without timescale directive will inherent timescale from calling module

• Verilog simulates with the smallest time precision unit specified for a given module

• Make time precision no smaller than necessary


• Propagation/Gate Delay

– Note: low-to-high delay typically longer than high-to-low as PMOS devices are weaker

• For balanced transitions, PMOS is 3x width NMOS, assuming same gate length


• Critical Path:

– The maximum possible clock rate is determined by the slowest logic path in the circuit, otherwise known as the critical path

– Will revisit with adders in Chapter 4

In this example, the slowest path is Ai -> Ci+1, assuming uniform gate and interconnect delay

3.9 Hardware Description Language • Gate Delays

– Recall that all physical circuits exhibit a propagation delay between the transition of a input a resulting transition on the output

– Adding gate delays, allows user to model propagation delays

– Ignored by synthesis tools • Hint: Don’t rely on gate delays

– Tools “back annotate” delays

after synthesis and place/route

// HDL Example 3.2 module simpleCircuit(A, B, C, D, E); output D, E; input A, B, C; wire w1; and #(30) G1(w1, A, B, C); not #(10) G2(E, C); or #(20) G3(D, w1, E); endmodule

3.9 Hardware Description Language • Boolean Expressions

– Verilog operators

Operator Precedence • Binary Operator Precedence

(A + B)/C is not the same as A + B/C

a & &b is not the same as a && b

correct syntax and required by LRM: a & (&b)

a | |b is not the same as a || b

correct syntax and required by LRM: a | (|b)

Integers – Sized or unsized

• Unsized is 32 bits

– x/X: Uninitialized variables or nets with conflicting drivers – z/Z: High impedance – The underscore character “_” is used for improved readability – The character “?” is alternative for z in the context of numbers

• The “?” character is also used as “don’t care” in casex and casez statements

Format Prefix Legal Characters

Binary ‘b 01xXzZ_?

Octal ‘o 0-7xXzZ_?

Decimal ‘d 0-9_

Hexadecimal ‘h 0-9a-fA-FxXzZ_?

Integer Stored as (underscores added for readability)

1 0000_0000_0000_0000_0000_0000_0000_0001 (left fills w/ zeros)

8’hAA 1010_1010

‘hF 0000_0000_0000_0000_0000_0000_0000_1111

6’hCA 00_1010

6’hA 00_1010

8’hx xxxx_xxxx (left fills with x)

Real Numbers

– Fixed or scientific notation • < value >.< value > • < mantissa >E< exponent > or < significand>e< exponent > *

– Cannot contain “Z” or “X” – Real numbers are rounded off to nearest integer

when assigned to integer – Negative numbers specified by leading minus sign

• Represented in 2’s complement format

– real: • Double precision floating point (typically 64 bit)

* IEEE floating point std. committee discourages the use of the term mantissa for scientific or floating point notation

User Defined Primitive (UDP) – The keywords and, or, etc. are defined by the system

and thus are system primitives

– The user can create additional primitives by defining them in tabular format • Scoped by table, endtable keywords

– Declared with primitive … endprimitive

– The current IEEE 1364 standard provides for

multiple-inputs/outputs UDPs but multiple outputs are not common

– The output terminal must be first in the terminal list

– All UDP terminals are scalar

– No bidirectional inout terminals allowed

The high impedance value (z) cannot be specified

UDPs

• Example from av16_svt16_composite_gate_verilog.v:

– Note: the //D0 D1… comment line is just a comment line

The table column order is determined by the input order

primitive mux2_UDP0_SVT16(Q, D0, D1, SEL1); output Q; input D0, D1, SEL1; table // D0 D1 SEL1 : Q 1 ? 0 : 1; ? 1 1 : 1; 0 ? 0 : 0; ? 0 1 : 0; 0 0 ? : 0; 1 1 ? : 1; endtable endprimitive

D0

D1

Q

SEL1

0

1

UDPs

primitive d_edge_ff(q, clock, data); output q; reg q; input clock, data; table // obtain output on rising edge of clock // clock data q q+ (01) 0 : ? : 0 ; (01) 1 : ? : 1 ; (0?) 1 : 1 : 1 ; (0?) 0 : 0 : 0 ; // ignore negative edge of clock (?0) ? : ? : - ; // ignore data changes on steady clock ? (??) : ? : - ; endtable endprimitive

Hardware Description Language (HDL)

`timescale 1ns/1ps // Verilog Model of Fig. 3.35 circuit module Simple_Circuit1(A, B, C, D, E) input A, B, C; output D, E; wire w1; and G1(w1, A, B); not G2(E, C); or G3(D, w1, E); endmodule

`timescale 1ns/1ps // Verilog Model of Fig. 3.35 circuit module Simple_Circuit2(A, B, C, D, E) input A, B, C; output D, E; wire w1; assign w1 = A && B; assign D = w1 ||E; assign E = !D; endmodule

`timescale 1ns/1ps // Verilog Model of Fig. 3.35 circuit primative Simple_Cir_UDP (A, B, C, D) input A, B, C; output D ; table A B C : D 0 0 0 : 1 0 0 1 : 1 0 1 0 : 1 0 1 1 : 1 1 0 0 : 0 1 0 1 : 0 1 1 0 : 1 1 1 1 : 1 endtable endprimative

HomeWork

Show your work

• 2.11 all

• 2.14 all

• 3.4 b, d, f

• 3.17

• 3.21

Logic Circuits II ECE 2411 Thursday 4:45pm-7:20pm Nathan ... 2016/ECE2411/Lecture1.pdf ·...

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