Logic and Digital Circuits: from Practice to Theory

Logic and Digital Circuits: from Practice to Theory

Gérard Berryhttp://www-sop.inria.fr/members/Gerard.Berry/

INRIA Sophia-Antipolis

Collège

de France, 2007-

2008 and

2009-

2010

Logic to

the Rescue, Nancy,

July

22nd, 2011

http://www-sop.inria.fr/members/Gerard.Berry/

G. Berry, Nancy 22/07/2011 2

Digital Circuits

SoC = Systems on Chip

PC microprocessorstelephones, DVD, TV, GPS,...

Sorrce Intel

G. Berry, Nancy 22/07/2011 3

Combinational Gates and Circuits

s a xor b xor c

s (a and b)

or (b and c) or (c and a)

ab

c

s

r

and or xor not (a and b) (not a) and b

ab

mux(c,a,b) =(c and a) or ((not c) and b) mux

cab

full adder

G. Berry, Nancy 22/07/2011 4

Combinational propagation

GOTRY PASS

REQ OK

GET_TOKEN PASS_TOKEN

GO1

1

0

Since the network is acyclic, outputs stabilizein bounded time if inputs are kept constant

Stabilization time is determined by the critical path

G. Berry, Nancy 22/07/2011 5

The Ripple-Carry Adder

++

a0b0

s0

++1

a

1b

1s

c1

++2a

2b2s

2c

3c

c = 00

For n bitstime n

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The von Neumann Logarithmic Adder

n

n

n+1

n+1a[n..2n-1]

b[n..2n-1]

a[0..n-1]

b[0..n-1]

s[0..n-1]

s’[0..n-1]n

n

n+1

n+1 0..n-1

0..n-1

s[n..2n]

n

01

n

s’[n..2n]01

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The von Neumann Logarithmic Adder

For n bitstime log(n)

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The Register

ra

a a0, a1, a2, ... r 0, a0, a1, a2, ... ra

a a0, a1, a2, ... r 1, a0, a1, a2, ... ra

a

rreg(a)

ck ck

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Sequential sampling

tick ! tick !clock

GOTRY PASS

REQ OK


GO1

1

0

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Sequential sampling

tick ! tick !clock

GOTRY PASS

REQ OK


GO1

1

0

0

0

0

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The Serial Adder

ab s ...00110

...01101...10011

6

13

19

Serial Adder

r

See the marvelous use of 2-adic numbers in“On Circuits and Numbers” by Jean Vuillemin

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Boolean Equation View

GOTRY PASS

REQ OK


GO1

1

0

OK REQ and GOPASS not REQ and GOGO TRY or GET_TOKENPASS_TOKEN reg(GET_TOKEN)

Waiting for the critical time solving the equations

13G. Berry, Nancy 22/07/2011

Micro-Architecture breakdown OK?performance OK?

software modelingmodel-checkingtheorem proving

Architecture functionality OK?performance OK?marketing OK?

know-howreviewsExcel / C prototypes

circuits equivalentto source?

formal verification

RTL Logic Designrandom-directed testformal verification

functionality OK?speed / area OK?power OK?

DFT (test) test coverage~100% ?

ATPGSAT

Place&Route connections?electrically OK?timing OK?

Design RulesChecking (DRC)

Masks$ 1,000,000

Chips packaging, testingreally works?

ESTEREL

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Combinational Circuit Proof Network

GOTRY PASS

REQ OK


GO1

1

0

Each operator is a proof componentCircuit graph of all proofs of outputs from inputs

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Constructive Boolean Propagation Logic

I e 0

I e and e’ 0

I e’ 0

I e and e’ 0

I e 1

I e and e’ 1

I e’ 1

I e 1

I e or e’ 1

I e’ 1

I e or e’ 1

I e 0

I e or e’ 0

I e’ 0

I e 0

I not e 1

I e 1

I not e 0

• Input vector I inputs → {0,1}• Formulae: I e b

I I I(I)

X e I e b

I X b

I e or not e 1 ssi I e 0 or I e 1

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The ABRO Synchronization Example

Memory WriteR : requestA : addressB : dataO : write

A / B /

A / OB / O

A B / O

R /

R /

R /

R /

Emit O as soon A and B have arrivedReset this behavior each R

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A / B /

A / OB / O

A B / O

R /

R /

R /

R /

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A / B /

A / OB / O

A B / O

R /

R /

R /

R /


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A / B /

A / OB / O

A B / O

R /

R /

R /

R /

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Priority problems:what if A, B, R together?

A / B /

A / OB / O

A B / O

R /

R /

R /

R /

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Esterel Linear Specification

loop abort { await A || await B }; emit O ; halt when R;end loop

loop abort { await A || await B }; haltwhen R;end loop

A / B /

A /B /

A B /

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A / B /

A / OB / O

A B / O

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loop abort { await A || await B }; emit O ; halt when Rend loop

A / B /

A / OB / O

A B / O

R /

R /

R /

R /

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A / B /

A / OB / O

A B / O

R /

R /

R /

R /

copies = residualsEsterel = sharing of residuals

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Esterel SyncCharts Linear Specification

A / B /

R /

/ O

Hierarchical synchronousconcurrent automata

(Synchronous Statecharts)


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Linear vs. Exponential

flat automaton Hierarchical automatonlinear

exponential explosion!

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Logical (SoS) Semantics

pE

E’ 0 p’ qE

F’ l q’

p ; q E’ U F’ l q’E

pE

E’ k p’ k 0

p ; qE’ k

p’ ; qE

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Logical (SoS) Semantics

pE

E’ k p’ qE

F’ l q’

p | qE

E’ U F’ max(k,l) p’ | q’

await sE

E 0 0

s E

await sE

E 1 await s

s E

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The ABRO Circuit (Proof Network)


suppressed by optimization

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Optimizing Register Allocation

e1

e2

e3

e0

a

b

b

ab

b

• 1-hot encoding state number explostion

e0 10e1 11e2 01e3 00

e0 01e1 10e2 11e3 11

good bad

n! possibilities, no heuristics !

• log(n) bits for n states can blow up the logic

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R

Ocombinational logic

registers

I

The key: balancing logic and registersEsterel / SyncCharts structural encoding

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The Secret: Linear Specification!

One register per explicit wait good logic / register balance

The better the program is written,the more efficient the circuit is!


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Replacing Register by Logic

Question: can we replace a given register by logic?Registers r1, r2,..., rn, reachability predicate (r1, r2,..., rn)

1. Question for r1 – looks difficult:

f. b1, b2,..., bn. (b1, b2,..., bn) b1 f(b2,..., bn)

2. Logical rephrasing – algorithmically much easier:

(0, b2,..., bn) (1, b2,..., bn) 0

Very efficient BDD-algorithms (Madre-Coudert-Touati)Yields results always better than manual designs

3. Iteration + heuristics

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Cyclic Circuit from Resource Sharing

F

G

O = if C then F(G(I)) else G(F(I))

C

C

I O

C10

10

10

Cyclic combinational circuits can be exponentiallysmaller than acyclic circuits for the same function

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Symmetric Round-Robin Protocol

A

B

okreq

reqok

only one ok in req orderafter the register set to1

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A

B

okreq

reqok

The 1 registerchanges every cycle

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Symmetric Round-Robin Protocol (4)

okreq

req

ok

req

ok

reqok

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Beware of the combinational cycle !

okreq

reqok

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The cycle is sound ifat least a register is 1,

since it is cut at an or gate

okreq

reqok

1

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okreq

reqok

The cycle is unsound ifall registers are 0

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The Three Kinds of Cyclic Circuits

2. Electrically and logically unsoundX XX not X

combinational part of the cyclic round-robinif all register outputs are 0

1. Electrically and logically sound (possibly under input conditions) ex: combinational part of the cyclic round-robin

if at least one register output is 1

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The Three Kinds of Cyclic Circuits

3. Strange circuitsHamlet : ToBe ToBe or not ToBe

ToBe

• Electrically stabilizes to 1 for some gate and wire delays, but not for all delays !

• Logically computes 1 in classical logic, but computes nothing in constructive logic

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Cyclic Circuits Analysis

When does a circuit stabilize for all delays?Which logical view is correct?

How to relate logic to electricity?

Theorem: with the right electrical delay model, electrical stabilization for all delays logical constructivity definedness w.r.t. ternary simulation

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Ternary simulation

1. Interpret equations over 0, 1, with 0 and 1 (Scott’s information ordering)

2. Monotonically extend basic Boolean functions

0 1 10 0 11 1 1 1

0 1 10 0 11 1 1 1

0 11 0

undefinable inC, Java, ML !

3. Compute the least fixpoint of the equation system

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Theorem: constructive propagation ternary simulation

• Solves good cyclic examples• Correctly rejects Hamlet

no constructive propagationleast fixpoint is ToBe

Questions: • Do they characterize electrical behavior?• How to model continuous-time signals?• What is the electrical meaning of ?

uninitialized? unstable? metastable?non-deterministic? etc.

G. Berry, Nancy

• Continous time in R+, discrete values in B {0,1}• Signal s: R+→B satisfying

– right-continuity: s(t) b >0. s[t,t+] b–non-Zenoness: finite number of changes for any [t,t’]

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Modeling Continuous Signals

i oDEL

DEL(i,o) (R+→B) (R+→B)

non-deterministic relation

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UI : Upbounded inertial delay model(Brzozowski-Seger 1995)

Inertiality: o cannot change without being unstable if o changes from not b to b at time t, then there exists > 0 s.t. i [t, t] b

Propagation: output cannot be unstable for time D without changing if i[t1,t2) b for t2 > t1+, then t[t1,t2] s.t. o[t,t2] b

i o

48G. Berry, Nancy 22/07/2011

0 1 2 3 4 5 6 7

i

o

o

49G. Berry, Nancy 22/07/2011

i

1

All wires UI-stabilize to 1, but constructive propagationand ternary simulation yield for them

Theorem (Shiple-Berry): if all wires and gates haveUI-delays, then constructiveness is equivalent toUI-stabilization

... but UI is non-compositional: delay→delay delay

2

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UN : Upbounded delay model(Mendler 2008)

Inertiality: outputs cannot change without unstable if o changes from not b to b at time t, then there exists > 0 s.t. i [t, t] b

i o

Propagation: output cannot be unstable for time D without changing if i[t1,t2) b for t2 > t1+, then t[t1,t2] s.t. o[t,t2] b

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The UN-logic

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UN is the Right Model (Mendler)

Theorem: for all circuits such that each combinational loop is cut by at least one UN-delay,

constructiveness UN-stabilisation

1. Deal with Horn-like clauses2. Define a simple entailment relation |3. Show equivalence between | and | for clauses4. Deduce that | performs electrical simulation5. Reduce to ternary simulation in the same logic

Constructiveness stabilization proved within the logic

G. Berry, Nancy

• Logic is fundamental for circuit design– design with Boolean logic – model-check for verification– use Boolean algorithms for optimization

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Conclusion

• Logic is fundamental to understand the relation between logic design and implementation– electricity is fundamentally constructive– UN-logic unifies continous and Boolean model

• Yet to be studied– non-Boolean signals– metastability modeling– application to SW real / discrete time fields (Matlab?)

Logic and Digital Circuits: from Practice to Theory

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