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Chapter 15: Design Examples Digital System Designs a nd Practices Using Ve rilog HDL and FPGAs @ 2008-2010, John Wiley 15-1 Chapter 15: Design Examples Department of Electronic Engineering National Taiwan Univers ity of Scien ce and Tec hnology Prof. Ming-Bo Lin
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Chapter 15: Design Examples
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-1
Chapter 15: Design Examples
Department of Electronic Engineering National Taiwan University of Science and Technology
Prof. Ming-Bo Lin
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Chapter 15: Design Examples
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-2
Syllabus
Objectives
BusData transfer General-purpose input and outputTimersUniversal asynchronous receiver and transmitter
A simple CPU design
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Chapter 15: Design Examples
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-3
Objectives
After completing this chapter, you will be able to:
Describe basic structures of µ P systemsUnderstand the basic operations of bus structuresUnderstand the essential operations of data transfer Understand the design principles of GPIOsUnderstand the design principles of timers
Understand the design principles of UARTsDescribe the design principles of CPUs
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Chapter 15: Design Examples
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-4
Syllabus
ObjectivesBus
A µ p system architectureBus structuresBus arbitration
Data transfer General-purpose input and output
TimersUniversal asynchronous receiver and transmitter A simple CPU design
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Chapter 15: Design Examples
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A Basic µ P System
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Chapter 15: Design Examples
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-6
Syllabus
ObjectivesBus
A µ p system architectureBus structuresBus arbitration
Data transfer General-purpose input and output
TimersUniversal asynchronous receiver and transmitter A simple CPU design
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Chapter 15: Design Examples
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Bus Structures
Tristate bususing tristate buffersoften called bus for short
Multiplexer-based bus
using multiplexers
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Chapter 15: Design Examples
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A Tristate Bus
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Chapter 15: Design Examples
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A Tristate Bus Example
// a tristate bus examplemodule tristate_bus (data, enable, qout);
parameter N = 2; // define bus widthinput enable;input [N-1:0] data;output [N-1:0] qout;wire [N-1:0] qout;
// the body of tristate busassign qout = enable ? data : {N{1'bz}};
endmodule
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Chapter 15: Design Examples
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A Bidirectional Bus Example
// a bidirectional bus examplemodule bidirectional_bus (data_to_bus, send, receive, data_from_bus, qout);
parameter N = 2; // define bus width
input send, receive;input [N-1:0] data_to_bus;output [N-1:0] data_from_bus;inout [N-1:0] qout; // bidirectional bus
wire [N-1:0] qout, data_from_bus;// the body of tristate busassign data_from_bus = receive ? qout : {N{1'bz}};assign qout = send ? data_to_bus : {N{1'bz}};endmodule
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Chapter 15: Design Examples
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A Multiplexer-Based Bus
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Chapter 15: Design Examples
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-12
Syllabus
ObjectivesBus
A µ p system architectureBus structuresBus arbitration
Data transfer General-purpose input and output
TimersUniversal asynchronous receiver and transmitter A simple CPU design
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Chapter 15: Design Examples
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Daisy-Chain Arbitration
Types of bus arbitration schemesdaisy-chain arbitrationradial arbitration
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Chapter 15: Design Examples
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-14
Syllabus
Objectives
BusData transfer Synchronous transfer mode
Asynchronous transfer modeGeneral-purpose input and outputTimersUniversal asynchronous receiver and transmitter A simple CPU design
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Chapter 15: Design Examples
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-15
Data Transfer Modes
Data transfer modessynchronous modeasynchronous mode
The actual data can be transferred in
parallel : a bundle of signals in parallelserial : a stream of bits
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Chapter 15: Design Examples
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Synchronously Parallel Data Transfers
Each data transfer is synchronous with clock signalBus master Bus slave
Two types
Single-clock bus cycleMultiple-clock bus cycle
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Chapter 15: Design Examples
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Synchronously Parallel Data Transfers
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Chapter 15: Design Examples
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Synchronously Serial Data Transfers
Explicitly clocking schemeImplicitly clocking scheme
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Chapter 15: Design Examples
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Synchronously Serial Data Transfers
Examples
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Chapter 15: Design Examples
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Syllabus
ObjectivesBusData transfer
Synchronous transfer mode
Asynchronous transfer modeGeneral-purpose input and outputTimersUniversal asynchronous receiver and transmitter A simple CPU design
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Chapter 15: Design Examples
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Asynchronous Data Transfers
Each data transfer occurs at randomControl approaches
strobe schemehandshaking scheme
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Chapter 15: Design Examples
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Strobe
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Chapter 15: Design Examples
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Handshaking
Four events are proceeded in a cycle order ready (request)data validdata acceptanceacknowledge
h l
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Chapter 15: Design Examples
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Handshaking
Two typessource-initiated transfer destination-initiated transfer
Ch 15 D i E l
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Chapter 15: Design Examples
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Asynchronously Serial Data Transfers
Transmitter Receiver
Ch t 15 D i E l
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Chapter 15: Design Examples
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Asynchronously Serial Data Transfers
Chapter 15: Design Examples
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Chapter 15: Design Examples
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-27
Syllabus
ObjectivesBusData transfer General-purpose input and output
TimersUniversal asynchronous receiver and transmitter
A simple CPU design
Chapter 15: Design Examples
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Chapter 15: Design Examples
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General-Purpose Input and Output Devices
The general-purpose input and output (GPIO)inputoutput
bidirectional
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Chapter 15: Design Examples
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-29
General-Purpose Input and Output Devices
An example of 8-bit GPIO
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Chapter 15: Design Examples
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-30
Design Issues of GPIO Devices
Readback capability of PORT register Group or individual bit controlSelection the value of DDR Handshaking control
Readback capability of DDR Input latch
Input/Output pull-upDrive capability
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Chapter 15: Design Examples
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-31
General-Purpose Input and Output Devices
The ith-bit of two GPIO examples
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Chapter 15: Design Examples
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-32
Syllabus
ObjectivesBusData transfer General-purpose input and output
TimersInterfaceBasic operation modes
Advanced operation modesUniversal asynchronous receiver and transmitter A simple CPU design
Chapter 15: Design Examples
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p g p
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-33
Timers
Important applicationstime-delay creationevent countingtime measurement
period measurement pulse-width measurementtime-of-day tracking
waveform generation periodic interrupt generation
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p g p
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-34
Timers
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Syllabus
ObjectivesBusData transfer General-purpose input and output
TimersInterfaceBasic operation modes
Universal asynchronous receiver and transmitter A simple CPU design
Chapter 15: Design Examples
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Basic Timer Operations
TimersWhat is a timer?What is a counter?What is a programmable counter?What is a programmable timer?
Basic operation modesterminal count (binary/BCD event counter)
rate generation(digital) monostable (or called one-shot)square-wave generation
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Terminal Count
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Rate Generation
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Retriggerable Monostable (One-Shot) Operation
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Square-Wave Generation
(b) Block diagram of square-wave mode
(a) A waveform example of square-wave mode
clk
out
3 2 1 0(4)0(4)3 2 14
Latch register = 4
Latch
timer
Data buswr
rd
out
gateclk
timer_loadgenerator
timer_enable
timer_load DCK
Q
timer is 1
Shift plus LSB
out logic
latch_load
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Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-41
Syllabus
ObjectivesBus
Data transfer General-purpose input and outputTimersUniversal asynchronous receiver and transmitter
InterfaceBasic transmitter structure
Basic receiver structureBaud-rate generators
A simple CPU design
Chapter 15: Design Examples
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Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 15-42
UARTs
Hardware modelthe CPU interfacethe I/O interface
Software modelreceiver data register (RDR)transmitter data register (TDR)status register (SR)
control register (CR)
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UARTs
Chapter 15: Design Examples
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Syllabus
ObjectivesBus
Data transfer General-purpose input and outputTimersUniversal asynchronous receiver and transmitter
InterfaceBasic transmitter structure
Basic receiver structureBaud-rate generators
A simple CPU design
Chapter 15: Design Examples
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Design Issues of UARTs
Baud rateSampling clock frequencyStop bitsParity check
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A Transmitter of UARTs
The transmittera transmitter shift data register (TSDR)
a TDR empty flag (TE)a transmitter control circuita TDR
parity generator
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A Transmitter of UARTs
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Syllabus
ObjectivesBus
Data transfer General-purpose input and outputTimersUniversal asynchronous receiver and transmitter
InterfaceBasic transmitter structure
Basic receiver structureBaud-rate generators
A simple CPU design
Chapter 15: Design Examples
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A Receiver of UARTs
The receiver a RDR
a receiver shift data register (RSDR)a status register a receiver control circuit
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A Receiver of UARTs
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Syllabus
ObjectivesBus
Data transfer General-purpose input and outputTimersUniversal asynchronous receiver and transmitter
InterfaceBasic transmitter structure
Basic receiver structureBaud-rate generators
A simple CPU design
Chapter 15: Design Examples
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Baud-Rate Generators
The baud-rate generator provides TxC and RxC
Design approachesMultiplexer-based approachTimer-based approachOthers
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Chapter 15: Design Examples
S ll b
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Syllabus
ObjectivesBusData transfer General-purpose input and outputTimersUniversal asynchronous receiver and transmitter A simple CPU design
Programming modelDatapath designControl unit design
Chapter 15: Design Examples
CPU B i O ti
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CPU Basic Operations
Chapter 15: Design Examples
Th S ft M d l f CPU
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The Software Model of CPU
The programming modelInstruction formatsAddressing modesInstruction set
Chapter 15: Design Examples
The Programming Mode
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The Programming Mode
Chapter 15: Design Examples
Instruction Formats
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Instruction Formats
Two major partsOpcode
Operand
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Addressing Modes
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Addressing Modes
The ways that operands are fetchedregister
indexedregister indirectimmediate
Chapter 15: Design Examples
The Instruction Set
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The Instruction Set
Double-operand instruction set
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The Instruction Set
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The Instruction Set
Single-operand instruction set
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The Instruction Set
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The Instruction Set
Jump instruction set
Chapter 15: Design Examples
Syllabus
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Syllabus
ObjectivesBus
Data transfer General-purpose input and outputTimersUniversal asynchronous receiver and transmitter A simple CPU design
Programming modelDatapath designControl unit design
Chapter 15: Design Examples
A Datapath Design
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A Datapath Design
Chapter 15: Design Examples
ALU Functions
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ALU Functions
Chapter 15: Design Examples
Syllabus
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Syllabus
ObjectivesBus
Data transfer General-purpose input and outputTimersUniversal asynchronous receiver and transmitter A simple CPU design
Programming modelDatapath designControl unit design
Chapter 15: Design Examples
A Control Unit
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The decoder-based approach
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A Control Unit
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The operations of T3 and T4 are determined separately byeach instruction
