LM3S2533Microcontroller - Farnell element14 · 10 General-PurposeTimers.....202 10.1...

LM3S2533 MicrocontrollerDATA SHEET

Copyr ight © 2007 Luminary Micro, Inc.DS-LM3S2533-1972

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November 30, 20072Preliminary

Table of ContentsAbout This Document .................................................................................................................... 20Audience .............................................................................................................................................. 20About This Manual ................................................................................................................................ 20Related Documents ............................................................................................................................... 20Documentation Conventions .................................................................................................................. 20

1 Architectural Overview ...................................................................................................... 221.1 Product Features ...................................................................................................................... 221.2 Target Applications .................................................................................................................... 281.3 High-Level Block Diagram ......................................................................................................... 281.4 Functional Overview .................................................................................................................. 291.4.1 ARM Cortex™-M3 ..................................................................................................................... 301.4.2 Motor Control Peripherals .......................................................................................................... 301.4.3 Analog Peripherals .................................................................................................................... 311.4.4 Serial Communications Peripherals ............................................................................................ 321.4.5 System Peripherals ................................................................................................................... 331.4.6 Memory Peripherals .................................................................................................................. 341.4.7 Additional Features ................................................................................................................... 341.4.8 Hardware Details ...................................................................................................................... 35

2 ARM Cortex-M3 Processor Core ...................................................................................... 362.1 Block Diagram .......................................................................................................................... 372.2 Functional Description ............................................................................................................... 372.2.1 Serial Wire and JTAG Debug ..................................................................................................... 372.2.2 Embedded Trace Macrocell (ETM) ............................................................................................. 382.2.3 Trace Port Interface Unit (TPIU) ................................................................................................. 382.2.4 ROM Table ............................................................................................................................... 382.2.5 Memory Protection Unit (MPU) ................................................................................................... 382.2.6 Nested Vectored Interrupt Controller (NVIC) ................................................................................ 38

3 Memory Map ....................................................................................................................... 424 Interrupts ............................................................................................................................ 445 JTAG Interface .................................................................................................................... 475.1 Block Diagram .......................................................................................................................... 485.2 Functional Description ............................................................................................................... 485.2.1 JTAG Interface Pins .................................................................................................................. 495.2.2 JTAG TAP Controller ................................................................................................................. 505.2.3 Shift Registers .......................................................................................................................... 515.2.4 Operational Considerations ........................................................................................................ 515.3 Initialization and Configuration ................................................................................................... 545.4 Register Descriptions ................................................................................................................ 545.4.1 Instruction Register (IR) ............................................................................................................. 545.4.2 Data Registers .......................................................................................................................... 56

6 System Control ................................................................................................................... 586.1 Functional Description ............................................................................................................... 586.1.1 Device Identification .................................................................................................................. 586.1.2 Reset Control ............................................................................................................................ 58

3November 30, 2007Preliminary

LM3S2533 Microcontroller

6.1.3 Power Control ........................................................................................................................... 616.1.4 Clock Control ............................................................................................................................ 616.1.5 System Control ......................................................................................................................... 636.2 Initialization and Configuration ................................................................................................... 646.3 Register Map ............................................................................................................................ 646.4 Register Descriptions ................................................................................................................ 65

7 Hibernation Module .......................................................................................................... 1187.1 Block Diagram ........................................................................................................................ 1197.2 Functional Description ............................................................................................................. 1197.2.1 Register Access Timing ........................................................................................................... 1197.2.2 Clock Source .......................................................................................................................... 1207.2.3 Battery Management ............................................................................................................... 1207.2.4 Real-Time Clock ...................................................................................................................... 1207.2.5 Non-Volatile Memory ............................................................................................................... 1217.2.6 Power Control ......................................................................................................................... 1217.2.7 Interrupts and Status ............................................................................................................... 1217.3 Initialization and Configuration ................................................................................................. 1227.3.1 Initialization ............................................................................................................................. 1227.3.2 RTC Match Functionality (No Hibernation) ................................................................................ 1227.3.3 RTC Match/Wake-Up from Hibernation ..................................................................................... 1227.3.4 External Wake-Up from Hibernation .......................................................................................... 1237.3.5 RTC/External Wake-Up from Hibernation .................................................................................. 1237.4 Register Map .......................................................................................................................... 1237.5 Register Descriptions .............................................................................................................. 124

8 Internal Memory ............................................................................................................... 1378.1 Block Diagram ........................................................................................................................ 1378.2 Functional Description ............................................................................................................. 1378.2.1 SRAM Memory ........................................................................................................................ 1378.2.2 Flash Memory ......................................................................................................................... 1388.3 Flash Memory Initialization and Configuration ........................................................................... 1398.3.1 Flash Programming ................................................................................................................. 1398.3.2 Nonvolatile Register Programming ........................................................................................... 1408.4 Register Map .......................................................................................................................... 1408.5 Flash Register Descriptions (Flash Control Offset) ..................................................................... 1418.6 Flash Register Descriptions (System Control Offset) .................................................................. 148

9 General-Purpose Input/Outputs (GPIOs) ....................................................................... 1619.1 Functional Description ............................................................................................................. 1619.1.1 Data Control ........................................................................................................................... 1629.1.2 Interrupt Control ...................................................................................................................... 1639.1.3 Mode Control .......................................................................................................................... 1649.1.4 Commit Control ....................................................................................................................... 1649.1.5 Pad Control ............................................................................................................................. 1649.1.6 Identification ........................................................................................................................... 1649.2 Initialization and Configuration ................................................................................................. 1649.3 Register Map .......................................................................................................................... 1669.4 Register Descriptions .............................................................................................................. 167


Table of Contents

10 General-Purpose Timers ................................................................................................. 20210.1 Block Diagram ........................................................................................................................ 20210.2 Functional Description ............................................................................................................. 20310.2.1 GPTM Reset Conditions .......................................................................................................... 20410.2.2 32-Bit Timer Operating Modes .................................................................................................. 20410.2.3 16-Bit Timer Operating Modes .................................................................................................. 20510.3 Initialization and Configuration ................................................................................................. 20910.3.1 32-Bit One-Shot/Periodic Timer Mode ....................................................................................... 20910.3.2 32-Bit Real-Time Clock (RTC) Mode ......................................................................................... 21010.3.3 16-Bit One-Shot/Periodic Timer Mode ....................................................................................... 21010.3.4 16-Bit Input Edge Count Mode ................................................................................................. 21110.3.5 16-Bit Input Edge Timing Mode ................................................................................................ 21110.3.6 16-Bit PWM Mode ................................................................................................................... 21210.4 Register Map .......................................................................................................................... 21210.5 Register Descriptions .............................................................................................................. 213

11 Watchdog Timer ............................................................................................................... 23811.1 Block Diagram ........................................................................................................................ 23811.2 Functional Description ............................................................................................................. 23811.3 Initialization and Configuration ................................................................................................. 23911.4 Register Map .......................................................................................................................... 23911.5 Register Descriptions .............................................................................................................. 240

12 Analog-to-Digital Converter (ADC) ................................................................................. 26112.1 Block Diagram ........................................................................................................................ 26212.2 Functional Description ............................................................................................................. 26212.2.1 Sample Sequencers ................................................................................................................ 26212.2.2 Module Control ........................................................................................................................ 26312.2.3 Hardware Sample Averaging Circuit ......................................................................................... 26412.2.4 Analog-to-Digital Converter ...................................................................................................... 26412.2.5 Test Modes ............................................................................................................................. 26412.2.6 Internal Temperature Sensor .................................................................................................... 26412.3 Initialization and Configuration ................................................................................................. 26512.3.1 Module Initialization ................................................................................................................. 26512.3.2 Sample Sequencer Configuration ............................................................................................. 26512.4 Register Map .......................................................................................................................... 26612.5 Register Descriptions .............................................................................................................. 267

13 Universal Asynchronous Receivers/Transmitters (UARTs) ......................................... 29413.1 Block Diagram ........................................................................................................................ 29513.2 Functional Description ............................................................................................................. 29513.2.1 Transmit/Receive Logic ........................................................................................................... 29513.2.2 Baud-Rate Generation ............................................................................................................. 29613.2.3 Data Transmission .................................................................................................................. 29713.2.4 Serial IR (SIR) ......................................................................................................................... 29713.2.5 FIFO Operation ....................................................................................................................... 29813.2.6 Interrupts ................................................................................................................................ 29813.2.7 Loopback Operation ................................................................................................................ 29913.2.8 IrDA SIR block ........................................................................................................................ 29913.3 Initialization and Configuration ................................................................................................. 29913.4 Register Map .......................................................................................................................... 300



13.5 Register Descriptions .............................................................................................................. 301

14 Synchronous Serial Interface (SSI) ................................................................................ 33514.1 Block Diagram ........................................................................................................................ 33514.2 Functional Description ............................................................................................................. 33514.2.1 Bit Rate Generation ................................................................................................................. 33614.2.2 FIFO Operation ....................................................................................................................... 33614.2.3 Interrupts ................................................................................................................................ 33614.2.4 Frame Formats ....................................................................................................................... 33714.3 Initialization and Configuration ................................................................................................. 34414.4 Register Map .......................................................................................................................... 34514.5 Register Descriptions .............................................................................................................. 346

15 Inter-Integrated Circuit (I2C) Interface ............................................................................ 37215.1 Block Diagram ........................................................................................................................ 37215.2 Functional Description ............................................................................................................. 37215.2.1 I2C Bus Functional Overview .................................................................................................... 37315.2.2 Available Speed Modes ........................................................................................................... 37515.2.3 Interrupts ................................................................................................................................ 37615.2.4 Loopback Operation ................................................................................................................ 37615.2.5 Command Sequence Flow Charts ............................................................................................ 37715.3 Initialization and Configuration ................................................................................................. 38315.4 I2C Register Map ..................................................................................................................... 38415.5 Register Descriptions (I2C Master) ........................................................................................... 38515.6 Register Descriptions (I2C Slave) ............................................................................................. 398

16 Controller Area Network (CAN) Module ......................................................................... 40716.1 Controller Area Network Overview ............................................................................................ 40716.2 Controller Area Network Features ............................................................................................ 40716.3 Controller Area Network Block Diagram .................................................................................... 40816.4 Controller Area Network Functional Description ......................................................................... 40916.4.1 Initialization ............................................................................................................................. 40916.4.2 Operation ............................................................................................................................... 41016.4.3 Transmitting Message Objects ................................................................................................. 41016.4.4 Configuring a Transmit Message Object .................................................................................... 41016.4.5 Updating a Transmit Message Object ....................................................................................... 41116.4.6 Accepting Received Message Objects ...................................................................................... 41116.4.7 Receiving a Data Frame .......................................................................................................... 41216.4.8 Receiving a Remote Frame ...................................................................................................... 41216.4.9 Receive/Transmit Priority ......................................................................................................... 41216.4.10 Configuring a Receive Message Object .................................................................................... 41216.4.11 Handling of Received Message Objects .................................................................................... 41316.4.12 Handling of Interrupts .............................................................................................................. 41316.4.13 Bit Timing Configuration Error Considerations ........................................................................... 41416.4.14 Bit Time and Bit Rate ............................................................................................................... 41416.4.15 Calculating the Bit Timing Parameters ...................................................................................... 41616.5 Controller Area Network Register Map ...................................................................................... 41816.6 Register Descriptions .............................................................................................................. 420

17 Analog Comparators ....................................................................................................... 44817.1 Block Diagram ........................................................................................................................ 449


Table of Contents

17.2 Functional Description ............................................................................................................. 44917.2.1 Internal Reference Programming .............................................................................................. 45117.3 Initialization and Configuration ................................................................................................. 45217.4 Register Map .......................................................................................................................... 45217.5 Register Descriptions .............................................................................................................. 453

18 Pulse Width Modulator (PWM) ........................................................................................ 46118.1 Block Diagram ........................................................................................................................ 46118.2 Functional Description ............................................................................................................. 46118.2.1 PWM Timer ............................................................................................................................. 46118.2.2 PWM Comparators .................................................................................................................. 46218.2.3 PWM Signal Generator ............................................................................................................ 46318.2.4 Dead-Band Generator ............................................................................................................. 46418.2.5 Interrupt/ADC-Trigger Selector ................................................................................................. 46418.2.6 Synchronization Methods ......................................................................................................... 46418.2.7 Fault Conditions ...................................................................................................................... 46518.2.8 Output Control Block ............................................................................................................... 46518.3 Initialization and Configuration ................................................................................................. 46518.4 Register Map .......................................................................................................................... 46618.5 Register Descriptions .............................................................................................................. 468

19 Pin Diagram ...................................................................................................................... 49720 Signal Tables .................................................................................................................... 49821 Operating Characteristics ............................................................................................... 51222 Electrical Characteristics ................................................................................................ 51322.1 DC Characteristics .................................................................................................................. 51322.1.1 Maximum Ratings ................................................................................................................... 51322.1.2 Recommended DC Operating Conditions .................................................................................. 51322.1.3 On-Chip Low Drop-Out (LDO) Regulator Characteristics ............................................................ 51422.1.4 Power Specifications ............................................................................................................... 51422.1.5 Flash Memory Characteristics .................................................................................................. 51622.2 AC Characteristics ................................................................................................................... 51622.2.1 Load Conditions ...................................................................................................................... 51622.2.2 Clocks .................................................................................................................................... 51622.2.3 Analog-to-Digital Converter ...................................................................................................... 51722.2.4 Analog Comparator ................................................................................................................. 51822.2.5 I2C ......................................................................................................................................... 51822.2.6 Hibernation Module ................................................................................................................. 51922.2.7 Synchronous Serial Interface (SSI) ........................................................................................... 51922.2.8 JTAG and Boundary Scan ........................................................................................................ 52122.2.9 General-Purpose I/O ............................................................................................................... 52222.2.10 Reset ..................................................................................................................................... 523

23 Package Information ........................................................................................................ 525A Serial Flash Loader .......................................................................................................... 527A.1 Serial Flash Loader ................................................................................................................. 527A.2 Interfaces ............................................................................................................................... 527A.2.1 UART ..................................................................................................................................... 527A.2.2 SSI ......................................................................................................................................... 527



A.3 Packet Handling ...................................................................................................................... 528A.3.1 Packet Format ........................................................................................................................ 528A.3.2 Sending Packets ..................................................................................................................... 528A.3.3 Receiving Packets ................................................................................................................... 528A.4 Commands ............................................................................................................................. 529A.4.1 COMMAND_PING (0X20) ........................................................................................................ 529A.4.2 COMMAND_GET_STATUS (0x23) ........................................................................................... 529A.4.3 COMMAND_DOWNLOAD (0x21) ............................................................................................. 529A.4.4 COMMAND_SEND_DATA (0x24) ............................................................................................. 530A.4.5 COMMAND_RUN (0x22) ......................................................................................................... 530A.4.6 COMMAND_RESET (0x25) ..................................................................................................... 530

B Register Quick Reference ............................................................................................... 532C Ordering and Contact Information ................................................................................. 552C.1 Ordering Information ................................................................................................................ 552C.2 Kits ......................................................................................................................................... 552C.3 Company Information .............................................................................................................. 552C.4 Support Information ................................................................................................................. 553


Table of Contents

List of FiguresFigure 1-1. Stellaris® 2000 Series High-Level Block Diagram ............................................................... 29Figure 2-1. CPU Block Diagram ......................................................................................................... 37Figure 2-2. TPIU Block Diagram ........................................................................................................ 38Figure 5-1. JTAG Module Block Diagram ............................................................................................ 48Figure 5-2. Test Access Port State Machine ....................................................................................... 51Figure 5-3. IDCODE Register Format ................................................................................................. 56Figure 5-4. BYPASS Register Format ................................................................................................ 57Figure 5-5. Boundary Scan Register Format ....................................................................................... 57Figure 6-1. External Circuitry to Extend Reset .................................................................................... 59Figure 7-1. Hibernation Module Block Diagram ................................................................................. 119Figure 8-1. Flash Block Diagram ...................................................................................................... 137Figure 9-1. GPIO Port Block Diagram ............................................................................................... 162Figure 9-2. GPIODATA Write Example ............................................................................................. 163Figure 9-3. GPIODATA Read Example ............................................................................................. 163Figure 10-1. GPTM Module Block Diagram ........................................................................................ 203Figure 10-2. 16-Bit Input Edge Count Mode Example .......................................................................... 207Figure 10-3. 16-Bit Input Edge Time Mode Example ........................................................................... 208Figure 10-4. 16-Bit PWM Mode Example ............................................................................................ 209Figure 11-1. WDT Module Block Diagram .......................................................................................... 238Figure 12-1. ADC Module Block Diagram ........................................................................................... 262Figure 12-2. Internal Temperature Sensor Characteristic ..................................................................... 265Figure 13-1. UART Module Block Diagram ......................................................................................... 295Figure 13-2. UART Character Frame ................................................................................................. 296Figure 13-3. IrDA Data Modulation ..................................................................................................... 298Figure 14-1. SSI Module Block Diagram ............................................................................................. 335Figure 14-2. TI Synchronous Serial Frame Format (Single Transfer) .................................................... 337Figure 14-3. TI Synchronous Serial Frame Format (Continuous Transfer) ............................................ 338Figure 14-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 ...................................... 339Figure 14-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .............................. 339Figure 14-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ..................................................... 340Figure 14-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ........................... 341Figure 14-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 .................... 341Figure 14-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ..................................................... 342Figure 14-10. MICROWIRE Frame Format (Single Frame) .................................................................... 343Figure 14-11. MICROWIRE Frame Format (Continuous Transfer) ......................................................... 344Figure 14-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ........................ 344Figure 15-1. I2C Block Diagram ......................................................................................................... 372Figure 15-2. I2C Bus Configuration .................................................................................................... 373Figure 15-3. START and STOP Conditions ......................................................................................... 373Figure 15-4. Complete Data Transfer with a 7-Bit Address ................................................................... 374Figure 15-5. R/S Bit in First Byte ........................................................................................................ 374Figure 15-6. Data Validity During Bit Transfer on the I2C Bus ............................................................... 374Figure 15-7. Master Single SEND ...................................................................................................... 377Figure 15-8. Master Single RECEIVE ................................................................................................. 378Figure 15-9. Master Burst SEND ....................................................................................................... 379



Figure 15-10. Master Burst RECEIVE .................................................................................................. 380Figure 15-11. Master Burst RECEIVE after Burst SEND ........................................................................ 381Figure 15-12. Master Burst SEND after Burst RECEIVE ........................................................................ 382Figure 15-13. Slave Command Sequence ............................................................................................ 383Figure 16-1. CAN Module Block Diagram ........................................................................................... 408Figure 16-2. CAN Bit Time ................................................................................................................ 415Figure 17-1. Analog Comparator Module Block Diagram ..................................................................... 449Figure 17-2. Structure of Comparator Unit .......................................................................................... 450Figure 17-3. Comparator Internal Reference Structure ........................................................................ 451Figure 18-1. PWM Module Block Diagram .......................................................................................... 461Figure 18-2. PWM Count-Down Mode ................................................................................................ 462Figure 18-3. PWM Count-Up/Down Mode .......................................................................................... 463Figure 18-4. PWM Generation Example In Count-Up/Down Mode ....................................................... 463Figure 18-5. PWM Dead-Band Generator ........................................................................................... 464Figure 19-1. Pin Connection Diagram ................................................................................................ 497Figure 22-1. Load Conditions ............................................................................................................ 516Figure 22-2. I2C Timing ..................................................................................................................... 519Figure 22-3. Hibernation Module Timing ............................................................................................. 519Figure 22-4. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement .............. 520Figure 22-5. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............................. 520Figure 22-6. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................................................. 521Figure 22-7. JTAG Test Clock Input Timing ......................................................................................... 522Figure 22-8. JTAG Test Access Port (TAP) Timing .............................................................................. 522Figure 22-9. JTAG TRST Timing ........................................................................................................ 522Figure 22-10. External Reset Timing (RST) .......................................................................................... 523Figure 22-11. Power-On Reset Timing ................................................................................................. 524Figure 22-12. Brown-Out Reset Timing ................................................................................................ 524Figure 22-13. Software Reset Timing ................................................................................................... 524Figure 22-14. Watchdog Reset Timing ................................................................................................. 524Figure 23-1. 100-Pin LQFP Package .................................................................................................. 525


Table of Contents

List of TablesTable 1. Documentation Conventions ............................................................................................ 20Table 3-1. Memory Map ................................................................................................................... 42Table 4-1. Exception Types .............................................................................................................. 44Table 4-2. Interrupts ........................................................................................................................ 45Table 5-1. JTAG Port Pins Reset State ............................................................................................. 49Table 5-2. JTAG Instruction Register Commands ............................................................................... 54Table 6-1. System Control Register Map ........................................................................................... 64Table 7-1. Hibernation Module Register Map ................................................................................... 123Table 8-1. Flash Protection Policy Combinations ............................................................................. 139Table 8-2. Flash Resident Registers ............................................................................................... 140Table 8-3. Flash Register Map ........................................................................................................ 140Table 9-1. GPIO Pad Configuration Examples ................................................................................. 165Table 9-2. GPIO Interrupt Configuration Example ............................................................................ 165Table 9-3. GPIO Register Map ....................................................................................................... 166Table 10-1. Available CCP Pins ........................................................................................................ 203Table 10-2. 16-Bit Timer With Prescaler Configurations ..................................................................... 206Table 10-3. Timers Register Map ...................................................................................................... 212Table 11-1. Watchdog Timer Register Map ........................................................................................ 239Table 12-1. Samples and FIFO Depth of Sequencers ........................................................................ 262Table 12-2. ADC Register Map ......................................................................................................... 266Table 13-1. UART Register Map ....................................................................................................... 300Table 14-1. SSI Register Map .......................................................................................................... 345Table 15-1. Examples of I2C Master Timer Period versus Speed Mode ............................................... 375Table 15-2. Inter-Integrated Circuit (I2C) Interface Register Map ......................................................... 384Table 15-3. Write Field Decoding for I2CMCS[3:0] Field (Sheet 1 of 3) ................................................ 389Table 16-1. Transmit Message Object Bit Settings ............................................................................. 411Table 16-2. Receive Message Object Bit Settings .............................................................................. 413Table 16-3. CAN Protocol Ranges .................................................................................................... 415Table 16-4. CAN Register Map ......................................................................................................... 418Table 17-1. Comparator 0 Operating Modes ...................................................................................... 450Table 17-2. Comparator 1 Operating Modes ..................................................................................... 450Table 17-3. Comparator 2 Operating Modes ...................................................................................... 451Table 17-4. Internal Reference Voltage and ACREFCTL Field Values ................................................. 451Table 17-5. Analog Comparators Register Map ................................................................................. 453Table 18-1. PWM Register Map ........................................................................................................ 466Table 20-1. Signals by Pin Number ................................................................................................... 498Table 20-2. Signals by Signal Name ................................................................................................. 502Table 20-3. Signals by Function, Except for GPIO ............................................................................. 506Table 20-4. GPIO Pins and Alternate Functions ................................................................................. 509Table 21-1. Temperature Characteristics ........................................................................................... 512Table 21-2. Thermal Characteristics ................................................................................................. 512Table 22-1. Maximum Ratings .......................................................................................................... 513Table 22-2. Recommended DC Operating Conditions ........................................................................ 513Table 22-3. LDO Regulator Characteristics ....................................................................................... 514Table 22-4. Detailed Power Specifications ........................................................................................ 515Table 22-5. Flash Memory Characteristics ........................................................................................ 516



Table 22-6. Phase Locked Loop (PLL) Characteristics ....................................................................... 516Table 22-7. Clock Characteristics ..................................................................................................... 516Table 22-8. Crystal Characteristics ................................................................................................... 517Table 22-9. ADC Characteristics ....................................................................................................... 517Table 22-10. Analog Comparator Characteristics ................................................................................. 518Table 22-11. Analog Comparator Voltage Reference Characteristics .................................................... 518Table 22-12. I2C Characteristics ......................................................................................................... 518Table 22-13. Hibernation Module Characteristics ................................................................................. 519Table 22-14. SSI Characteristics ........................................................................................................ 519Table 22-15. JTAG Characteristics ..................................................................................................... 521Table 22-16. GPIO Characteristics ..................................................................................................... 523Table 22-17. Reset Characteristics ..................................................................................................... 523Table C-1. Part Ordering Information ............................................................................................... 552


Table of Contents

List of RegistersSystem Control .............................................................................................................................. 58Register 1: Device Identification 0 (DID0), offset 0x000 ....................................................................... 66Register 2: Brown-Out Reset Control (PBORCTL), offset 0x030 .......................................................... 68Register 3: LDO Power Control (LDOPCTL), offset 0x034 ................................................................... 69Register 4: Raw Interrupt Status (RIS), offset 0x050 ........................................................................... 70Register 5: Interrupt Mask Control (IMC), offset 0x054 ........................................................................ 71Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................... 72Register 7: Reset Cause (RESC), offset 0x05C .................................................................................. 73Register 8: Run-Mode Clock Configuration (RCC), offset 0x060 .......................................................... 74Register 9: XTAL to PLL Translation (PLLCFG), offset 0x064 .............................................................. 78Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070 ...................................................... 79Register 11: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 .......................................... 81Register 12: Device Identification 1 (DID1), offset 0x004 ....................................................................... 82Register 13: Device Capabilities 0 (DC0), offset 0x008 ......................................................................... 84Register 14: Device Capabilities 1 (DC1), offset 0x010 ......................................................................... 85Register 15: Device Capabilities 2 (DC2), offset 0x014 ......................................................................... 87Register 16: Device Capabilities 3 (DC3), offset 0x018 ......................................................................... 89Register 17: Device Capabilities 4 (DC4), offset 0x01C ......................................................................... 92Register 18: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 .................................... 93Register 19: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 .................................. 95Register 20: Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 ......................... 97Register 21: Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 .................................... 99Register 22: Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 ................................. 102Register 23: Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 ....................... 105Register 24: Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 ................................... 108Register 25: Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 ................................. 110Register 26: Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 ....................... 112Register 27: Software Reset Control 0 (SRCR0), offset 0x040 ............................................................. 114Register 28: Software Reset Control 1 (SRCR1), offset 0x044 ............................................................. 115Register 29: Software Reset Control 2 (SRCR2), offset 0x048 ............................................................. 117

Hibernation Module ..................................................................................................................... 118Register 1: Hibernation RTC Counter (HIBRTCC), offset 0x000 ......................................................... 125Register 2: Hibernation RTC Match 0 (HIBRTCM0), offset 0x004 ....................................................... 126Register 3: Hibernation RTC Match 1 (HIBRTCM1), offset 0x008 ....................................................... 127Register 4: Hibernation RTC Load (HIBRTCLD), offset 0x00C ........................................................... 128Register 5: Hibernation Control (HIBCTL), offset 0x010 ..................................................................... 129Register 6: Hibernation Interrupt Mask (HIBIM), offset 0x014 ............................................................. 131Register 7: Hibernation Raw Interrupt Status (HIBRIS), offset 0x018 .................................................. 132Register 8: Hibernation Masked Interrupt Status (HIBMIS), offset 0x01C ............................................ 133Register 9: Hibernation Interrupt Clear (HIBIC), offset 0x020 ............................................................. 134Register 10: Hibernation RTC Trim (HIBRTCT), offset 0x024 ............................................................... 135Register 11: Hibernation Data (HIBDATA), offset 0x030-0x12C ............................................................ 136

Internal Memory ........................................................................................................................... 137Register 1: Flash Memory Address (FMA), offset 0x000 .................................................................... 142Register 2: Flash Memory Data (FMD), offset 0x004 ......................................................................... 143



Register 3: Flash Memory Control (FMC), offset 0x008 ..................................................................... 144Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................ 146Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................ 147Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 ..................... 148Register 7: USec Reload (USECRL), offset 0x140 ............................................................................ 149Register 8: Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 ................... 150Register 9: Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 ............... 151Register 10: User Debug (USER_DBG), offset 0x1D0 ......................................................................... 152Register 11: User Register 0 (USER_REG0), offset 0x1E0 .................................................................. 153Register 12: User Register 1 (USER_REG1), offset 0x1E4 .................................................................. 154Register 13: Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 .................................... 155Register 14: Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 .................................... 156Register 15: Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C ................................... 157Register 16: Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 ............................... 158Register 17: Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 ............................... 159Register 18: Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C ............................... 160

General-Purpose Input/Outputs (GPIOs) ................................................................................... 161Register 1: GPIO Data (GPIODATA), offset 0x000 ............................................................................ 168Register 2: GPIO Direction (GPIODIR), offset 0x400 ......................................................................... 169Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404 .................................................................. 170Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 ........................................................ 171Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C ................................................................ 172Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410 ................................................................... 173Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414 ........................................................ 174Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ................................................... 175Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C ................................................................ 176Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 ............................................ 177Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 ........................................................ 179Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 ........................................................ 180Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 ........................................................ 181Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C ......................................................... 182Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510 ................................................................ 183Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514 ........................................................... 184Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 ................................................ 185Register 18: GPIO Digital Enable (GPIODEN), offset 0x51C ................................................................ 186Register 19: GPIO Lock (GPIOLOCK), offset 0x520 ............................................................................ 187Register 20: GPIO Commit (GPIOCR), offset 0x524 ............................................................................ 188Register 21: GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 ....................................... 190Register 22: GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 ....................................... 191Register 23: GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 ....................................... 192Register 24: GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC ...................................... 193Register 25: GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 ....................................... 194Register 26: GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4 ....................................... 195Register 27: GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 ....................................... 196Register 28: GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC ...................................... 197Register 29: GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 .......................................... 198Register 30: GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 .......................................... 199Register 31: GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 .......................................... 200


Table of Contents

Register 32: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC ......................................... 201

General-Purpose Timers ............................................................................................................. 202Register 1: GPTM Configuration (GPTMCFG), offset 0x000 .............................................................. 214Register 2: GPTM TimerA Mode (GPTMTAMR), offset 0x004 ............................................................ 215Register 3: GPTM TimerB Mode (GPTMTBMR), offset 0x008 ............................................................ 217Register 4: GPTM Control (GPTMCTL), offset 0x00C ........................................................................ 219Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018 .............................................................. 222Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C ..................................................... 224Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ................................................ 225Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024 .............................................................. 226Register 9: GPTM TimerA Interval Load (GPTMTAILR), offset 0x028 ................................................. 228Register 10: GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C ................................................ 229Register 11: GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 ................................................... 230Register 12: GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 .................................................. 231Register 13: GPTM TimerA Prescale (GPTMTAPR), offset 0x038 ........................................................ 232Register 14: GPTM TimerB Prescale (GPTMTBPR), offset 0x03C ....................................................... 233Register 15: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ........................................... 234Register 16: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ........................................... 235Register 17: GPTM TimerA (GPTMTAR), offset 0x048 ........................................................................ 236Register 18: GPTM TimerB (GPTMTBR), offset 0x04C ....................................................................... 237

Watchdog Timer ........................................................................................................................... 238Register 1: Watchdog Load (WDTLOAD), offset 0x000 ...................................................................... 241Register 2: Watchdog Value (WDTVALUE), offset 0x004 ................................................................... 242Register 3: Watchdog Control (WDTCTL), offset 0x008 ..................................................................... 243Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C .......................................................... 244Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 .................................................. 245Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ............................................. 246Register 7: Watchdog Test (WDTTEST), offset 0x418 ....................................................................... 247Register 8: Watchdog Lock (WDTLOCK), offset 0xC00 ..................................................................... 248Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ................................. 249Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ................................. 250Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 ................................. 251Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................ 252Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ................................. 253Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ................................. 254Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ................................. 255Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ................................. 256Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 .................................... 257Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 .................................... 258Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 .................................... 259Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC .................................. 260

Analog-to-Digital Converter (ADC) ............................................................................................. 261Register 1: ADC Active Sample Sequencer (ADCACTSS), offset 0x000 ............................................. 268Register 2: ADC Raw Interrupt Status (ADCRIS), offset 0x004 ........................................................... 269Register 3: ADC Interrupt Mask (ADCIM), offset 0x008 ..................................................................... 270Register 4: ADC Interrupt Status and Clear (ADCISC), offset 0x00C .................................................. 271Register 5: ADC Overflow Status (ADCOSTAT), offset 0x010 ............................................................ 272Register 6: ADC Event Multiplexer Select (ADCEMUX), offset 0x014 ................................................. 273



Register 7: ADC Underflow Status (ADCUSTAT), offset 0x018 ........................................................... 276Register 8: ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020 ............................................. 277Register 9: ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028 ................................. 278Register 10: ADC Sample Averaging Control (ADCSAC), offset 0x030 ................................................. 279Register 11: ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0), offset 0x040 ............... 280Register 12: ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044 ........................................ 282Register 13: ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048 ................................ 285Register 14: ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068 ................................ 285Register 15: ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088 ................................ 285Register 16: ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset 0x0A8 ............................... 285Register 17: ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset 0x04C ............................. 286Register 18: ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset 0x06C ............................. 286Register 19: ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset 0x08C ............................ 286Register 20: ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset 0x0AC ............................ 286Register 21: ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1), offset 0x060 ............... 287Register 22: ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2), offset 0x080 ............... 287Register 23: ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064 ........................................ 288Register 24: ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084 ........................................ 288Register 25: ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3), offset 0x0A0 ............... 290Register 26: ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4 ........................................ 291Register 27: ADC Test Mode Loopback (ADCTMLB), offset 0x100 ....................................................... 292

Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 294Register 1: UART Data (UARTDR), offset 0x000 ............................................................................... 302Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 304Register 3: UART Flag (UARTFR), offset 0x018 ................................................................................ 306Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020 ............................................. 308Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 309Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 310Register 7: UART Line Control (UARTLCRH), offset 0x02C ............................................................... 311Register 8: UART Control (UARTCTL), offset 0x030 ......................................................................... 313Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 315Register 10: UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 317Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 319Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 320Register 13: UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 321Register 14: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 323Register 15: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 324Register 16: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 325Register 17: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 326Register 18: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 327Register 19: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 328Register 20: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 329Register 21: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 330Register 22: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 331Register 23: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 332Register 24: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 333Register 25: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 334


Table of Contents

Synchronous Serial Interface (SSI) ............................................................................................ 335Register 1: SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 347Register 2: SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 349Register 3: SSI Data (SSIDR), offset 0x008 ...................................................................................... 351Register 4: SSI Status (SSISR), offset 0x00C ................................................................................... 352Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 354Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 355Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 357Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 358Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 359Register 10: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 360Register 11: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 361Register 12: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 362Register 13: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 363Register 14: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 364Register 15: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 365Register 16: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 366Register 17: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 367Register 18: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 368Register 19: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 369Register 20: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 370Register 21: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 371

Inter-Integrated Circuit (I2C) Interface ........................................................................................ 372Register 1: I2C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 386Register 2: I2C Master Control/Status (I2CMCS), offset 0x004 ........................................................... 387Register 3: I2C Master Data (I2CMDR), offset 0x008 ......................................................................... 391Register 4: I2C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... 392Register 5: I2C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... 393Register 6: I2C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. 394Register 7: I2C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ........................................... 395Register 8: I2C Master Interrupt Clear (I2CMICR), offset 0x01C ......................................................... 396Register 9: I2C Master Configuration (I2CMCR), offset 0x020 ............................................................ 397Register 10: I2C Slave Own Address (I2CSOAR), offset 0x000 ............................................................ 399Register 11: I2C Slave Control/Status (I2CSCSR), offset 0x004 ........................................................... 400Register 12: I2C Slave Data (I2CSDR), offset 0x008 ........................................................................... 402Register 13: I2C Slave Interrupt Mask (I2CSIMR), offset 0x00C ........................................................... 403Register 14: I2C Slave Raw Interrupt Status (I2CSRIS), offset 0x010 ................................................... 404Register 15: I2C Slave Masked Interrupt Status (I2CSMIS), offset 0x014 .............................................. 405Register 16: I2C Slave Interrupt Clear (I2CSICR), offset 0x018 ............................................................ 406

Controller Area Network (CAN) Module ..................................................................................... 407Register 1: CAN Control (CANCTL), offset 0x000 ............................................................................. 421Register 2: CAN Status (CANSTS), offset 0x004 ............................................................................... 423Register 3: CAN Error Counter (CANERR), offset 0x008 ................................................................... 426Register 4: CAN Bit Timing (CANBIT), offset 0x00C .......................................................................... 427Register 5: CAN Interrupt (CANINT), offset 0x010 ............................................................................. 429Register 6: CAN Test (CANTST), offset 0x014 .................................................................................. 430Register 7: CAN Baud Rate Prescalar Extension (CANBRPE), offset 0x018 ....................................... 432



Register 8: CAN IF1 Command Request (CANIF1CRQ), offset 0x020 ................................................ 433Register 9: CAN IF2 Command Request (CANIF2CRQ), offset 0x080 ................................................ 433Register 10: CAN IF1 Command Mask (CANIF1CMSK), offset 0x024 .................................................. 434Register 11: CAN IF2 Command Mask (CANIF2CMSK), offset 0x084 .................................................. 434Register 12: CAN IF1 Mask 1 (CANIF1MSK1), offset 0x028 ................................................................ 437Register 13: CAN IF2 Mask 1 (CANIF2MSK1), offset 0x088 ................................................................ 437Register 14: CAN IF1 Mask 2 (CANIF1MSK2), offset 0x02C ................................................................ 438Register 15: CAN IF2 Mask 2 (CANIF2MSK2), offset 0x08C ................................................................ 438Register 16: CAN IF1 Arbitration 1 (CANIF1ARB1), offset 0x030 ......................................................... 439Register 17: CAN IF2 Arbitration 1 (CANIF2ARB1), offset 0x090 ......................................................... 439Register 18: CAN IF1 Arbitration 2 (CANIF1ARB2), offset 0x034 ......................................................... 440Register 19: CAN IF2 Arbitration 2 (CANIF2ARB2), offset 0x094 ......................................................... 440Register 20: CAN IF1 Message Control (CANIF1MCTL), offset 0x038 .................................................. 441Register 21: CAN IF2 Message Control (CANIF2MCTL), offset 0x098 .................................................. 441Register 22: CAN IF1 Data A1 (CANIF1DA1), offset 0x03C ................................................................. 443Register 23: CAN IF1 Data A2 (CANIF1DA2), offset 0x040 ................................................................. 443Register 24: CAN IF1 Data B1 (CANIF1DB1), offset 0x044 ................................................................. 443Register 25: CAN IF1 Data B2 (CANIF1DB2), offset 0x048 ................................................................. 443Register 26: CAN IF2 Data A1 (CANIF2DA1), offset 0x09C ................................................................. 443Register 27: CAN IF2 Data A2 (CANIF2DA2), offset 0x0A0 ................................................................. 443Register 28: CAN IF2 Data B1 (CANIF2DB1), offset 0x0A4 ................................................................. 443Register 29: CAN IF2 Data B2 (CANIF2DB2), offset 0x0A8 ................................................................. 443Register 30: CAN Transmission Request 1 (CANTXRQ1), offset 0x100 ................................................ 444Register 31: CAN Transmission Request 2 (CANTXRQ2), offset 0x104 ................................................ 444Register 32: CAN New Data 1 (CANNWDA1), offset 0x120 ................................................................. 445Register 33: CAN New Data 2 (CANNWDA2), offset 0x124 ................................................................. 445Register 34: CAN Message 1 Interrupt Pending (CANMSG1INT), offset 0x140 ..................................... 446Register 35: CAN Message 2 Interrupt Pending (CANMSG2INT), offset 0x144 ..................................... 446Register 36: CAN Message 1 Valid (CANMSG1VAL), offset 0x160 ....................................................... 447Register 37: CAN Message 2 Valid (CANMSG2VAL), offset 0x164 ....................................................... 447

Analog Comparators ................................................................................................................... 448Register 1: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x00 .................................... 454Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x04 ......................................... 455Register 3: Analog Comparator Interrupt Enable (ACINTEN), offset 0x08 ........................................... 456Register 4: Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x10 ......................... 457Register 5: Analog Comparator Status 0 (ACSTAT0), offset 0x20 ....................................................... 458Register 6: Analog Comparator Status 1 (ACSTAT1), offset 0x40 ....................................................... 458Register 7: Analog Comparator Status 2 (ACSTAT2), offset 0x60 ....................................................... 458Register 8: Analog Comparator Control 0 (ACCTL0), offset 0x24 ....................................................... 459Register 9: Analog Comparator Control 1 (ACCTL1), offset 0x44 ....................................................... 459Register 10: Analog Comparator Control 2 (ACCTL2), offset 0x64 ...................................................... 459

Pulse Width Modulator (PWM) .................................................................................................... 461Register 1: PWM Master Control (PWMCTL), offset 0x000 ................................................................ 469Register 2: PWM Time Base Sync (PWMSYNC), offset 0x004 ........................................................... 470Register 3: PWM Output Enable (PWMENABLE), offset 0x008 .......................................................... 471Register 4: PWM Output Inversion (PWMINVERT), offset 0x00C ....................................................... 472Register 5: PWM Output Fault (PWMFAULT), offset 0x010 ................................................................ 473Register 6: PWM Interrupt Enable (PWMINTEN), offset 0x014 .................................................

LM3S2533Microcontroller - Farnell element14 · 10 General-PurposeTimers.....202 10.1...

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Transcript of LM3S2533Microcontroller - Farnell element14 · 10 General-PurposeTimers.....202 10.1...