LM-03VHDL - Iowa State Universityclass.ece.iastate.edu/cpre381/lectures/LM-03VHDL.pdf · VHDL for...

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CprE 583 – Reconfigurable Computing

Learning Module-03VHDL Basics

Joseph ZambrenoElectrical and Computer Engineering

Iowa State University

www.ece.iastate.edu/~zambrenorcl.ece.iastate.edu

VHDL was written by a bunch of software guys who knew nothing abouthardware. We beat on it until you could do hardware with it. – David Bishop

LM-03.2LM-03.2CprE 583 (VHDL Basics)Zambreno, Fall 2014 © ISUZambreno, Fall 2014 © ISU

Quick Points• MP-1: Platform Introduction

• Resources for the next couple of weeks (in order of usefulness):1. Mealy and Tappero, Free Range

VHDL, 2011.• Available on Blackboard• Chapters 1-5 will get you started• Exercises are basic, but useful!

2. Hauck and DeHon, Chapter 6• Not a guide, but some decent examples

3. These lecture notes• Goal – cover only the important basics!


VHDL

• VHDL is a language for describing digitalhardware used by industry worldwide

–VHDL is an acronym for VHSIC (Very High Speed Integrated Circuit) Hardware Description Language

• Developed in the early ’80s• Four versions in common use: VHDL-87,

VHDL-93, VHDL-2002, VHDL-2008


VHDL v. Verilog

Government Developed

Commercially Developed

Ada based C based

Strongly Type Cast Mildly Type Cast

Difficult to learn Easier to Learn

More Powerful Less Powerful

VHDL Verilog


VHDL for Synthesis

VHDL for Specification

VHDL for Simulation

VHDL for Synthesis


Naming and Labeling

• VHDL is not case sensitiveExample:

Names or labelsdatabus

Databus

DataBus

DATABUS

are all equivalent

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Naming and Labeling (cont.)General rules of thumb (according to VHDL-87)

1. All names should start with an alphabet character (a-z or A-Z)2. Use only alphabet characters (a-z or A-Z) digits (0-9) and

underscore (_)3. Do not use any punctuation or reserved characters within a name

(!, ?, ., &, +, -, etc.)4. Do not use two or more consecutive underscore characters (__)

within a name (e.g., Sel__A is invalid)5. All names and labels in a given entity and architecture must be

unique


Free Format• VHDL is a “free format” language

– No formatting conventions, such as spacing or indentation imposed by VHDL compilers. Space and carriage return treated the same way.

Example:if (a=b) then

orif (a=b) then

orif (a =

b) then

are all equivalent


Comments• Comments in VHDL are indicated with a “double dash”,

i.e., “--”• Comment indicator can be placed anywhere in the

line• Any text that follows in the same line is treated as

a comment• Carriage return terminates a comment• No method for commenting a block extending

over a couple of lines

Examples:-- main sub-circuitData_in <= Data_bus; -- reading data from the input FIFO


Design Entity

Design Entity - most basic building block of a design

One entity can have many different architectures

entity declaration

architecture 1

architecture 2

architecture 3

design entity


Entity Declaration

• Entity Declaration describes the interface of the component, i.e. the input and outputports

ENTITY nand_gate ISPORT(

a : IN STD_LOGIC;b : IN STD_LOGIC;z : OUT STD_LOGIC

);END nand_gate;

Reserved words

Entity name Port names Port typeSemicolon

No Semicolon

Port modes (data flow directions)


Entity Declaration (cont.)

ENTITY entity_name IS

PORT (

port_name : signal_mode signal_type;

port_name : signal_mode signal_type;

………….

port_name : signal_mode signal_type);

END entity_name;

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Architecture

• Describes an implementation of a design entity • Architecture example:

• Simplified syntax:

ARCHITECTURE model OF nand_gate ISBEGIN

z <= a NAND b;END model;

ARCHITECTURE architecture_name OF entity_name IS

[ declarations ]

BEGIN

code

END architecture_name;


Entity Declaration and Architecture

LIBRARY ieee;USE ieee.std_logic_1164.all;


a : IN STD_LOGIC;b : IN STD_LOGIC;z : OUT STD_LOGIC);

END nand_gate;



nand_gate.vhd


Port Modes

Can’t read out within an entity

Entity Port signal

Driver residesinside the entity

z

c

Port signalEntity

Driver residesinside the entity

Signal X can beread inside the entity

x

c

z

Signal can beread insidethe entity

EntityPort signal

Driver may reside both inside and outside of the entity

a

a

Entity

Port signal

Driver residesoutside the entity


Port Modes (cont.)

• The Port Mode of the interface describes the direction in which data travels with respect to the component– In: Data comes in this port and can only be read within

the entity. It can appear only on the right side of a signal or variable assignment

– Out: The value of an output port can only be updated within the entity. It cannot be read. It can only appear on the left side of a signal assignment

– Inout: The value of a bi-directional port can be read and updated within the entity model. It can appear on both sides of a signal assignment

– Buffer: Used for a signal that is an output from an entity. The value of the signal can be used inside the entity, which means that in an assignment statement the signal can appear on the left and right sides of the <= operator


• Write VHDL entity declarations that describe the following black-box diagrams:

• What’s wrong with the following entity declaration?

EX-03.1: Entity Declarations

Qsys2

16

Q2

4

clk

in1

in3

in220led_R

sys1led_G

rst

my_sig

clk

led_B

ENTITY ckt_a ISPORT(

J,K : IN STD_LOGIC;CLK : IN STD_LOGICQ : OUT STD_LOGIC;)

END;





END nand_gate;



Library Declarations

Use all definitions from the package

std_logic_1164

IEEE Library declaration

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Library Declarations (cont.)

LIBRARY library_name;

USE library_name.pkg_name.pkg_parts;


Library Components

LIBRARY

PACKAGE 1 PACKAGE 2

TYPES

CONSTANTS

FUNCTIONS

PROCEDURES

COMPONENTS

TYPES

CONSTANTS

FUNCTIONS

PROCEDURES

COMPONENTS


Common Libraries• IEEE

– Specifies multi-level logic system, including STD_LOGIC, and STD_LOGIC_VECTOR data types

– Needs to be explicitly declared

• STD– Specifies pre-defined data types (BIT, BOOLEAN,

INTEGER, REAL, SIGNED, UNSIGNED, etc.), arithmetic operations, basic type conversion functions, basic text i/o functions, etc.

– Visible by default

• WORK– Current designs after compilation– Visible by default


STD_LOGIC Demystified




END nand_gate;



Hmm?


STD_LOGIC Demystified (cont.)

Value Meaning

‘X’ Forcing (Strong driven) Unknown

‘0’ Forcing (Strong driven) 0

‘1’ Forcing (Strong driven) 1

‘Z’ High Impedance

‘W’ Weak (Weakly driven) Unknown

‘L’ Weak (Weakly driven) 0. Models a pull down.

‘H’ Weak (Weakly driven) 1. Models a pull up.

‘-’ Don't Care


Resolving Logic Levels

X 0 1 Z W L H -

X X X X X X X X X

0 X 0 X 0 0 0 0 X

1 X X 1 1 1 1 1 X

Z X 0 1 Z W L H X

W X 0 1 W W W W X

L X 0 1 L W L W X

H X 0 1 H W W H X

- X X X X X X X X

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Wires and Bundles

• SIGNAL a : STD_LOGIC;

• SIGNAL b : STD_LOGIC_VECTOR(7 DOWNTO 0);

• SIGNAL c : STD_LOGIC_VECTOR(0 to 7);

wire

a

bundle

b

1

8

bundle

c

8


Standard Logic VectorsSIGNAL a: STD_LOGIC;SIGNAL b: STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL c: STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL d: STD_LOGIC_VECTOR(7 DOWNTO 0);SIGNAL e: STD_LOGIC_VECTOR(15 DOWNTO 0);SIGNAL f: STD_LOGIC_VECTOR(8 DOWNTO 0);

a <= ‘1’;b <= ”0000”; -- Binary base assumed by defaultc <= B”0000”; -- Binary base explicitly specifiedd <= ”0110_0111”; -- To increase readabilitye <= X”AF67”; -- Hexadecimal basef <= O”723”; -- Octal base


Vectors and Concatenation

SIGNAL a: STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL b: STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL c, d, e: STD_LOGIC_VECTOR(7 DOWNTO 0);

a <= ”0000”; b <= ”1111”; c <= a & b; -- c = ”00001111”

d <= ‘0’ & ”0001111”; -- d <= ”00001111”

e <= ‘0’ & ‘0’ & ‘0’ & ‘0’ & ‘1’ & ‘1’ &‘1’ & ‘1’; -- e <= ”00001111”


VHDL Design Styles

Components andinterconnects

structural

VHDL Design Styles

dataflow

Concurrent statements

behavioral

• Registers• State machines• Test benches

Sequential statements

Subset most suitable for synthesis


XOR3 Example

ENTITY xor3 IS

PORT(

A : IN STD_LOGIC;

B : IN STD_LOGIC;

C : IN STD_LOGIC;

Result : OUT STD_LOGIC);

end xor3;


Dataflow Descriptions

• Describes how data moves through the system and the various processing steps

• Dataflow uses series of concurrent statements to realize logic– Concurrent statements are evaluated at the same

time– Order of these statements doesn’t matter

• Dataflow is most useful style when series of Boolean equations can represent a logic

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XOR3 Example (cont.)

ARCHITECTURE dataflow OF xor3 ISSIGNAL U1_out: STD_LOGIC;BEGIN

U1_out <=A XOR B;Result <=U1_out XOR C;

END dataflow;

U1_out


Structural Description• Structural design is the simplest to understand

– Closest to schematic capture– Utilizes simple building blocks to compose logic functions

• Components are interconnected in a hierarchical manner• Structural descriptions may connect simple gates or

complex, abstract components• Structural style is useful when expressing a design that

is naturally composed of sub-blocks


XOR3 Example (cont.)ARCHITECTURE structural OF xor3 ISSIGNAL U1_OUT: STD_LOGIC;

COMPONENT xor2 ISPORT (

I1 : IN STD_LOGIC;I2 : IN STD_LOGIC;Y : OUT STD_LOGIC);

END COMPONENT;

BEGINU1: xor2 PORT MAP (I1 => A,

I2 => B,Y => U1_OUT);

U2: xor2 PORT MAP (I1 => U1_OUT,I2 => C,Y => Result);

END structural;

I1I2

Y

XOR2

AB

CRESULT

U1_OUT

XOR3

A

B

C

ResultXOR3


Component and Instantiation

• Named association connectivity (recommended)

COMPONENT xor2 ISPORT(


END COMPONENT;

U1: xor2 PORT MAP (I1 => A,I2 => B,Y => U1_OUT);

COMPONENT xor2 ISPORT(


END COMPONENT;

U1: xor2 PORT MAP (A, B, U1_OUT);

• Positional association connectivity (notrecommended)


Behavioral Description• Accurately models what happens on the inputs

and outputs of the black box • Uses PROCESS statements in VHDL

ARCHITECTURE behavioral OF xor3 ISBEGINxor3_behave: PROCESS (A,B,C)BEGIN

IF ((A XOR B XOR C) = '1') THENResult <= '1';

ELSEResult <= '0';

END IF;END PROCESS xor3_behave;END behavioral;


• For the following function descriptions, write dataflow VHDL models:

1. F(A,B,C,D) = A’CD’ + B’C + BCD’2. F(A,B,C,D) = (A’+B) (B’+C+D’) (A’+D)

EX-03.2: Dataflow VHDL

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Testbenches

TestbenchProcesses

Generating

Stimuli

Design Under Test (DUT)

Observed Outputs


Testbench Definition

• Testbench applies stimuli (drives the inputs) to the Design Under Test (DUT) and (optionally) verifies expected outputs

• The results can be viewed in a waveform window or written to a file

• Since Testbench is written in VHDL, it is not restricted to a single simulation tool (portability)

• The same Testbench can be easily adapted to test different implementations (i.e. different architectures) of the same design


ENTITY tb IS--TB entity has no ports

END tb;

ARCHITECTURE arch_tb OF tb IS--Local signals and constants

COMPONENT TestComp --All DUT component declarationsPORT ( );

END COMPONENT;-----------------------------------------------------BEGIN

testSequence: PROCESS -- Input stimuliEND PROCESS;DUT:TestComp PORT MAP(); -- Instantiations of DUTs

END arch_tb;

Testbench Anatomy


Testbench for XOR3LIBRARY ieee;USE ieee.std_logic_1164.all;

ENTITY xor3_tb ISEND xor3_tb;

ARCHITECTURE xor3_tb_architecture OF xor3_tb ISCOMPONENT xor3PORT(A : IN STD_LOGIC;B : IN STD_LOGIC;C : IN STD_LOGIC;Result : OUT STD_LOGIC );END COMPONENT;

-- Stimulus signals - mapped to the input and inout ports of tested entitySIGNAL test_vector: STD_LOGIC_VECTOR(2 DOWNTO 0);SIGNAL test_result : STD_LOGIC;


Testbench for XOR3 (cont.)

BEGINUUT : xor3PORT MAP (

A => test_vector(0),B => test_vector(1),C => test_vector(2),Result => test_result);

Testing: PROCESSBEGINtest_vector <= "000";WAIT FOR 10 ns;test_vector <= "001";WAIT FOR 10 ns;test_vector <= "010";WAIT FOR 10 ns;…

…test_vector <= "011";WAIT FOR 10 ns;test_vector <= "100";WAIT FOR 10 ns;test_vector <= "101";WAIT FOR 10 ns;test_vector <= "110";WAIT FOR 10 ns;test_vector <= "111";WAIT FOR 10 ns;

END PROCESS;END xor3_tb_architecture;


• A process can be given a unique name using an optional LABEL

• This is followed by the keyword PROCESS

• The keyword BEGIN is used to indicate the start of the process

• All statements within the process are executed SEQUENTIALLY. Hence, order of statements is important

• A process must end with the keywords END PROCESS

Testing: PROCESSBEGIN

test_vector<=“00”;WAIT FOR 10 ns;test_vector<=“01”;WAIT FOR 10 ns;test_vector<=“10”;WAIT FOR 10 ns;test_vector<=“11”;WAIT FOR 10 ns;

END PROCESS;

A process is a sequence of instructions referred to as sequential statements

The keyword PROCESS

What is a Process?

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• The execution of statements continues sequentially till the last statement in the process

• After execution of the last statement, the control is again passed to the beginning of the process

Process Execution


test_vector<=“00”;WAIT FOR 10 ns;test_vector<=“01”;WAIT FOR 10 ns;test_vector<=“10”;WAIT FOR 10 ns;test_vector<=“11”;WAIT FOR 10 ns;

END PROCESS;

Program control is passed to the first statement after BEGIN

Ord

er

of

exe

cutio

n


• The last statement in the PROCESS is a WAIT instead of WAIT FOR 10 ns

• This will cause the PROCESS to suspend indefinitely when the WAIT statement is executed

• This form of WAIT can be used in a process included in a testbench when all possible combinations of inputs have been tested or a non-periodical signal has to be generated

WAIT Statements


test_vector<=“00”;WAIT FOR 10 ns;test_vector<=“01”;WAIT FOR 10 ns;test_vector<=“10”;WAIT FOR 10 ns;test_vector<=“11”;WAIT;

END PROCESS;

Program execution stops here

Ord

er

of

exe

cutio

n


WAIT FOR vs. WAIT

WAIT FOR: waveform will keep repeating itself forever

WAIT: waveform will keep its state after the last wait instruction.

0 1 2 3

…

0 1 2 3 …


Loop Statement

• Loop Statement

• Repeats a Section of VHDL Code• Example: process every element in an array in the

same way

FOR i IN range LOOPstatements

END LOOP;


Loop Statement Example


test_vector<="000";FOR i IN 0 TO 7 LOOP

WAIT FOR 10 ns;test_vector<=test_vector+”001";

END LOOP;END PROCESS;


Loop Statement Example (cont.)


test_ab<="00";test_sel<="00";FOR i IN 0 TO 3 LOOP

FOR j IN 0 TO 3 LOOPWAIT FOR 10 ns;test_ab<=test_ab+"01";

END LOOP;test_sel<=test_sel+"01";

END LOOP;END PROCESS;

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Recap – PROCESS Block

• List of signals to which the process is sensitive

• Whenever there is an event on any of the signals in the sensitivity list, the process fires

• Every time the process fires, it will run in its entirety

• WAIT statements are NOT allowed in a processes with sensitivity list

label: process (sensitivity list)declaration part

beginstatement part

end process;


Processes in VHDL

• Processes describe sequential behavior• Processes in VHDL are very powerful

statements• Allow to define an arbitrary behavior that may

be difficult to represent by a real circuit• Not every process can be synthesized

• Use processes with caution in the code to be synthesized

• Use processes freely in testbenches


Mixed Style Modeling

ProcessPorts

in

in

out

out

inout

Component

Component

Signal

Dataflow Expression

X <= (Y = ‘1’) and (Z = “110”)

Process (clk)if clk’Event andclk=‘1’ thenCount <= Count + 1;end if;end process;


Dataflow VHDL

• All concurrent statements• Major instructions:

– Concurrent signal assignment ()– Conditional concurrent signal assignment (when-

else)– Selected concurrent signal assignment (with-

select-when)– Generate scheme for equations (for-generate)


Dataflow Example – Full Adder

ENTITY fulladd ISPORT ( x : IN STD_LOGIC ;

y : IN STD_LOGIC ; cin : IN STD_LOGIC ;s : OUT STD_LOGIC ; cout : OUT STD_LOGIC ) ;

END fulladd ;

ARCHITECTURE dataflow OF fulladd ISBEGIN

s <= x XOR y XOR cin ;cout <= (x AND y) OR (cin AND x) OR (cin AND y) ;

END dataflow ;


Logical Operators

• AND, OR, NAND, NOR, XOR, NOT, XNOR• Only NOT has order of precedence• Otherwise, no implied precedence• Example: y = ab + cd

– y <= a AND b or c AND d; -- Equivalent to– y <= ((a AND b) OR c) AND d ; -- Equivalent to– y = (ab + c)d

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Arithmetic Operators

• For basic arithmetic operators on std_logictypes, use the IEEE libraries

• Standard addition, subtraction, multiplication

LIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.numeric_std.all;

-- Alternately, use SIGNED typessignal A : UNSIGNED(3 downto 0); signal B : UNSIGNED(3 downto 0);signal C : UNSIGNED(3 downto 0);……C <= A + B;


16-bit AdditionLIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.std_logic_unsigned.all; -- “Older” library for arithmetic using std_logic

ENTITY adder16 ISPORT ( Cin : IN STD_LOGIC ;

X, Y : IN STD_LOGIC_VECTOR(15 DOWNTO 0) ;S : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ;Cout : OUT STD_LOGIC ) ;

END adder16 ;

ARCHITECTURE Dataflow OF adder16 IS SIGNAL Sum : STD_LOGIC_VECTOR(16 DOWNTO 0) ;

BEGINSum <= ('0' & X) + Y + Cin ;S <= Sum(15 DOWNTO 0) ;Cout <= Sum(16) ;

END Dataflow ;


Conditional Signal Assignment

target_signal <= value1 when condition1 elsevalue2 when condition2 else

. . .valueN-1 when conditionN-1 elsevalueN;

When - Else

.…Value N

Value N-1

Condition N-1

Condition 2Condition 1

Value 2Value 1

Target Signal

…0

1

0

1

0

1


2:1 Multiplexer

LIBRARY ieee ;USE ieee.std_logic_1164.all ;

ENTITY mux2to1 ISPORT (w0, w1, s : IN STD_LOGIC ;

f : OUT STD_LOGIC ) ;END mux2to1 ;

ARCHITECTURE dataflow OF mux2to1 ISBEGIN

f <= w0 WHEN s = '0' ELSE w1 ;END dataflow ;


Priority EncoderLIBRARY ieee ;USE ieee.std_logic_1164.all ;

ENTITY priority ISPORT (w : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;

y : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) ;z : OUT STD_LOGIC ) ;

END priority ;

ARCHITECTURE dataflow OF priority ISBEGIN

y <= "11" WHEN w(3) = '1' ELSE "10" WHEN w(2) = '1' ELSE"01" WHEN w(1) = '1' ELSE"00" ;

z <= '0' WHEN w = "0000" ELSE '1' ;END dataflow ;


Selected Signal Assignment

choices_1

choices_2

choices_N

expression1

expression2

expressionN

target_signal

with choice_expression selecttarget_signal <= expression1 when choices_1,

expression2 when choices_2,. . .

expressionN when choices_N;

With –Select-When

choice expression

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4:1 Multiplexer


ENTITY mux4to1 ISPORT ( w0, w1, w2, w3 : IN STD_LOGIC ;

s : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;f : OUT STD_LOGIC ) ;

END mux4to1 ;

ARCHITECTURE dataflow OF mux4to1 ISBEGIN

WITH s SELECTf <= w0 WHEN "00",

w1 WHEN "01",w2 WHEN "10",w3 WHEN OTHERS ;

END dataflow ;


• Using dataflow VHDL, create a simple ALU that implements the following four functions:– F=A+B (when OP==“00”)– F=A-B (when OP==“01”)– F=AB (when OP==“10”)– F=A|B (when OP==“11”)

EX-03.3: Simple ALU Implementation

myALUF

A

OP

B

32

32

2

32


Generate Statements

• A way to simplify a pattern of concurrent statements

• Can’t do regular FOR…LOOP in dataflow

For - Generate

label: FOR identifier IN range GENERATEBEGIN{Concurrent Statements}

END GENERATE;


Parity Examplexor_out(1)

xor_out(2)xor_out(3) xor_out(4)

xor_out(5) xor_out(6)xor_out(7)

xor_out(0)

ARCHITECTURE parity_dataflow OF parity ISSIGNAL xor_out: STD_LOGIC_VECTOR (7 DOWNTO 0);BEGIN

xor_out(0) <= parity_in(0);G2: FOR i IN 0 TO 6 GENERATE

xor_out(i+1) <= xor_out(i) XOR parity_in(i+1);end generate G2; parity_out <= xor_out(7);

END parity_dataflow;


w 0

w 3

y 0

y 1

z

w 1

w 2

w 0

En

y 0

w 1

y 1

y 2

y 3

s(0)

0

1

s(1)

0

1

r(0)

r(1)

r(2)

r(3)

r(4)

r(5)

p(0)

p(1)

p(2)

p(3)

q(0)

q(1)

ena

z(0)

z(1)

z(2)

z(3)

dec2to4

priority

Structural Mapping Example


Structural Mapping Example (cont.)


ENTITY priority_resolver ISPORT (r : IN STD_LOGIC_VECTOR(5 DOWNTO 0) ;

s : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;z : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ;

END priority_resolver;

ARCHITECTURE structural OF priority_resolver IS

SIGNAL p : STD_LOGIC_VECTOR (3 DOWNTO 0) ;SIGNAL q : STD_LOGIC_VECTOR (1 DOWNTO 0) ;SIGNAL ena : STD_LOGIC ;

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COMPONENT mux2to1

PORT (w0, w1, s : IN STD_LOGIC ;

f : OUT STD_LOGIC ) ;

END COMPONENT ;

COMPONENT priority

PORT (w : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;

y : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) ;

z : OUT STD_LOGIC ) ;

END COMPONENT ;

COMPONENT dec2to4

PORT (w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;

En : IN STD_LOGIC ;

y : OUT STD_LOGIC_VECTOR(0 TO 3) ) ;

END COMPONENT ;

Structural Mapping Example (cont.)


Structural Mapping Example (cont.)BEGIN

u1: mux2to1 PORT MAP ( w0 => r(0) ,w1 => r(1),s => s(0),f => p(0));

p(1) <= r(2);p(1) <= r(3);u2: mux2to1 PORT MAP ( w0 => r(4) ,

w1 => r(5),s => s(1),f => p(3));

u3: priority PORT MAP ( w => p,y => q,z => ena);

u4: dec2to4 PORT MAP ( w => q,En => ena,y => z);

END structural;


Behavioral Latch

LIBRARY ieee ; USE ieee.std_logic_1164.all ;

ENTITY latch IS PORT ( D, Clock : IN STD_LOGIC ;

Q : OUT STD_LOGIC) ; END latch ;

ARCHITECTURE Behavior OF latch IS BEGIN

PROCESS ( D, Clock ) BEGIN

IF Clock = '1' THENQ <= D ;

END IF ; END PROCESS ;

END Behavior;

D Q

Clock

Clock D

0 1 1

–0 1

0 1

Truth table

Q(t+1)

Q(t)


Behavioral Flip Flop

LIBRARY ieee ; USE ieee.std_logic_1164.all ;

ENTITY flipflop IS PORT ( D, Clock : IN STD_LOGIC ;

Q : OUT STD_LOGIC) ; END flipflop ;

ARCHITECTURE Behavior_1 OF flipflop IS BEGIN

PROCESS ( Clock ) BEGIN

IF Clock'EVENT AND Clock = '1' THEN Q <= D ;

END IF ; END PROCESS ;

END Behavior_1 ;

D Q

Clock

Clk D

0 1

0 1

Truth table

Q(t+1)

Q(t)0 –Q(t)1 –


• Provide a VHDL behavioral model of the D flip-flop shown below. The S and R inputs are an active low asynchronous preset and clear. Assume the S input takes precedence over the R input in the case where both are asserted simultaneously

EX-03.4: Basic Memory Elements

CLK

D

S

R

Q

nQ


N-bit Register with Reset

ENTITY regn ISGENERIC ( N : INTEGER := 16 ) ;PORT ( D : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;

Resetn, Clock : IN STD_LOGIC ;Q : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;

END regn ;

ARCHITECTURE Behavior OF regn ISBEGIN

PROCESS ( Resetn, Clock )BEGIN

IF Resetn = '0' THENQ <= (OTHERS => '0') ;

ELSIF Clock'EVENT AND Clock = '1' THENQ <= D ;

END IF ;END PROCESS ;

END Behavior ;

Resetn

Clock

regn

N N

D Q

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4-bit Up-Counter with Reset

LIBRARY ieee ;USE ieee.std_logic_1164.all ;USE ieee.std_logic_unsigned.all ;

ENTITY upcount ISPORT ( Clock, Resetn, Enable : IN STD_LOGIC ;

Q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)) ;END upcount ;

Q

Enable

Clockupcount

4

Resetn


4-bit Up-Counter with Reset (cont.)

ARCHITECTURE Behavior OF upcount ISSIGNAL Count : STD_LOGIC_VECTOR (3 DOWNTO 0) ;

BEGINPROCESS ( Clock, Resetn )BEGIN

IF Resetn = '0' THENCount <= "0000" ;

ELSIF (Clock'EVENT AND Clock = '1') THENIF Enable = '1' THEN

Count <= Count + 1 ;END IF ;

END IF ;END PROCESS ;Q <= Count ;

END Behavior ;

Q

Enable

Clockupcount

4

Resetn


Shift Register With Parallel Load

D(3)

D Q

Clock

Enable

SinD(2)

D Q

D(1)

D Q

D(0)

D Q

Q(0)Q(1)Q(2)Q(3)

Load


Shift Register With Load (cont.)


ENTITY shift4 ISPORT ( D : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;

Enable : IN STD_LOGIC ;Load : IN STD_LOGIC ;Sin : IN STD_LOGIC ;Clock : IN STD_LOGIC ;Q : BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0) ) ;

END shift4 ;

Q

Enable

Clockshift4

4

D

Load

Sin

4


Shift Register with Load (cont.)

ARCHITECTURE Behavior_1 OF shift4 ISBEGIN

PROCESS (Clock)BEGIN

IF Clock'EVENT AND Clock = '1' THENIF Load = '1' THEN

Q <= D ;ELSIF Enable = ‘1’ THEN

Q(0) <= Q(1) ;Q(1) <= Q(2); Q(2) <= Q(3) ; Q(3) <= Sin;

END IF ;END IF ;

END PROCESS ;END Behavior_1 ;

Q

Enable

Clockshift4

4

D

Load

Sin

4


• These slides contain material developed and copyright by:– Phillip Jones (ISU)– Russell Tessier (UMass)– Kris Gaj (GMU)– John Wawrzynek (UC-Berkeley)– Seth Goldstein (CMU)– Scott Hauck (UW)

Acknowledgments

LM-03VHDL - Iowa State Universityclass.ece.iastate.edu/cpre381/lectures/LM-03VHDL.pdf · VHDL for...

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