Lizard - Cortex-A8 CPU Module - Hardware Manual · 2019-02-23 · systems, automation and point of...

DAVE

www.dave.eu

CREATION: Sep 2009

LAST REVISION: Jul 2013

VERSION: 1.0.7

Hardware Manual

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Lizard Hardware Manual

Trademarks

Ethernet® is a registered trademark of XEROX Corporation

All other trademarks are the property of their respective owners

Copyright

All rights reserved. Specifications may change any time without notification.

Disclaimer

DAVE does not assume any responsibility about availability, supplying and support about all the products

mentioned in this manual that are not strictly part of the Aria module.

Life Support Applications

Lizard CPU Modules are not designed for use in life support appliances, devices, or systems where

malfunction of these products can reasonably be expected to result in personal injury. DAVE Srl

customers who are using or selling these products for use in such applications do so at their own risk and

agree to fully indemnify DAVE Srl for any damage resulting from such improper use or sale.

Company Address

DAVE S.r.L.

Via Talponedo 29/A

33080 Porcia (PN) – Italy

Phone: +39 0434 921215

e-mail: [email protected]

URL: www.dave.eu

Technical Support

e-mail: [email protected]

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mailto:[email protected]

http://www.dave-tech.it/


History

Version Date Notes

0.9.0 October 2009 First draft

0.9.9 March 2009 Released with Lizard Embedded Linux Kit 1.0.0

1.0.0 July 2010 Revision for Lizard Embedded Linux Kit 1.1.0 release

1.0.1 Nov 2010 Fixed J2.90 ball signal

1.0.2 Apr 2011 Minor fixesAdded RTC peripheral description

1.0.3 May 2011 Updated chapter 5 (Power Supply)

1.0.4 June 2011 Fixes on title page

1.0.5 January 2012 Added DLxxxxxx1 part numberUpdated chapters 3, 5, 6, 9 with DLxxxxxx1 information

1.0.6 Mar 2012 Removed DSI informationFixed product code table (Section 9)

1.0.7 July 2013 Fixed USB host ports description

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Contents

1 Introduction......................................................................................................................................... 9

1.1 Block Diagram...............................................................................................................................................10

2 Specifications ................................................................................................................................... 11

3 Module design................................................................................................................................... 12

3.1 System architecture.......................................................................................................................................123.1.1 Basic core....................................................................................................................................................................12

3.1.1.1 NOR flash.................................................................................................................................................................12

3.1.1.2 NAND flash...............................................................................................................................................................12

3.1.1.3 DDR2 memory bank.................................................................................................................................................13

3.1.2 Additional peripherals and interfaces.............................................................................................................................13

3.1.2.1 Serial EEPROM........................................................................................................................................................13

3.1.2.2 Touch screen controller.............................................................................................................................................13

3.1.2.3 CAN interface...........................................................................................................................................................13

3.1.2.4 USB ports.................................................................................................................................................................14

3.1.2.5 USB OTG port..........................................................................................................................................................14

3.1.2.6 SD/MMC ports..........................................................................................................................................................14

3.1.2.7 Parallel and serial RGB digital video bus....................................................................................................................14

3.1.2.8 TVOUT interfaces.....................................................................................................................................................14

3.1.2.9 VPFE interface..........................................................................................................................................................14

3.1.2.10 CPU JTAG..............................................................................................................................................................14

3.1.2.11 UARTs....................................................................................................................................................................15

3.1.2.12 CPLD/Keypad controller..........................................................................................................................................15

3.1.2.13 CPLD JTAG............................................................................................................................................................16

3.1.2.14 I/O Expander...........................................................................................................................................................16

3.1.2.15 SPI.........................................................................................................................................................................17

3.1.2.16 I²S..........................................................................................................................................................................17

3.1.2.17 Ethernet PHY..........................................................................................................................................................17

3.1.2.18 Silicon Serial Number..............................................................................................................................................18

3.1.2.19 RTC........................................................................................................................................................................18

3.1.2.20 GPIOs....................................................................................................................................................................18

3.2 GPMC bus interfacing....................................................................................................................................193.2.1 Interfacing non-multiplexed devices requiring up to 10 address lines...............................................................................19

3.2.2 Interfacing multiplexed devices......................................................................................................................................19

3.2.3 Interfacing non-multiplexed devices requiring more than 10 address lines.......................................................................20

3.3 Boot options................................................................................................................................................... 20

3.4 Clock scheme................................................................................................................................................21

4 Board layout and Physical..................................................................................................................22

5 Power Supply.................................................................................................................................... 24

5.1 PSU section................................................................................................................................................... 24

5

5.2 Power consumption.......................................................................................................................................24

5.3 Power on/off requirements..............................................................................................................................255.3.1 DLxxxxxx0 part number................................................................................................................................................25

5.3.2 DLxxxxxx1 part number................................................................................................................................................26

5.3.3 DLxxxxxx0 and DLxxxxxx1 differences..........................................................................................................................26

6 Connectors pinout.............................................................................................................................. 27

6.1 How to read this section.................................................................................................................................27

6.2 Pins descriptions............................................................................................................................................286.2.1 Carrier board mating connector J1.................................................................................................................................28

6.2.2 Carrier board mating connector J2.................................................................................................................................33

7 Resource allocation........................................................................................................................... 37

7.1 Resource allocation........................................................................................................................................377.1.1 Simplified memory map................................................................................................................................................37

7.1.2 IRQs............................................................................................................................................................................37

8 Host board design guidelines..............................................................................................................38

9 Naming, order codes and standard releases.......................................................................................39

10 Agency approvals............................................................................................................................ 40

11 Support........................................................................................................................................... 40

FiguresFig. 1: CPLD susbsystem simplified clock diagram.............................................................................................16Fig. 2: Example of address/data non-multiplexed device interfacing.....................................................................19Fig. 3: Example of address/data non-multiplexed device interfacing.....................................................................20Fig. 4: Example about how to change bootstrap strategy....................................................................................21Fig. 5: Board layout - top view........................................................................................................................... 22Fig. 6: Lizard Board.......................................................................................................................................... 23Fig. 7: Board layout - bottom view......................................................................................................................23Fig. 8: Power on/off cycles for DLxxxxxx0 part numbers.....................................................................................25Fig. 9: Power up sequence for DLxxxxxx1.........................................................................................................26

Index of TablesTab. 1: NOR flash specifications........................................................................................................................12Tab. 2: NAND flash specifications...................................................................................................................... 12Tab. 3: DDR2 SDRAM specifications................................................................................................................. 13Tab. 4: EEPROM specifications......................................................................................................................... 13Tab. 5: Touch screen controller specifications....................................................................................................13Tab. 6: CAN interface specifications.................................................................................................................. 14Tab. 7: USB host ports specifications................................................................................................................. 14Tab. 8: UART1 allocation.................................................................................................................................. 15

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Tab. 9: UART2 allocation.................................................................................................................................. 15Tab. 10: UART3 allocation................................................................................................................................ 15Tab. 11: Keypad controller configuration............................................................................................................15Tab. 12: Keypad controller configuration............................................................................................................16Tab. 13: I/O expander processor connection......................................................................................................16Tab. 14: I/O expander available lines................................................................................................................. 17Tab. 15: Ethernet PHY specifications.................................................................................................................17Tab. 16: Ethernet PHY specifications.................................................................................................................18Tab. 17: RTC specifications.............................................................................................................................. 18Tab. 18: Default bootstrap pins configuration......................................................................................................21Tab. 19: clock sources configuration..................................................................................................................21Tab. 20: Power on/off requirements of DLxxxxxx0 part numbers.........................................................................25Tab. 21: Electrical differences between DLxxxxxx0 and DLxxxxxx1.....................................................................26

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8

Technical Data

CPU Texas Instruments AM3505/AM3517ARMv7 architectureCortex A8 @ 500 MHz

Multimedia NEON Media Technology (Advanced SIMD coprocessor)PowerVR SGX530 Graphics Accelerator (up to 10MPoly/s)Support for OpenGL ES 1.1/2.0, OpenVG 1.1, OpenGL 2.0/3.0

Supervisor On board power supply supervision and power sequencerWatchdog

Memory Cache 16 Kbyte instruction, 16 Kbyte data, 256 Kbyte L2SDRAM 64, 128, 256 MB DDR2NOR 8, 16, 32, 128 MBNAND All sizes, on requestSRAM 64 KbyteEEPROM YesInterfacesLAN Fast Ethernet 10/100 MbpsUART 3x UART portsUSB 2x Full Speed Host ports, 1 x OTG portCAN 1 port (2.0B protocol)External Bus GPMC 16-bit busDebug JTAG IEEE 1149.1 Test Access PortPC Card 2x SD/MMC cardAudio I²SOther 2x I²C channels

1x 1-Wire1x SPI channelGPIOs available

VideoResolution Up to 2048x2048 @ 24bpp, 74.25 MHz pixel clockType TFTTouch Screen YesTV out YesInput VPFE 8-bit video port inMechanicalConnectors 2x 140 pins 0.6mm pitchPhysical 68.5 mm x 50.9 mmTemperature Commercial (0°C / +70°C) Temperature Range

Industrial (-40°C / +85°C) Temperature Range

PSUInput 3.3V, voltage regulation on boardConsumption TBD

SoftwareBootloader U-BootMultitasking OS Linux 2.6.xx

Windows CE 6.xAndroid 2.x

1 Introduction

is a General Purpose CPU module powered by the AM3517/AM3505 application processor, the high performance ARM Cortex-A8 microprocessor from Texas Instruments optimized for system integration. These processors belong to the “Sitara” family.

is the cutting edge solution for a high range of applications where extended connectivity, sophisticated displays and rich user-interfaces are required, including industrial, electronics, smart home controllers, security systems, automation and point of service, based both on Linux and Windows CE.

offers high flexibility, great performances, low power consumption and a rich interfaces set, with full compliance to industrial specifications, including working in the extended temperature range (-40/+85 °C).

is designed to be easily included in customer's embedded systems, due to the small form factor and the inexpensive stacking connectors. Moreover, Lizard has been designed to be back-compatible with DAVE's Zefeer ARM9 CPU module, so that, except for some interfaces, two CPU module families can be plugged on the same host board.

All interface signals are routed through two 140 pin 0.6mm pitch stacking connectors. Users should complete hardware interfaces and connectors when they want to use them through the host board.

A full overview of the board is given, both from mechanical and electrical point of view. Nevertheless, for detailed information, user should refer to components manufacturer’s data sheet ([1]).

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1.1 Block Diagram

10

DDR232-256MB

TFT

NANDFlash

TOUCH

UART 1 (8-wire)

ETH 10/100

I2C-2

VPFE (Camera In)

TS CTRL

ADC

EEPROM

I/OExpander RTC

PSU

I2C-1

TV OUT

8 X 8 KEYPAD KEYPADCONTROLLER

LATCH

PHY

2 x MMC

PHYUSB 2

UART 2 (4-wire)

UART 3 (4-wire)

GPIO

1 x SPI (MCSPI1)

CAN

JTAG

USB OTG

PHYUSB 1

1-WIRE

ADDR/DATA/CTRL Muxed

ADDR/DATA/CTRL DeMuxed

I2C-3

I2S (MCBSP2)

14

0 x 2

0.6

mm

pitch

TI AM3505TI AM3517

Cortex A-8

NORFlash

32 bits

8 bits

14

0 x 2

0.6

mm

pitch

MCBSP3/MCBSP4

2 Specifications

CPU Texas Instruments AM3517Texas Instruments AM3505

Clock Speed 500 MHzRAM 64, 128 and 256 MBFlash NOR 8, 16, 32 and 128 MBFlash NAND Up to 1 GB

Supervision On-board power supply supervision and power sequencerWatchdog

Power supply +3.3V

Form Factor 68.5 mm x 50.9 mm

Connectors 2 x Hirose FX8C-140S-SV (J1, J2)

Mating connectors Hirose FX8C-140P-SV (5 mm board-to-board height)Hirose FX8C-140P-SV1 (6 mm board-to-board height)Hirose FX8C-140P-SV2 (7 mm board-to-board height)Hirose FX8C-140P-SV4 (9 mm board-to-board height)Hirose FX8C-140P-SV6 (11 mm board-to-board height)

Agency Approvals EN 55022 (t.b.o.)EN 61000-4-3 (t.b.o.)EN 61000-4-4 (t.b.o.)EN 61000-4-6 (t.b.o.)

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3 Module design

3.1 System architectureThis section describes the basic system architecture underling Lizard processor module.

3.1.1 Basic coreAs shown in section 1.1 on page 10, the heart of Lizard module is composed by the following components:

• Texas Instruments AM3505/AM3517 CPU• Power Supply Unit• DDR2 Memory bank• NOR and NAND flash banks• 2 x 140 pin connectors

3.1.1.1 NOR flash

NOR flash is a Spansion Mirrorbit device. The following table lists its main specifications. By default this device is connected to GPMC_NCS0 chip select and acts as boot memory (Fast XIP booting wait monitoring OFF). Optionally, it can be connected to GPMC_NCS7.

3.1.1.2 NAND flash

This memory is a 8-bit wide NAND flash. By default it is connected to GPMC_NCS7 chip select. Optionally it can be connected to GPMC_NCS0 to act as boot memory.

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CPU connection GPMC bus

Size min 4 MByte

Size max 128 MByte

Width 16 bit

Tab. 1: NOR flash specifications


Page size 512 byte, 2 kbyte or 4 kbyte

Size min 32 MByte

Size max 2 GByte

Width 8 bit

Tab. 2: NAND flash specifications

3.1.1.3 DDR2 memory bank

DDR2 SDRAM memory bank is composed by 2 16-bit width chips resulting in 32-bit combined width.

3.1.2 Additional peripherals and interfacesSurrounding the core described in previous section, several peripherals and components are available. They are described in the following sections.

3.1.2.1 Serial EEPROM

One EEPROM is available to provide additional non-volatile storage area for user-specific usage.

3.1.2.2 Touch screen controller

For modules with DLxxxxxx0 part number, the on-board touch screen controller is a TI TSC2007 device; for modules with DLxxxxxx1 part number, the touch screen controller is a TI TSC2003 device. TSC2007 and TSC2003 are fully software compatible. The touch screen controller is connected to the I2C bus.

3.1.2.3 CAN interface

High End CAN Controller (HECC) integrated in “Sitara” processor is connected to on-board PHY. CANH and CANL lines are routed to connector J1. On-board PHY can be optionally unpopulated in order to route to J1

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CPU connection SDRAM bus

Size min 64 MB

Size max 256 MB

Width 32 bit

Tab. 3: DDR2 SDRAM specifications

Device 24LC32

CPU connection I2C2 bus (default address 1010011b; least two address bits can be modified via pins EEPROM_A1 and EEPROM_A2)

Size 4 kByte

Tab. 4: EEPROM specifications

Device Texas Instruments TSC2003 (for DLxxxxxx1) and TSC2007 (for DLxxxxxx0)

CPU connection • I2C2 bus (address 1001000b)• IRQ line is connected to ETK_D8

Tab. 5: Touch screen controller specifications

processor signals HECC1_TXD (J1.96 becomes CAN TX) and HECC1_RXD (J1.98 becomes CAN RX). This allows to implement on carrier board hosting Lizard module custom CAN interface (i.e. opto-isolated).

3.1.2.4 USB ports

Lizard provides two USB Full Speed Host ports with on-board PHY.

3.1.2.5 USB OTG port

Lizard provides a standard USB OTG 2.0 port. This interface refers to high-speed USB OTG controller integrated in processor that includes OTG PHY too.

3.1.2.6 SD/MMC ports

Two standard MMC/SD/SDIO interfaces are available on Lizard module. They refer to MMC/SD/SDIO1 and MMC/SD/SDIO2 host controllers integrated in processor.

3.1.2.7 Parallel and serial RGB digital video bus

This bus originates from the LCD controller integrated in the AM3505/AM3517 CPU. It supports up to 24-bit pixel depth.

3.1.2.8 TVOUT interfaces

Lizard provides standard Composite and S-Video TV out interfaces. They refer to TV out encoder integrated in “Sitara” processor.

3.1.2.9 VPFE interface

Lizard offers Video Processing FrontEnd capabilities through a 8-bit Video port input. Raw data input can be connected to the CCDC signals routed to the J1 connector.

3.1.2.10 CPU JTAG

This port is available on connector J2. It routes CPU JTAG signals.

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Device Texas Instruments SN65HVD232

CPU connection HECC controller

Tab. 6: CAN interface specifications

Device ST-Ericsson ISP1105W-G

CPU connection USB host subsystem port 1 and port 2

Tab. 7: USB host ports specifications

3.1.2.11 UARTs

Three UART ports are routed to Lizard connectors.

Since AM3517/3505 processor provides 4-wire native UARTs and for the sake of Zefeer compatibility, some additional pins – configured as GPIOs – have to be used to emulate DSR, DTR, CD and RI signals. They are detailed in the following list:

• ETK_D3 may act as UART1_DTR• ETK_CLK may act as UART1_DSR• MCBSP1_CLKR may act as RI• any unused pin may act as CD1.

3.1.2.12 CPLD/Keypad controller

Lizard provides a 8x8 keypad interface that is implemented in a CPLD. This device is connected to the processor's GPMC bus as follows:

• address: GPMC_A[4:1]• data: GPMC_D[7:0]• chip select: GPMC_NCS6• interrupt request: ETK_D10.

1No specific pins are allocated for this functionality on Zefeer module.

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Device UART1 (8-wire)

CPU connection UART1 port plus I/O pins

Tab. 8: UART1 allocation


CPU connection UART2 port



CPU connection UART3 port


Device XC2C64A-7


Tab. 11: Keypad controller configuration

Even if default implementation is keypad controller, CPLD can be used to implement user specific functions (for example additional GPIOs). To have more information about this option please contact technical support at [email protected].

3.1.2.13 CPLD JTAG

CPLD JTAG port is accessible by processor in order to implement software-controlled programming. The signals are connected as shown in following table and depicted in Fig. 1 on page 16. Signals are connected through buffers that are by default tri-stated. To enable them, I/O_EXP15 line must set to low logic level.

3.1.2.14 I/O Expander

Lizard provides additional GPIOs through a PCA9555 I/O Expander. This device is connected to the I2C2 bus. Interrupt line is connected to ETK_D5 processor pad.

16

Device PCA9555

CPU connection I2C2 bus (default 7-bit address: 0100111)

Tab. 13: I/O expander processor connection

JTAG signal CPU pad

TDO MCSPI2_CLK

TDI MCSPI2_SIMO

TMS I/O_EXP14

TCK ETK_D4

JTAG enable I/O_EXP15

Tab. 12: Keypad controller configuration

Fig. 1: CPLD susbsystem simplified clock diagram

AM3517/05 CPLDGPMC bus

TRI-STATE BUFFERS

GPIOs JTAG

J1

CONNECTOR


PCA9555 provides 16 I/O lines. Twelve of them are available on main connectors as detailed in the following table. These lines are internally pulled-up to 3.3V through a 10kOhm resistor. Also please note that IO1_15 line is used internally to enable CPLD JTAG connection. For more details please refer to section 3.1.2.12.

3.1.2.15 SPI

An SPI channel is available on Lizard (MCSPI1 port). This port provides three chip selects (MCSPI1_CS0, MCSPI1_CS1 and MCSPI1_CS2).

3.1.2.16 I²S

For Zefeer pinout compatibility, an I²S channel is available on connector J2. I²S channel is implemented by MCBSP2 port.

3.1.2.17 Ethernet PHY

Ethernet PHY provides interface signals required to implement the 10/100 Ethernet port. It is connected to processor EMAC controller through RMII interface.

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Device SMSC LAN8700IC-AEZG

CPU connection EMAC (RMII); address is 0x11

Tab. 15: Ethernet PHY specifications

PC9555 I/O line Connector pin

IO0_0 J1.91

IO0_1 J1.93

IO0_2 J1.99

IO0_3 J1.101

IO0_4 J1.103

IO0_5 J1.105

IO0_6 J1.92

IO0_7 J1.94

IO1_8 J1.106

IO1_9 J1.108

IO1_10 J1.110

IO1_15 J1.14

Tab. 14: I/O expander available lines

3.1.2.18 Silicon Serial Number

A silicon Serial Number Pin is available on Lizard. It is connected to the 1-Wire bus.

3.1.2.19 RTC

Lizard provides an on-board DS1374 real time clock connected to the I2C bus. Interrupt line is connected to ETK_D6 processor pad.

3.1.2.20 GPIOs

Most of the AM3517 pins can be used as GPIOs. The complete list of the GPIOs is reported on Section 2.3 of the microprocessor datasheet ([1]). A signal can be used as GPIO when it is configured to work on mode 4. The signal multiplexer can be configured both on u-boot and the operating system. For more information on how to use GPIOs, please refer to [2].

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Device Dallas/Maxim DS2401+

CPU connection 1-Wire Bus (see table 6.2.1, pin J1.37)

Tab. 16: Ethernet PHY specifications

Device DS1374

CPU connection I2C2 bus (default address 1101000b)

Tab. 17: RTC specifications

3.2 GPMC bus interfacingGenerally speaking, “Sitara” processors allow to interface these kinds of address/data devices:

• non-multiplexed (limited to 10 address lines)• multiplexed (up to 26 address lines).

Lizard module is conceived in order to seamlessly interface, besides these types, non-multiplexed devices that require more than 10 address lines too. This is possible thanks to the fact that it is equipped with on-board latching/demultiplexing circuitry. The following sections deals with these different cases in more detail.

3.2.1 Interfacing non-multiplexed devices requiring up to 10 address lines

This first type is supported seamlessly by GPMC bus but it is limited to 10 address lines.

Fig. 2 shows a real-world example referred to non-multiplexed device (SMSC LAN9221 ethernet controller). In this case 8 out of 10 available address lines are actually used.

3.2.2 Interfacing multiplexed devicesTBD

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Fig. 2: Example of address/data non-multiplexed device interfacing

3.2.3 Interfacing non-multiplexed devices requiring more than 10 address lines

Fig. 3 shows a real-world example referred to non-multiplexed device requiring more than 10 address lines (Spansion S29GL01GP13FFIV10 NOR flash memory). In this case all of 26 available address lines are used on order to address all the device (128 MB).

3.3 Boot optionsThanks to the versatility of internal BootROM, “Sitara” processors provide a rich set of boot options and different configurations. These are described in detail on chapter “Applications Processor Initialization” of AM35x Technical Reference Manual. Reading of this is strongly recommended in order to understand processor bootstrap strategy.Generally speaking, two on-board mutually exclusive options are available about boot memory (see also sections 3.1.1.1 and 3.1.1.2 on page 12):

• NAND flash• NOR flash (default)

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Fig. 3: Example of address/data non-multiplexed device interfacing

The default boot sequence is:1. NOR flash (Fast XIP booting wait monitoring OFF)2. USB3. UART3

This corresponds to the bootstrap pins configuration shown in Tab. 18.

Bootstrap pins are routed to main connectors in order to allow to change bootstrap strategy in user's application. The following reference schematic shows a simple resistor network that can be implemented on carrier board hosting Lizard module. For each SYS_BOOT pin it is possible to populate upper or lower side resistor in order to change default value that is set on module itself.

3.4 Clock schemeThe following table lists how clock sources allocation.

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Clock frequency Clocked device(s)

26.0 MHz CPU

50.0 MHz EMAC end ethernet PHY

32.768 kHz on-board RTC

Tab. 19: clock sources configuration

SYS_BOOT pin Bootstrap value

5 1 (peripheral booting)

4 1

3 1

2 1

1 1

0 1

Tab. 18: Default bootstrap pins configuration

Fig. 4: Example about how to change bootstrap strategy

4 Board layout and Physical

Lizard has been designed to fit on a 68.5 x 50.9 mm2 area.

The following figures show Lizard mechanical specifications.

22

Fig. 5: Board layout - top view

23

Fig. 6: Lizard Board

Fig. 7: Board layout - bottom view

5 Power Supply

5.1 PSU sectionPowering is usually a delicate operation. In Lizard modules this operation has been embedded in the module

and therefore power sequencing is self-contained and simplified. Nevertheless, power must be provided from carrier board, and therefore users should be aware of the ranges power supply can assume as well as all other parameters. Apart from backup supply voltage for on-board RTC, one power voltage is required (VIN). Two power schemes may be adopted:

1. VIN = 3.3V (Zefeer compatibility)2. VIN in the range 3.6V-6V.

Scheme #1 is supported by default. In case scheme #2 is required, please contact technical support for more details.

5.2 Power consumptionPower consumption may vary largely depending several factors such as operating system, user application

software etc. For this reason it is actually impossible – and probably useless – to identify an actual worst case. Rather a consumption data is provided referring to an actual case that is very close to the majority of actual applications.

The consumption measurement refers to the following conditions:• VIN = 3.3V• Operating system: linux 2.6.32• Root file system: Angstrom 2011.03, mounted via NFS• NAND flash erase in progress• LCD video output: 320x240 @ 60 Hz

Under these conditions, a power consumption of 1.5W has been measured.

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5.3 Power on/off requirements

5.3.1 DLxxxxxx0 part numberTable 20 lists the requirements of power on/off cycles – also depicted in Fig. 8 – that apply to Lizard

DLxxxxxx0 part numbers.

25

Fig. 8: Power on/off cycles for DLxxxxxx0 part numbers

Parameter Min Max Unit

Commercial temperature range (0/+70°C)

Industrial temperature range (-40/+85°C)

Off ramp 2 2 - kV/s

tOFF 0.3 1.2 - s

On ramp 12 12 - kV/s

VOFF - - 0.3 V

Tab. 20: Power on/off requirements of DLxxxxxx0 part numbers

Vin = 3.3V

V

t

toff

Voff

OFF RAMP ON RAMP

5.3.2 DLxxxxxx1 part numberIn order to simplify implementation of host board power supply unit, Lizard DLxxxxxx1 part number family has

been made available. DLxxxxxx1 modules have just one requirement to comply with, and it is related to the touch controller. The following diagram shows the power up sequence requirements that must be respected in order to make sure that the TSC2003 is reset to a default working state after every power up. During the power up process, the I2C bus must be in an idle state, that is the SCL and SDA pins must be high before the power supply pin (+Vcc) ramps up to 0.9 V). The Vhigh value is 2V.

5.3.3 DLxxxxxx0 and DLxxxxxx1 differencesApart from power on/off requirements, there are some slight electrical differences between DLxxxxxx0 and

DLxxxxxx1. These are summarized in table Tab. 21. From the functional perspective, the two part number families are equivalent.

26

Type of difference DLxxxxxx0 DLxxxxxx1

ADC0_IN (pin J1.15) voltage range [0-3.3] V [0-2.5] V

ESD Protection Level on touch controller pins (J1.39, J1.41, J1.43, J1.45)

25 kV air; 15 kV contact 2 kV

Tab. 21: Electrical differences between DLxxxxxx0 and DLxxxxxx1

Fig. 9: Power up sequence for DLxxxxxx1

V

t

t≥0

+0.9V

t

t

I²C Bus Activity

I²C Bus Activity

+Vcc

I²C_SCL

I²C_SDA

Vhigh

Vhigh

Vhigh

6 Connectors pinout

6.1 How to read this sectionThe following tables report the pinout of the Lizard connectors.

Each row in the pin-out tables reports the following information:

Pin Reference to the connector pin

Pin Name Pin (signal) name

Internal Connections

AM.<cpu_pad_name> : pin directly connected to CPU pad named < cpu_pad_name>XC.I/O: pin directly connected to CPLD I/O pinTSC.<x> : pin connected to the touchscreen connectorEXP.<x> : pin connected to the I/O expanderEEPROM.<x> : pin connected to the EEPROMCAN.<x> : pin connected to the CAN transceiverLCH.<x> : pin connected to the demuxing LATCHLAN.<x> : pin connected to the LAN PHYUSB.<x> : pin connected to the USB transceiver

Function Function associated to the pin

Ball/pin # CPU ball/pin number (for CPU directly connected pins only)

Supply Group Power Supply Group

Voltage I/O voltage

27

6.2 Pins descriptions

6.2.1 Carrier board mating connector J1

J1 – ODD [1 - 139]Pin Pin Name Internal Connections Function Ball /

pin #Supply Group

Type Voltage Note

J1.1 DGND DGND -J1.3 DGND DGND -J1.5 USB0_DM AM.USB0_DM Usb port 0 D- F24 I/OJ1.7 UART3_RX AM.UART3_RX_IRRX Uart 3 Receive Data P1 I Mode 4 = gpio_xxJ1.9 VBAT - - -J1.11 ETK_D6 AM.ETK_D6 Embedded Trace Data 6 AD19 VDDSHV O 1.8V/3.3V Mode 4 = gpio_20, I/OJ1.13 ADC_GND - -J1.15 ADC0_IN TSC.AUX ADC input TSC2007:

[0-3.3] VFor DLxxxxxx0 models

(TSC2007): voltage range is [0-3.3 V]

For DLxxxxxx1 models (TSC2003): voltage range is [0-

2.5 V]

TSC2003: [0-2.5] V

J1.17 USB0_ID AM.USB0_ID Usb port 0 op. mode ID pin G25 VDDA3P3V_USBPHY

I/O 3.3V

J1.19 UART3_RTS/JTAG_EMU0 AM.UART3_RTS_SD Uart 3 Request To Send N3 VDDSHV O 1.8V/3.3VJ1.21 UART3_CTS/JTAG_EMU1 AM.UART3_CTS_RCTX Uart 3 Clear To Send N2 VDDSHV I/O 1.8V/3.3VJ1.23 DSS_DATA18/DSI_DY0 AM.DSS_DATA18 LCD Pixel Data bit 18 W25 VDDSHV O 1.8V/3.3V Mode 4 = gpio_xxJ1.25 DSS_DATA19/DSI_DX0 AM.DSS_DATA19 LCD Pixel Data bit 19 V24 VDDSHV O 1.8V/3.3V Mode 4 = gpio_xxJ1.27 DSS_DATA20/DSI_DY1 AM.DSS_DATA20 LCD Pixel Data bit 20 V25 VDDSHV O 1.8V/3.3V Mode 4 = gpio_xxJ1.29 DSS_DATA21/DSI_DX1 AM.DSS_DATA21 LCD Pixel Data bit 21 U21 VDDSHV O 1.8V/3.3V Mode 4 = gpio_xxJ1.31 DSS_DATA22/DSI_DY2 AM.DSS_DATA22 LCD Pixel Data bit 22 U22 VDDSHV O 1.8V/3.3V Mode 4 = gpio_xxJ1.33 DSS_DATA23/DSI_DX2 AM.DSS_DATA23 LCD Pixel Data bit 23 U23 VDDSHV O 1.8V/3.3V Mode 4 = gpio_xxJ1.35 DGND DGND -J1.37 HDQ_SIO AM.HDQ_SIO Bidirectional HDQ 1-Wire

control and data interfaceL25 VDDSHV I/O 1.8V/3.3V Mode 4 = gpio_xx

J1.39 TSC_XP TSC.X+ Touch screen X+ Please consider the use of ESD protection devices on carrier

board when connected to actual touch screen.

J1.41 TSC_XM TSC.X- Touch screen X- Please consider the use of ESD protection devices on carrier


28


pin #Supply Group

Type Voltage Note

J1.43 TSC_YP TSC.Y+ Touch screen Y+ Please consider the use of ESD protection devices on carrier


J1.45 TSC_YM TSC.Y- Touch screen Y- Please consider the use of ESD protection devices on carrier


J1.47 DSS_DATA17 AM.DSS_DATA17 LCD Pixel Data bit 17 W24 VDDSHV O 1.8V/3.3V Mode 4 = gpio_xxJ1.49 DSS_DATA15 AM.DSS_DATA15 LCD Pixel Data bit 15 W22 VDDSHV O 1.8V/3.3V Mode 4 = gpio_xxJ1.51 DSS_DATA13 AM.DSS_DATA13 LCD Pixel Data bit 13 Y25 VDDSHV O 1.8V/3.3V Mode 4 = gpio_xxJ1.53 DSS_DATA11 AM.DSS_DATA11 LCD Pixel Data bit 11 Y23 VDDSHV O 1.8V/3.3V Mode 4 = gpio_xxJ1.55 DSS_DATA9 AM.DSS_DATA9 LCD Pixel Data bit 9 AA25 VDDSHV O 1.8V/3.3V Mode 4 = gpio_xxJ1.57 DSS_DATA7 AM.DSS_DATA7 LCD Pixel Data bit 7 AA23 VDDSHV O 1.8V/3.3V Mode 4 = gpio_xxJ1.59 DSS_DATA5 AM.DSS_DATA5 LCD Pixel Data bit 5 AB24 VDDSHV O 1.8V/3.3V Mode 4 = gpio_xxJ1.61 DSS_DATA3 AM.DSS_DATA3 LCD Pixel Data bit 3 AC24 VDDSHV O 1.8V/3.3V Mode 4 = gpio_xxJ1.63 DGND DGND -J1.65 DSS_DATA1 AM.DSS_DATA1 LCD Pixel Data bit 1 AD25 VDDSHV O 1.8V/3.3V Mode 4 = gpio_xxJ1.67 MCSPI2_CS0 AM.MCSPI2_CS0 Multichannel Serial Port

Interface 2 – SPI Enable 0AA16 VDDSHV I/O 1.8V/3.3V

Mode 4 = gpio_xxJ1.69 DSS_VSYNC AM.DSS_VSYNC LCD Vertical Synchronization AD23 VDDSHV O 1.8V/3.3V Mode 4 = gpio_xxJ1.71 DSS_PCLK AM.DSS_PCLK LCD Pixel Clock AE23 VDDSHV O 1.8V/3.3V Mode 4 = gpio_xxJ1.73 KP_ROW1 XC.I/O Keypad Row 1J1.75 KP_ROW3 XC.I/O Keypad Row 3J1.77 KP_ROW5 XC.I/O Keypad Row 5J1.79 KP_ROW7 XC.I/O Keypad Row 7J1.81 KP_COL1 XC.I/O Keypad Col 1J1.83 KP_COL3 XC.I/O Keypad Col 3J1.85 KP_COL5 XC.I/O Keypad Col 5J1.87 KP_COL7 XC.I/O Keypad Col 7J1.89 DGND DGND -J1.91 I/O_EXP0 EXP.P00 I/O Exp. Port 0 – channel 0J1.93 I/O_EXP1 EXP.P01 I/O Exp. Port 0 – channel 1J1.95 N.C.J1.97 JTAG_RTCK AM.JTAG_RTCK JTAG - ARM Clock

EmulationT21 VDDSHV O 1.8V/3.3V

J1.99 I/O_EXP2 EXP.P02 I/O Exp. Port 0 – channel 2J1.101 I/O_EXP3 EXP.P03 I/O Exp. Port 0 – channel 3J1.103 I/O_EXP4 EXP.P04 I/O Exp. Port 0 – channel 4J1.105 I/O_EXP5 EXP.P05 I/O Exp. Port 0 – channel 5J1.107 USB0_DRVVBUS AM.USB0_DRVVBUS Usb 0 – digital output to

control external supplyE25 VDDSHV O

J1.109 SYS_BOOT1 AM.SYS_BOOT1 Boot Configuration Mode – bit 1

AA1 VDDSHV I 1.8V/3.3V

J1.111 SYS_CLKOUT1 AM.SYS_CLKOUT1 Configurable output clock 1 N25 VDDSHV O 1.8V/3.3VJ1.113 DGND DGND -J1.115 SYS_CLKOUT2 AM.SYS_CLKOUT2 Configurable output clock 2 M25 VDDSHV O 1.8V/3.3V Mode 4 = gpio_xx

29


pin #Supply Group

Type Voltage Note

J1.117 MMC2_DAT2 AM.MMC2_D2 MMC/SD card 2 – Data bit 2 AD12 VDDSHV I/O 1.8V/3.3V Mode 4 = gpio_xxJ1.119 MMC1_DAT0 AM.MMC1_D0 MMC/SD card 1 – Data bit 0 AC9 VDDSHV I/O 1.8V/3.3V Mode 4 = gpio_xxJ1.121 MMC1_DAT1 AM.MMC1_D1 MMC/SD card 1 – Data bit 1 AD9 VDDSHV I/O 1.8V/3.3V Mode 4 = gpio_xxJ1.123 MMC1_DAT2 AM.MMC1_D2 MMC/SD card 1 – Data bit 2 AE9 VDDSHV I/O 1.8V/3.3V Mode 4 = gpio_xxJ1.125 MMC1_DAT3 AM.MMC1_D3 MMC/SD card 1 – Data bit 3 AA10 VDDSHV I/O 1.8V/3.3V Mode 4 = gpio_xxJ1.127 MMC1_DAT4 AM.MMC1_D4 MMC/SD card 1 – Data bit 4 AB10 VDDSHV I/O 1.8V/3.3V Mode 4 = gpio_xxJ1.129 MMC1_DAT5 AM.MMC1_D5 MMC/SD card 1 – Data bit 5 AC10 VDDSHV I/O 1.8V/3.3V Mode 4 = gpio_xxJ1.131 TV_OUT1 AM.TV_OUT1 TV analog output composite K21 VDDA_DAC O 1.8VJ1.133 TV_OUT2 AM.TV_OUT2 TV analog output S-Video H24 VDDA_DAC O 1.8VJ1.135 MMC1_CMD AM.MMC1_CMD MMC/SD card 1 – Command AB9 VDDSHV I/O 1.8V/3.3V Mode 4 = gpio_xxJ1.137 MMC1_CLK AM.MMC1_CLK MMC/SD card 1 – Clock AA9 VDDSHV I/O 1.8V/3.3V Mode 4 = gpio_xxJ1.139 DGND DGND -

J1 – EVEN [2 - 140]Pin Pin Name Internal Connections Function Ball/

pin #Supply Group

Type Voltage Note

J1.2 DGND DGND -J1.4 DGND DGND -J1.6 USB0_DP AM.USB0_DP Usb port 0 D+ F25 I/OJ1.8 UART3_TX AM.UART3_TX_IRTX Uart 3 Transmit Data P2 VDDSHV O 1.8V/3.3VJ1.10 EEPROM_A0 EEPROM.A1 Eeprom address line 0J1.12 EEPROM_A1 EEPROM.A2 Eeprom address line 1J1.14 I/O_EXP15 EXP.P17 I/O Exp. Port 1 – channel 7J1.16 USB0_VBUS AM.USB0_VBUS Usb port 0 VBUS/USB power signal G24 VDDA3P3V_U

SBPHYI/O 3.3V

J1.18 CCDC_FIELD AM.CCDC_FIELD VPFE/CCDC field id signal AD21 VDDSHV I/O 1.8V/3.3VJ1.20 CCDC_HD AM.CCDC_HD VPFE/CCDC horizontal sync AE2 VDDSHV I/O 1.8V/3.3VJ1.22 CCDC_WEN AM.CCDC_WEN VPFE/CCDC write enable AE3 VDDSHV I/O 1.8V/3.3VJ1.24 CCDC_VD AM.CCDC_VD VPFE/CCDC vertical sync AD3 VDDSHV I/O 1.8V/3.3VJ1.26 CCDC_PCLK AM.CCDC_PCLK VPFE/CCDC pixel clock AD2 VDDSHV I/O 1.8V/3.3VJ1.28 DGND DGND -J1.30 CCDC_DATA0 AM.CCDC_DATA0 VPFE/CCDC data bit 0 AD4 VDDSHV I 1.8V/3.3VJ1.32 CCDC_DATA1 AM.CCDC_DATA1 VPFE/CCDC data bit 1 AE4 VDDSHV I 1.8V/3.3VJ1.34 CCDC_DATA2 AM.CCDC_DATA2 VPFE/CCDC data bit 2 AC5 VDDSHV I 1.8V/3.3VJ1.36 CCDC_DATA3 AM.CCDC_DATA3 VPFE/CCDC data bit 3 AD5 VDDSHV I 1.8V/3.3VJ1.38 CCDC_DATA4 AM.CCDC_DATA4 VPFE/CCDC data bit 4 AE5 VDDSHV I 1.8V/3.3VJ1.40 CCDC_DATA5 AM.CCDC_DATA5 VPFE/CCDC data bit 5 Y6 VDDSHV I 1.8V/3.3VJ1.42 CCDC_DATA6 AM.CCDC_DATA6 VPFE/CCDC data bit 6 AB6 VDDSHV I 1.8V/3.3VJ1.44 CCDC_DATA7 AM.CCDC_DATA7 VPFE/CCDC data bit 7 AC6 VDDSHV I 1.8V/3.3VJ1.46 DSS_DATA16 AM.DSS_DATA16 LCD Pixel Data bit 16 W23 VDDSHV O 1.8V/3.3VJ1.48 DSS_DATA14 AM.DSS_DATA14 LCD Pixel Data bit 14 W21 VDDSHV O 1.8V/3.3VJ1.50 DSS_DATA12 AM.DSS_DATA12 LCD Pixel Data bit 12 Y24 VDDSHV O 1.8V/3.3V

30


pin #Supply Group

Type Voltage Note

J1.52 DGND DGND -J1.54 DSS_DATA10 AM.DSS_DATA10 LCD Pixel Data bit 10 Y22 VDDSHV O 1.8V/3.3VJ1.56 DSS_DATA8 AM.DSS_DATA8 LCD Pixel Data bit 8 AA24 VDDSHV O 1.8V/3.3VJ1.58 DSS_DATA6 AM.DSS_DATA6 LCD Pixel Data bit 6 AB25 VDDSHV O 1.8V/3.3VJ1.60 DSS_DATA4 AM.DSS_DATA4 LCD Pixel Data bit 4 AC25 VDDSHV O 1.8V/3.3VJ1.62 DSS_DATA2 AM.DSS_DATA2 LCD Pixel Data bit 2 AC23 VDDSHV O 1.8V/3.3VJ1.64 DSS_DATA0 AM.DSS_DATA0 LCD Pixel Data bit 0 AD24 VDDSHV O 1.8V/3.3VJ1.66 DSS_ACBIAS AM.DSS_ACBIAS AC bias control (STN)/Pixel data

enable (TFT)AE24 VDDSHV O 1.8V/3.3V

J1.68 DSS_HSYNC AM.DSS_HSYNC LCD horizontal synchronization AD22 VDDSHV O 1.8V/3.3VJ1.70 MCSPI2_SOMI AM.MCSPI2_SOMI Multichannel Serial Port Interface 2

– Slave data out, master data inAB16 VDDSHV I/O 1.8V/3.3V

J1.72 KP_ROW0 XC.I/O Keypad Row 0J1.74 KP_ROW2 XC.I/O Keypad Row 2J1.76 DGND DGND -J1.78 KP_ROW4 XC.I/O Keypad Row 4J1.80 KP_ROW6 XC.I/O Keypad Row 6J1.82 KP_COL0 XC.I/O Keypad Col 0J1.84 KP_COL2 XC.I/O Keypad Col 2J1.86 KP_COL4 XC.I/O Keypad Col 4J1.88 KP_COL6 XC.I/O Keypad Col 6J1.90 SYS_BOOT0 AM.SYS_BOOT0 Boot Configuration Mode – bit 0 Y4 VDDSHV I 1.8V/3.3VJ1.92 I/O_EXP6 EXP.P06 I/O Exp. Port 0 – channel 6J1.94 I/O_EXP7 EXP.P07 I/O Exp. Port 0 – channel 7J1.96 CAN_H CAN.CANH CAN High When the on-board CAN

transceiver is by-passed, this signal is CAN TX (3.1.2.3)

J1.98 CAN_L CAN.CANL CAN Low When the on-board CAN transceiver is by-passed, this signal is CAN RX (3.1.2.3)

J1.100 DGND DGND -J1.102 MMC1_DAT6 AM.MMC1_D6 MMC/SD card 1 – Data bit 6 AD10 VDDSHV I/O 1.8V/3.3VJ1.104 MMC1_DAT7 AM.MMC1_D7 MMC/SD card 1 – Data bit 7 AE10 VDDSHV I/O 1.8V/3.3VJ1.106 I/O_EXP8 EXP.P10 I/O Exp. Port 1 – channel 8J1.108 I2C4_SDA/I/O_EXP9 EXP.P11 I2C channel 4 – Serial bidirectional

dataJ1.110 I2C4_SCL/I/O_EXP10 EXP.P12 I2C channel 4 – Master serial clockJ1.112 ETK_D12 AM.ETK_D12 Embedded Trace Data 12 AE21 VDDSHV O 1.8V/3.3V Mode 4 = gpio_26, I/OJ1.114 SYS_CLKREQ AM.SYS_CLKREQ Request from device for system

clockM24 VDDSHV I/O 1.8V/3.3V

J1.116 MMC2_DAT7 AM.MMC2_D7 MMC/SD card 2 – Data bit 7 AE13 VDDSHV I/O 1.8V/3.3VJ1.118 MMC2_DAT3 AM.MMC2_D3 MMC/SD card 2 – Data bit 3 AE12 VDDSHV I/O 1.8V/3.3VJ1.120 MMC2_DAT6 AM.MMC2_D6 MMC/SD card 2 – Data bit 6 AD13 VDDSHV I/O 1.8V/3.3VJ1.122 MMC2_DAT4 AM.MMC2_D4 MMC/SD card 2 – Data bit 4 AB13 VDDSHV I/O 1.8V/3.3VJ1.124 MMC2_DAT5 AM.MMC2_D5 MMC/SD card 2 – Data bit 5 AC13 VDDSHV I/O 1.8V/3.3VJ1.126 DGND DGND -J1.128 MMC2_CLK AM.MMC2_CLK MMC/SD card 2 – Clock AD11 VDDSHV O 1.8V/3.3V

31


pin #Supply Group

Type Voltage Note

J1.130 MMC2_CMD AM.MMC2_CMD MMC/SD card 2 – Command AE11 VDDSHV I/O 1.8V/3.3VJ1.132 MMC2_DAT0 AM.MMC2_D0 MMC/SD card 2 – Data bit 0 AB12 VDDSHV I/O 1.8V/3.3VJ1.134 MMC2_DAT1 AM.MMC2_D1 MMC/SD card 2 – Data bit 1 AC12 VDDSHV I/O 1.8V/3.3VJ1.136 I2C3_SCL AM.I2C3_SCL I2C channel 3 – Master serial clock W4 VDDSHV I/O 1.8V/3.3VJ1.138 I2C3_SDA AM.I2C3_SDA I2C channel 3 – Serial bidirectional

dataW5 VDDSHV I/O 1.8V/3.3V

J1.140 DGND DGND -

32

6.2.2 Carrier board mating connector J2

J2 – ODD [1-139]Pin Pin Name Internal Connections Default function Ball/

pin #Supply Group

Type Voltage Note

J2.1 VIN +3V3 -J2.3 DGND DGND -J2.5 GPMC_D0 AM.GPMC_D0 GPMC data bit 0 G5 VDDSHV I/O 1.8V/3.3V

J2.7 GPMC_D2 AM.GPMC_D2 GPMC data bit 2 G3 VDDSHV I/O 1.8V/3.3VJ2.9 GPMC_D4 AM.GPMC_D4 GPMC data bit 4 G1 VDDSHV I/O 1.8V/3.3VJ2.11 GPMC_D6 AM.GPMC_D6 GPMC data bit 6 H1 VDDSHV I/O 1.8V/3.3VJ2.13 GPMC_D8 AM.GPMC_D8 GPMC data bit 8 J4 VDDSHV I/O 1.8V/3.3VJ2.15 GPMC_D10 AM.GPMC_D10 GPMC data bit 10 J2 VDDSHV I/O 1.8V/3.3VJ2.17 GPMC_D12 AM.GPMC_D12 GPMC data bit 12 K4 VDDSHV I/O 1.8V/3.3VJ2.19 GPMC_D14 AM.GPMC_D14 GPMC data bit 14 K2 VDDSHV I/O 1.8V/3.3VJ2.21 LATCHED_A16 - Latched address A16 - - O 3.3V See section 3.2.3 on page 20J2.23 GPMC_A2 AM.GPMC_A2 General purpose memory address

bit 2E2 VDDSHV O 1.8V/3.3V

J2.25 GPMC_A4 AM.GPMC_A4 General purpose memory address bit 4

F7 VDDSHV O 1.8V/3.3V






J2.33 LATCHED_A2 - Latched address A2 - - O 3.3V See section 3.2.3 on page 20J2.35 VINJ2.37 DGND DGND -J2.39 LATCHED_A4 - Latched address A4 - - O 3.3V See section 3.2.3 on page 20J2.41 LATCHED_A6 - Latched address A6 - - O 3.3V See section 3.2.3 on page 20J2.43 LATCHED_A8 - Latched address A8 - - O 3.3V See section 3.2.3 on page 20J2.45 LATCHED_A10 - Latched address A10 - - O 3.3V See section 3.2.3 on page 20J2.47 LATCHED_A12 - Latched address A12 - - O 3.3V See section 3.2.3 on page 20J2.49 LATCHED_A14 - Latched address A14 - - O 3.3V See section 3.2.3 on page 20J2.51 GPMC_NCS0 AM.GPMC_NCS0 GPMC Chip Select 0 L2 VDDSHV O 1.8V/3.3VJ2.53 GPMC_NCS2 AM.GPMC_NCS2 GPMC Chip Select 2 M4 VDDSHV O 1.8V/3.3VJ2.55 GPMC_NCS4 AM.GPMC_NCS4 GPMC Chip Select 4 M2 VDDSHV O 1.8V/3.3VJ2.57 GPMC_NWE AM.GPMC_NWE GPMC Write Enable R3 VDDSHV O 1.8V/3.3VJ2.59 GPMC_NADV_ALE AM.GPMC_NADV_ALE GPMC address valid/address latch enable N5 VDDSHV O 1.8V/3.3VJ2.61 GPMC_CLK AM.GPMC_CLK GPMC Clock N1 VDDSHV O 1.8V/3.3VJ2.63 MCBSP2_FSX AM.MCBSP2_FSX Multichannel buffered serial port 2 –

Combined frame synchronizationD25 VDDSHV I/O 1.8V/3.3V

J2.65 VIN +3V3J2.67 DGND DGND -J2.69 MCSPI1_CLK AM.MCSPI1_CLK Multichannel Serial Port Interface 1 -

SPI ClockAE14 VDDSHV I/O 1.8V/3.3V

33

J2 – ODD [1-139]Pin Pin Name Internal Connections Default function Ball/

pin #Supply Group

Type Voltage Note

J2.71 MCBSP_CLKS AM.MCBSP_CLKS Multichannel buffered serial port – External clock input

P25 VDDSHV I 1.8V/3.3V

J2.73 MCSPI1_CS0 AM.MCSPI1_CS0 Multichannel Serial Port Interface 1 - SPI Enable 0

AB15 VDDSHV I/O 1.8V/3.3V

J2.75 MCBSP1_CLKR AM.MCBSP1_CLKR Multichannel buffered serial port 1 – Receive clock

R25 VDDSHV I/O 1.8V/3.3V

J2.77 MCBSP1_DR AM.MCBSP1_DR Multichannel buffered serial port 1 – Receive serial data

P23 VDDSHV I 1.8V/3.3V

J2.79 MCBSP1_FSR AM.MCBSP1_FSR Multichannel buffered serial port 1 – Receive frame synchronization

P21 VDDSHV I/O 1.8V/3.3V

J2.81 MCBSP3_CLKX AM.MCBSP3_CLKX Multichannel buffered serial port 3 – Combined serial clock

A24 I/O

J2.83 MCBSP3_DX AM.MCBSP3_DX Multichannel buffered serial port 3 – Transmitted serial data

B24 VDDSHV I/O 1.8V/3.3V

J2.85 MCBSP4_CLKX AM.MCBSP4_CLKX Multichannel buffered serial port 4 – Combined serial clock

B23 I/O

J2.87 MCBSP4_DX AM.MCBSP4_DX Multichannel buffered serial port 4 – Transmitted serial data

B22 VDDSHV I/O 1.8V/3.3V

J2.89 GPMC_WAIT2 AM.GPMC_WAIT2 GPMC External indication of wait T5 VDDSHV I 1.8V/3.3VJ2.91 RSTn AM.SYS_nRESWARM Warm Boot Reset Y3 VDDSHV I/O 1.8V/3.3VJ2.93 UART2_RTS AM.UART2_RTS Uart 2 Request To Send F19 VDDSHV O 1.8V/3.3VJ2.95 SYS_BOOT5 AM.SYS_BOOT5 Boot Configuration Mode – bit 5 AB2 VDDSHV I 1.8V/3.3VJ2.97 MCSPI1_CS1 AM.MCSPI1_CS1 Multichannel Serial Port Interface 1 -

SPI Enable 1AD14 VDDSHV I/O 1.8V/3.3V

J2.99 MCSPI1_CS2 AM.MCSPI1_CS2 Multichannel Serial Port Interface 1 - SPI Enable 2

AE15 VDDSHV I/O 1.8V/3.3V

J2.101 VIN +3V3J2.103 DGND DGND -J2.105 JTAG_TDI AM.JTAG_TDI JTAG Test Data Input T23 VDDSHV I 1.8V/3.3VJ2.107 JTAG_TMS AM.JTAG_TMS_TMSC JTAG Test Mode Select T22 VDDSHV I/O 1.8V/3.3VJ2.109 PORSTn AM.SYS_nRESPWRON Power On Reset Y2 VDDSHV I 1.8V/3.3VJ2.111 ETH_LED4 LAN.SPEED100 Ethernet Speed LedJ2.113 ETH_LED3 -J2.115 ETH_LED2 LAN.LINK Ethernet Link LedJ2.117 ETH_LED1 LAN.ACTIVITY Ethernet Activity LedJ2.119 ETH_LED0 LAN.FDUPLEX Ethernet Full Duplex LedJ2.121 UART1_TX AM.UART1_TX Uart 1 Transmit data AA19 VDDSHV O 1.8V/3.3VJ2.123 UART1_RTS AM.UART1_RTS Uart 1 Request To Send Y19 VDDSHV I 1.8V/3.3VJ2.125 ETK_CLK/UART1_DSR AM.ETK_CLK Uart 1 Data Set Ready AD17 VDDSHV O 1.8V/3.3V Mode=4, gpio_12J2.127 ETH_CTTD - Reference for Tx wiring central tapJ2.129 ETH_TX- LAN.TXN Ethernet Transmit data -J2.131 ETH_TX+ LAN.TXP Ethernet Transmit data +J2.133 ETH_RX+ LAN.RXP Ethernet Receive data +J2.135 ETH_RX- LAN.RXN Ethernet Receive data -J2.137 ETH_CTRD - Reference for Rx wiring central tapJ2.139 DGND DGND -

34

J2 – EVEN [2-140]Pin Pin Name Internal Connections Function Ball/

pin #Supply Group

Type Voltage Note

J2.2 DGND DGND -J2.4 GPMC_D1 AM.GPMC_D1 GPMC data bit 1 G4 VDDSHV I/O 1.8V/3.3VJ2.6 GPMC_D3 AM.GPMC_D3 GPMC data bit 3 G2 VDDSHV I/O 1.8V/3.3VJ2.8 GPMC_D5 AM.GPMC_D5 GPMC data bit 5 H2 VDDSHV I/O 1.8V/3.3VJ2.10 GPMC_D7 AM.GPMC_D7 GPMC data bit 7 J5 VDDSHV I/O 1.8V/3.3VJ2.12 GPMC_D9 AM.GPMC_D9 GPMC data bit 9 J3 VDDSHV I/O 1.8V/3.3VJ2.14 GPMC_D11 AM.GPMC_D11 GPMC data bit 11 J1 VDDSHV I/O 1.8V/3.3VJ2.16 GPMC_D13 AM.GPMC_D13 GPMC data bit 13 K3 VDDSHV I/O 1.8V/3.3VJ2.18 GPMC_D15 AM.GPMC_D15 GPMC data bit 15 K1 VDDSHV I/O 1.8V/3.3VJ2.20 DGND DGND -J2.22 GPMC_A1 AM.GPMC_A1 General purpose memory address

bit 1E3 VDDSHV O 1.8V/3.3V


E1 VDDSHV O 1.8V/3.3V







J2.32 LATCHED_A1 - Latched address A1 - - O 3.3V See section 3.2.3 on page 20J2.34 LATCHED_A3 - Latched address A3 - - O 3.3V See section 3.2.3 on page 20J2.36 LATCHED_A5 - Latched address A5 - - O 3.3V See section 3.2.3 on page 20J2.38 LATCHED_A7 - Latched address A7 - - O 3.3V See section 3.2.3 on page 20J2.40 LATCHED_A9 - Latched address A9 - - O 3.3V See section 3.2.3 on page 20J2.42 LATCHED_A11 - Latched address A11 - - O 3.3V See section 3.2.3 on page 20J2.44 LATCHED_A13 - Latched address A13 - - O 3.3V See section 3.2.3 on page 20J2.46 LATCHED_A15 - Latched address A15 - - O 3.3V See section 3.2.3 on page 20J2.48 GPMC_NCS1 AM.GPMC_NCS1 GPMC Chip Select 1 L1 VDDSHV O 1.8V/3.3VJ2.50 GPMC_NCS3 AM.GPMC_NCS3 GPMC Chip Select 3 M3 VDDSHV O 1.8V/3.3VJ2.52 GPMC_NCS5 AM.GPMC_NCS5 GPMC Chip Select 5 M1 VDDSHV O 1.8V/3.3VJ2.54 DGND DGND -J2.56 GPMC_NOE AM.GPMC_NOE GPMC Output Enable R2 VDDSHV O 1.8V/3.3VJ2.58 GPMC_NBE0_CLE AM.GPMC_NBE0_CLE GPMC Lower Byte

Enable/Command Latch EnableR4 VDDSHV O 1.8V/3.3V

J2.60 GPMC_NBE1 AM.GPMC_NBE1 GPMC Upper Byte Enable T1 VDDSHV O 1.8V/3.3VJ2.62 GPMC_WAIT1 AM.GPMC_WAIT1 GPMC External Indication of Wait T4 VDDSHV I 1.8V/3.3VJ2.64 GPMC_NCS7 AM.GPMC_NCS7 GPMC Chip Select 7 N4 VDDSHV O 1.8V/3.3VJ2.66 SYS_nIRQ AM.SYS_nIRQ External FIQ interrupt Y1 VDDSHV I 1.8V/3.3VJ2.68 MCBSP2_CLKX AM.MCBSP2_CLKX Multichannel buffered serial port 2 –

Combined Serial ClockC25 I/O

J2.70 MCBSP2_DR AM.MCBSP2_DR Multichannel buffered serial port 2 – Received Serial Data

B25 VDDSHV I 1.8V/3.3V

J2.72 MCSPI1_SOMI AM.MCSPI1_SOMI Multichannel Serial Port Interface 1 - Slave Data Out, Master Data In

AC15 I/O

35

J2 – EVEN [2-140]Pin Pin Name Internal Connections Function Ball/

pin #Supply Group

Type Voltage Note

J2.74 MCBSP2_DX AM.MCBSP2_DX Multichannel buffered serial port 2 – Transmitted Serial Data

D24 VDDSHV I/O 1.8V/3.3V

J2.76 MCSPI1_SIMO AM.MCSPI1_SIMO Multichannel Serial Port Interface 1 - Slave Data In, Master Data Out

AD15 I/O

J2.78 MCBSP1_CLKX AM.MCBSP1_CLKX Multichannel buffered serial port 1 – Combined Serial Clock

N24 I/O

J2.80 MCBSPI1_DX AM.MCBSP1_DX Multichannel buffered serial port 1 – Transmitted Serial Data

P22 VDDSHV I/O 1.8V/3.3V

J2.82 DGND DGND -J2.84 MCBSP1_FSX AM.MCBSP1_FSX Multichannel buffered serial port 1 –

Combined Frame SynchronizationP24 VDDSHV I/O 1.8V/3.3V


C24 VDDSHV I 1.8V/3.3V

J2.88 MCBSP3_FSX AM.MCBSP3_FSX Multichannel buffered serial port 3 – Combined Frame Synchronization

C23 VDDSHV I/O 1.8V/3.3V


A23 VDDSHV I 1.8V/3.3V

J2.92 MCBSP4_FSX AM.MCBSP4_FSX Multichannel buffered serial port 4 – Combined Frame Synchronization

A22 VDDSHV I/O 1.8V/3.3V

J2.94 GPMC_WAIT3 AM.GPMC_WAIT3 GPMC External Indication of Wait U1 VDDSHV I 1.8V/3.3VJ2.96 JTAG_TDO AM.JTAG_TDO JTAG Test Data Output T24 VDDSHV O 1.8V/3.3VJ2.98 JTAG_TCK AM.JTAG_TCK JTAG Test Clock U25 VDDSHV I 1.8V/3.3VJ2.100 JTAG_TRSTn AM.JTAG_nTRST JTAG Test Reset U24 VDDSHV I 1.8V/3.3VJ2.102 MRSTn - Master reset inputJ2.104 UART2_CTS AM.UART2_CTS Uart 2 Clear To Send F20 VDDSHV I 1.8V/3.3VJ2.106 I2C2_SCL AM.I2C2_SCL I2C channel 2 – Master serial clock W1 VDDSHV I/O 1.8V/3.3VJ2.108 I2C2_SDA AM.I2C2_SDA I2C channel 2 – Serial bidirectional

dataW2 VDDSHV I/O 1.8V/3.3V

J2.110 SYS_BOOT4 AM.SYS_BOOT4 Boot Configuration Mode – bit 4 AB1 VDDSHV I 1.8V/3.3VJ2.112 SYS_BOOT3 AM.SYS_BOOT3 Boot Configuration Mode – bit 3 AA3 VDDSHV I 1.8V/3.3VJ2.114 EEPROM_WP EEPROM.WP Eeprom Write Protect InputJ2.116 DGND DGND -J2.118 SYS_BOOT2 AM.SYS_BOOT2 Boot Configuration Mode – bit 2 AA2 VDDSHV I 1.8V/3.3VJ2.120 UART2_TX AM.UART2_TX Uart 2 Transmit Data E24 VDDSHV O 1.8V/3.3VJ2.122 UART2_RX AM.UART2_RX Uart 2 Receive Data E23 VDDSHV I 1.8V/3.3VJ2.124 USBP1 USB1.D+ Usb Host port 1 D+J2.126 USBP2 USB2.D+ Usb Host port 2 D+J2.128 UART1_RX AM.UART1_RX Uart 1 Receive Data W20 VDDSHV I 1.8V/3.3VJ2.130 UART1_CTS AM.UART1_CTS Uart 1 Clear To Send Y20 VDDSHV I 1.8V/3.3VJ2.132 ETK_D3/UART1_DTR AM.ETK_D3 Uart 1 Data Terminal Ready AA18 VDDSHV O 1.8V/3.3V Mode=4, gpio_17J2.134 USBM1 USB1.D- Usb Host port 1 D-J2.136 USBM2 USB2.D- Usb Host port 2 D-J2.138 VIN +3V3 -J2.140 DGND DGND -

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7 Resource allocation

7.1 Resource allocationThis section describes how the resources are allocated in terms of memory regions and IRQs.

7.1.1 Simplified memory maptbd

7.1.2 IRQstbd

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8 Host board design guidelines

tbd

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9 Naming, order codes and standard releases

Each Lizard module reports a marking code label on top side that identifies the specific model according to order code. Please see below for part number decoder.

Product: Lizard

Code structureDQ p f r n c t s iiii

Family Processor Flash nor

size

DDR RAM Size Flash nand size Boot Temp. Range Submodel Identifier

DL = Dave

Lizard

A = AM3517

B = AM3505

0 = 0MB

3 = 4MB

5 = 32MB

6 = 64MB

7 = 128MB

6 = 64MB

7 = 128MB

8 = 256MB

0 = 0MB

1 = 1024MB

2 = 128MB

0= boot

from NAND

1= boot

from NOR

C = commercial

(0/+70°C)

I =

industrial(-

40/+85°C)

See table

below

Combined with other

fields, identifies

univocally the product

Submodel Description

0 Standard

1 CS Rev B

Valid combinations (for combinations not listed here please contact our sales department)

DLA7810I0R Lizard, AM3517, 128MB NOR, 256MB RAM, 1GB NAND, Industrial Temp. Range, NAND boot, RoHS compliant

DLA7811IxR Lizard, AM3517, 128MB NOR, 256MB RAM, 1GB NAND, Industrial Temp. Range, NOR boot, RoHS compliant

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10 Agency approvals

The following tests have been considered inherent and applicable:

• EN 55022 : Emission of radiated disturbances tbd• EN 61000-4-3 : Immunity to RF electromagnetic fields tbd• EN 61000-4-4 : Immunity to fast transient bursts (mains) tbd• EN 61000-4-4 : Immunity to fast transient bursts (communication lines) tbd• EN 61000-4-6 : Immunity to RF conducted disturbances (mains) tbd• EN 61000-4-6 : Immunity to RF conducted disturbances (communication lines) tbd

Test reports (tbd) available on request.

11 Support

To contact technical support, please send an e-mail to address [email protected]

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Bibliography1: Texas Instruments, AM3517/05 ARM Microprocessor Datasheet, 20102: Dave, Lizard Embedded Linux Kit Software Manual, 2009

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