Lithography and Design in Partnership: A New Roadmap Andrew B. Kahng UCSD Depts. of CSE and ECE...

Lithography and Design in Partnership: A New Roadmap

Andrew B. KahngUCSD Depts. of CSE and ECE

[email protected]://vlsicad.ucsd.edu/

mailto:[email protected]

http://vlsicad.ucsd.edu/

Andrew B. Kahng 2SPIE Advanced Lithography 2008

Outline

• Two Cultures, Two Roadmaps

• Lithography changes the Design roadmap

• Design changes the Lithography roadmap

• Toward a shared Litho-Design roadmap


Two Mindsets

DESIGN• Golden model of Process

• SPICE

• Don’t know how it was obtained

• To sell the chip, meet spec

• power and timing

• Mechanism for checking:

• verify at “corners”

• Don’t know how they were obtained

PROCESS• Golden model of Chip

• Polygon data

• Don’t know how it was obtained

• To sell the wafer, meet spec

• shapes and currents

• Mechanism for checking:

• measure silicon


Two Kinds of “Beyond the Die”DESIGN

Die

Package

Board

System

Wafer

Wafer-to-Wafer Lot-to-Lot

PROCESS


Two Roadmaps

CD UniformityMEEF dense line

MEEF isolated line

LinearityCD MTT

Data volumeDefect size

Chip sizeLeakage powerDynamic powerMax frequency

MTTFReuse

Circuit families


What Is The Connection?

• Device• Model• Circuit• Product• Cost

LITHOCD uniformity MEEF dense

MEEF isolatedLinearity CD MTT

Data volume Defect size

DESIGNChip size

Leakage powerDynamic powerMax frequency

MTTFReuse

Circuit families

A1 A2

B1 B2

C1 C2nlnr

VDD

WL

BLb BL

BSIM Model


Outline






1. Layout Restriction: RDRs• RETs, DRCs, physics Risk, Margin, Cost• Give designers freedom from choice• Area cost of RDRs = one-time, inevitable ‘reset’

Irregular active geometryIrregular poly geometryOff-grid contact placement

Beyond L3GO: All geometryrepresented as lines and dots


Requirement: Grid-Based Layout

• Not a slam dunk– Logic: contact landing, diffusion, area optimization– SRAM: SNM multiple diffusion widths– Clouded by imperfect cost and feasibility analyses

• Win: scaling, model guardband reduction, TAT

45nm 45nm (IBM, IEDM06)

model guardband reduction


Design Impact of Model Guardband

• Random Defect Yield (Yr)– Strong function of area (A)

• Guardband reduction less design time, less chip area !

– (Timing closure is easier)

• Parametric Yield (Ys)– Function of design guardband

• Guardband reduction less yield at wafer sort

k

k

Ad

Ad

k

k

kPr

)1(

)(

)(!

)(

) chipon defects#(

k = 0 Binomial PDF

)1( AdYrWorst case (α = ): Poisson

Adr eY

2

)01.01(3

2

)01.01(3

2

1%)(

xerf

xerfxYs

34.1%34.1%

13.6%13.6% 2.1%

-3

0.1%

-2 -1 1 2 3

0 . 0

0 . 1

0 . 2

0 . 3

0 . 4

• Example: normal distribution with BC / WC = -3σ / +3σ

– x% guardband reduction

– 0% reduction: Ys=0.9973

– 40% reduction: Ys=0.9281


Guardband Impact = Methodology Lever• UCSD 2007: Design methodology can use model guardband as lever to

trade off TAT, chip area and power, and sort yield• Complements variability reductions in the manufacturing process

– Random defect yield will increase– Parametric yield will decrease– TAT will decrease– (Moore’s Law: 1% per week)

138

140

142

144

146

148

150

152

154

156

158

0 10 20 30 40 50 60

Reduced GB (%)

# o

f g

oo

d d

ice

per

waf

er

no clustering

alpha=0.42

alpha=0.43

alpha=0.44

alpha=0.45

alpha=0.5

alpha=1

alpha=10

alpha=1000

• Example: 20% guardband reduction 4% increase in good die /wafer


2. Double Patterning Lithography (DPL)

• ORAMEX (Ordinary Resist And Multiple Exposure), IBM 1998• Challenges

– Equipment: overlay margin– Design: layout decomposition, design rules, new OPC for DPL

First Mask Second Mask

+

Combined exposure

Desired pattern


Layout Splitting and Coloring

• Find min-cost color assignment– Non-touching features with

0 < d(i,j) < t different colors– Touching features assigned different

colors incur cost cij

Layout Fracturing

Conflict Graph Construction

Conflict Cycle Detection

Node Splitting forConflict Cycle Removal

ILP based or heuristic Graph Coloring

Conflict

Cycle?

Node Splittingfor Touching Features

Yes

No


Smart Dividing Point Selection

• Split polygons to have maximum overlap• Reduce CD variation from LES, misalignment

= +

= +


Limits of Layout Decomposition

• Require DPL-compliant design

o1

o2

= +

Layout Decomposition Two Masks with Extended Overlap Design Change(Increase space)

Decomposition (1) Decomposition (2) Design Change(Increase space)

Design Change(Reduce size)


Hierarchical ILP Solver (UCSD 2008)

• Layout decomposition– Solves all conflict cycles with largest possible overlap lengths

• Scalable runtime from hierarchical graph decomposition– 32nm dense layout: ~2400 sec / mm2, 1 CPU, fully parallelizable

t# conflict

cycles

overlap lengthsRuntime

(s)49nm 70nm 72nm

60 0 0 0 0 101.4

64 123 0 0 0 109.9

68 251 0 125 0 104.9

72 728 0 125 295 99.4

76 737 0 125 295 94.1

80 770 0 125 295 93.6

84 778 0 125 295 92.6

88 872 97 125 295 93.0

• Testcase: 0.5mm x 0.5mm block, TSMC 90nm– 20K standard cells– High layout density: 90% utilization

• GDS scaled down by 0.4 minimum width: 40nm

minimum space: 56nm• Vary distance threshold t from 60nm to 88nm

– 1.1 to 1.6 times minimum spacing


3. Analyses of Bimodal CD Distribution

• Bimodal distribution in DPL– Poly gates made by two independent processes– Gate CD distributions in two groups can differ

• Loss of correlations (spatial, line-space)

Group 1 Group 2

Mean ofGroup 1

Mean ofGroup 2

Source: Wikipedia


Unimodal Modeling Is Pessimistic

• Conventional unimodal representation does not capture bimodal process variation

• DPL modeling, analysis requirements = ?

BC of G1

BC of G2 WC of G1

WC of G2

G1G2


Monte Carlo Simulation

• SPICE model– 65nm, Typical corner (TT), 1.0V,

25C• SPICE circuit

– 65nm NVT: Nominal CD is “60nm”

• CD variation model– Assumption: small mean

difference• Group1: N(meanG1=59nm, 3σ=5)• Group2: N(meanG2=61nm, 3σ=5)

• Comparison– {Rise/Fall Delay, Leakage} of

unimodal and bimodal distribution

605954 61

BimodalGroup2

Worst CDBest CD

Unimodal

56 64 66

6nm3σ 60nm,Mean

5nm3σ 61nm, Mean

5nm3σ 59nm, Mean

uniuni

G2G2

G1G1

2n


Path Delay, Leakage (10K MC Iterations)• Bimodal distribution two distinct simulation cases

– DPL1: gate (2i+1) is in Group1 and gate (2i) is in Group2– DPL2: gate (2i+1) is in Group2 and gate (2i) is in Group1

Delay (mean)

4.65E-11

4.70E-11

4.75E-11

4.80E-11

4.85E-11

4.90E-11

4.95E-11

5.00E-11

DPL1 DPL2 DPL1 DPL2

Bimodal Unimodal Bimodal Unimodal

Delay (sigma)

0

5E-13

1E-12

1.5E-12

2E-12

2.5E-12

DPL1 DPL2 DPL1 DPL2


Leakage (mean)

0.00E+00

1.00E-08

2.00E-08

3.00E-08

4.00E-08

5.00E-08

DPL1 DPL2 DPL1 DPL2


Leakage (sigma)

0.00E+00

5.00E-07

1.00E-06

1.50E-06

2.00E-06

DPL1 DPL2 DPL1 DPL2


risefall

risefall

Input 1Input 0

Input 1Input 0

• Unimodal representation is too pessimistic• Different characteristics of DPL1 and DPL2 coloring affects timing


Severe Methodology Implications

• Pervasive design flow changes– SPICE modeling to capture bimodal distribution ?– Cell characterization: multiple timing libraries for DPL1,

DPL2 ?– Timing modeling based on actual placement and DPL mask

coloring of each cell ?– New spatial correlation modeling (intra-exposure, transistor-

level) ?

• Note:– Path delay variation may actually decrease, but this cannot

be exploited due to loss of spatial correlations


Outline






1. Power-Limited Frequency Roadmap• Power, thermal limits to maximum clock frequency (UCSD 2007)

– ITRS MPU (HP) frequency roadmap updated in 2007

• Ripple effect relaxed lithography CD 3 requirement ?

FrequencyRequirement

IntrinsicDelay (CV/I)Requirement

PhysicalLgate

Requirement

CD ControlRequirement

~1.6 per node(based on device enhancement)

1.25per node(to meet power requirement)

0

20

40

60

80

100

1202

00

7

20

09

20

11

20

13

20

15

20

17

20

19

20

21

Year

Fre

qu

enc

y (G

Hz) ITRS 2005 ITRS 2007


2. Design Awareness: Slack

• Positive timing slack can be exploited to reduce power and relax RET, litho requirements

CLKSlack = Trequired – Tarrival

1

1

1

1

2

2

1

2

CLK

1

1

1

2

5

7

3

4

7

4

2

2

1

5

53

Tarrival

Trequired

+2

+1

+2

0

0 0

0

0

-

-

-

-

-

-

-

-

Gates of positive-slack

cells can have larger

CD variation budget!


Design Awareness: Redundancy

Redundant Via Non-Tree Routing(Loop)

Metal Dummy Fill

• Redundant features require less pattern fidelity• Implications

– RET complexity, inspection + defect disposition flows– Reduced impact of process variability on design


3. “Design For Equipment”• Systematic variation impacts Mitigate or Exploit

– OPC + fracturing: Major field, subfield boundary aware?– Overlay error: x- vs. y-direction bias of correction depending on circuit and layout?– Other: Model-based OPC error, CMP pattern-dependence

• Two directions for optimization– Given cell placement, optimize the dose map– Given dose map, optimize the placement

• Idea– Increase dose for timing-critical device more speed– Decrease dose for non-critical device less leakage

• Example: ASML DoseMapper– APC: global CD uniformity in step-and-scan tool


ASML DoseMapper

• DoseMapper– Adjust exposure dose to improve CDU– Compensate ACLV and AWLV

• Unicom (slit direction)– Change intensity profile across slit – Actuator: variable-profile gray filter– Maximum correction range: +/- 5%

• Dosicom (scan direction)– Change intensity profile along scan direction– Dose profile can have higher-order corrections– Maximum correction range: +/- 5%

• Dose Sensitivity– Linewidth has approximately linear relationship

with exposure dose– E.g., dose sensitivity (DS): -2nm / %

Adjust exposure dose

Slit and Scan directions

Scan Direction

Slit profile


Placement-Aware Dose Map

• Same target CD for all devices• Leaves parametric yield

improvement on the table• No “design awareness’’

UCSD (2007): different CDsTraditional: same CDs

• Setup-timing critical device larger dose faster switching

• Hold-timing critical device smaller dose less leakage

• Improve timing yield without leakage penalty


Dose Map-Aware Placement

• Given a dose map and a placement, swap critical cells to high-dose regions and non-critical cells to low-dose regions

• Heuristic priorities based on (1) number of critical paths passing through cell, and (2) slacks of critical paths

path P2

Dose (D1)

Dose (D2)

path P1

Before Cell-Swapping

path P2

D1

D2

path P1

After Cell-Swapping

Dose: D1<D2, Timing Criticality: P1>P2


Example DoseMap Result (UCSD 2007)

• Test case: TSMC90, ~20K standard cells• DoseMap Optimization: 9.3% cycle time improvement (0.13% leakage increase)

– Essentially: near-maximum frequency gain, zero leakage penalty• DoseMap Optimization + dosePlace: 9.6% cycle time (0.2% leakage)

Dose optimization results with different grids

Nom Lgate

20 x 20 20 x 50

DMopt imp. (%) DMopt imp. (%) DMopt imp. (%)

MCT (ns) 1.844 7.331 1.810 9.048 1.805 9.327

2430.2 2626.2 -8.066 2527.9 4.020 2433.6 0.138

Runtime (s)

-- 35.5 47.6 142.0

10 x 10

1.990

Pleakage

(µW)

Need roadmap of enablement


Outline






Why A Shared Roadmap?

• Process: changes what is possible• Design: realizes what is possible• Neither by itself guarantees market success of ICs

• If either is too risky or expensive neither wins

48% CAGR Performance

More Than Moore:ITRS Consumer Stationary Driver

Nor

mal

ized

pe

rfor

man

ce

200

6

200

8

201

0

201

2

201

4

201

6

201

8

202

0

30% CAGR# cores

14-17% CAGR Device speed

1

10

100

1000

If we do not hang together, we will surely hang separately

-- Benjamin Franklin

– Embedded software– Architecture– Stacked integration– …– “Dark Future” (2000 Japan DA Show keynote): electronics

industry finds workarounds for both process and design


Goal: Principled Connections

• Example: Line End Taper

• Balanced technology requirements• Balanced R&D investments “Shared Red Bricks”

Litho and RET metrics

Electrical and Design metrics

Layout practices and design rules


Worst DOF

(b) Slope

(c) Bulge

(a) Typical

Moderate

(d) Asymmetry

Best DOF

Active

Poly

Aggressive

Which Shape Is Best For Design?


Line-End Tapering

• Tapering– A gradual lessening of width towards one end – We use the word “taper(ing)” to describe the shape

of a polysilicon line-end

LW0

LEG

Line-End Shortening

Line-End Bridging

• Traditional Taper MetricMake as rectangular as possible, meeting line-end

gap (LEG) and line-width (LW0) rules


Superellipse-Based Shape Model • “Academic” basis for shape modeling (UCSD 2007)

• Superellipse

• Parameters of superellipse– LEE: b’= b-c+k– a: gate length = size of 2*a– n: ‘roundness’ of superellipse– k: shift in y-direction (Bulge)– : rotation (Asymmetry)

1

nn

cb

ky

a

x

b

x

y

Diffusion

Gate

b’

x

y

ko

o

(a) Bulge (b) Asymmetry

c

a

a


Electrical Impact of Line-End Extension

• Line-end extension increases Cg

– fringe capacitance between line-end extension and channel

Cg

Vth

BfbV 2

Increasing LEE

Increasing Field

misalignment

• Cg affect Vth, following Vth model equation.– Cg increase Vth decrease– Cg decrease Vth increase

• Misalignment error can make large difference in Ion and Ioff

• Ion and Ioff are functions of Vth

– Vth increase Ion, Ioff decrease– Vth decrease Ion, Ioff increase


Capacitance Modeling of LEE

• LEE makes fringing fields to the channel– Fringing field weakens as distance increases

taperchannelgate CCC

Poly

Active

3D view Side view

Active

Oxide

ti

tox

li

Ctaper,i

Cedge

,1

,

N

iitaperedgetaper CCC

nomedge

nn

ii

i

iiitaper

L

lC

cb

khal

h

tlC

0

/1

,

12

hi

Gate on channel Gate on LEE

Poly


Location-Based Current Model

• LEE affects current (Ion and Ioff) at gate edge– As LEE area increases, current at gate edge increases

sharply. Increase depends on Ctaper

80nm fixed

Varied:10, 40, 60nm 70nm fixed

80nm fixedDiffusion

Diffusion

Gate

2.20E+07

2.30E+07

2.40E+07

2.50E+07

2.60E+07

2.70E+07

1 4 7 10 13 16 19 22 25 28 31 34 37 40 43 46 49 52 55

60nm 40nm 10nm

distancetaperon eCi

* From DaVinci)( _ toptaperCi

channel

0

i

Incremental current due to top LEE

i

channel

0

)( _bottomtaperCi

Incremental current due to bottom LEE

+ +i

0

0i

channelCurrent without LEE effect0

bottomtapertoptaper CiCiii __0

measure

N

smodel IsiI 1

0i

channel

i

s=1s=2

s=3 … s=Ns=N-1

…


Electrical Difference Geometric Difference

• Must consider electrical impact of shape

• Lithographers prefer rectangular shapes with sharp edges

• This comes at cost of litho + RET complexity

• Is there a sweet spot?

Small ‘n’

Large ‘n’

Drawn Gate

b

x

y

oDiffusion

Gate

Ioff vs. LEE shape

1.40E-10

1.41E-10

1.42E-10

1.43E-10

1.44E-10

1.45E-10

1.46E-10

1.47E-10

1.48E-10

2.5 3.0 3.5 4.0 4.5 5.0

Superellipse Exponent (n)

Ioff

(A

)

0.00

0.50

1.00

1.50

2.00

2.50

3.00

3.50

4.00

4.50

5.00

Ioff

Re

du

ctio

n(%

)Ioff(A)

Ioff Reduction (%)

1

nn

cb

ky

a

x

a


Example: LEE Rule vs. Bitcell Leakage

• LEE shape changes LEE length vs. Ioff relationship• Sweep LEE and ‘n’ of super-ellipse, measure Ioff

4.00E-10

6.00E-10

8.00E-10

1.00E-09

1.20E-09

1.40E-09

1.60E-09

1.80E-09

2.00E-09

100 90 80 70 60 50 40 30 20

LEE (nm)

Ioff

(A)

0

2

4

6

8

10

12

14

Are

a R

ed

uct

ion

(%

)

n=2.5

n=3.0

n=3.5

n=4.0

n=4.5

n=5.0

Area Reduction (%)

Based on taper shape, LEE can beoptimized to reduce bitcell size

Small ‘n’

Large ‘n’a b c1 d d

c2

e

c2 d

b c3 f

f c3

b

b dh

ha

aac1 bg

gPG

PD

PU

Small ‘n’

Large ‘n’

Poly

Diffusion NWell

ContactPoly

Diffusion NWell

Contact


Summary

• Two Cultures, Two Roadmaps– Increasingly linked

• Lithography changes the Design roadmap– Inevitable RDRs: sooner than later– DPL: new layout and analysis technology requirements

• Design changes the Lithography roadmap– Macro effects: frequency Lgate 3– Design awareness– Design for Equipment

• Toward a shared Litho-Design roadmap– Compelling motivation: Looming workarounds– Let’s get to work !!!


THANK YOU!


Tearing ITRS-Lithography Roadmap

• CD tolerance is major factor of impacting power/timing variability for 65nm and below

• Developing design methods that overcome variability requires reasonably accurate CD tolerance estimates

• Problem in current ITRS-litho roadmap– No breakdowns for across field, across wafer, across lot, etc– No breakdowns for random, systematic– No breakdowns for detailed systematic factors

• Gate CD control includes errors from all sources due to masks, imperfect OPC, ET/DOF, and resist and all spatial length scales (across field, across wafer, between lots)

• We need to make sure we are being realistic in terms of what tolerances we quote, and what type of layout they are predicted for


ACLV CD Tolerance Factors in Litho Roadmap

• Only ACLV CD tolerance extracted using detrating factor– Set 80% derating factor for ACLV (α=80%, β=10%, λ=10%)

• All tolerance factors are not in roadmap– Litho-roadmap needs to show other systematic factors (proximity, ET/DOF, etc)

222 ALLVAWLVACLVCDVar 22 RandomSystematicACLV

ACLV = Across Chip Linewidth VariationACWV = Across Wafer Linewidth VariationALLV = Across Lot Linewidth Variation

ITRS Factor Derating Factor

Linearity/MTT 12%Visible Uniformity 10%

LER 10%

Overlay 8%

ProximityInvisible ET/DOF 40%

Resist

Mask

ITRS Factor

Linearity/MTT SystematicVisible Uniformity Systematic

LER Random

Overlay Random

Proximity SystematicInvisible ET/DOF Systematic

Resist Systematic

Mask Systematic


Extract CD Tolerance from Litho Roadmap

• Systematic/random variations are divided• Each factor is divided by the derating factor

– help designer who tries to reduce CD tolerance of each factor

% of physical gate length 8 8 8 8 8 8 9 9 8

2005 2006 2007 2008 2009 2010 2011 2012 2013Table 69aMPU gate length (nm) 32 28 25 23 20 18 16 14 13Table 77aLER (3 sigma) (nm) 4.2 3.8 3.4 3 2.7 2.4 2.1 1.9 1.7Table 78aGate CD control (3 sigma) (nm) 3.3 2.9 2.6 2.3 2.1 1.9 1.7 1.5 1.3Overlay (3 sigma) (nm) 15 13 11 10 9 8 7 6 6Mask magnification 4 4 4 4 4 4 4 4 4MEEF - isolated lines 1.4 1.4 1.6 1.8 2 2.2 2.2 2.2 2.2CDU - isolated (3 sigma) (nm) 3.8 3.4 2.6 2.1 1.7 1.3 1.2 1.1 1MEEF - dense lines 2 2 2.2 2.2 2.2 2.2 2.2 2.2 2.2CDU - dense (3 sigma) (nm) 7.1 6 4.8 4.3 3.8 3.4 3 2.7 2.4Linearity (nm) 13 11 10 9 8 7.2 6.4 5.6 5.1CD mean to target (nm) 6.4 5.6 5.2 4.6 4 3.6 3.2 2.8 2.6CalculationsCDU - isolated lines (3 sigma) (nm) 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1CDU- dense (3 sigma) (nm) 0.4 0.3 0.3 0.2 0.2 0.2 0.2 0.1 0.1Linearity + mean to target (nm) 0.6 0.5 0.5 0.4 0.4 0.3 0.3 0.3 0.2derated overlay (3 sigma) (nm) 1.2 1.0 0.9 0.8 0.7 0.6 0.6 0.5 0.5mask/proximity/exposure/DOF/resist 2.2 2.0 1.8 1.6 1.4 1.3 1.2 1.0 0.9rss of the systematic numbers (nm) 2.3 2.0 1.9 1.6 1.5 1.4 1.2 1.1 0.9plus the random variations (nm) 2.6 2.3 2.

11.8 1.7 1.5 1.4 1.2 1.0

LGATE Tolerance Computation from 2005 ITRS


Require More Metrics in ITRS DFM Roadmap

• Lithography (DPL)– Difference of mean – CD variability for each

process– Vth variability for each

process• Other metric for design

– % area of redundancy circuit– Variability of difference

between low- and high-Vth • DFM Tool

– Requires DFM tool metric– Accuracy should be

supported by ITRS-Modeling – Fast simulation in circuit level

is also required as well as accuracy

AccuracyCD (photo/etch) prediction

Process Junction depthTopography estimation

Ion/Ioff accuracyDevice Long-channel Vt

Vt rolloffCircuit delay

Circuit I-V errorParasitic C-V

DFM Roadmap

Modeling Roadmap


Guardbands: Inevitable? At What Cost?

• Process change: O(weeks)• Design change: O(days-months)

– But takes O(months) to assess in silicon

• Design tweak to fit process : impossible• Process tweak to fit design : what we do today• SPICE, RCX models are fixed guardbands

inevitable

• What is the cost of guardbands to the design?

Pe

rfo

rma

nc

e

Technology Node


Timing and Leakage Optimization Flow

• Dose Map opt– Input– Coeff calibration– Timing analysis– Dose map opt– Optimal dose map

• Placement opt– Update design– Timing analysis– Critical path

identification– Dose-aware place– Legalization– ECO routing

Design TimingAnalysis

Dose mapOpt. Delay

Cell Library

OriginalDose map

TimingAnalysis

Critical path

OptimalDose map

Updateddesign

Optimizeddesign

PlacementOpt.

Dose Map

Placement

Lithography and Design in Partnership: A New Roadmap Andrew B. Kahng UCSD Depts. of CSE and ECE...

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Transcript of Lithography and Design in Partnership: A New Roadmap Andrew B. Kahng UCSD Depts. of CSE and ECE...