Library description y 05/2014 Block for monitoring 24V DC ...

http://support.automation.siemens.com/WW/view/en/61450284

Library description 05/2014

Block for monitoring 24V DCload circuitsS7-300/400, SITOP PSE200U with single –channel signaling,STEP 7 V12 SP1


Warranty and liability

Block for monitoring 24V DV load circuitsEntry-ID: 61450284, V1.1, 05/2014 2

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Warranty and liability

Note The Application Examples are not binding and do not claim to be completeregarding the circuits shown, equipping and any eventuality. The ApplicationExamples do not represent customer-specific solutions. They are only intendedto provide support for typical applications. You are responsible for ensuring thatthe described products are used correctly. These application examples do notrelieve you of the responsibility to use safe practices in application, installation,operation and maintenance. When using these Application Examples, yourecognize that we cannot be made liable for any damage/claims beyond theliability clause described. We reserve the right to make changes to theseApplication Examples at any time without prior notice.If there are any deviations between the recommendations provided in theseapplication examples and other Siemens publications – e.g. Catalogs – thecontents of the other documents have priority.

We do not accept any liability for the information contained in this document.

Any claims against us – based on whatever legal reason – resulting from the use ofthe examples, information, programs, engineering and performance data etc.,described in this Application Example shall be excluded. Such an exclusion shallnot apply in the case of mandatory liability, e.g. under the German Product LiabilityAct (“Produkthaftungsgesetz”), in case of intent, gross negligence, or injury of life,body or health, guarantee for the quality of a product, fraudulent concealment of adeficiency or breach of a condition which goes to the root of the contract(“wesentliche Vertragspflichten”). The damages for a breach of a substantialcontractual obligation are, however, limited to the foreseeable damage, typical forthe type of contract, except in the event of intent or gross negligence or injury tolife, body or health. The above provisions do not imply a change of the burden ofproof to your detriment.

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Table of contents


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Table of contentsWarranty and liability ................................................................................................... 2

1 Overview of the Library ..................................................................................... 4

1.1 Different user scenarios ....................................................................... 51.2 Block diagram ....................................................................................... 61.3 Hardware and software requirements .................................................. 71.4 Library resources .................................................................................. 7

2 Blocks of the Library ......................................................................................... 8

2.1 List of the blocks ................................................................................... 82.2 Explanation of the blocks ................................................................... 102.2.1 PSE_DIAG (FB50) block .................................................................... 10

3 Working with the Library................................................................................. 15

3.1 Integrating the library into STEP 7 ..................................................... 15Opening the SITOP_Library_V12_S7-300_S7-400 ........................... 15

3.2 Integrating the library blocks into the STEP 7 project ........................ 173.3 Downloading the blocks to the S7 CPU ............................................. 223.4 Using the library with STEP 7 V13 (TIA Portal).................................. 28

4 Notes and Support ........................................................................................... 31

5 References ....................................................................................................... 33

6 Glossary ........................................................................................................... 33

7 History............................................................................................................... 33

1 Overview of the Library1.1 Different user scenarios


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1 Overview of the LibraryWhat you get

This document describes the SITOP_Library_V12_S7-300_S7-400. The blocklibrary provides you with the tested code with clearly defined interfaces. They canbe used as a basis for your task to be implemented.The main focus of this document is to describe all blocks of the block library the functionality implemented through these blocks

Furthermore, this documentation shows possible fields of application and helps youintegrate the library into your STEP 7 project using step-by-step instructions.

1 Overview of the Library1.1 Different user scenarios


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1.1 Different user scenarios

Possible fields of application for using the PSE_DIAG (FB50) block of theSITOP_Library_V12_S7-300_S7-400

The SITOP PSE200U electronic selectivity module is designed to be connected toa stabilized 24 V DC power supply with an output current up to 40 A. The SITOPPSE200U allows the 24 V DC output voltage generated by a stabilized powersupply to be split between four load circuits. For each output, the rated current canbe set individually with a potentiometer in the range from 0.5 A to 3 A or in therange from 3 A to 10 A, depending on the type. When the rated current isexceeded, the output will be disabled after a certain period of time and can bere-enabled using buttons or remote reset after a waiting time.The states of all four load circuits are serially coded via the STATE output of thePSE200U module with single-channel signaling.The PSE_DIAG (FB50) block of the SITOP_Library_V12_S7-300_S7-400evaluates the serial code of the STATE output in the S7-300 CPU or S7-400 CPU.

The following section shows a scenario for the possible use of the PSE_DIAG(FB50) block of the SITOP_Library_V12_S7-300_S7-400:

ScenarioVia a digital input module, the signal of the STATE output is read in and evaluatedby the S7-300 CPU. This allows you to monitor the state of channels OUT 1 toOUT 4 in the user program of the CPU.The S7-300 CPU detects, for example, if the motor connected to load circuit OUT 1has generated an overload.The S7-300 CPU detects, for example, if the lighting connected to load circuitOUT 2 has caused a short circuit.

Figure 1-1

M

Remote ResetSTATE

OUT 1

OUT 2

S7-300PS CPU DI

+ -

DC

24V

PSE200U

1 Overview of the Library1.2 Block diagram


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1.2 Block diagram

The figure below shows the schematic sequence of the function.The STATE output of the PSE200U module with single-channel signaling providesa signal that serially codes the states of all four outputs OUT 1 to OUT 4.To evaluate the signal of the STATE output, call the PSE_DIAG (FB50) block in theuser program of the CPU. At its output, the PSE_DIAG (FB50) block indicates thestate of the four outputs.

Figure 1-2

PSE 200U

S

S7-300 CPU

0 0 11

OUT 4OUT 3OUT 2OUT 1

OUT1

PSE_DIAGOUT2OUT3OUT4

„1“„1“„0“„0“

1 Overview of the Library1.3 Hardware and software requirements


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1.3 Hardware and software requirements

Requirements for this libraryTo be able to use the functions of the library described in this document, thefollowing hardware and software requirements must be met:

HardwareTable 1-1

No. Component Order no. Qty. Alternative

1 SIMATIC S7 CPU E.g., CPU 315-2 PN/DP 1 Any S7-300/400 CPU2 DI 8 / DO 8 6ES7323-1BH01-0AA0 13 SITOP PSE200U 3A 6EP1961-2BA31 1 SITOP PSE200U 10A,

order no. 6EP1961-2BA41

SoftwareTable 1-2

No. Component Order no. Qty.

1 STEP 7 V12 SP1 Upd4 configuration software 6ES7822-1AA02-0YA5 1

1.4 Library resources

What will you find in this section?The following section gives you an overview of the size of the blocks of theSITOP_Library_V12_S7-300_S7-400 in the work memory.

Note You can change the object names of the blocks. In this case, you have to modifythe symbolic names of these blocks in the symbol table.

Overall sizeThe overall size of all blocks of the SITOP_Library_V12_S7-300_S7-400 in thework memory is 4682 bytes (4.68 Kbytes).

Size of the individual blocksTable 1-3

Block Symbol Size in main memory

FB50 PSE_DIAG 2780 bytesDB iDB_PSE_DIAG 286 bytesFC14 GT_DT 338 bytesFC34 SB_DT_DT 1278 bytes

TON -RD_SYS_T -

2 Blocks of the Library2.1 List of the blocks


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2 Blocks of the LibraryWhat will you find in this section?

This chapter lists and explains all blocks of theSITOP_Library_V12_S7-300_S7-400. Before that, however, you are informed ofthe blocks that are essentially involved in the implementation of the functions.

2.1 List of the blocks

The following table lists all blocks of the library.Table 2-1

Block Symbol Classification Description

FB50 PSE_DIAG In-house development The function block evaluates thesignal of the STATE output of thePSE200U.

DB50 iDB_PSE_DIAG Instance DB of the PSE_DIAG(FB50) block

The inputs, outputs and staticvariables of the PSE_DIAG (FB50)block are stored in this data block.

FC14 GT_DT Relational expressions Comparing time valuesIn the PSE_DIAG (FB50) block,relational expressions are used tocompare the contents of twovariables of the date and time typeto see which is larger.When compiling the software, theFC14 “GT_DT” function isautomatically created in thefollowing folder: “Program blocks >System blocks > Programresources”.

FC34 SB_DT_DT Instruction T_DIFF from the“Instructions" task card >“Extended Instructions” palette >“Date and time-of-day”

Calculating the time differenceThe function subtracts two times(DT format) and provides a periodas a result (TIME format).The instruction T_DIFF isinternally called in the PSE_DIAG(FB50) block.When compiling the software, theFC34 “SB_DT_DT” function isautomatically created in thefollowing folder: “Program blocks >System blocks > Programresources”.

TON “Instructions” task card > “BasicInstructions” palette> “Timeroperations”

Generating an on-delay timerThe instruction TON is internallycalled in the PSE_DIAG (FB50)block.

RD_SYS_T “Instructions” task card >“Extended Instructions” palette >“Date and time-of-day”

Reading the timeThe instruction RD_SYS_T isinternally called in the PSE_DIAG(FB50) block.

2 Blocks of the Library2.1 List of the blocks


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Note The instance DB of the PSE_DIAG (FB50) block is generated when thePSE_DIAG (FB50) block is called.

2 Blocks of the Library2.2 Explanation of the blocks


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2.2 Explanation of the blocks

This chapter explains the PSE_DIAG (FB50) block which is part of theSITOP_Library_V12_S7-300_S7-400.

2.2.1 PSE_DIAG (FB50) block

FigureFigure 2-1

Principle of operation of the PSE_DIAG (FB50) blockVia the IMPULSE input, the PSE_DIAG (FB50) block reads in the STATE output ofthe PSE200U module with single-channel signaling to evaluate the signalsequence of the STATE output and indicate the state of outputs OUT 1 to OUT 4 ofthe PSE200U module with single-channel signaling at the CHANNEL_STATEoutput of the PSE_DIAG (FB50) block.One frame of the signal consists of one start bit and four channel bits, eachseparated by a pause bit. The start bit is always “1” and the pause bits are always“0”. The channel bits signal the state of channels OUT 1 to OUT 4.Figure 2-2 shows the signal sequence of the STATE output of the PSE200Umodule with single channel message.



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Figure 2-2

START START

Sta

teO

UT

1

Sta

teO

UT

2

Sta

teO

UT

3

Sta

teO

UT

4

C1 P P P P

State

P C2 C3 C4‘1’

‘0’t

2750 ms

Principle of operation of the SITOP PSE200U module with single channel messageTable 2-2 shows which status causes channels OUT 1 to OUT 4 to go to the “1” or“0” state.

Table 2-2

Status LED of the PSE200U State OUT1 to OUT4

Device starting up, supply voltage missing Off 0Output enabled Green 1Output current > rated current Flashing green 1Output was automatically disabled Red 0Automatic disable can be reset Flashing red 0Output manually disabled Flashing orange 0Output defective (internal fuse has tripped) Off 0Device over temperature Red running light 0

Function characteristicsFigure 2-3 provides a graphical representation of the functional sequences of thePSE_DIAG (FB50) block.

Figure 2-3

IMPULSE

BUSY

DONE

C4 START C1 C2 C3 C4 START C1 C2 C3 C4 START C1

Reaction of the block


Signal of the STATEoutput of the PSE

Frame 1 Frame 2

Decoding Decoding



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Fehler! Verweisquelle konnte nicht gefunden werden. provides a graphicalrepresentation of the functional sequences of the PSE_DIAG (FB50) block in caseof an error, e. g. if the PSE200U module is defective and does not provide a signalat the STATE output. Therefore, a signal change does not occur at the IMPULSEinput of the PSE_DIAG (FB50) block. If a signal change does not occur for morethan 6 seconds, the ERROR output will be set to TRUE for one cycle and the value16#8002 will be output at the STATUS output. As long as the PSE_DIAG (FB50)block does not detect a signal change at the IMPULSE input, the ERROR outputwill be set to TRUE for one cycle and the value 16#8002 will be output at theSTATUS output every 6 seconds.

Figure 2-4

IMPULSE

ERROR

STATUSReaction of the block


Signal of the STATEoutput of the PSE

6 sec

BUSY

Remedy, e. g.replace PSE200U

16#8002


16#000016#0000

Call environment of the PSE_DIAG (FB50) blockThe PSE_DIAG (FB50) block must be called cyclically. This can be done either inOB1 or alternatively in a time interrupt OB.

Note The maximum cycle time of OB1 or the time interrupt OB is 100 ms. If the cycletime exceeds 100 ms, the PSE_DIAG (FB50) block will output an error with thevalue 16#8001 at the STATUS output.



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InputsTable 2-3

Parameter Data type Description

IMPULSE BOOL Input via which the signal of the STATE output of the PSE isread in.Figure 2-2 shows the time sequence of the signal as anexample.

COM_RST BOOL When there is a positive edge, a reset will be triggered. Allparameters (static variables and outputs of the PSE_DIAG(FB50) block) will be reset.

OutputsTable 2-4

Parameter Data type Description

DONE BOOL TRUE if a frame was evaluated completely and withouterrors and the state of outputs OUT 1 to OUT 4 of thePSE200U module with single channel message is displayedat the CHANNEL_STATE output of the PSE_DIAG (FB50)block.Set to TRUE for only one cycle.

BUSY BOOL TRUE if the PSE_DIAG (FB50) block is active.Set to FALSE if a message was successfully evaluated andthe data of the CHANNEL_STATE output can be accepted.

CHANNEL_STATE BYTE State of channels OUT 1 to OUT 4Bit 0 = 1, if channel OUT 1 has the state 0Bit 0 = 0, if channel OUT 1 has the state 1Bit 1 = 1, if channel OUT 2 has the state 0Bit 1 = 0, if channel OUT 2 has the state 1Bit 2 = 1, if channel OUT 3 has the state 0Bit 2 = 0, if channel OUT 3 has the state 1Bit 3 = 1, if channel OUT 4 has the state 0Bit 3 = 0, if channel OUT 4 has the state 1Bit 4: Not assignedBit 5: Not assignedBit 6: Not assignedBit 7: Not assignedTable 2-2 shows an overview of possible channel states.

STATUS WORD Status if ERROR=TRUESet to TRUE for only one cycle.

ERROR BOOL TRUE, if an error occurs when executing the routine.Set to TRUE for only one cycle.Default value: FALSE



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Status and error displaysTable 2-5

Status Meaning Remedy / notes

16#8001 Cycle time of 100 ms exceeded Call the PSE_DIAG (FB50) block in the timeinterrupt OB with a cycle time of max.100ms.

16#8002 No signal change was detected at theIMPULSE input for at least 6s.

Check if the STATE output of the PSE200Umodule with single-channel signaling isconnected to the digital input module.Check if the power supply is connected tothe PSE200U module with single-channelsignaling.

3 Working with the Library3.1 Integrating the library into STEP 7


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3 Working with the LibraryWhat will you find in this section?

This chapter consists of instructions for integrating theSITOP_Library_V12_S7-300_S7-400 into your STEP 7 project and instructions forusing the library blocks.

3.1 Integrating the library into STEP 7

The table below lists the steps for integrating theSITOP_Library_V12_S7-300_S7-400 into your STEP 7 project. After integratingthe library, you can use the blocks of the SITOP_Library_V12_S7-300_S7-400.

Note The following section assumes that a STEP 7 project exists.

Table 3-1

No. Action

1. The library is available on the HTML page from which you downloaded this document. Savethe library “61450284_SITOP_Library_S7-300_400_STEP7_V12_CODE.zip” to your harddisk.

2. Unzip the library.3. Once you have unzipped the library, open it in STEP 7 V12.

RequirementThe “Libraries” task card is displayed.

Opening the SITOP_Library_V12_S7-300_S7-400To open the SITOP_Library_V12_S7-300_S7-400, proceed as follows:

3 Working with the Library3.1 Integrating the library into STEP 7


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Table 3-2

No. Action

1. In the “Global libraries” palette in the toolbar, click on “Open global library” or in the “Options”menu, select the “Global libraries > Open library” command.The “Open global library” dialog box opens.

2. Select the following global library: SITOP_Library_V12_S7-300_S7-400. You can identify thelibrary file by the file name extension “al12”.Click on the “Open” button.

3 Working with the Library3.2 Integrating the library blocks into the STEP 7 project


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No. Action

3. The SITOP_Library_V12_S7-300_S7-400 is opened and inserted into the “Global libraries”palette.

3.2 Integrating the library blocks into the STEP 7 project

The table below lists the steps for integrating the blocks of theSITOP_Library_V12_S7-300_S7-400 into your STEP 7 project.



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Table 3-3

No. Action

1. After the SITOP_Library_V12_S7-300_S7-400 has been opened, you open your STEP 7 project.2. In the “Master copies” folder of the SITOP_Library_V12_S7-300_S7-400, you will find all elements

listed in Table 2-1.

3. Use the drag & drop function to insert the blocks of the SITOP_Library_V12_S7-300_S7-400 intothe “Program blocks” folder of your device, for example the S7-300 CPU.



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No. Action

4. In the Project tree, open the time interrupt OB (OB35) in the “Program blocks” folder of yourdevice, for example the S7-300 CPU. Now use the drag & drop function to move the PSE_DIAG(FB50) block from the Project tree to any network of the time interrupt OB (OB35).

5. Enter the name and number of the associated instance data block. Exit the dialog box with “OK”.



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No. Action

6. Open the newly generated instance data block and disable the “Retain” option for all variables ofthe instance DB. This overwrites the variables of the instance DB with the defined initial valueswhen the CPU is restarted.

7. Assign values to all necessary formal parameters.

8. Save the project.



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No. Action

9. In the Project tree, right-click on the device, for example the S7-300 CPU, and select the “Compile> Software (rebuild all blocks)” context menu. All blocks of the user program are compiled.

3 Working with the Library3.3 Downloading the blocks to the S7 CPU


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3.3 Downloading the blocks to the S7 CPU

The table below lists the steps for downloading all blocks of your user program tothe S7 CPU.

Downloading via TCP/IPIf your S7 CPU has an integrated PROFINET interface or your S7 station includesan Industrial Ethernet CP, you can download the blocks to the S7 CPU via TCP/IP.

Table 3-4

No. Action

1. Ensure that your PC/PG and the S7 CPU are located in the same subnet.2. In the Project tree, select the device, for example the S7-300 CPU.

In the toolbar you click on the “Download to device” button to download the hardware configurationand the software to the S7-CPU.The “Extended download to device” or “Load preview” dialog box opens automatically.



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No. Action

3. The “Extended download to device” dialog box opens automatically only if the access path from thePG/PC to the S7-300 CPU has to be set.In the “Extended download to device” dialog box, make the following settings to access theS7-300 CPU via TCP/IP: Type of the PG/PC interface: PN/IE PG/PC interface: Network card of the PG/PC

In “Compatible devices in target subnet”, the S7-300 CPU is shown with its IP address or theIndustrial Ethernet CP is displayed with its IP address.Select S7-300 CPU or the Industrial Ethernet CP and click on the “Load” button.



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No. Action

4. In the “Load preview” dialog box, click on the “Load” button to start loading.

5. In the “Load results” dialog box, click on the “Finish” button to finish loading.

Downloading via MPIYou can also download the blocks to the S7 CPU via the MPI or MPI/DP interface.



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Table 3-5

No. Action

1. Use a PROFIBUS bus cable or an MPI cable to connect the PC/PG to the MPI or MPI/DP interfaceof the S7 CPU.

2. In the Project tree, select the device, for example the S7-300 CPU.In the toolbar you click on the “Download to device” button to download the hardware configurationand the software to the CPU.The “Extended download to device” or “Load preview” dialog box opens automatically.



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No. Action

3. The “Extended download to device” dialog box opens automatically if the access path from thePG/PC to the S7-300 CPU has to be set.In the “Extended download to device” dialog box, make the following settings to access theS7-300 CPU via MPI: Type of the PG/PC interface: MPI PG/PC interface: PROFIBUS PC CP, e. g. CP5611

In “Compatible devices in target subnet”, the S7-300 CPU is displayed with its MPI address.Select the S7-300 CPU and click on the “Load” button.



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No. Action

4. In the “Load preview” dialog box, click on the “Load” button to start loading.

5. In the “Load results” dialog box, click on the “Finish” button to finish loading.

3 Working with the Library3.4 Using the library with STEP 7 V13 (TIA Portal)


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3.4 Using the library with STEP 7 V13 (TIA Portal)

The table below lists the steps for integrating theSITOP_Library_V12_S7-300_S7-400 which is generated with STEP 7 V12 SP1Upd4, into STEP 7 V13. After integrating the library, you can use the blocks of thelibrary in STEP 7 V13.

Note The following section assumes that a STEP 7 project exists.

Table 3-6

No. Action

1. The library is available on the HTML page from which you downloaded this document. Savethe library “61450284_SITOP_Library_S7-300_400_STEP7_V12_CODE.zip” to your harddisk.

2. Unzip the library.3. Once you have unzipped the library, open it in STEP 7 V13.

RequirementThe “Libraries” task card is displayed.

Open and upgrade the SITOP_Library_V12_S7-300_S7-400 libraryTo open and upgrade the SITOP_Library_V12_S7-300_S7-400, proceed asfollows:



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Table 3-7

No. Action

1. In the “Global libraries” palette in the toolbar, click on “Open global library” or in the “Options”menu, select the “Global libraries > Open library” command.The “Open global library” dialog box opens.

2. Select the following global library: SITOP_Library_V12_S7-300_S7-400. You can identify thelibrary file by the file name extension “al12”.Click on the “Open” button.



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No. Action

3. The following message is opened automatically.Click on the „Yes“ button. The library is upgraded to STEP 7 V13.

4. The upgraded library is opened and inserted into the “Global libraries” palette with a new name:SITOP_Library_V12_S7-300_S7-400_V13.

5. Now you can integrate the blocks of the upgraded librarySITOP_Library_V12_S7-300_S7-400_V13 into your STEP 7 project (see chapter 3.2).

4 Notes and Support


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4 Notes and SupportWhat will you find in this section?

This chapter provides further support for handling the describedSITOP_Library_V11_S7-300_S7-400.

Updating the libraryThe following table lists the steps that show you how to check whether the blocks of the library are up to date and how to integrate a later version of a block from the

SITOP_Library_V11_S7-300_S7-400 into your STEP 7 project.Table 4-1

No. Action

1. Perform the following steps for the PSE_DIAG (FB50) block of the library. In the Project tree, right-click on the PSE_DIAG (FB50) block. In the context menu, select the

“Properties” option. In the displayed “Properties” window, select the “Information” tab. Compare the current version number in the “Version” output field with the latest release from

the Siemens Industry Online Support.

2. To update the blocks of the library in your STEP 7 project, integrate the latest version of theSITOP_Library_V12_S7-300_S7-400 into STEP 7 V12 (see chapter 3.1).

4 Notes and Support


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No. Action

3. In your STEP 7 project, delete the PSE_DIAG (FB50) block of the library in the “Program blocks”folder.Do not delete the function block call in the Main (OB1) block.

4. As described in chapter 3.2 up to step 3, add the latest version of the PSE_DIAG (FB50) blockfrom the SITOP_Library_V12_S7-300_S7-400 into your STEP 7 project.

5 References


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5 ReferencesThe following list is by no means complete and only provides a selection of usefulinformation.Table 5-1

Topic Title

\1\ Reference to thedocument


\2\ Siemens IndustryOnline Support

http://support.automation.siemens.com

\3\ SITOPPSE200U 3A


\4\ SITOPPSE200U 10A


\5\ STEP 7ProfessionalV12 SP1


6 GlossaryTable 6-1

Abbreviation Description

DI Digital input modulePS Power supplyS STATE output of the PSE200U module with single-channel

signaling. The signal of the output is a serial code thatprovides information on the state of outputs OUT 1 to OUT 4of the PSE200U module with single-channel signaling.

7 HistoryTable 7-1

Version Date Modification

V1.0 07/2012 First issueV1.1 05/2014 Update for STEP 7 V12 SP1 Upd4

Add the chapter 3.4


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