LG GT500 GT505 Service Manual

Service Manual

Model : G

T500

Internal Use Only

Service ManualGT500

Date: June, 2009 / Issue 1.0

- 3 -Copyright © 2009 LG Electronics. Inc. All right reserved.

Only for training and service purposes

LGE Internal Use Only

Table Of Contents

1. INTRODUCTION ............................................... 5

1.1 Purpose ......................................................................5

1.2 Regulatory Information .................................................5

2. PERFORMANCE ............................................... 7

2.1 System Overview .........................................................7

2.2 Usable environment .....................................................8

2.3 Radio Performance ......................................................8

2.4 Current Consumption .................................................16

2.5 RSSI .........................................................................16

2.6 Battery Bar ................................................................16

2.7 Sound Pressure Level ................................................17

2.8 Charging ...................................................................18

3. Technical Description .................................. 19

3.1 Digital Baseband (DBB) & Multimedia Processor ..........19

3.2 Visual part .................................................................39

3.3 Audio Part .................................................................47

3.4 GPADC (General Purpose ADC) and AUTOADC2 ...........54

3.5 Charger control .........................................................55

3.6 Voltage Regulation .....................................................61

3.7 RF Technical Description ............................................62

4. TROUBLE SHOOTING ..................................... 73

4.1 Power ON Trouble ......................................................73

4.2 USB Trouble ..............................................................74

4.3 SIM Detect Trouble ....................................................75

4.4 MicroSD card Trouble ................................................76

4.5 Key and Touch Screen Trouble ....................................77

4.6 Camera Trouble .........................................................81

4.7 Main LCD Trouble ......................................................87

4.8 Keypad Backlight Trouble ...........................................90

4.9 Audio Trouble Shooting ..............................................93

4.10 Charger Trouble Shooting .......................................108

4.11 Bluetooth Trouble ...................................................111

4.12 Wi-Fi Trouble .........................................................114

4.13 GPS Trouble ..........................................................116

4.14 RF Component ......................................................119

4.15 Procedure to check ...............................................120

4.16 Checking Common Power Source Block ..................121

4.17 Checking VCXO Block ............................................128

4.18 Checking Front End Module Block ..........................132

4.19 Checking Front End Module Block input logic ..........133

4.20 Checking WCDMA Block ........................................144

4.21 Checking GSM Block .............................................157

5. Download ................................................... 169

5.1 Requirements ..........................................................169

5.2 GT500 / GT505 Download .......................................170

6. Block Diagram ........................................... 178

7. CIRCUIT DIAGRAM ...................................... 179

8. BGA Pin Map .............................................. 189

9. PCB LAYOUT ............................................... 195

10. CALIBRATION ............................................ 203

10.1 General Description ...............................................203

10.2 Environment ..........................................................203

10.3 Calibration Environment .........................................204

10.4 Program Operation ................................................205

11. EXPLODED VIEW & REPLACEMENT

PART LIST ................................................. 211

11.1 EXPLODED VIEW ...................................................211

11.2 Replacement Parts ................................................213

11.3 Accessory .............................................................243




1. INTRODUCTION

1. INTRODUCTION

Copyright © 2008 LG Electronics. Inc. All right reserved. Only for training and service purposes


1.1 Purpose

This manual provides the information necessary to repair, calibration, description and download the features of this model.

1.2 Regulatory Information

A. Security

Toll fraud, the unauthorized use of telecommunications system by an unauthorized part (for example, persons other than your company’s employees, agents, subcontractors, or person working on your company’s behalf) can result in substantial additional charges for your telecommunications services. System users are responsible for the security of own system. There are may be risks of toll fraud associated with your telecommunications system. System users are responsible for programming and configuring the equipment to prevent unauthorized use. The manufacturer does not warrant that this product is immune from the above case but will prevent unauthorized use of common-carrier telecommunication service of facilities accessed through or connected to it.

The manufacturer will not be responsible for any charges that result from such unauthorized use.

B. Incidence of Harm

If a telephone company determines that the equipment provided to customer is faulty and possibly causing harm or interruption in service to the telephone network, it should disconnect telephone service until repair can be done. A telephone company may temporarily disconnect service as long as repair is not done.

C. Changes in Service

A local telephone company may make changes in its communications facilities or procedure. If these changes could reasonably be expected to affect the use of the this phone or compatibility with the network, the telephone company is required to give advanced written notice to the user, allowing the user to take appropriate steps to maintain telephone service.

D. Maintenance Limitations

Maintenance limitations on this model must be performed only by the manufacturer or its authorized agent. The user may not make any changes and/or repairs expect as specifically noted in this manual. Therefore, note that unauthorized alternations or repair may affect the regulatory status of the system and may void any remaining warranty.



1. INTRODUCTION

Copyright © 2008 LG Electronics. Inc. All right reserved. Only for training and service purposes


E. Notice of Radiated Emissions

This model complies with rules regarding radiation and radio frequency emission as defined by local regulatory agencies. In accordance with these agencies, you may be required to provide information such as the following to the end user.

F. Pictures

The pictures in this manual are for illustrative purposes only; your actual hardware may look slightly different.

G. Interference and Attenuation

Phone may interfere with sensitive laboratory equipment, medical equipment, etc.Interference from unsuppressed engines or electric motors may cause problems.

H. Electrostatic Sensitive Devices

ATTENTION

Boards, which contain Electrostatic Sensitive Device (ESD), are indicated

by the sign. Following information is ESD handling:

• Service personnel should ground themselves by using a wrist strap when exchange system

boards.

• When repairs are made to a system board, they should spread the floor with anti-static mat

which is also grounded.

• Use a suitable, grounded soldering iron.

• Keep sensitive parts in these protective packages until these are used.

• When returning system boards or parts like EEPROM to the factory, use the protective

package as described.




2. PERFORMANCE

2. PERFORMANCE

2.1 System Overview

Item Specification

Shape GSM850/900/1800/1900 & WCDMA Band 1, 8 Bar type - Dual Mode Handset

Size 107 x 54.5 x 11.8 mm

Weight 98g (with standard battery)

Power 1000mAh Li-ion

Over 200 Min (WCDMA, Tx=10 dBm, Voice)

Over 200 Min (GSM, Tx=Max, Voice)

Over 300 hrs (WCDMA, DRX=7)

Over 300 hrs (GSM, Paging period=5)

Antenna Intenna type

Main LCD 3"(400x240), 262K TFT Color LCD

Main LCD BL White LED Backlight

Vibrator Yes (Coin Type)

Speaker Yes

MIC Yes (SMD Type)

Receiver Yes

Earphone Jack Yes

SIM Socket Yes(SIM Block Type) : 3.0V & 1.8V

Volume Key Push Type ( + , - )

Camera Key Push Type

External Memory Micro SD Socket

I/O Connect 5 Pins

Talk Time

Standby Time



2. PERFORMANCE

2.2 Usable environment

1) Environment

2) Environment (Accessory)

* CLA : 12~24V (DC)

2.3 Radio Performance

1) Transmitter – GSM Mode

Item Spec. Unit

Voltage 3.7 (Typ), 3.4 (Min), (Shut Down: 3.2) V

Operating Temp. -20 ~ + 60 °C

Storage Temp. -30 ~ + 85 °C

Humidity max. 85 %

Item Spec. Min Typ. Max Unit

Power Available power 100 220 240 Vac

No

9k ~ 1GHz -39dBm

1G ~ 1710MHz -33dBm

1710M ~ 1785MHz -39dBm

1785M ~ 12.75GHz -33dBm

100k ~ 880MHz -60dBm 100k ~ 880MHz -60dBm

880M ~ 915MHz -62dBm 880M ~ 915MHz -62dBm

915M ~ 1000Mz -60dBm 915M ~ 1000MHz -60dBm

1G ~ 1.71GHz -50dBm 1G ~ 1.71GHz -50dBm

1.71G ~ 1.785GHz -56dBm 1.71G ~ 1.785GHz -56dBm

1.785G ~ 12.75GHz -50dBm 1.785G ~ 12.75GHz -50dBm

Item

1

DCS/PCSGSM

ConductedSpuriousEmission

-39dBm

-33dBm

MS allocatedChannel

100k ~ 1GHz

Idle Mode

1G ~ 12.75GHz




2. PERFORMANCE

No

30M ~ 1GHz -36dBm

MS allocated 1G ~ 1710MHz -30dBm

Channel 1710M ~ 1785MHz -36dBm

Radiated 1785M ~ 4GHz -30dBm

Spurious 30M ~ 880MHz -57dBm 30M ~ 880MHz -57dBm

Emission 880M ~ 915MHz -59dBm 880M ~ 915MHz -59dBm

Idle Mode 915M ~ 1000Mz -57dBm 915M ~ 1000MHz -57dBm

1G ~ 1.71GHz -47dBm 1G ~ 1.71GHz -47dBm

1.71G ~ 1.785GHz -53dBm 1.71G ~ 1.785GHz -53dBm

1.785G ~ 4GHz -47dBm 1.785G ~ 4GHz -47dBm

2

0 ~ 100kHz +0.5dB 0 ~ 100kHz +0.5dB

200kHz -30dB 200kHz -30dB


Due to 400kHz -60dB 400kHz -33dB

Output RF modulation 600 ~ 1800kHz -66dB 600 ~ 1800kHz -60dB

Spectrum 1800 ~ 3000kHz -69dB 1800 ~ 6000kHz -60dB

3000 ~ 6000kHz -71dB ≥6000kHz -73dB

≥6000kHz -77dB



1200kHz -21dB 1200kHz -24dB

1800kHz -24dB 1800kHz -27dB

1

DCS/PCSGSM

-36dBm

-30dBm

30M ~ 1GHz

1G ~ 4GHz

Item

Frequency Error ±0.1ppm ±0.1ppm

3 Phase Error ±5(RMS) ±5(RMS)

±20(PEAK) ±20(PEAK)

Condition TU50: ±100Hz TU50: ±150Hz

3dB below reference sensitivity 3dB below reference sensitivity

Frequency Error Under RA250: ±200Hz RA250: ±250Hz

TU3: ±150Hz TU1.5: ±200Hz

5Due to

Switchingtransient

4

Multipath and Interference HT100: ±100Hz HT100: ±250Hz



2. PERFORMANCE

No Item

800kHz

PowercontrolLevel

Power(dBm)

Tolerance(dB)

PowercontrolLevel

Power(dBm)

Tolerance(dB)

5 33 ±3 0 30 ±3

6 31 ±3 1 28 ±3

7 29 ±3 2 26 ±3

8 27 ±3 3 24 ±3

9 25 ±3 4 22 ±3

10 23 ±3 5 20 ±3

11 21 ±3 6 18 ±3

12 19 ±3 7 16 ±3

13 17 ±3 8 14 ±3

14 15 ±3 9 12 ±4

15 13 ±3 10 10 ±4

16 11 ±5 11 8 ±4

17 9 ±5 12 6 ±4

18 7 ±5 13 4 ±4

19 5 ±5 14 2 ±5

15 0 ±5

9 Burst timing

GSM DCS/PCS

Frequency offset

Intermodulation product shouldbe Less than 55dB below thelevel of Wanted signal

Mask IN

Intermodulationattenuation

–7

8Transmitter

Output Power

Mask IN




2. PERFORMANCE

2) Transmitter – WCDMA Mode

No Item Specification

1 Maximum Output Power Class3: +24dBm(+1/-3dB) Class4: +21dBm(±2dB)

2 Frequency Error ±0.1ppm

3 Open Loop Power control in uplink ±9dB@normal, ±12dB@extreme

4 Inner Loop Power control in uplink

Adjust output (TPC command) cmd 1dB 2dB 3dB +1 +0.5/1.5 +1/3 +1.5/4.5 0 -0.5/+0.5 -0.5/+0.5 -0.5/+0.5 -1 -0.5/-1.5 -1/-3 -1.5/-4.5 group(10equal command group) +1 +8/+12 +

5 Minimum Output Power -50dBm(3.84MHz)

6 Out-of-synchronization handling of output power Qin/Qout:DPCCH quality levels Toff@DPCCH/lor:-22->-28dB Ton@DPCCH/lor:-24->-18dB

7 Transmit OFF Power -56dBm(3.84M)

8 Transmit ON/OFF Time Mask ±25us PRACH, CPCH, uplink compressed mode

9 Change of TFC

±25us power varies according to the data rate DTX: DPCH off (minimize interference between UE)

10 Power setting in uplink compressed ±3dB(after 14slots transmission gap)

11 Occupied Bandwidth(OBW) 5MHz(99%)

12 Spectrum emission Mask

-35-15*(∆f-2.5)dBc@∆f=2.5~3.5MHz, 30k -35-1*(∆f-3.5)dBc@∆f=3.5~7.5MHz, 1M -39-10*(∆f-7.5)dBc@∆f=7.5~8.5MHz, 1M -49 dBc@∆f=8.5~12.5MHz, 1M



2. PERFORMANCE


13 Adjacent Channel Leakage Ratio(ACLR) 33dB@5MHz, ACP>-50dBm 43dB@10MHz, ACP>-50dBm

14 Spurious Emissions *: additional requirement

-36dBm@f=9~150KHz, 1k BW -36dBm@f=150KHz~30MHz, 10k -36dBm@f=30~1000MHz, 100k -30dBm@f=1~12.75GHz, 1M -41dBm*@1893.5~1919.6MHz, 300k -67dBm*@925~935MHz, 100k -79dBm*@935~960MHz, 100k -71dBm*@1805~1880MHz, 100k

15 Transmit Intermodulation -31dBc@5MHz, Interferer -40dBc -41dBc@10MHz, Interferer -40dBc

16 Error Vector Magnitude(EVM) 17.5% (>-20dBm) (@12.2k, 1DPDCH+1DPCCH)

17 Transmit OFF Power -15dB@SF=4, 768kbps, multi-code transmission

3) Receiver - GSM Mode

No GSM DCS/PCS

1 -105dBm -105dBm

2 C/Ic=7dB C/Ic=7dB

3 Adjacent Channel 200kHz C/Ia1=-12dB C/Ia1=-12dB

Rejection 400kHz C/Ia2=-44dB C/Ia2=-44dB

4 Wanted Signal: -98dBm 1’st interferer: -44dBm 2’st interferer: -45dBm

Wanted Signal: -96dBm1’st interferer: -44dBm2’st interferer: -44dBm

5Wanted Signal: -101dBm

Unwanted Signal: Depend on freq. Wanted Signal: -101dBm

Unwanted Signal: Depend on freq.Blocking Response

(TCH/FS Class II, RBER)

Item

Sensitivity (TCH/FS Class II)

Co-Channel Rejection(TCH/FS Class II, RBER,

TUhigh/FH)

Intermodulation Rejection




2. PERFORMANCE

4) Receiver – WCDMA Mode


1 Reference Sensivitivity Level -106.7dBm(3.84M)

2 Maximum Input Level -25dBm(3.84MHz) -44dBm/3.84MHz(DPCH_Ec) UE@+20dBm output power(class3)

3 Adjacent Channel Selectivity(ACS) 33dB UE@+20dBm output power(class3)

-56dBm/3.84MHz@10MHz UE@+20dBm output power(class3)

-44dBm/3.84MHz@15MHz UE@+20dBm output power(class3)

-44dBm/3.84MHz@f=2050~2095 & 2185~2230MHz, band a) UE@+20dBm output power(class3)



6 Spurious Response -44dBm CW UE@+20dBm output power(class3)

-46dBm CW@10MHz & -46dBm/3.84MHz@20MHz UE@+20dBm output power(class3)

-57dBm@f=9KHz~1GHz, 100k BW

-47dBm@f=1~12.75GHz, 1M

-60dBm@f=1920~1980MHz, 3.84MHz

-60dBm@f=2110~2170MHz, 3.84MHz

8 Spurious Emissions

4 In-band Blocking

5 Out-band Blocking

7 Intermodulation Characteristic



2. PERFORMANCE

5) Bluetooth Mode

5.1) Transmitter

No Item

1 Out Power

2 Power Density

3 Power Control

4 TX Output Spectrum -Frequency range

5 TX Output Spectrum -20dB Bandwidth

6 Tx Output Spectrum -Adjacent channel Po

7 Modulation Characteristics

8 Init. Carrier Freq. Tolerance

9 Carrier Frequency Drift

Freq.Range Operating Standby

30MHz~1GHz -36dBm -57dBm

Above 1GHz~12.75GHz -30dBm -47dBm

1.8~1.9GHz -47dBm -47dBm

5.15~5.3GHz -47dBm -47dBm

Power density < 20dBm per 100kHz EIRP

Option 2dB ≤ step size ≤ 8dB

fmax & fmin @ below the level of -30dBm (100khz BW) within 2.4GHz~2.4835GHz

10

1 slot : ≤ ± 25kHz 3 slot : ≤ ± 40kHz 5 slot : ≤ ± 40kHz Maximum drift rate ≤ 20KHz/50usec

Specification

Out of Band Spurious Emissions

≤ 1MHz

≤ -20dBm @ C/I = 2MHz≤ -40dBm @ C/I ≥ 3MHz

140kHz ≤ delta f1 avg ≤175kHz delta f2max ≥115kHz at least 99.9% of alldeltaf2max delta f2avg/deata f1avg≥0.8

≤ ±75KHz

Class 2 : -6~4dBm




2. PERFORMANCE

5.2) Receiver

No Item

1 Sensitivity single slot packets

2 Sensitivity multi slot packets

Interference Ratio

Co-Channel interference, C/I co-channel 11dB

Adjacent(1MHz)interference, C/I 1MHz 0dB

Adjacent(2MHz)interference, C/I 2MHz -30dB

Adjacent(≥3MHz)interference, C/I ≥3MHz -40dB

Adjacent(≥3MHz)interference to in band -9dB

mirror frequency, C/I image ±1MHz -20dB

interfering Signal Frequency Power Level

30MHz~2000MHz -10dBm



3000MHz~12.75GHz -10dBm

5 Intermodluation Performance

6 Maximum Input Level

BER ≤ 0.1%@wanted signal -67dBm

BER ≤ 0.1%@wanted signal -64dBm static sinwave signal at f1=-39dBm a BT modulated signal f2=-39dBm(payload PRBS15)

BER ≤ 0.1%@-20dBm

Specification

BER≤0.1%@-70dBm

BER≤0.1%@-70dBm

BER ≤ 0.1%@ (Low,Mid,High Frequency) 2405MHz, 2441MHz, 2477MHz

C/I performance

Blocking Characteristic

3

4



2. PERFORMANCE

GSM WCDMA

BAR 7 -92±2 =< RSSI -90±2 =< RSSI

BAR 5 -97±2 =< RSSI -105±2 =< RSSI

BAR 4 -100±2 =< RSSI -109±2 =< RSSI

BAR 2 -103±2 =< RSSI -111±2 =< RSSI

BAR 1 -105±2 =< RSSI -113±2 =< RSSI

BAR 0 -105±2 > RSSI -113±2 > RSSI

2.4 Current Consumption

(VT test : Speaker off, LCD backlight On)

Stand by Voice Call VT

310 Hours = 3.2mA 210 Min = 280 mA 150 Min = 400 mA

(DRX=7) (Tx=10dBm) (Tx=10dBm)

300 Hours = 3.3 mA 205 Min = 290 mA

(paging=5period) (Tx=Max)

WCDMA

GSM

2.5 RSSI

2.6 Battery Bar

Indication Voltage

BAR 3 (100%) : level full 4.17V ± 0.05V

BAR 3 (40%) -> 2 개 (12%) 3.72 ± 0.05V

BAR 2 (12%) -> 1 개 (3%) 3.62 ± 0.05V

BAR 1 (3%) -> Icon Blinking & Alerting Sound

3.53 ± 0.05V

POWER OFF 3.20 ± 0.05V




2. PERFORMANCE

2.7 Sound Pressure Level

No

NOM

MAX

NOM -1±3dB

MAX -15±3dB

NOM

MAX

NOM

MAX

5

6

NOM

MAX

NOM -47dBPA under

MAX -36dBPA under

A NOM

C MAX

O NOM -1±3dB

U MAX -12±3dB

S NOM

T MAX

I NOM

C MAX

13

14

NOM

MAX

NOM -45dBPA under

MAX -40dBPA under

SEND

REV.

SEND

REV.

SEND

REV.

SEND

REV.

Specification

1 Sending Loudness Rating (SLR) 8±3dB

Test Item

3 Side Tone Masking Rating (STMR)

2 Receiving Loudness Rating (RLR)

4 Echo Loss (EL) 40dB over

refer to TABLE 30.3

Receiving Distortion (RD) refer to TABLE 30.4

17dB over

8±3dB

-64dBm0p under

8 Idle Noise-Receiving (INR)

MS

7 Idle Noise-Sending (INS)

Sending Distortion (SD)

40dB over

Sending Distortion (SD) refer to TABLE 30.3

25dB over

refer to TABLE 30.4

15 Idle Noise-Sending (INS) -55dBm0p under

16 Idle Noise-Receiving (INR)

HEADSET

Receiving Distortion (RD)

17

TDMA NOISEGSM: Power Level: 5DCS: Power Level: 0

(Cell Power: -90 ~ -105dBm)Acoustic(Max Vol.)

MS/HEADSET SLR: 8±3dBMS/HEADSET RLR: -13±1dB/-

15dB(SLR/RLR: mid-Value Setting)

MS

GSM

-62dBm under

DCS

Headset

GSM

DCS

9 Sending Loudness Rating (SLR)

10 Receiving Loudness Rating (RLR)

11 Side Tone Masking Rating (STMR)

12 Echo Loss (EL)



2. PERFORMANCE

2.8 Charging

· Normal mode: Complete Voltage: 4.2V

Charging Current: 700mA

· Await mode: In case of During a Call, should be kept 3.9V

(GSM: It should be kept 3.9V in all power level

WCDMA: It will not be kept 3.9V in some power level)

· Extend await mode: At Charging prohibited temperature(0°C under or 45°C over)

(GSM: It should be kept 3.7V in all power level

WCDMA: It will not be kept 3.7V in some power level)




3. Technical Description

3.1 Digital Baseband (DBB) & Multimedia Processor

3.1.1 General DescriptionAccess subsystem

- Access Central Processing Unit (CPU) subsystem – ARM926, Joint Test Action Group (JTAG), Embedded Trace Module (ETM), Instruction and Data (I&D)-cache, and I&D-TCM

- Access peripheral subsystems – Subscriber Identity Module (SIM) interface, IrDA®, Universal Serial Bus(USB), Universal Asynchronous Receiver/Transmitter (UART), and so on

- Digital Signal Processor (DSP) subsystem – CEVA-X1620, JTAG, Static Random Access Memory (SRAM),and Program Data Read Only Memory (PDROM)

- EDGE/GSM/GPRS (EGG) subsystem – EGG hardware accelerators

-WCDMA subsystem – WCDMA hardware accelerators

-Application subsystem

- Application CPU subsystem – containing ARM926, JTAG, ETM, I&D-cache, and I&D-TCM

- Application peripheral subsystems – I2C™, keypad, UART, and so on

- Graphics subsystem – XGAM subsystem

- Audio Processing Execution (APEX) and video encoder subsystems In addition to the two subsystems above, there is also a test block, chip control block, and a pad multiplexing block residing at the top level

DSP

- The Digital Signal Processor Subsystem (DSPSUB) includes a DSP megacell, which contains the DSP CPU together with a tightly coupled memory. The DSP is the Ceva-X 1620 core with a 64 KiB instruction RAM and a 64 KiB data RAM. It also contains debug logic and interfaces. In addition to the megacell, the DSPSUB includes external memories, peripheral units, and interfaces. The DSP megacell is clocked at 208 MHz.

- The DSPSUB includes an AHB master and an AHB slave interface. The AHB master provides a direct access to the Internal Random Access Memory (IRAM) in the EGG core through the AHB. The AHB slave interface allows the CPU and the DMA to access in the program and data RAM residing in the DSPSUB.

Image Signal Processor(MV9319)

- MV9319 is high-end Image Signal Processor (ISP) supporting image sensors up to 5 mega pixels. Its powerful image processing fuctions such as edge enhancement, color correction, advance interpolation, Auto White Balancing increases the quality of sensor image. MV9319 also supports serial interfaces to Flash LED control.

WCDMA subsystem

- The digital baseband controller WCDMA subsystem incorporate a WCDMA modem

- An interface to the WCMDA together with memory control and an internal single port RAM. The WCDMAsubsystem has three AHB slave interfaces.

- The Ericsson DB 3200 also includes HSDPA class 6 functionality.

- The WCDMA subsystem is handled and provided by Ericsson.

XGAM subsystem

- The XGAM subsystem is a graphics acceleration module that provides hardware support in the creation of visual imagery and the transfer of this data to a display. The XGAM also provides support for connecting a Camera module. The visual data could be graphics, still images, or video.

- The XGAM subsystem is handled and provided by Ericsson.

Operation and Services

- I2C™ Interface

- SIM Interfaces

- General Purpose I/O (GPIO) Interface

- External Memory Interface that supports NAND, NOR, PSRAM, SDRAM,

- JTAG

- RTC

- ETM9

3. Technical Description



3. TECHNICAL DESCRIPTION

Figure 3-1-1 GT500 Block Diagram

GT500 Block Diagram





3.1.2 External memory interfaceRF calibration data, Audio parameters and battery calibration data etc are stored in flash memory area.

A. GT500

2Gb NAND flash memory + 1Gb SDRAM

Table 3- 1- 1. External Memory Interface Spec. of GT500

Figure 3- 1- 2. External Memory Configuration of GT500

Dev ice Part Name Maker Item Time Size Speed

Program speed 200µs 1 page = 528 Byte 2.64MByte/s

Erase speed 2ms 1 Block = 16K Byte 8MByte/s

NAND flash K5D1G12ACD-D075 Samsung

Data Communication- IrDA ® (SIR)- UARTs (ACB, EDB (RS232))- USBPackage- 12 by 12 mm 376 balls, 0.5mm pitch TFBGA Production Package




3.1.3 Hardware Architecture

A. Block Diagram

Figure 3-1-4. Application system of Ericsson DB3200

Figure 3-1-3. Access system of Ericsson DB3200

g





B. CPU Subsystem

- Access CPU subsystem

The digital baseband controller includes an access CPU subsystem, which includes the submodulesdescribed below. • 32 KiB I-cache • 32 KiB D-cache • Page table • Memory Management Unit (MMU) • JTAG • ETM9 • 26 KiB I-TCM • 8 KiB D-TCM

- Application CPU subsystem

The digital baseband controller includes an Application CPU subsystem, which includes the submodules described below. • 32 KiB I-cache • 32 KiB D-cache • Page table • MMU • JTAG • ETM9 • 8 KiB I-TCM • 8 KiB D-TCM

C. Peripheral Hardware Subsystem

The digital baseband controller includes hardware that supports mobile terminal peripheralssuch as a MMC, SD, UART, I2C, USB, keypad, and infrared. Collectively, this hardware comprises the Peripheral subsystem.The functional blocks of the Peripheral subsystem connect to the peripheral bus through fourseparate bridges, which provide a simple interface to support different timing and memory access arrangements.

D. DSP Hardware Subsystem

The Digital Signal Processor Subsystem (DSPSUB) includes a DSP megacell, which contains the DSP CPU together with a tightly coupled memory. The DSP is the Ceva-X 1620 core with a 64 kiBinstruction RAM and a 64 kiB data RAM. It also contains debug logic and interfaces. In addition to the megacell, the DSPSUB includes external memories, peripheral units, and interfaces. The DSP megacell is clocked at 208 MHz.The DSPSUB includes an AHB master and an AHB slave interface. The AHB master provides a direct access to the Internal Random Access Memory (IRAM) in the EGG core through the AHB. The AHB slave interface allows the CPU and the DMA to access in the program and data RAM residing in the DSPSUB.

E. XGAM Subsystem

The XGAM subsystem is a graphics acceleration module that provides hardware support in the creation of visual imagery and the transfer of this data to a display. The XGAM also provides support for connecting a Camera module. The visual data could be graphics, still images, or video. The XGAM subsystem is handled and provided by Ericsson.




F. System Control Subsystem

The SYSCON is responsible for clock generation and clock and reset distribution within the digital baseband controller, as well as to external devices.The digital baseband controller chip-ID number is readable from the SYSCON. The block is a slave peripheral under control of the ARM processor. The programming of the SYSCON controls the fundamental modes of operation within the digital baseband controller. Individual blocks can also be reset and their clocks held inactive by accessing the appropriate control registers.

3.1.4 RF Interface

A. GSM Radio Link Interface

DB3200 controls GSM RF part using these signals through GSM RF chip-RF3300.RF_DATA_ARF_DATA_B

RF_DATA_CRF_DATA_STRB

Figure 3-1- 5. Schematic of GSM RF Interface

B. WCDMA Radio Link Interface

RF_WCDMA_PA_0_ENRF_WCDMA_PA_1_ENRF_WCDMA_DCDC_ENRF_WCDMA_PWRDET_EN

Figure 3-1-6. Schematic of WCDMA RF Interface

TX_ADC_STRBD15

RF_DATA_AB15B16

RF_DATA_BC15

RF_DATA_C

A16RF_DATA_STRB

QDATA_AMP_MSBIDATA_FREQ_MSB

AMP_FREQ_LSB

DATA_STRTX_ADC_STRB

B14RF_WCDMA_PA_0_EN

D14RF_WCDMA_PA_1_EN

RF_WCDMA_PWRDET_EC13

B6TX_POW

B13RF_WCDMA_DCDC_EN

DAC_I_NEGE7D7

DAC_I_POSE6

DAC_Q_NEGDAC_Q_POS

D6

D9ADC_I_NEG

C9ADC_I_POS

ADC_Q_NEGC8D8

ADC_Q_POS

WTX_BAND_2_ENWTX_BAND_1_EN

WRX_Q_P

WPOW_DET_EN

WTX_BAND_8_5_EN

WTX_I_NWTX_I_PWTX_Q_NWTX_Q_P

WRX_I_NWRX_I_PWRX_Q_N

WPOW_DET





3.1.5 SIM Interface

SIM interface scheme is shown in Figure3-1-7.

SDAT, SCLK, SRST ports are used to communicate DBB(DB3200) with

ABB(AB3100) and filter.

Table 3-1-2. SIM Interface

Figure 3-1-7. SIM Interface

3.1.6 UART Interface

UART signals are connected to DB3200 GPIO through IO connector

Table 3-1-3. UART Interface

SIM (Interface between DBB and ABB)

SDAT SIM card bidirectional data line

SCLK SIM card reference clock

SRST SIM card async/sync reset

VDD

DAT

CLK CARD

RST

SIMVCC

AB3100

SDAT SIMDAT

SCLK SIMCLK

SRST SIMRST

DB3200

SDAT

SCLK

SRST

VDDE_1V8

10K10K

UART0

Resource Name Note

ACC_GPIO_2 ACC_UART0_RX ACC Receive Data

ACC_GPIO_3 ACC_UART0_TX ACC Transmit Data

UART1

APP_GPIO_0 APP_UART_RX APP Receive Data

APP_GPIO_1 APP_UART_TX APP Transmit Data




3.1.7 GPIO (General Purpose Input/Output) map

In total 60 allowable resources. This model is using 35 resources.GPIO Map, describing application, I/O state are shown in below table.

Table 3-1-4. DB3200 ACC GPIO Map Table

OutputACC_GP_WLAN_RESETnACC_GPIO_30

OutputACC_GP_USB_CSACC_GPIO_27

InputACC_GP_SPI_WLAN_IRQnACC_GPIO_28

OutputACC_GP_GPS_RESETnACC_GPIO_29

OutputACC_GP_WLAN_ENACC_GPIO_31

Access GPIO

GPIO Assigned Name Init Status

ACC_GPIO_0 ACC_USB_HS_STP Output

ACC_GPIO_1 ACC_USB_HS_DIR Output

ACC_GPIO_2 ACC_UART0_RX Input

ACC_GPIO_3 ACC_UART0_TX Output

ACC_GPIO_4 ACC_USB_HS_IN_CLK Input

ACC_GPIO_5 ACC_USB_HS_NXT Input

ACC_GPIO_10 ACC_USB_HS_DATA(4) Input




ACC_GPIO_16 ACC_UART3_RX Input

ACC_GPIO_17 ACC_UART3_TX Output

ACC_GPIO_20 ACC_UART3_CTS Input

ACC_GPIO_21 ACC_UART3_RTS Output

ACC_GPIO_22 ACC_SPI_3AXIS_CSn Output

ACC_GPIO_26 Not used Output

ACC_GPIO_32 ACC_GP_WLAN_PWR_DOWNn Output





3.1.8 GPIO (General Purpose Input/Output) map

Table 3-1-5. DB3200 APP GPIO Map Table

Application GPIO

GPIO Assigned Name Init Status

APP_GPIO_0 APP_UART_RX Input

APP_GPIO_1 APP_UART_TX Output

APP_GPIO_2 APP_GP_ISP_FLASH_SET Output

APP_GPIO_4 APP_GP_VGA_SDN Output

APP_GPIO_7 APP_GP_TOUCH_SCL Output

APP_GPIO_8 APP_GP_TOUCH_SDA Output/

APP_GPIO_10 input Output

APP_GPIO_11 APP_GP_TOUCH_LDO_EN Output

APP_GPIO_12 APP_GP_ISP_LDO_EN Output

APP_GPIO_13 APP_GP_LCD_ID Input

APP_GPIO_14 Not used Output

APP_GPIO_16 APP_GP_MOTORLDO_EN Output

APP_GPIO_17 APP_MMC_FB_CLK Input

APP_GPIO_21 APP_GP_LCD_IF1 Output

APP_GPIO_22 APP_GP_USW_SCL Output

APP_GPIO_23 APP_GP_USW_SDA Output/

APP_GPIO_24 input Input/Output

APP_GPIO_25 DCON (Dedicated) Output




3.1.9 USB

The USB block supports the implementation of a “High-speed" device fully compliant to USB 2.0 standard. It provides an interface between the CPU (embedded local host) and the USB wire, and handles USB transactions with minimal CPU intervention.The USB specification allows up to 15 pairs of endpoints. Data for each endpoint is buffered in RAM within the USB block and is read/written from the endpoint FIFO using DMA transfers or FIFO register access. High-speed (high throughput) endpoints can use DMA while slower endpoints can use FIFO register access.The USB block can request up to six DMA channels, three for IN endpoints and three for OUT endpoints.

Table 3-1-6. USB Signal Interface of DB3200

USB data7USB_DAT7

USB chip selectUSB_CS_PD

USB data0USB_DAT0

USB data1USB_DAT1

USB data2USB_DAT2

USB data3USB_DAT3

USB data4USB_DAT4

USB data5USB_DAT5

USB data6USB_DAT6

ULPI stop signalUSB_STP

ULPI direction signalUSB_DIR

USB clockUSB_CLK

ULPI next signalUSB_NXT

Power supply for Asta USB blockVBUS

NoteUSB Function





Figure 3-1-8. Schematic of DB3200 USB block

Figure 3-1-9. Schematic of USB Transceiver

J2USB_SE0_VMUSB_DAT_VP

K2

USB_OEL3

ACC_GPIO_4K8F1

ACC_GPIO_5ACC_GPIO_6

J8G3

ACC_GPIO_7H3


G2

G4

L8ACC_GPIO_2

G1ACC_GPIO_3

J3ACC_GPIO_0ACC_GPIO_1

K3

ACC_GPIO_10H9E1


H10D1


F3D4

ACC_GPIO_15ACC_GPIO_16_USBPRB

C3G5


E4

ACC_USB_HS_STP

USB_DATA(0)USB_DATA(1)USB_DATA(2)

ACC_USB_HS_IN_CLKACC_USB_HS_NXT

ACC_USB_HS_DATA(4)ACC_USB_HS_DATA(5)ACC_USB_HS_DATA(6)ACC_USB_HS_DATA(7)

ACC_USB_HS_DIR

ACC_UART3_RXACC_UART3_TX

ACC_UART3_CTSACC_UART3_RTS

ACC_GP_USB_CSACC_GPS_START

ACC_USB_HS_DATA(3)


USB Transceiver

10V

High Speed USB Interface

1%

TP501

TP502

0R

655

VDDE_1V8

R509

1K

51K

R50

0

C51

50.

1u

C51

40.

1u

R64

1

0

TP500

12K

R51

0

4.7u

C51

6

RREF

STPD6

TESTC4

F4VBUS

VC

CF

3

B5VCC_IO1VCC_IO2

B2

F5XTAL1XTAL2

F6

B6C6

DATA7

E5DIR

DMC1D1

DPFAULT

E2

GN

D1

C5

D2

GN

D2

GN

D3

E4

D3ID

NC

1F

1F

2N

C2

D5NXT PSW_N

D4

E6REF1V8

E3REG3V3

C2

CFG0E1

B4CFG1CFG2

B3

CHIP_SELC3A4

CLOCKDATA0

B1A1

DATA1DATA2

A2A3

DATA3DATA4

A5A6

DATA5DATA6

ISP1508AETU502

C5130.1u

2.2u

C51

7

0.1uC500

4.7uC501

4.7uC512

VBAT

ACC_USB_HS_NXTACC_USB_HS_STP

USB_XTAL1

VBUS

USB_DPUSB_DM

ACC_GP_USB_CSACC_USB_HS_IN_CLK


ACC_USB_HS_DATA(3)ACC_USB_HS_DATA(4)ACC_USB_HS_DATA(5)ACC_USB_HS_DATA(6)ACC_USB_HS_DATA(7)

ACC_USB_HS_DIR




3.1.11 Bluetooth Interface

GT500 supports Bluetooth operation using ST’s STLC2593C Bluetooth module.

A. General Description

The Bluetooth interface utilizes the SPI interface for control signals going to and from the Bluetooth module. The SPI is also used for data transmissions.

It uses the PCM interface for transmitting audio to and from the Bluetooth module.

The Bluetooth module uses both the 26 MHz master clock signal and the 32,768 kHz low-frequency clock signal for internal timing within the Bluetooth module. The intention is to use the low-frequency clock as a low-power timing provider and to use the 26 MHz as a high precision timing reference used mainly by the Bluetooth radio during operation.

The clock request mechanism is used to minimize current consumption for the total system.

The intention is to use the CLKREQ signal to ask for the master clock when needed, for example, when the Bluetooth radio is operating.

B. SPI InterfaceThe physical SPI interface is made up of 5 signals : clock, chip select, data in, data out and interrupt. When the SPI mode is selected , these signals are available through the BT_UART/BT_SPI and BT_HOST_WAKEUP pins.The SPI interface is Master at the Host side, and Slave at the BT Controller side. It is designed to work with the H4 and enhanced H4 protocol.Also synchronous data packet transfer (sSCO) over HCI is supported.The SPI data length and endianness are configurable.The SPI interface can only operate in half duplex mode.

C. PCM Interface

The PCM interface is used to send audio to and from the Bluetooth module. The interface is a synchronous interface using a PCM clock and a PCM sync signal for synchronization. Two data signals are used for data, one in each direction.

The PCM clock signal operates at frequencies as high as 1 MHz. The word length of the audio data can be 8 or 16 bits. Furthermore, the PCM interface has a function known as MP-PCM, which is an addressing scheme, used to have more than two devices talking on the bus.

To add this function, the data pins have to be bi-directional. Additionally, the position of the audio data relative to the frame sync pulse must be selectable. During the periods within a frame that a device is not transmitting audio data, it must put both PCM data signals in a high-impedance state to allow other devices access.

D. Master Clock and Clock Request Interface

The master clock (MCLK) is a 26 MHz signal used as the high precision clock signal for the Bluetooth module. The signal can be switched on and off by the platform. The master clock request (CLKREQ) is used by the Bluetooth module to ask for the master clock.

If the Bluetooth module asserts the signal high, it gets the master clock. The other alternative for the Bluetooth module is to set the clock request output to high impedance state, indicating that it does not need the master clock. The Bluetooth module receives the master clock, if other parts of the chipset request it.

E. Low Frequency Clock Interface

The low-frequency clock signal (RTCCLK) is used by the Bluetooth module as a low-power clock. The clock is used in different Bluetooth modes, like sniff and park, to have a correct timing on the Bluetooth air interface without having the master clock running.





The low-frequency clock is always present, in some applications even when the chipset ispowered down.

F. STLC2593C

Based on Ericsson Technology Licensing Baseband Core (EBC) Bluetooth™ specification compliance: V2.1 + EDR.(“Lisbon”)– Point-to-point, point-to-multi-point (up to 7 slaves) and scatternet capability– Support ACL and SCO links– Entended SCO (eSCO) links– Faster Connection HW support for packet types– ACL: DM1, DM3, DM5, DH1, DH3, DH5, 2-DH1, 2-DH3,2-DH5,3-DH1,3-DH3, 3-DH5– SCO: HV1, HV3 and DV– eSCO: EV3, EV4, EV5, 2-EV3, 2-EV5, 3-EV3, 3-EV5 Adaptive Frequency Hopping (AFH) Channel Quality Driven Data Rate (CQDDR) “Lisbon” Feature– Encryption Pause/Resume (EPR)– Entended Inquiry Response (EIR)– Link Supervision Time Out (LSTO)– Secure Simple Pairing– Sniff Subrating– Quality of Service (QoS) : Packet Boundary Flag, Erroneous Data Delivery Transmit Power– Power Class 2 and Power Class 1.5 (above 4 dBm)– Programmable output power– Power Class 1 compatible HCI– HCI H4 and enhanced H4 Transport Layer– HCI proprietary commands (e.g. peripherals control)– Single HCI command for patch/upgrade download– eSCO over HCI supported Supports Pitch-Period Error Concealment (PPEC) Efficient and flexible support for WLAN coexistence scenarios Low power consumption– Ultra low power architecture with 3 different low power levels– Deep Sleep modes, including Host-power saving feature– Dual Wake-up mechanism: initiated by the Host or by the Bluetooth device Communication interfaces– Fast UART up to 4 MHz– Flexible SPI interface up to 13 MHz– PCM interface– Up to 10 additional flexibly programmable GPIOs– External interrupts possible through the GPIOs– Fast I2C interface as master Clock support– System clock input (digital or sine wave) at 9.6, 10, 13, 16, 16.8, 19.2, 26, 33.6 or 38.4MHz– Low Power clock input at 3.2, 32 and 32.768 kHz ARM7TDMI CPU Memory organization– On chip RAM, including provision for patches– On chip ROM, preloaded with SW up to HCI Ciphering support up to 128 bits key11




G. GT500 Bluetooth Schematic

Figure 3-1-11. Schematic of STLC2593C

Clock- Clock request

Connected to CLKREQ of DB3200 and AB3100, input to RF3300- Fast clock : 26MHz

Supplied MCLK from RF3300Frequency deviation : ±20ppm

- Low power clock : 32.768kHzSupplied RTCCLK from AB3100

Power- Supplied 2.75V, 1.8V from internal regulators of AB3100

Reset- RESOUT2n signal of DB3200 controls STLC2593C reset.

SPI- Connected to SPI of DB3200- HCI interface between DB3200 and STLC2593C

PCM- Audio signal interface between DB3200/AB3100 and STLC2593C

ANT- 2.4GHz, 50 ohm matching

Keep away from noise signals

on L1, L2 and L3

Common GND on L1, L2 and L3

Careful routing of BT_CLK

Analog GND must be Isolated from

RF GND: Isolate from Common GND

VDD_BT

R73

4

100K

C7340.1u

120p

C74

3

DEA212450BT-7043C15

BP1

4BP2 BP_DC

2

3G

16

G2

1U_BP

VDDE_1V8

FL730

VBAT

R739

110

0

R73

5

110

R741

VDDK_2V75

VSS_BT_ANA

10p

C74

2

100K

R73

2

A23 GND

5VCC

Y4

1 _OE

SN74LVC1G125DRLRU730

VDD_BT

C7390.1u

VDDK_2V75

FB73060

VDDE_1V8

100K

R73

8

DNIR733

C73

50.

1u

C7300.1u

C73

60.

1u

R74

0

0

22n

C74

1

VDDE_1V8

VDDE_1V8

VDDE_1V8

VDDE_1V8

4.7uC731

R730

33

R7370

1uC737

VSS_BT_ANA

VDDE_1V8

100pC732

VSS_BT_RF

VSS_BT_RF

1uC738

R73

1

100K

C74

022

n

VDDE_1V8

C7330.1u

L5L6

NC6

A5

FM_LOUTB5

FM_RCLKD7

C8FM_RFGND

C5FM_ROUT

C9FM_RSTB

E9FM_SCLK

FM_SDIOD8

FM_SENBD9

FM_VAA4

FM_VDB3

FM_VIOD6

D4NC1NC2

F7F8

NC3NC4

L4

NC5

H1L1

BT_VSSRF2BT_VSSRF3

J2K2

BT_VSSRF4

BT_WAKEUPL9

B8FM_FMIP

FM_GND1A3B4

FM_GND2FM_GND3

B6

FM_GND4B7C4

FM_GND5C6

FM_GND6C7

FM_GND7FM_GND8

D5

FM_GPIO1A7A6

FM_GPIO2FM_GPIO3

G4H3

BT_VSSANA11H4

BT_VSSANA12

D2BT_VSSANA2BT_VSSANA3

E3

BT_VSSANA4F1F2

BT_VSSANA5BT_VSSANA6

F3F4

BT_VSSANA7G1

BT_VSSANA8G3

BT_VSSANA9

H6BT_VSSDIG1

H7BT_VSSDIG2BT_VSSDIG3

H8K8

BT_VSSDIG4L8

BT_VSSDIG5

BT_VSSRF1

C1C2

BT_RSVR_NBT_RSVR_RF

M2

BT_TEST1H2G2

BT_TEST2

BT_UART_CTSK6

J6BT_UART_RTS

BT_UART_RXDH9

G7BT_UART_TXD

E6BT_VDD_CLD

M6BT_VIO_ABT_VIO_B

J9

BT_VIO_CN3N5

BT_VIO_DBT_VIO_E

G8

BT_VSSANA1D1

BT_VSSANA10

E2E4

BT_HVA5BT_HVD

N7

BT_LP_CLKK9

BT_PCM_AK5M5

BT_PCM_B

M4BT_PCM_CLK

N4BT_PCM_SYNC

BT_REF_CLK_INF6

BT_REG_CTRLJ4

K7BT_RESETN

J1BT_RFNBT_RFP

K1

BT_RSVR_CL1B2

BT_RSVR_CL2C3M8

BT_RSVR_DBT_RSVR_DSM

BT_CLK_REQ_IN_2

J7BT_CLK_REQ_OUT_1

J8BT_CLK_REQ_OUT_2

BT_CONFIG_1L7

BT_CONFIG_2M7N6

BT_CONFIG_3

BT_GPIO_0G9

K4BT_GPIO_10

K3BT_GPIO_11

BT_GPIO_16J3L3

BT_GPIO_8

BT_GPIO_9M3

BT_HOST_WAKEUPE8

BT_HVA1L2D3

BT_HVA2BT_HVA3

E1

BT_HVA4

STLC2593U731

BT_AF_PRGG6

BT_CLK_REQ_IN_1E7F9

VDD_BT

0R

742

RESOUT2_n

PCM_DLDPCM_ULD

PCM_CLKPCM_SYNC

BT_CLKREQ_n

BT_TXRX

RESOUT1_n

FM_LPFM_RP

PTA_BT_STATEPTA_BT_PRIO

BT_CLKREQ_n

BT_CLKMCLKSEC

ACC_GP_SPI_BT_CSn

RTCCLK

APP_I2C_SCL

APP_I2C_SDA

BT_CLK

FM_ANT

WLAN_SLEEPn

ACC_SPI_MOSI

PTA_WLAN_ACTIVE

ACC_GP_SPI_BT_IRQ

RTCCLK

ACC_SPI_CLK

ACC_SPI_MISO

APP_GP_FM_GPIO2





3.1.12 MicroSD Interface card

GT500 supports the MicroSD card interface as external memory card.

MicroSD card has 4-data line, so GT500 uses 4-data lines.

All control and data lines are connected to DB3200.

Cause of the difference between DB3200 and MicroSD card, a level shifter should be added.

Table 3-1-7. MicroSD card Interface

Card detection- When there are no card in MicroSD card socket, APP_GP_MMC_DETn pin is high cause of an external

pull-up.- If card is inserted in socket, APP_GP_MMC_DETn pin is changed to Low cause of the mechanical switch

in the socket.

- If card is removed, APP_GP_MMC_DETn pin changes high.

Figure 3-1-12. Micro SD card and Schematic of Micro SD card Interface

MicroSD card Interface

APP_GP_MMC_DETn Card detection, connected to GPIO of DB3200

MICROSD_CMD_2V7 Command/Response

MICROSD_CLK_2V7 Clock

MICROSD_DAT[3:0]_2V7 Data line

VDDG_2V85 Supply voltage from AB3100 internal LDO

VDDE_1V8

DAT1AA2 D1

DAT1BB4

DAT2A DAT2BC4

A4DAT3A

D4DAT3B

GND1B3

GND2C3

A5VCCA

D5VCCB

SN74AVCA406EZXYRU403

A3CLKA

D3CLKB

CLK_FA1

CMDAB1

C2CMDB

CMD_DIRB5

B2DAT0A DAT0B

D2DAT0_DIR

C5

DAT123_DIRC1

C4090.1u

2 4 6 8

1 3 5 7

C410

RA

400

100K

0.1u

VDDG_2V85

100K

R63

7

MICROSD_DAT3_2V85

MICROSD_CMD_2V85

MICROSD_DAT0_2V85

MICROSD_DAT1_2V85MICROSD_DAT2_2V85

MICROSD_CLK_2V85

APP_MMC_FB_CLKMICROSD_CLK

MICROSD_CMD_DIRMICROSD_CMD

MICROSD_DAT_DIRMICROSD_DAT0

MICROSD_DAT1MICROSD_DAT2MICROSD_DAT3

1608

Hirose ( Micro-SD Socket, Normal ,T= 1.68)

MICROSD SOCKET

ENSY0020901

220K

R41

9

EV

LC

18S

0201

5

VA40

3

VA40

2

EV

LC

18S

0201

5

VA40

5

EV

LC

18S

0201

5

SWA SWB

4

6

DM3AT-SF-PEJ

2

5

3

78

1

GND

S400

R416 2.2

EV

LC

18S

0201

5

VA40

1

EVLC18S02003VA406

EV

LC

18S

0201

5

VA40

4

VDDG_2V85

VDDE_1V8

VA40

0

EV

LC

18S

0201

5

10uC408

MICROSD_DAT0_2V85

MICROSD_CLK_2V85

MICROSD_DAT1_2V85

APP_GP_MMC_DETn

MICROSD_CMD_2V85





3.1.13 Power On Sequence

User presses END key and then ONSWAn signal is changed to Low.

AB3100 initiates the internal oscillator and powers on the regulators.

AB3100 generates power for DB3200.

AB3100 releases the power reset signal (PWRRSTn) and generates an interrupt(IRQ0n) to DB3200.

Figure 3-1-13. Power On Sequence

DB3200

PWRRSTN

IRQ0_N

AB3100

PWRRST_N

IRQ

ONSWA_N

Power for DB3200

PWRRSTn

IRQ0nONSWAn

Press END key





Figure 3-1-14. Key Circuit

3.1.14 Key PadThere are 8 buttons in Figure 3-1-14/15. ‘END’ Key is connected ONSWAn for AB3100.

Table 3-1-8. Key Matrix Mapping Table

KEYOUT4

KEYIN0 KEYIN1 KEYIN2 KEYIN3 KEYIN4 KEYIN5 GND

KEYOUT0 SEND

KEYOUT1 Clear camera

KEYOUT2 Lock AF

KEYOUT3

GNDVOLUME

DOWN

END

(ONSWA_n)

VOLUME

UP

SEND CLEAR KEY END KEY AUTO FOCUS KEY

HALF SHUTTER

FULL SHUTTER

SEND

A

B B_

C C_

D

EVPAHBD6ASW1000

RB521S-30

D1000

ENDCLR

ONSWA_n

KEYIN3

KEYIN0

KEYOUT1

KEYOUT0

ONSWA_n

KEYIN3

KEYOUT2

KEYOUT1

VOLUME KEYTOUCH LOCK KEY

VOLUME_UPVOLUME_DOWNLOCK

KEYIN0KEYIN2

KEYOUT2

KEYIN0




3.1.15 Touch Screen

When Touch button and Touch screen is touched, Interrupt is given to DB3200 than, it read the status register what coordinate is touched by I2C. I2C is realize by DB3200 GPIO..

Figure 3-1-15. Touch screen schematics

EUSY0337101

TOUCH SCREEN DRIVER IC

RS

B6.

8CS

T2R

ZD

402

ZD

403

RS

B6.

8CS

T2R

B2A0

A1C2

A1AUX

GNDD2

PENIRQ-B1 D1

SCL

C1SDA

VDD_REFA2A3

X+C3

X-

Y+B3 D3

Y-

TSC2007IYZGRU405

ZD

401

RS

B6.

8CS

T2R

VDD_TOUCH_2V8

DN

IR

424 2.7K

R42

2

R42

0

0

0.1u

C412

R42

12.

7K

C411

1u

RS

B6.

8CS

T2R

ZD

400

TOUCH_Y+

TOUCH_X-

TOUCH_Y-

APP_GP_TOUCH_PENIRQn_2V75 APP_GP_TOUCH_SCL_2V75

APP_GP_TOUCH_SDA_2V75

TOUCH_X+

TOUCH LEVEL SHIFTER

R42

5

51K

0R423

VDD_TOUCH_2V8VDDE_1V8

R426 0

C3

B4

C4

B4GND

B3OE V

CC

AB

2

B1

VC

CB

U404TXS0104EZXUR

A1A1

A2A2

A3A3

A4

A4

C1B1

C2

B2

B3

0

R64

2

APP_GP_TOUCH_SDA

APP_GP_TOUCH_SCL

APP_GP_TOUCH_SCL_2V75

APP_GP_TOUCH_PENIRQn


APP_GP_TOUCH_PENIRQn_2V75





3.1.16 A-GPS

GT500 supports A-GPS operation using Broadcom BCM4750 A-GPS module.

The BCM4750 is a single chip, single die AGPS receiver that combines a high-performance RF front end with an adaptive baseband processor. The BCM4750’s small footprint and minimal parts count provide significant reductions in the design, layout, manufacturing, and testing resources required to integrate AGPS technology with mobile handsets and portable devices.

The BCM4750 uses a host-based integration architecture that splits processing functions between the GPS chip and the CPU on the host system. Host-based architecture enables a simplified IC design that can be executed in a much smaller and less expensive package than competing System on Chip solutions which require an onchip CPU subsystem and flash memory in addition to the RF and baseband blocks. Demands on the host CPU are minimal and no real time requirements are imposed.

Feature

• Fully integrated GPS RF front-end and baseband processor on a single CMOS die

• Supports UART, I2C, and SPI host interfaces

• Industry-leading power consumption efficiency

• Synchronization input, PPS output

• Fractional-N Synthesizer supports reference frequencies from 10 to 40 MHz

• Companion software driver supports Assisted, Autonomous, and Enhanced Autonomous operating mode

Figure 3-1-16. Functional Block Diagram of BCM4750




GT500 A-GPS Schematic

Figure 3-1-16. Schematic of BCM4750

GP

S L

NA

blo

ck

100pC772

C771

0.1u

AL

M-1612

FIL

_OU

T4

3G

ND

RF

_IN2

1S_D

VD

D5

2.2u

U770

C770

TP

751

C757NA

L750

6.8nH

C764

1u

VD

DE

_1V8

C762

1u

VG

PS

_1V8

2.2nHL770

10nHL771

0R

772

VSSD1VSSD2

D3D7

VSSD3E4

VSSD4VSSD5

E5

VSSD6F4

VSSIFSUBB3C1

VSSRFSYNTH

TD

O

F1

TE

ST

MO

DE

TM

SA

5

TR

ST

_NA

6

G6

TX

_SD

A_M

ISO

D4

VD

DC

OR

E1

VD

DC

OR

E2

D6

E3

VD

DC

OR

E3

VD

DC

OR

E4

E6

VD

DIF

SY

NT

HD

1

VDDIO1B6G3

VDDIO2VDDIO3

G7

F6

VD

DL

P_L

PR

EG

OU

T

VD

DR

FD

2

VP

DD

5

B5CNTIN

G1

CT

S_N

_I2C_G

RP

1_SC

S_N

F7

INT

R_N

A3LPREGIN

RE

SE

T_N

G4

RF

INB

1

E2

RF

RE

GO

UT

E1

RF

SR

EG

OU

T

F5RTCCLK

RT

S_N

_I2C_G

RP

0_MO

SI

G5

RX

_SC

L_S

CK

G2

F3

STA

ND

BY

_N

SYNC_PPSE7

A7

TC

K

TCXOA2

TD

IC

7B

7

U751

AT

ES

T0

B2

AT

ES

T1

C3

BB

RE

GO

UT

A4

C4BBRFREGIN

BM

S0

C6

B4

BM

S1_I2C

_A0

BM

S2_U

AR

TC

S_N

C5

F2

BC

M4750

C755

2.2nH

100nH C758

100nH

L772

0 R750

C761

1u

VD

DE

_1V8

1u C763

TP

753

1C

N7501

CN

751

X750

1G

ND

1

GN

D2

3

NC

12

5N

C2

OU

T4

VC

C6

KT

2520F16369A

CW

18T100K

R756

TP

752

C751

0.1u

C760

1u

2.2uC

750

C752

1u

C756 0.5p

1u C759

VG

PS

_1V8

10

R770

R757

0

AC

C_G

P_G

PS

_PO

N

GP

S_C

NT

IN

AC

C_U

AR

T3_T

X

AC

C_G

P_G

PS

_PO

N

AC

C_G

PS

_STA

RT

RT

CC

LK

AC

C_U

AR

T3_C

TS

AC

C_G

P_G

PS

_RE

SE

Tn

AC

C_U

AR

T3_R

TS

AC

C_U

AR

T3_R

X

GP

S P

ow

er

0

R755

C766 1u

VG

PS

_1V8

VB

AT

1uC765

3C

E2

GN

D

5PGND

VD

D4

1V

OU

T

RP

101K182D

U752

AC

C_G

P_G

PS

_PO

N

GP

S C

lock B

uffer

R754

100K

0.1uC

753

R75210

33

R753

C754

2.2u

VD

DE

_1V8

AGN

D

OE

VC

CY

NL

17SZ

126XV

5T2G

U750

MC

LK

SE

C

GP

S_C

NT

IN

AC

C_G

P_G

PS

_PO

N





3.2.1 Camera & Camera Interface

Figure 3-2-1. Camera Interface (in DB3200)

Figure 3-2-2. 5M Camera Connector(24Pin – Main Board)

3.2 Visual part

TP

221

PD

I_D

6N

22

PD

I_D

7N

15

PD

I_R

ES

_NK

20K

23P

DI_

C0

PD

I_C

1J1

6

PD

I_C

2K

22

PD

I_C

3K

16L

22P

DI_

C4

L21

PD

I_C

5P

DI_

D0

L23

L20

PD

I_D

1P

DI_

D2

M22 J20

PD

I_D

3M

23P

DI_

D4

K15

PD

I_D

5

W23

CI_

D7_

CL

K1_

PC

I_D

8_D

AT

1_M

W22

CI_

D9_

DA

T1_

PV

22

U23

CI_

HS

YN

C

U21

CI_

PC

LK

CI_

RE

S_N

T21

R20

CI_

VS

YN

C

U19

CI_

D0

CI_

D1

V19

V20

CI_

D2_

CL

K0_

MC

I_D

3_C

LK

0_P

W20

CI_

D4_

DA

T0_

MU

20T

20C

I_D

5_D

AT

0_P

CI_

D6_

CL

K1_

MV

23

TP

222

TP

223

LC

D_V

SY

NC

LC

D_D

ATA

[4]

LC

D_D

ATA

[5]

LC

D_D

ATA

[6]

LC

D_D

ATA

[7]

LC

D_W

E_N

LC

D_R

SL

CD

_CS

_N

LC

D_R

ES

ET

_N

CI_

DA

TA[4

]C

I_D

ATA

[5]

CI_

PC

LK

CI_

VS

YN

CC

I_H

SY

NC

CI_

RE

S_n

CI_

DA

TA[7

]C

I_D

ATA

[6]

CI_

DA

TA[0

]

CI_

DA

TA[2

]

LC

D_D

ATA

[0]

LC

D_D

ATA

[1]

LC

D_D

ATA

[2]

LC

D_D

ATA

[3]

LC

D_R

D_N

CI_

DA

TA[1

]

CI_

DA

TA[3

]

LC Filter for power noise from GSM RF

0.1u

CAM_DVDD_1V8

C60

6

C60

70.

1u

R614 47

FB

600

1P1

P22

3P3

P44 5

P5

6P6

P77

8P8

ICMF214P101M

FL603

7.5p

7

8

9

C610

13

14

15

16

17

18

19

2

20

21

22

23

24

3

4

5

6

CN603

GB042-24S-H10-E3000ENBY0034201

1

10

11

12

P1

1 2P

23

P3

P4

45

P5

P6

6P

77

P8

8

D603PRSB6.8C

UL

CA

2114

C01

5FR

VA60

0

CAM_AVDD_2V8

CAM_AFVDD_2V8

PRSB6.8CD602

47nHL600

BLM15AG100PN1FB602

FB

601

C6222.2u

C621220p

ISP_SENS_I2C_SDA5MCAM_RESET_N

ISP_SENS_I2C_SCL

DATANCLKP

DATAP

CLKN ISP_SENS_MCLK




Figure 3-2-3. ISP Interface (MV9319)

Figure 3-2-4. Flash LED (Sub Board)

PRSB6.8C

D601

C6VDDA_2_8RXVDDA_2_8TX

A7

VDDCOD3

VDDCO_ED4

VDDIO_2_8VE5

C5VSSA_RX

B7VSSA_TX

F1VSYNCO

H4SDO4SDO5

G4SDO6

F4F5

SDO7

SEL1G8

H7SIMO_S_GPIO31

SMCKOF8

SOMI_S_GPIO30G7

D1SRESET

H6SS_S_SDO8

A8TCLKTCLKB

B8C7

TDATATDATAB

C8

A4TEST_0

F7TXD

PCLKOE1

RCLKA6B6

RCLKBA5

RDATARDATAB

B5

RGVDD_1_8VE4

RXDE7

SCLK_S_SDO9H8

SCL_M_SS_MA2

A3SCL_S

B2SDA_M_MISO_M

SDA_SB3

F2SDO0SDO1

H3G3

SDO2SDO3

F3

GPIO10_SCLK_MA1B1

GPIO11_MOSI_M

GPIO20_PWM0H1G2

GPIO21_PWM1H2

GPIO22_PWM2GPIO23_PWM3

D2

H5GPIO24_SCLK_M

GPIO25_SS_MF6G6

GPIO26_MISO_MG5

GPIO27_MOSI_M

GPIO28_SCL_MC1C2

GPIO29_SDA_M

HSYNCOE2

MCLKE8C3

NRESET

NSRESETG1

MV9319

D6AVDD

D5AVDDP

B4DGND1

C4DGND2

D7DGND3DGND4

D8

DGND5E3

DGND6E6

U602

ISP_DVDD_1V84.

3KR

619

FB603

1uC619

C6231u

R61

84.

3K

C6151u

0.1uC609

0.1uC616

TP601

ISP_DVDD_1V8

C6181u

ISP_AVDD_2V8

0R632

C6201u

1uC608

R617 100ohm

C6171u

0.1uC624

0R633

TP600

ISP_GP_FLASH_ENISP_GP_FLASH_SET

ISP_GP_FLASH_INH

ISP_SENS_I2C_SCL

CLKN

DATAN

ISP_SENS_I2C_SDA

CLKP

DATAP

APP_I2C_SCLAPP_I2C_SDA

CI_DATA[6]CI_DATA[5]CI_DATA[4]

CI_DATA[2]CI_DATA[3]

CI_DATA[7]SYSCLK0

CI_HSYNCCI_VSYNC

CI_RES_n

CI_PCLK

5MCAM_RESET_N

ISP_SENS_MCLK


CAMERA FLASH LED

R80

610

0K

AGND4

1CT

2EN_SETFLEN

3 12FLGND

FLINH10

FLOUTA13

FLOUTB11

GND9

15G

_SL

UG

IN5

LX6

OUT87

PGND

14RSET

L8001u

U800 AAT1270IFO-T1

VA806EVLC14S02050

EVLC14S02050VA807

C8002.2u

VBAT

100K

R80

7

200K

R80

1

DNIC806

LD800

C80147n

2.2uC807


ISP_GP_FLASH_INH





Figure 3-2-5. VGA Camera (TCM9001MD)

(SMT type_VGA FPCB)

Figure 3-2-6. VGA Camera FPCB Interface with main board

51R904

CAM_DVDD_1V8

VDD15_1A5

VDD15_2E4

D2VSYNC

0.1uC913

DATA6C3D4

DATA7

A3DCLK

DVDDB6

B5EXTCLK

GND1A4

GND2C4

GND3E2E3

GND4

HSYNCD1

IOVDDA2

F1

PG

ND

C6PWRDWN

D3RESET

D6SCLSDA

C5

U901TCM9000MD

E5AVDD

B3DATA0

B1DATA1DATA2

B2

DATA3B4C1

DATA4DATA5

C2

C9000.1u

CAM_AVDD_2V8

0.1uC901

CI_PCLK

CI_RES_n

SYSCLK0

CI_DATA[0]CI_DATA[1]CI_DATA[2]CI_DATA[3]CI_DATA[4]CI_DATA[5]CI_DATA[6]CI_DATA[7]

CI_HSYNC

APP_GP_VGA_SDN


CI_VSYNC

PLUG

28

29

3

30

31

32

33

34

4

5

6

7

8

9

13

14

15

16

17 18

19

2

20

21

22

23

24

25

26

27

CN9011

10

11

12

CAM_DVDD_1V8

47R910

CAM_AVDD_2V8

CN9021

2

SPK_RCV-

SPK_RCV+

TOUCH_Y+

TOUCH_X+

TOUCH_X-

TOUCH_Y-

CI_DATA[1]

CI_DATA[5]

CI_DATA[3]

SPK_RCV-

SPK_RCV+

APP_I2C_SCL

APP_I2C_SDA

CI_RES_n

SYSCLK0

APP_GP_VGA_SDN

CI_DATA[0]

CI_DATA[7]

CI_DATA[6]

CI_VSYNC

CI_HSYNC

CI_PCLK

CI_DATA[2]

CI_DATA[4]




Table 3-2-1. Interface between Main board and 5M camera (in Main)

Table 3-2-2. Interface between VGA Camera FPCB and main board.

The 5M Camera modules are connected to 24-pin main board and VGA Camera module

is mounted to VGA FPCB and VGA FPCB is connected to 34-pin main board.

Its interface is dedicated camera interface port in DB3200. The camera port supply 24MHz master

clock to 5M ISP and 12Mhz Master clock to VGA module and receive 48MHz pixel clock(15fps) for ISP

and 9.5Mhz pixel clock(15fps) for VGA camera, vertical sync signal, horizontal sync signal, reset signal

and 8bits YUV data from camera module.

The camera module is controlled by I2C port.

Pin No. Symbol Description Pin No. Symbol Description

1 GND Ground 34 GND Ground

2 SYSCLK0 VGA MCLK 33 CAM_AVDD_2V8 Analog Voltage


4 TOUCH_X+ touch signal 31 CAM_DVDD_1V8 I/O & Digital Voltage

5 TOUCH_X- touch signal 30 CI_DATA[0] Parallel Data 0

6 TOUCH_Y+ touch signal 29 CI_DATA[1] Parallel Data 1

7 TOUCH_Y- touch signal 28 CI_DATA[2] Parallel Data 2

8 GND Ground 27 CI_DATA[3] Parallel Data 3

9 GND Ground 26 CI_DATA[4] Parallel Data 4

10 APP_GP_VGA_SDN VGA shutdown 25 CI_DATA[5] Parallel Data 5

11 APP_I2C_SDA I2C DATA 24 CI_DATA[6] Parallel Data 6

12 APP_I2C_SCL I2C Clock 23 CI_DATA[7] Parallel Data 7

13 CI_RES_n CAMERA RESET 22 CI_HSYNC horizontal sync

14 GND Ground 21 CI_VSYNC vertical sync

15 SPK_RCV+ speaker signal 20 GND Ground

16 SPK_RCV - speaker signal 19 CI_PCLK Camera Pixel clock






Figure 3-2-5. 1.8V and 2.8V Camera Regulator

APP_GP_ISP_LDO_EN enables 1.8V & 2.8V regulator for ISP. (ISP : 2.8V for anlalog, 1.8V for I/O and digital),

Figure 3-2-6. Camera Regulator for ISP

3.2.2 Camera Regulator

APP_GP_CAM_LDO_EN enables 1.8V & 2.8V Camera Regulator for both 5M and VGA Camera.

(5M : 2.8V for analog, 2.8V for AF VDD control, 1.8V for I/O, 1.8V for digital), (VGA : 2.8V for analog, 1.8V for I/O, digital)

CAM_AFVDD_2V8

5.6KR616

VBAT

C61

31u

0

R634

CAM_AVDD_2V8

1uC

611

NC1NC2

6

PG

ND

9

1VIN VOUT1

87

VOUT2

RT9011-MGPQWU601

EN12

EN23

GND54

CAM_DVDD_1V8C

612

1u 1uC

614

APP_GP_CAM_LDO_EN

VBAT

0

R635

R625

5.6K

ISP_DVDD_1V8

1uC6289

PG

ND

VIN1 8

VOUT1VOUT2

7

C6271u

U603 RT9011-MGPQW

2EN1

3EN2

5GNDNC1

46

NC2

1uC629

1uC630

ISP_AVDD_2V8

APP_GP_ISP_LDO_EN




3.2.3 Display & LCD FPC Interface LCD module include device in table 3-2

Device Type

Main LCD 240 RGB 400 262K Color TFT LCD

Main LCD Backlight 5 White LEDs

Table 3-2-3. Device in LCD Module

LCD Module is connected to Key FPCB with 40-pin Connector and key FPCB is connected to Main board with 50-pin connector.

The LCD is controlled by 8-bit PDI(Parallel Data Interface) in DB3200.

Table 3-2-4. LCD module Connector

Close to ABBR62

810

K

C625 47n

G2

10

INOUT_A11

2INOUT_A2

INOUT_A33

4INOUT_A4

9INOUT_B1

INOUT_B28

7INOUT_B3

INOUT_B46

9

8INOUT_B2

INOUT_B37

6INOUT_B4

FL601

EVRC14S03Q030050R

5G

1

EVRC14S03Q030050R

FL602

5G

1

G2

10

1INOUT_A1

INOUT_A22

3INOUT_A3

4INOUT_A4

INOUT_B1

R610 10K

R60

310

K

47nC626

LCD_AVDD_2V8

100ohmR627

INOUT_B37

6INOUT_B4

PRSB6.8C

D600

5G

110

G2

1INOUT_A1

INOUT_A22

3INOUT_A3

4INOUT_A4

INOUT_B19

8INOUT_B2

EVRC14S03Q030050R

FL600

DN

IR

611 Z

D60

5R

SB

6.8C

ST

2R

PR

SB

6.8C

ZD

601

FB604FB605

1uC

604

R626 100ohm

0

R62

1

PR

SB

6.8C

ZD

600

4.7K

R60

9

100K

R62

2

10K

R60

4

RS

B6.

8CS

T2R

ZD

606

LCD_DVDD_1V8

R60

8D

NI

VDDE_1V8

VA60

3IC

VS

0514

X35

0FR

10K

R60

7

VBAT

C60

51u

414243444546474849

5

50

6789

272829

3

30313233343536373839

4

401213141516171819

2

202122232425 26

51 52

53 54

1

1011

CN604

LCD_DATA[7]

LCD_DATA[3]

LCD_DATA[1]LCD_DATA[2]

LCD_DATA[0]

ONSWA_nKEYIN2

LCD_DATA[4]


WLED_PWR

WLED1

KEYIN0

CCO1

KEYOUT0

KEYOUT2

KEY_LED1

TRICKLE

LCD_VSYNC

LCD_RESET_N

APP_GP_LCD_IF1

WLED5WLED4WLED3WLED2

APP_GP_LCD_ID

KEYOUT1

KEYIN3

MIC1P

LCD_RD_N

LCD_RS

LCD_WE_N

LCD_CS_N

KEY_LED2

MIC1N





3.2.4 LCD Module Block diagram

Figure 3-2-9. LCD Module Block diagram

Data(0~7)




3.2.5 LCD Backlight IlluminationThere are 5 white LEDs in LCD Backlight circuit which is driven Charge Pump(AAT3169).

APP_GP_BL_EN is used for Backlight brightness control.

3.2.6 Keypad IlluminationThere are 4 side view white LEDs in Main board backlight circuit, which are driven by LED1, LED2 port from

AB3100.

Figure 3-2-11. Keypad Backlight LED Interface and Backlight Circuit

Figure 3-2-10. SUB PMIC Circuit LCD Backlight

0R631

0

R62

9

100K

R63

0

C6351u

C63

31u

VBAT

1uC

632

C634

10GND

9IN

OUTCP6

PGND15

1u

U604 AAT3169IFO-T1

C1+4

5C1-

C2+7

C2-8

11D1D2

1213

D314

D41

D52

D6

EN_SET3


APP_GP_BL_EN

WLED_PWR

WLED1

LD1003

SSC-TWH104-HL

VB

AT

SSC-TWH104-HL

LD1001

LD1002

SSC-TWH104-HL

LD1000

SSC-TWH104-HL

KEY_LED2

KEY_LED1

B4

LE

D1_

NA

4L

ED

2_N

D3

LE

D3_

NC

3

KE

Y_L

ED

2K

EY

_LE

D1





3.3. Audio Part

3.3.1 Audio Part Block Diagram

Figure 3-3-1. Audio Part Block Diagram

3.3.2 Audio Signal Processing & Interface

Audio signal processing is divided Uplink path and downlink path.

The uplink path amplifies the audio signal from MIC and converts this analog signal to digital signal

and then transmit it to DBB Chip (DB3200).

This transmitted signal is reformed to fit in GSM & WCDMA Frame format and delivered to RF Chip.

The downlink path amplifies the signal from DBB chip (DB3200) and outputs it to Receiver (or Speaker).

The audio interface consists of PCM encoding and decoding circuitry, microphone amplifiers and

earphone drivers.

The PCM encoder and decoder blocks are two-channel, 16-bit circuits with programmable gain

amplifiers (PGA).

The decoder has a receive volume control. The audio inputs and outputs can be switched to normal or auxiliary ports.




Figure 3-3-2. Audio Interface Detailed Diagram(AB3100)

Figure 3-3-3 . Audio Section scheme

1%

Audio Subsystem

Audio Subsystem

1%

C343

B3

B1

VD

D

A3

VS

S

18000p

A4

C1PA5

D3

GN

D

HPLA2

HPRA1

INA1D2

INA2D1

C2INB1

C1INB2

D5OUT+

B5OUT-

C4

PG

ND

C5

PV

DD

RXIN+D4B4

RXIN-

SCLC3

SDA

MAX9877AEWP_TG45U301

B2BIAS

C1N

C342 1u

C3340.1u

C3541u

C3331u

15R323

VA30

0IC

VL

0505

101V

150F

R

VBAT

15R322

C332

1u

C35

322

p

C33

61u

C35

222

p

C339 1u

VA30

1IC

VL

0505

101V

150F

R

18000pC344

C338 1u

HS_EAR_L

HS_EAR_R

SPK_RCV-

SPK_RCV+

AMP_I2C_SCLAMP_I2C_SDA

EAR_REAR_L

SPKRPSPKRN

BEARPBEARN

Main MIC

C100047p

3

O4

P1

MIC100

SPU0410HR5H-PB

G12

G2

CCO1

MIC1NMIC1P





3.3.3 Audio Mode

Audio Mode includes three states.( Voice call, Midi.MP3).

Each states is sorted by the total 7 Modes according to external Devices

(Receiver,Loud Speaker,Headset).

Video Telephony Mode Operate on state of the WCDMA CALL.

Table 3-3-1. Audio Mode

Voice call

MIDI

MP3

Receiver Mode

Loud Speaker Mode

Headset Mode

Video Telephony Mode

Only Loud Speaker

Loud Speaker Mode

Headset Mode

ModeAB3100 In /Out Port

OUTIN

MIC1P/MIC1N BEARP/BEARN

SPKRP/SPKRN

AUXO1/AUXO2

AUXO1/AUXO2

MIC1P/MIC1N

MIC1P/MIC1N

MIC2P/MIC2N

SPKRP/SPKRN

SPKRP/SPKRN

SPKR/SPKN




3.3.4 Voice Call

A. Voice call Downlink Mode(Receiver, Speaker, Headset)

Figure 3-3-4. Voice call Downlink Scheme

This section provides a detailed description of the Voice Call RX functions.

The voice decoder accepts a serial input stream of linear PCM coded speech. The receive band-pass filter is the next step in the CODEC receive path. Following the filter is the DAC, followed by a PGA enabling to adjust or trim the circuit in the product for different sensitivity of the earphone and spread in the RX path. The final step in the receive path is the auxiliary output. The auxiliary audio amplifier is intended to drive low impedance headphones. The earphone amplifier and the auxiliary audio outputs can be powered down (muted) via I2C. Both the earphone driver and one of the auxiliary drivers can simultaneously provide an output signal during voice decoding.

• Receiver Mode : BEARP/N Port Receiver(32Ω)

• Loud Speaker / Video Telephony Mode : AB3100 SPK Amp SPKR/N

AUDIO AMP(TPA6205) Speaker(8Ω)

•Headset Mode : Auxiliary audio amplifier AUXO1/2

AUDIO AMP(MAX9724D) Head Phone





This section provides a detailed description of the Voice Call TX functions.

Figure 3-3-5. Voice call Uplink Scheme

B. Voice Call Uplink Mode (Receiver,Speaker,Headset)

From the audio path view point, voice call has the same structure as video telephony. The TXMIX connection enables insertion of audio into the uplink audio path. This can, for example, be used to play dictation recordings for the listener at the other party, in a voice call or video telephony call. The connection to TXMIX from the Audio Mixer must be performed in 8 kHz mono, since this is supported by the Voice mode. Due to performance reasons it may not be possible to decode every audio format during video telephony.

Each Voice Uplink Mode paths shown below.

Receiver Mode : C-MIC(SPM0410LR5H) AB3100 Input(MIC1N/1P)Loud Speaker Mode : C-MIC(SPM0410LR5H) AB3100 Input(SPK1N/1P)Video Telephony Mode : C-MIC(SPM0410LR5H) AB3100 Input(MIC1N/1P)Headset Mode : Headset MIC Analog Switch(FSA201) AB3100 Input(AUXI1N/1P)




3.3.5 MIDI (Ring Tone Play)

This section provides a detailed description of the MIDI and WAV-file functions.

Figure 3-3-6 External MIDI path

3.3.6 MP3 (Audio Player)

This section provides a detailed description of the MP3 file functions.

Figure 3-3-7. MP3 Scheme

MP3 function supports PCM 44/48KHz sampling rate.The PCM44/48 RX-path is intended to be used as a audio amp and one speaker.

In Figure 2-4-6, External MIDI path is the same as Voice Loudspeaker downlink Mode ,

except source in DB3200 (DSP and Audio Mixer).

MIDI : DB3200 PCM Decoder Auxiliary audio amplifier SPKRP/N Port

AUDIO AMP(TPA6205A) Speaker(8Ω)





3.3.7 Video Telephony

This section provides a description of the Video Telephony functions.

Figure 3-3-8. Video Telephony Scheme

Video Telephony Mode has same paths with Loud Speaker Mode.

3.3.8 Audio Main Component

There are 4 components in GT500 schematic Diagram. Part Number marked on GT500 Schematic

Diagram.

Table 3-3-2. Audio Component List

MaximMAX9877AEWP_TG45Audio Amp3

I-soundSGEY0003741Ear-jack SET4

KNOWLES ACOUSTICSSPU0410HR5H-PBMIC2

Ki-RinSUSY0027506Speaker/Receiver1

MAKERPART NUMBERITEMNO




3.4 GPADC (General Purpose ADC) and AUTOADC2

The GPADC consists of a 14 input MUX and an 8-bit ADC. The analog input signal is selectedwith the MUX and converted in the ADC. The GPADC has a built in controller, AUTOADC2, which is able to operate in the background without software intervention. The AUTOADC2 periodically measures the battery voltage or current. (Fig.2-4-1) shows the schematic of GPADC part. The GPADC channel spec is as following (Table 2-4-1).

Fig 3-4-1. Schematic of GPADC and AUTOADC2

ADC 2 channels

Resource Name Description

GPA3 PCB_VERSION HW PCB Version check

GPA7 VBACKUP Backup battery

Table 3-4-1. GPADC channel spec

Fig 3-4-2. GPADC and AUTOADC2 Block diagram

GPA

2C

9

B8

GPA

3A

8G

PA4

C8

GPA

5G

PA6

D8

GPA

7B

7

GPA

0A

9

GPA

1B

9

GPA

12C

7

TP

300

PC

B_V

ER

SIO

NT

ES

TOU

TR

TE

MP

VB

AC

KU

P





Name Type Unused Description

CHS+ Analog VBAT Current sensing input positive

CHS- Analog VBAT Current sensing input negative

Table 3-5-1. Charger Control channel spec

Fig. 3-5-1. Battery charging circuit

3.5 Charger control

A programmable charger in AB3100 is used for battery charging. It is possible to set limits for the output voltage at CHS- and the output current from DCIO via the sense resistor to CHS-. The voltage at CHS- and the current feed to CHS- cannot be measured directly by the GPADC. Instead, the two measuring amplifiers translate these inputs to a voltage proportional to the input and within the range of the GPADC. (Fig.3-5-1) shows the schematic of charging control part.

Direction of BAT and GND

Charging

Route as a differential pair

Phone ground return path

USB charging path

Discharging


Make an Area at 8, 9 Layer

Causion when PCB lLayout

Charging Circuit

22pC337

VDDC_2V65

VBUS

VDDE_1V8

2

C1

1

D302

KDS221E_RTK

A1_C2

3A2

0.1uC346 C347

1u

VBAT_H

1/4WR324

VBAT

2012

1% 0.025

VBAT

M7

VS

S_S

PK

RV

SS

_BE

AR

N5

VBUSE2

P13VDD_AUDIO

P3VDD_AUXO

VDD_BEARP6

VDD_IOA12

VDD_REFG1

VDD_SPKRP7

A13VREF

SRST_NM2

D12TEST

F2TRICKLE

VBAT_DG2

N3SDAT

B10

SPA

RE

1A

2S

PAR

E2

M1SCLK

IREFA14

H1CHSENSEP

DAC_CLKC4

DAC_DATC5

B5DAC_STR

F1DCIODCIO_INT

J2

J13FGSENSEN

J14FGSENSEP

BDATAA11

CHREGH3

H2CHSENSEND1

D2

D3

D4

G1

G2

S1

S2

Q300 SIA911DJ

0.1uC348

VA605varistor

C3490.1u

300KR320

C33022p

C33133u

D301 RSX101VA-30TR

C34

51u

1%1/4W2012

0.1R316

D1

D2

1 2 3

CN

300

1u

R317

VDD_REF

VBAT

R32

110

0K

R314

0 TRICKLE

FGS+

FGS-

VBUSCHS-

BDATA

FGS+

DCIO_INT

OTP

VBUS

CHREG

RF_CTRL_DATA

RF_CTRL_CLKRF_CTRL_STR_1

CHREG

DCIO_INT

FGS-

CHS+

CHS+

BDATA

CHS-

SRST_nSCLK

SDAT





FGS+ Analog VBAT Fuel gauge current sensing input positive

FGS- Analog VBAT Fuel gauge current sensing input negative

Table 3-5-2. Fuel Gauge channel spec

Fig. 3-5-2. The analog front-end of the fuel gauge block

Fig. 3-5-3 The Schematic of the fuel gauge block

3.5.1 Fuel Gauge

AB3100 supports the measurement of the current consumption/charging current in the GT500 with a fuel gauge block. By constantly integrating the current flowing into and out of the battery, the fuel gauge block is used to determine the remaining battery capacity. The function of the fuel gauge block is schematically described in (Fig.3-5-3). A sense resistor R_FGSENSE is connected in series with the battery. The voltage across the resistor, equivalent to the current entering/leaving the battery, is integrated using an ADC block.



1/4WR3242012

1% 0.025

FGS+

FGS-

SRST_NM2

VBAT_DG2

N3SDAT

M1SCLK

H1CHSENSEP

J13FGSENSEN

J14FGSENSEP

BDATAA11

CHREGH3

H2CHSENSEN

VA605varistor

VBAT

FGS+

FGS-

CHREG

CHS+

BDATA

CHS-

SRST_nSCLK

SDAT





3.5.2 Battery Temperature Measurement

The BDATA node, the constant current source, feed the battery data output while monitoring the voltage at the battery data node with GPADC. This battery data is converted to the battery temperature. (Fig.3-5-5) shows the schematic of battery temperature measurement part.


BDATA Digital Input/Output Unconnected current output

Table 3-5-3 BDATA channel spec

Fig 3-5-4. Battery Temperature Measurement

Disch

22pC337

2

C1

1

D302

KDS221E_RTK

A1_C2

3A2

300KR320

D1

D2

1 2 3

CN

300

BDATASRST_N

M2

N3SDAT

M1SCLK

J13FGSENSEN

J14FGSENSEP

BDATAA11

VA605varistor

FGS+

FGS-

BDATA

SRST_nSCLK

SDAT




3.5.3 Charging Part

The charging block in AB3100 processes the charging operation by using VBAT voltage. It is enabled or disabled by the assertion/negation of the external signal DCIO. Part of the charging block are activated and deactivated depending on the level of VBAT. (Fig.3-5-6) shows the schematic of charging part.

Fig. 3-5-6 Battery Block Indication

Fig. 3-5-5. Charging Part

When VBAT is below a certain value, 3.2V, a current generator take care of initial charging of the CHSENSE+ node and internal trickle charge signal is active. This part of the charging block is powered on and active when DCIO is asserted. The DCIO signal is asserted when its voltage is above the voltage at VBAT. As soon as generator is turned off and all parts of the charging block are functional and active.Battery block indication as shown in (Fig.3-5-7)

Fig. 3-5-6 Battery Block Indication

4.17 ~3.72 (V) 3.72 ~3.62 (V) 3.62 ~3.53 (V) 3.53 ~3.20 (V)

100~40 (%) 40~12 (%) 12~3 (%) 3~0(%)


Charging



USB charging path

Discharging




Charging Circuit

22pC337

VDDC_2V65

VBUS

VDDE_1V8

2

C1

1

D302

KDS221E_RTK

A1_C2

3A2

0.1uC346 C347

1u

VBAT_H

1/4WR324

VBAT

2012

1% 0.025

VBAT

M7

VS

S_S

PK

RV

SS

_BE

AR

N5

VBUSE2

P13VDD_AUDIO

P3VDD_AUXO

VDD_BEARP6

VDD_IOA12

VDD_REFG1

VDD_SPKRP7

A13VREF

D12TEST

F2TRICKLE

VBAT_DG2

N3SDAT

B10

SPA

RE

1A

2S

PAR

E2

SCLK

IREFA14

H1CHSENSEP

DAC_CLKC4

DAC_DATC5

B5DAC_STR

F1DCIODCIO_INT

J2

J13FGSENSEN

J14FGSENSEP

BDATAA11

CHREGH3

H2CHSENSEND1

D2

D3

D4

G1

G2

S1

S2

Q300 SIA911DJ

0.1uC348

VA605varistor

C3490.1u

300KR320

C33022p

C33133u

D301 RSX101VA-30TR

C34

51u

1%1/4W2012

0.1R316

D1

D2

1 2 3

CN

300

1u

R317

VDD_REF

VBAT

R32

110

0K

R314

0 TRICKLE

FGS+

FGS-

VBUSCHS-

BDATA

FGS+

DCIO_INT

OTP

VBUS

CHREG

RF_CTRL_DATA


CHREG

DCIO_INT

FGS-

CHS+

CHS+

BDATA

CHS-

SCLKSDAT





Trickle charging

When the VBAT is below a certain value, 3.2V, a current generator take care of internal trickle charge signal is active. The charging current is set to 50mA.

Table. 3-5-4. Trickle charging spec

Parameter Min Typ Max Unit

Trickle current 30 40 60 mA

Normal charging

When the VBAT voltage is within limits or the internal regulators are turned on, the current source for trickle charging is turned off and all parts of the charging block are active. The charging method is ‘CCCV’. (Constant Current Constant Voltage)This charging method is used for Lithium chemistry battery packs. The CCCV method regulates the charge current and the VBAT voltage. This charging method prevents the battery voltage to go above the charge set in the CCCV algorithm. (Fig.3-5-8) shows the charging voltage and charging current change.

Fig. 3-5-7. CCCV charging method




• Charging Method : CCCV (Constant Current Constant Voltage)• Maximum Charging Voltage : 4.2V• Maximum Charging Current : 700mA• Nominal Battery Capacity : 950 mAh• Charger Voltage : 5.1V• Charging time : Max 3.5h• Full charge indication current (icon stop current) : 80mA• Low battery POP UP : Idle - 3.43V, Dedicated – 3.43V• Low battery alarm interval : Idle - 3 min, Dedicated - 1 min• Cut-off voltage : standby : 3.25V, Call : 3.25V

Charging of Extended Temperature

When the battery temperature is outside the normal charging specification, the battery voltage, VBAT, is maintained at 3.7V.

• Under 0 °C : Extended temperature• From 0 °C to 45 °C : Normal charging temperature• Over 45 °C : Extended temperature





3.6. Voltage Regulation

The LDO regulators and the BUCK converter generate a range of programmable voltages, each optimized for its load. When the analog baseband controller boots up or down, internal signals activate or deactivate the LDO regulators and the BUCK converter. In active mode, the LDO regulators and the BUCK converter are activated and deactivated through I2C. The low power regulator is on all the time and has extremely low power consumption with limited output current. It provides power for the 32 kHz oscillator and the real-time clock (RTC).

Table. 3-6-1. LDO and Buck

LDO Net Name Output Voltage Output Current UsageLDO_A VDDA_2V8 2.8V 150mA RF TranceiverLDO_D VDDD_2V65 2.65V 200mA AB3100 analog

VDDE_1V8 1.8V Memory, I/OVDIGRAD_1V8 1.8V RF3300 Digital

LDO_C VDDC_2V65 2.65V 200mA AB3100 Audio BlockLDO_H VDDH_2V75 2.75V 200mA 3Axis

LDO_F VDDF_2V5 2.5V 30mA DB3200 analogLDO_G VDDG_2V85 2.85V 100mA SD card, LCDLDO_K VDDK_2V75 2.75V 200mA BluetoothLDO_LP VBACKUP 2.2V 6.5mA Backup Battey

BUCK VCORE 1.2V 600mA DB3200 core

200mALDO_E




Figure 3-7-1. Block diagram of RF part

3.7.1. General Description

The RF platform of GT500 supports two different communication modes (WCDMA/GSM modes) including four communication bands (WCDMA2100/WCDMA900/GSM850/900/1800/1900). The all the RF blocks can be divided into three main parts, which are a WCDMA part, a GSM, and a RF front-end. Different from other general solutions, the RF front-end of GT500 consists of an antenna switch and an EDGE power amplifier module (PAM). The simplified block diagram is shown in Figure 3-7-1.

3.7. RF Technical Description

3.7.2. WCDMA Part

The W-CDMA transceiver uses differential analog in-phase and quadrature-phase interfaces, that is an IQ-interface, both in the receiver and transmitter information path. The transceiver has the following general features: . Power class : Power class 3 (+24dBm) in Band I. Power class : Power class 3 (+24dBm) in Band VIII. Zero-IF Receiver.No IF filter needed . Direct IQ modulation transmitter

U330

GSM/EDGEPA + Ant Sw.

ANT

VAPC

RADCLK

RADDAT

RADSTR

VBAT

2.75 VVRAD

1.8 VVIO

PA

PA

GSM850/900 Input

DCS/PCSInput

ESD

2.75 VVRAD

LNA

LNA

LNA

LNA

LNA

AD

AD

090

LPF+ ChP PhD

÷N.M

VCO

LPF ChP PhD

÷N.M

+ 090

+

DAC

DAC

XO

DAC

VCO

VCO

LNA

LNA

WCDMA LB

WCDMA HB

WCDMA HB

WCDMA HB

CLK

DATA

STROBESerial

Control

WTxQB

WTxQA

WTxIB

WTxIA

GSM/EDGE

AM

DAC

RFCtrl1

RFCtrl2

RFCtrl1

RFCtrl2

GSM/EDGE HB

GSM/EDGE LB

WCDMA LB

WCDMA HB

WCDMA HB

GSM/EDGELB

GSM/EDGELB

GSM/EDGEHB

GSM/EDGEHB

WRxIA

WRxIB

WRxQB

WRxQA

EDataA

EDataB

EDataC

EDataStr

WCDMA/GSM/GPRS/EDGE TRX

MCLK

CLKREQ

MCLKSec

XOXOn

XOp

26MHzX-tal

VBAT

VccWPA

VccWPA

Powercoupler

Powercoupler

VccWPA

VccWPA

RF Pow det

DetEn

BiasDET En

BiasDET En

BiasDET En

UL: 1920 – 1980 MHzDL: 2110 – 2170 MHz

UL: 1749.9 – 1784.9 MHzDL: 1844.9 – 1879.9 MHz

UL: 830 – 840 MHzDL: 875 – 885 MHz

824 – 915 MHz

1710 – 1910 MHz

1930 – 1990 MHz

1805 – 1880 MHz

925 – 960 MHz

869 – 894 MHz

WDCDCREF

WPOW_DET_EN

FB

Switch

PWM/PFM

En

ControlLogic

RFCtrl1





Figure 3-7-2. WCDMA Transmitter Architecture

3.7.2.1. Transmitter Part

The W-CDMA transmitter architecture is an on frequency linear direct up-conversion IQ-modulator. The TX IQ modulator has differential voltage I and Q inputs. It converts input signals to RF output frequency and is designed to achieve LO and image suppression. The in-phase and quadrature-phase reconstruction filters are fully integrated and a programmable gain amplifier implements the gain control. The transmit output stage provides at least +5 dBm at maximum power control at the single-ended 50 Ωoutput. Gain is set through the 3-wire bus. An external SAW filter between the W-CDMA circuit and the power amplifier is used to improve noise performance. Two 10-bit DACs are used to control the DC/DC converter and the PA gain. After the power amplifier, the signal is sent through an isolator and through the duplex filter, which directs the transmit signal to the antenna connector through the antenna switch. The supply voltage and bias of the power amplifier are adapted depending on the output power to achieve high efficiency at every transmitter power level. A high efficiency DC/DC converter regulates the supply voltage and the bias operation point is controlled by a D/A-converter in the W-CDMA radio circuit. These DACs are controlled through the 3-wire-bus


ANT

VAPC

RADCLK

RADDAT

RADSTR

VBAT

2.75 VVRAD

1.8 VVIO

PA

PA

GSM850/900 Input

DCS/PCSInput

ESD

2.75 VVRAD

LNA

LNA

LNA

LNA

LNA

AD

AD

090

LPF+ ChP PhD

÷N.M

VCO

LPF ChP PhD

÷N.M

+ 090

+

DAC

DAC

XO

DAC

VCO

VCO

LNA

LNA

WCDMA LB

WCDMA HB

WCDMA HB

WCDMA HB

CLK

DATA

STROBESerial

Control

WTxQB

WTxQA

WTxIB

WTxIA

GSM/EDGE

AM

DAC

RFCtrl1

RFCtrl2

RFCtrl1

RFCtrl2

GSM/EDGE HB

GSM/EDGE LB

WCDMA LB

WCDMA HB

WCDMA HB

GSM/EDGELB

GSM/EDGELB

GSM/EDGEHB

GSM/EDGEHB

WRxIA

WRxIB

WRxQB

WRxQA

EDataA

EDataB

EDataC

EDataStr


MCLK

CLKREQ

MCLKSec

XOXOn

XOp

26MHzX-tal

VBAT

VccWPA

VccWPA

Powercoupler

Powercoupler

VccWPA

VccWPA

BiasDET En

DET

BiasDET En

UL: 1920 – 1980 MHzDL: 2110 – 2170 MHz

UL: 1749.9 – 1784.9 MHzDL: 1844.9 – 1879.9 MHz

UL: 830 – 840 MHzDL: 875 – 885 MHz

824 – 915 MHz

1710 – 1910 MHz

1930 – 1990 MHz

1805 – 1880 MHz

925 – 960 MHz

869 – 894 MHz

WDCDCREF

FB

Switch

PWM/PFM

En

ControlLogic

RFCtrl1




Figure 3-7-3. WCDMA Receiver Architecture

3.7.2.2. Receiver Part

The W-CDMA receiver architecture is a direct down-conversion Zero Intermediate Frequency (ZIF) receiver with integrated low-pass channel filter, i.e. the front-end receiver converts the aerial RF signal from W-CMDA band I down to a ZIF. The first stage consists of one single-ended low noise amplifier (LNA) with a 16 dB gain step. This LNA is followed through an external filter by an IQ down-mixer which consists of a mixer in parallel driven by quadrature out-of-phase LO signals. The In phase (I) and Quadrature phase (Q) ZIF signal are then low pass filtered to provide protection from high frequency offset interferer fed into the channel filter. The front-end zero IF I and Q outputs are applied to the integrated low-pass channel filter with a provision for 4 x 8 dB gain steps in front of the filter. The filter is a self-calibrated 6 pole, 2 zero filter with a cut-off frequency around 2.15 MHz and a second order group delay compensation (2 poles, 2 zeroes). Once filtered,the zero IF I and Q signals are further amplified with provision of 31 x 1 dB steps and DC offset compensation. The zero IF output buffer provides close rail-to-rail outputs signal.


ANT

VAPC

RADCLK

RADDAT

RADSTR

VBAT

2.75 VVRAD

1.8 VVIO

PA

PA

GSM850/900 Input

DCS/PCSInput

ESD

2.75 VVRAD

LNA

LNA

LNA

LNA

LNA

AD

AD

090

LPF+ ChP PhD

÷N.M

VCO

LPF ChP PhD

÷N.M

+ 090

+

DAC

DAC

XO

DAC

VCO

VCO

LNA

LNA

WCDMA LB

WCDMA HB

WCDMA HB

WCDMA HB

CLK

DATA

STROBESerial

Control

WTxQB

WTxQA

WTxIB

WTxIA

GSM/EDGE

AM

DAC

RFCtrl1

RFCtrl2

RFCtrl1

RFCtrl2

GSM/EDGE HB

GSM/EDGE LB

WCDMA LB

WCDMA HB

WCDMA HB

GSM/EDGELB

GSM/EDGELB

GSM/EDGEHB

GSM/EDGEHB

WRxIA

WRxIB

WRxQB

WRxQA

EDataA

EDataB

EDataC

EDataStr


MCLK

CLKREQ

MCLKSec

XOXOn

XOp

26MHzX-tal

VccWPA

VccWPA

Powercoupler

Powercoupler

VccWPA

VccWPA

BiasDET En

DET

BiasDET En

UL: 1920 – 1980 MHzDL: 2110 – 2170 MHz

UL: 1749.9 – 1784.9 MHzDL: 1844.9 – 1879.9 MHz

UL: 830 – 840 MHzDL: 875 – 885 MHz

824 – 915 MHz

1710 – 1910 MHz

1930 – 1990 MHz

1805 – 1880 MHz

925 – 960 MHz

869 – 894 MHz

WDCDCREF

FB

Switch

PWM/PFM

En

ControlLogic

RFCtrl1





3.7.2.3. Synthesizer

WCDMA Transmitter Synthesizer

All RF frequencies are generated in the WCDMA Tx 4 GHz VCO, subsequently divided by2 or 4 to arrive at the final frequency.The WCDMA Tx RF-VCO is locked to the XO in a fractional N PLL consisting of a prescaler, a phase frequency detector, a charge-pump, a sigma-delta modulator, and a fully integrated loop filter.Automatic trimming of the VCO center frequency and the RC constant ensures that the variation of the PLL dynamics is sufficiently low.

GSM/EDGE and WCDMA Receiver Synthesizer

All RF frequencies are generated in either of the two 4 GHz VCOs, subsequently divided by 2 or 4 (depending on final frequency). The selection of either of the two VCOs is done using the digital bus.The selected RF-VCO is locked to the XO in a fractional N PLL consisting of a prescaler, a phase-frequency detector, a charge-pump, a sigma-delta modulator, and a fully integrated loop filter.Automatic trimming of the VCO center frequency and the RC constant ensures that the variation of the PLL dynamics is sufficiently low.

Figure 3-7-4. WCDMA Transceiver schematic

RF TRANCEIVER

TEMP SENSOR

closed to RF3300

0R162

C178 33p

R16

8D

NI

R166 0

L120NA

VDDA_2V8

R1283.9nH

22p

C16

7

4.3nH R125

C164 15p

WTXHB129

WTXHB233

WTXHB331

WTXIN24

35WTXLB

23WTXLP

WTXQN2625

WTXQP

XON1718

XOP

MCLKSEC20

57PGND

37RFCTRL1RFCTRL2

36

STR10

13TESTOUT

27VCCA1VCCA2

51

VCCD21

WRXHB138

WRXHB242

3WRXINWRXIP

4

WRXLB40

1WRXQNWRXQP

2

16G

ND

1019

GN

D11

GN

D12

22

GN

D13

28 30G

ND

1432

GN

D15

34G

ND

16

GN

D2

53

GN

D3

49

GN

D4

47 45G

ND

543

GN

D6

41G

ND

739

GN

D8

5G

ND

9

MCLK15

CLK12

14CLKREQ

11DATA

52EAMMOD

8EDATAAEDATAB

9

EDATAC6

EDATASTR7

48ERXHB1

50ERXHB2

ERXLB144

ERXLB246

56ETXHB

54ETXLB

GN

D1

55

U111RF3300

0

R151

DN

IC

191

L118 10nH

DN

IR

139

1800FB100R124 390

33p

C16

0

R13

627

0

2.2nHL106

270

R13

1

DN

IR

148

OUT

FL107SAFEA1G88KB7F00

G1

2

G2

5

G33

IN1 4

R15

0D

NI

C18

110

0p

NAL114

L105NA

NAL109

DN

IC

187

PT

100

4.7K

C16

5D

NI

NAL112

DN

IC

189

R13

227

0

DNI

R145

27R134

VDIGRAD_1V8

C16

9D

NI

DN

IR

159

0 R133

DN

IR

158

3.9pC159

DN

IR

164

C179

10nH

2 GND1

GND24

1HOT1

HOT23

26MHzTN4-26562

X100

8.2nHL110

VRAD_2V8

DN

I

R12

7

2.7p

C17

0

10nHL113

GND5GND610

IN_881_51

IN_942_54

OUT_881_59

6OUT_942_5

FL104

SAWEN881MBA0F25

GND12

GND27

3GND3

8GND4

5

R14

9D

NI

DN

IC

188

L1155.6nH

R143560

0R130

22p

C16

3

VDDA_2V8R129 27

0.01

uC

162

270

R13

7

A23 GND

5VCC

Y4

1 _OE

SN74LVC1G125DRLR

U108

3.3pC177

0

R161

5

G33

IN1 4

OUT

0R144

G1

3

G2 G3

5

1IN OUT

4

FL106SAFEB1G95KA0F00

G1

2

G2

SAFEB897MAM0F00FL105

2

0R157

VRAD_2V8

R142 18p

L1043.3nH

R14

6

4.7K

GND12

GND27

3GND3

8GND4

5GND5GND6

10

IN_1842_51

IN_19604

OUT_1842_59

6OUT_1960

FL103

SAWEN1G84BC0F25

DN

IC

161

R14

1D

NI

DN

IC

185

DN

IR

155

R165

0

3.3pC172

0R152

C16

60.

01u

DN

IR

138

560R123

39nH L116

L1172.2nH

R140

C180

0

DNI

1.8pL119

DN

I

R15

3

R12

6

0

NAL107

L111NA

WRX_BAND_1

WRX_BAND_2

WRX_BAND_8_5

TX_ADC_STRB_2V8

WTX_BAND_2_TO_PA

WTX_BAND_1_TO_PA

TX_ADC_STRB

MCLKSEC

GRX_1800

GRX_850

GRX_900

GTX_1800_1900

GTX_850_900

MCLK

WTX_BAND_8_5_TO_PA

WTX_I_NWTX_I_P

WTX_Q_P

TX_ADC_STRB_2V8

GRX_1900


AMP_FREQ_LSBDATA_STR

WDCDC_EN

WRX_I_NWRX_I_P

WRX_Q_NWRX_Q_P

ADOUT

RTEMP

RF_CTRL_CLK

RF_CTRL_DATA

WTX_Q_N

RF_CTRL_STR_1

TESTOUTMCLKREQ

GTX_VAM




3.7.2.4. Power Amplifier Module

The SKY77182 Power Amplifier module is a fully matched 10-pad surface mount module developedfor Wideband Code Division Multiple Access (WCDMA) applications. This small and efficient power amplifier packs full coverage of the 1920–1980 MHz bandwidth into a single compact package.

The SKY77181 Power Amplifier module is a fully matched 8-pad surface mount module developed forWideband Code Division Multiple Access (WCDMA) applications. This small and efficient poweramplifier packs full coverage of the 880–915 MHz bandwidth into a single compact package.

Figure 3-7-5. SKY77182 Functional Block Diagram

Figure 3-7-6. SKY77181 Functional Block Diagram





Figure 3-7-8. WCDMA PAM schematic

3.7.3. WCDMA/EDGE/GPRS/GSM RF block

The transceiver is a multi-mode transceiver for WCDMA/EGDE/GPRS/GSM.The EDGE/GPRS/GSM part of the transceiver use a digital baseband interface that is shared between received and transmitted data. The receive interface is based on I and Q data and the transmitter interface is based on envelope and frequency data.The WCDMA part of the transceiver use differential analog in-phase and quadraturephase interfaces, that is an IQ-interface, in the receiver and the transmitter data paths.The EDGE/GSM/GPRS part of the transceiver has the following general features:

• Power class

- GMSK low bands: Class 4 (33 dBm)- GMSK high bands: Class 1 (30 dBm)- 8PSK low bands: Class E2 (27 dBm)- 8PSK high bands: Class E2 (26 dBm)- WCDMA: class 3 (+24dBm)

WCDMA PA Block

R12

0

24

L100

18p

C12

222

p

C1581000p

NAC117

0.1u

7GND4

8GND5

9GND6

1RX

TX3

C101

1OUT

4TER

FL100 SAYFP1G95AA0B00

ANT6

GND12

GND24

GND35

U103 LDC151G8620Q-359

COU3

IN2

3.6nHC124

GND312

14GND4IN_BAND_2

2

6IN_BAND_5

13OUT_BAND_2

OUT_BAND_59

PGND15

10VBIAS

VC211

4VCC1

VCONT5

VEN_BAND_21

7VEN_BAND_5

SKY77175U105

3GND1

GND28

C13

8D

NI

22p

DN

IC

151

C12

1

C1430.5p

C1151000p 1000p

C116

C133 DNI

56

R11

7

0.1uC154

GND3GND4GND5GND6

RX

TX

ACMD-7407FL101

ANT

GND1GND2

DA

P7

4ENGND

3

OUT6

5REF

2RF_IN

VDD1

U100 LMV221

U104

3COU

2IN

OUT1

TER4

100pC135

LDC151G8620Q-359

1000

pC

137

8

VCONT3

VEN4

DN

I

R11

3

U107 SKY77181

GND15

GND26

PGND9

2RF_IN

7RF_OUT

VBIAS1

VCC

R12

1

56

GND2GND3GND4

GND5GND6

RX

TX

LT56BFL102

ANT

GND1

C10633nF

0.1uC149

C14

222

p

C1501000p

1.8nH

VBAT

100pC146

L101

VBAT

100pC145

L1038.2nH

DNIC156

C1526.8nH

C119 100p

R10

0

DN

I

1000pC102

C118NA

0.1u

C134 100p

C110

0.1u

FC

120

R103

120

C147 22p

VBAT

C1571000p

R116 DNI

R10

4

75

C10

522

p

10uC148

R11

80

R10

9

56

RFIN6

RFOUT

4VBIAS VCC

5

VCTRL2

VENB1

10uC155

U102 SKY77182

7GND1

GND28

PGND9

3

C10

422

p

1000pC153

1K

R102

1000

pC

141

C12

7

VRAD_2V8VDDA_2V8

L60

12.

2nH

DN

I

C10

30.

1uF

DN

IC

123

COU32

IN

OUT1

TER4

U106 LDC15874M19Q-360

R652

0

C10010u

R10

7

10

1.5p

C12

8

0

R10

1

C63

63.

3nH

C11122p

C14

422

pD

NI

C13

6

WRX_BAND_1WTX_BAND_2_EN

WTX_BAND_2_TO_PA

WRF_BAND_1

WRF_BAND_2

WRF_BAND_8_5

VCC_WPA

BIAS_CTRL

BIAS_CTRL

WTX_BAND_1_EN

WTX_BAND_1_TO_PA

WPOW_DET_EN

WRX_BAND_8_5

WRX_BAND_2

WPOW_DET

WTX_BAND_8_5_EN

WTX_BAND_8_5_TO_PA

BIAS_CTRL




Figure 3-7-9. GSM Transceiver Architecture

3.7.3.1. Transmitter Part

Transmitter

There are two transmitter blocks, one for GSM/EDGE and one for WCDMA.

GSM/EDGE Transmitter Block

• A separate block is used to convert the digital bit streams from the baseband into parallel words to be used in the DACs and Sigma Delta modulator. This block also includes programmable delays for optimizing timing between the different modulation paths. A separate output is generated for the auto-tuning block of the second FM path. The block also outputs a low-frequency square wave to the FM paths, to enhance the speed of the auto tuning for the second FM path.


ANT

VAPC

RADCLK

RADDAT

RADSTR

VBAT

2.75 VVRAD

1.8 VVIO

PA

PA

GSM850/900 Input

DCS/PCSInput

ESD

2.75 VVRAD

LNA

LNA

LNA

LNA

LNA

AD

AD

090

LPF+ ChP PhD

÷N.M

VCO

LPF ChP PhD

÷N.M

+ 090

+

DAC

DAC

XO

DAC

VCO

VCO

LNA

LNA

WCDMA LB

WCDMA HB

WCDMA HB

WCDMA HB

CLK

DATA

STROBESerial

Control

WTxQB

WTxQA

WTxIB

WTxIA

GSM/EDGE

AM

DAC

RFCtrl1

RFCtrl2

RFCtrl1

RFCtrl2

GSM/EDGE HB

GSM/EDGE LB

WCDMA LB

WCDMA HB

WCDMA HB

GSM/EDGELB

GSM/EDGELB

GSM/EDGEHB

GSM/EDGEHB

WRxIA

WRxIB

WRxQB

WRxQA

EDataA

EDataB

EDataC

EDataStr


MCLK

CLKREQ

MCLKSec

XOXOn

XOp

26MHzX-tal

VBAT

VccWPA

VccWPA

Powercoupler

Powercoupler

VccWPA

VccWPA

RF Pow det

DetEn

BiasDET En

BiasDET En

BiasDET En

UL: 1920 – 1980 MHzDL: 2110 – 2170 MHz

UL: 1749.9 – 1784.9 MHzDL: 1844.9 – 1879.9 MHz

UL: 830 – 840 MHzDL: 875 – 885 MHz

824 – 915 MHz

1710 – 1910 MHz

1930 – 1990 MHz

1805 – 1880 MHz

925 – 960 MHz

869 – 894 MHz

WDCDCREF

WPOW_DET_EN

FB

Switch

PWM/PFM

En

ControlLogic

RFCtrl1





• The combined DAC and LP filter is used to convert the digital words of the digital block into analog signals. The LP filters are 3rd order Bessel reconstruction filters.• The second FM path is used to add the high-frequency part of the FM to the VCO. It also includes an auto-tuning block that compensates for VCO gain variations.• The AM block converts the differential voltage from the DAC to a single-ended output that drives the PA. The output is scaled according to the desired output power, and an offset can be added for PA linearization.• The Tx-buffer is used to drive the PA with the correct power level. A divide by 2 or 4 block is used to generate the correct output frequency from the 4 GHz VCO.

WCDMA Transmitter Block

The transmitter has differential voltage I and Q inputs. The IQ signal is filtered in a second order LP filter before it is up-converted to the RF in the direct IQ mixer. Automatic trimming of the filter RC constant ensures that the bandwidth variation is sufficiently low.The signal path is split in one low and three high band paths. The RF signal is amplified in a PGA, which is controlled by the 3-wire control bus. The low band and two of the high band transmit output stages provide +5 dBm (minimum) and the last high band output stage provide +7 dBm (minimum) at maximum power control. The output power is setthrough the serial bus.

3.7.3.2. Receiver part

Receiver

The receiver is a homodyne receiver with direct conversion of the received radio channel to baseband I and Q channels.The receiver block consists of multi-band front ends with separate LNAs, a common mixer and a common LP filter with configurable bandwidth.

GSM/EDGE Receiver

The front end block is followed by a baseband block with active anti-aliasing filters that also suppress blocking signals and interferers. Automatic trimming of the filter RC constant ensures that the bandwidth variation is sufficiently low. The baseband block is followed by a fully integrated ADC of sigma delta structure with high dynamic range. The analog signals are converted to digital bit-streams in a sigma delta converter. The digital output signals are sent over a serial interface to the digital baseband controller for further processing and detection.

WCDMA Receiver

The front end block is followed by a baseband block with active anti-aliasing filters that suppress blocking signals and interferers. Automatic trimming of the filter RC constant ensures that the bandwidth variation is sufficiently low. The baseband signal is amplified in a PGA, which is controlled by the 3-wire control bus. The PGA has a built in second order loop for DC-offset cancellation. The output of the receiver is analog differential I, Q signals.




3.7.4. Front-End Module (FEM)

A single antenna is used for all bands. The single antenna is used for all transmission and reception. The Front End block connects the proper block in the radio system to the antenna. The Front End has two inputs for EDGE/GSM/GPRS, one for low band (850/900 MHz) and one for high band (1800/1900 MHz). The EDGE/GSM/GPRS power amplifier output is filtered by the low pass filter in the Front End and then connected to the antenna through a switch. In receive mode, the EDGE/GSM/GPRS signal from the antenna passes through the switch to one of the four receive SAW filters. The SAW filter provides receiveband selectivity.

In GSM/GRPS/EDGE systems, transmit and receive operations are divided in time and the switch connects the proper block in accordance with the mode of operation (that is, transmit or receive; one at a time).In WCDMA the transmit outputs from the WCDMA transceiver are filtered by an external SAW filter that cleans up the spectrum. The SAW filter output is connected to the power amplifier, one for each band. For power control, a sample of the transmit output is taken by a directional coupler and converted to a DC level by the power detection circuit. This signal is used to control the transmitter output power. The transmit signal passes through an isolator and then a duplexer. The duplexer output is selected by the switch in the Front End for connection to the antenna. In WCDMA receive mode the signal from the antenna is switched by the Front End to the correct duplexer. The output from the duplexer is connected to the LNA input in the WCDMA receiver.

Figure 3-7-10. Front-End Module





3.7.4.1. Front End Part

SKY77521 is a transmit and receive Front End Module (FEM) designed in a very low profile (1 mm), compact form factor for quad-band cellular handsets comprising GSM850/900, DCS1800, and PCS1900 operation — a complete transmit VCO-to-Antenna and Antenna-to receive SAW filter solution. The FEM also supports Class 12 General Packet Radio Service (GPRS) multi-slot operation and EDGE Polar Modulation. WCDMA switch-through support is provided by three dedicated high-linearity ports.

Figure 3-7-12. Front End part schematic

Figure 3-7-11. SKY77521Functional Block Diagram

GSM PA WITH ASM

0R1140R115

0R112

33pC113

_TXEN8

LB_RF_IN3 9

MODE

PG

ND

131 32

PG

ND

2P

GN

D3

33 34P

GN

D4

RSVD10

RX11615

RX2RX3

1413

RX4

VAPC4

VBATT5

WCDMA11819

WCDMA2WCDMA3

20

BS176

BS2

GND12

27GND10GND11

2829

GND12GND13

30

11GND2GND3

1221

GND4GND5

22

GND623

GND72425

GND8GND9

26

1HB_RF_IN

SKY77521

U101

17ANT

C13

922

p

22pC112

VBAT

C14

022

p

DN

IR

106

R111 0 100pL102

KMS-518

SW100

AC G1

G2

C13

2D

NI

DN

IC

126

10u

C10

7

22pC114

47p

C10

9

C13

022

p

DNIR108

R105 0

22p

C12

9

22pC125ANT

G1G2

0.01

uC

108

SW101UFL-R-SMT10

WRF_BAND_2

WRF_BAND_1

GRX_1800GRX_1900

GTX_VAM

ANTSW3

ANTSW2

ANTSW0

ANTSW1

GTX_1800_1900GTX_850_900

WRF_BAND_8_5

GRX_850GRX_900




3.7.5. Control Flow

The access side of the digital baseband controller controls the overall radio system. In both EDGE/GSM/GPRS and W-CDMA air interface mode, the digital baseband controller controls the radio system through a three-wire serial bus. The digital baseband controller also manages PA band control and the antenna switch mechanism in the front end module. The 26 MHz VCXO clock residing in the GSM/EDGE transceiver is turned on only when required, the digital baseband controller initiates this. The EDGE/GSM/GPRS RF system requires control, which is temperature dependent. The temperature within the RF system is estimated by a voltage measurement performed by the analog baseband controller. The control flow for the RF system is shown in Figure 3-7-11.

Figure 3-7-13. RF Control Flow




4. TROUBLE SHOOTING

4. TROUBLE SHOOTING

4.1 Power ON Trouble

START

No

Change main board

changemain battery

Yes

Yes

No

No

The voltage of main battery

is higher than 3.3V ?

END key operates well?

UART_TX(TP1) level is 1.8V

when END key pressed.

Follow thekeypad Troubleshooting guide

Check the voltage.

VDDA_2V8 (TP2) 2.8V

VDDD_2V65 (TP3) 1.5V

VDDE_1V8 (TP4) 1.8V

VDDC_2V65(TP5) 2.65V

VDDH_2V75(TP6) 2.75V

VDDF_2V5 (TP7) 2.5V

VDDG_2V85 (TP8) 2.75V

VDDK_2V75(TP9) 2.75V

VCORE(TP10) 1.2V

TP2TP3 TP4

TP5

TP6 TP7

TP8

TP9

TP10

< Main Board – Bottom side >

4.1 Power ON Trouble 4.1 Power ON Trouble

TP802

TP800

TP804

TP801

TP803

OTP_SUB

APP_ACC_UART_TX

CTS_ON

VPPFLASH_E

APP_ACC_UART_RX

BLM18PG121SN1J

to RF3300 digital

120ohm 1608 2A 50mohm Bead

to Hall Switch and AB3100 BEAR

to All I/O Supplies and Memory

to RF3300 Power Detector

to SD Card and LCD

to Bluetooth

to AB3100 CODECs/ADC/PLL

2.8*2.6*1.0 0.7A 240mohm 20%

to DB3210 CORE

Parallel with VCORE

1608

to DB3100 analog

to 3xis

Local ground plane

VDDA_2V8

4.7uHL300

C309

VDDH_2V75 VDDF_2V5

1u

0R303

R304 0

R305 0

0R310

VCOREVBAT_C

R307 0

VBAT

2.2uC303

C3104.7u

C3042.2u

RB521S-30

VDDC_2V65

D300

C3111u

R312 0

10uC315

2.2uC307

0R302

R309 0

1uC312

C3022.2u

C3190.1u10u

C317C3140.1u

0R306

10u

VDDK_2V75

C318

4.7K

R311

VDDD_2V65 VBAT

VDDG_2V85

1u

FB300

C308

VDDE_1V8 VDIGRAD_1V8

0R308

VDDC_2V65

VDDH_2V75

VDDG_2V85

VDDF_2V5

VBAT

EXT_LDO

VDDD_2V65

VDDA_2V8

VCORE

VDDK_2V75

VDDE_1V8

VDIGRAD_1V8

VBACKUP

TP1

TP2

TP3TP4

TP5

TP6

TP7

TP8

TP9 TP10



4. TROUBLE SHOOTING

START(Connect a USB Cable from a PC)

Change main board

Yes

NoChange main board

Yes

ACC_GP_USB_CS(TP3) is 1.8V?No

Yes


TP1

TP2

Is it open statebetween USW_ID(TP1) & TP2?

Finish

TP3

4.2 USB Trouble 4.2 USB Trouble

If Maxim, then 4.7uF

TI : PD = USB,

MUIC

If TI, then 10nF

MAXIM : NA = U

C5094.7u

VBAT

DNIR507

ICC3

INT

B2

A2ISET

A1MIC

B1RES

SC

LC

2C

1S

DA

B3U1U2

A3B4

UID

VBD5

U501

D4AUD1

D3AUD2

D2BAT

CAPD1

COM1C5B5

COM2

A4DN1

A5DP2

GNDC4

MAX14526EEWP_TCC6

R508 DNI2

V

2.2K

R504

0R502USW_ID

USW_DMUSW_DP

10V

TP501

0R

655

51K

R50

0

TP500

RREF

STPD6

TESTC4

F4VBUS

VC

CF

3

B5VCC_IO1VCC_IO2

B2

F5XTAL1XTAL2

F6

B6C6

DATA7

E5DIR

DMC1D1

DPFAULT

E2

GN

D1

C5

D2

GN

D2

GN

D3

E4

D3ID

NC

1F

1F

2N

C2

D5NXT PSW_N

D4

E6REF1V8

E3REG3V3

C2

CFG0E1

B4CFG1CFG2

B3

CHIP_SELC3A4

CLOCKDATA0

B1A1

DATA1DATA2

A2A3

DATA3DATA4

A5A6

DATA5DATA6

ISP1508AETU502

C5130.1u

0.1uC500

4.7uC501

4.7uC512

VBAT





ACC_USB_HS_DIR

TP2




4. TROUBLE SHOOTING

SIM control path

- DB3200 generates SIM interface signals(1.8V level) to AB3100.

- AB3100 converts SIM interface signals to 3V.

SIM works well? Finish

START

Yes

Reconnect SIM card

Resolder J800 on main PCBand check the contact

between J800 and SIM card

Change Sub board

SIM works well? FinishYes

No

No

SIM works well? FinishYes

No

Change SIM card

< Sub Board >

J800

4.3 SIM Detect Trouble

5VPP

J800

3CLK

GND4

7GND1GND2

86

I_ORST

2VCC

1



4. TROUBLE SHOOTING

< Main Board - Top side >

S100

MicroSD works well?

START

Yes

Re-insert MicroSD card

Check operation of MicroSD card using other notebook or PDA

Change main board

MicroSD works well? FinishYes

No

No

MicroSD works well? Change the MicroSDNo

Yes

Re-insert MicroSD

Yes

No

Yes

VDDG_2V85 (TP1) is same to 2.85V?

Finish

Change Main board

Yes

NoAPP_GP_MMC_DETn(TP2) is same to 0 V? Change Main board

TP1 TP2

4.4 MicroSD card Trouble

HENSWA SWB

4

6

2

5

3

78

1

GND

R416 2.2




4. TROUBLE SHOOTING

4.5 Key and Touch Screen Trouble

4.5.1 Key Trouble

Key works well?

START

Yes

Press the key button

No

Change the key FPCB.

Finish

Change Main Board

Check key button.If Key button is pressed orappearance is abnormal,Change the key button.

works well?Yes

Finish

No

Check BtoB connector(CN2)Re-assemble CN2.

Check connector soldering.Re-solder CN2.

works well?Yes

Finish

No

works well?Yes

Finish

No

1

2



4. TROUBLE SHOOTING

Check key button.If Key button is pressed orappearance is abnormal,Change the key button.

1

Check BtoB connector(CN2)Re-assemble CN2.

Check connector soldering.Re-solder CN2.

2

CN2




4. TROUBLE SHOOTING

4.5.2 Touch Screen Trouble

Touch screen works well? Finish

START

Yes

Reboot the phone

Perform Touch Calibration

No

Touch screen works well? FinishYes

No

Check connector.CN400, CN901

Re-assemble or Re-solder.


No

1

Check U404, U405, U406 and peripheral circuit.

Re-solder U404, U405, U406 and peripheral circuit.


No

2

Change main board


No

Change touch window



4. TROUBLE SHOOTING

Check connector.CN400, CN901

Re-assemble or Re-solder.

1

Check U404, U405, U406 and peripheral circuit.

Re-solder U404, U405, U406 and peripheral circuit.

2

CN400

CN901

U405

U404

U406

Peripheral circuit




4. TROUBLE SHOOTING

4.6 Camera TroubleCamera control signals are generated by DB3200 with ISP

4.6.1 5M Camera

START

Press END Key

to turn on the power

Is the circuit powered?

Reconnect the 5M 24pin B to B connector

5M Camera’s Operation is OK?

Change 5M Camera

Follow the Power On Trouble

Shooting

YES

NO

YES

5M Camera Works

NO

Change U603

YES

NO

Pin8 of U603 or C627=2.8V?Pin7 of U603 or C628=1.8V?

1

2

Change Main Board



4. TROUBLE SHOOTING


CN600

U603

1 2

< Main Board – Top side >

C628

C627

pin8pin7

VBAT

0

R635

R625

5.6K

ISP_DVDD_1V8

1uC6289

PG

ND

VIN1 8

VOUT1VOUT2

7

C6271u

U603 RT9011-MGPQW

2EN1

3EN2

5GNDNC1

46

NC2

1uC629

1uC630

ISP_AVDD_2V8

APP_GP_ISP_LDO_EN

C627C628




4. TROUBLE SHOOTING

4.6.2 VGA Camera

VGA Camera control signals are generated by DB3200.

START

Press END Key


Is the circuit powered? Follow the Power On Trouble Shooting

YES

NO

YES

NO

NO

Pin31(TP3) of CN503) or pin 7 of U 601(TP4)=1.8V?Pin33(TP1) of CN503) or pin 8 of U 601(TP2) =2.8V?

2

C900(TP6)=1.8V?C901(TP5) =2.8V?

Reconnect the 34pin B to B connector

CN503 and VGA 34pin Camera Connector

VGA Camera Operation OK?

1

Change U601

Change VGA FPCBNO

YES

C913 (TP7) =1.5V?

NO

YES

Check the CN 901 soldering status And resolder the CN 901.

1

VGA Camera works well.

YES



4. TROUBLE SHOOTING

CN 503

CN901

Main board (Bottom)VGA CAM FPCB (Top)

1




4. TROUBLE SHOOTING

CN 503

1

34 18

17

TP1 (pin33) TP3(pin31)

Main board (Bottom)

2

TP2 (pin8)

TP4 (pin7)

U601

Main board (Top)

CAM_AFVDD_2V8

5.6KR616

VBAT

C61

31u

0

R634

CAM_AVDD_2V8

1uC

611

NC1NC2

6

PG

ND

9

1VIN VOUT1

87

VOUT2

RT9011-MGPQWU601

EN12

EN23

GND54

CAM_DVDD_1V8

C61

21u 1u

C61

4

APP_GP_CAM_LDO_EN

TP4

TP2



4. TROUBLE SHOOTING

TP5

TP6

VGA CAM FPCB(Bottom)

TP7

51R904

CAM_DVDD_1V8

VDD15_1A5

VDD15_2E4

D2VSYNC

0.1uC913

DATA6C3D4

DATA7

A3DCLK

DVDDB6

B5EXTCLK

GND1A4

GND2C4

GND3E2E3

GND4

HSYNCD1

IOVDDA2

F1

PG

ND

C6PWRDWN

D3RESET

D6SCLSDA

C5

U901TCM9000MD

E5AVDD

B3DATA0

B1DATA1DATA2

B2

DATA3B4C1

DATA4DATA5

C2

C9000.1u

CAM_AVDD_2V8

0.1uC901

CI_PCLK

CI_RES_n

SYSCLK0


CI_HSYNC

APP_GP_VGA_SDN


CI_VSYNC

TP5

TP6

TP7




4. TROUBLE SHOOTING

4.7 Main LCD Trouble

LCD control signals are generated by DB3200.

START

Press END Keyto turn on the power.

Is the circuit powered?

Is the R600 (TP1) 1.8V?And

Is the R601(TP2) 2.8V?

YES

NOFollow the Power On Trouble Shooting

Reconnect the LCD FPCB 50pin(CN2) and 40pin (CN1) LCD connector.

OrChange Key FPCB.

1

No

No

Change the U604

Yes

LCD display OK?

YES

Yes

LCD display OK?

Is the backlight on?

Is the backlight on?

Reconnect the LCD FPCB 50pin(CN2) and 40pin (CN1) LCD connector.

OrChange Key FPCB.

NO

No

The LCD works

2

YesYes

The LCD works

NoChange the U600

3

Is the LCD ID High? (CN1 Pin3 (TP3))

No Change LCD

Yes

IS the CN1 Pin11(TP4) Low?And

Is the CN1 pin 19(TP5) high?

5

NoChange

the mainboard

Yes

1

6



4. TROUBLE SHOOTING

Main board (Bottom)

Key FPCB

U604U600

1 CN 2

CN 1

2 3

Key FPCB 40 pin B to B Connector Key FPCB 50 pin B to B Connector




4. TROUBLE SHOOTING

CN 1

TP3 (pin3)

5

6

Key FPCB(Bottom)

U604

R600

R601

4

Main board (Bottom)

TP1

TP2

TP4 (pin11)

TP5 (pin19)

1

2021

40

LDO for LCD Power

C60

11u

0R

601

VOUT187

VOUT2

RT9011-MGPQWU600

EN12

EN23

GND54

NC1NC2

6

PG

ND

9

1VIN

1uC

603

R60

00

LCD_DVDD_1V8

R654 00R653

C60

21u

VBAT

LCD_AVDD_2V8

APP_GP_LCD_DLDO_ENAPP_GP_LCD_ALDO_EN

TP1

TP2



4. TROUBLE SHOOTING

4.8 Keypad Backlight Trouble

START

Press END Key


Keypad Backlight Works?

YES

NO

VBAT applied? (TP1) Change Main Board

NO

Check V at LD1000 or LD1001 or LD1002 or LD1003 is confirm

(TP2)

NOChange LD1000 or LD1001

Of LD1002 or LD 1003

YES

YES

YES

Keypad Backlight Works

Check V at R626(TP3)orR627(TP4) is confirm

NO

Change Key FPCB

1

1

2

Keypad Backlight Works




4. TROUBLE SHOOTING

TP1

Key FPCB(Top)

TP2

1

LD1003

SSC-TWH104-HL

VB

AT

SSC-TWH104-HL

LD1001

LD1002

SSC-TWH104-HL

LD1000

SSC-TWH104-HL

KEY_LED2

KEY_LED1TP1

TP1



4. TROUBLE SHOOTING

CN604

2

TP3 TP4

Main board (Bottom)




4. TROUBLE SHOOTING

4.9.1. Receiver

4.9 Audio Trouble Shooting

• Signals to the receiver

– Receiver signals are generated at AB3100

• BEARP, BEARN

– Receiver path :

• AB3100 (BEARP, BEARN)

• R322, R323 on main board

• Camera FPCB

• Receiver

Note : It is recommended that engineer should check the soldering of R, L, C along the corresponding path before every step.



4. TROUBLE SHOOTING

START

Connect the phone to network

Equipment and setup call.

Setup 1KHz tone out.

Does the sine wave appear

at TP1, TP2 ?Change the main board


at Number TP3, TP4

in the main B’d CN503?

Change U301


at EAR(+) PAD(TP5) in LCD FPCB?Change the Camera FPCB

Is the soldering of the

receiver OK?Resolder the Receiver

Can you hear sine wave

out of the receiver ?Change the Receiver

END

YES

YES

YES

YES

YES

NO

NO

NO

NO

NO

1

2

3

3

The sine wave not appear




4. TROUBLE SHOOTING

TP2

1

Main PCB Bottom

3

2

1

18

17

34

CN503

Main PCB Bottom

Camera FPCB Bottom

TP1

TP3 TP4

TP5

U301

1%

Audio Subsystem

Audio Subsystem

1%

C343

B3

B1

VD

D

A3

VS

S

18000p

A4

C1PA5

D3

GN

D

HPLA2

HPRA1

INA1D2

INA2D1

C2INB1

C1INB2

D5OUT+

B5OUT-

C4

PG

ND

C5

PV

DD

RXIN+D4B4

RXIN-

SCLC3

SDA


B2BIAS

C1N

C342 1u

C3340.1u

C3541u

C3331u

15R323

VA30

0IC

VL

0505

101V

150F

R

VBAT

15R322

C332

1u

C35

322

p

C33

61u

C35

222

p

C339 1u

VA30

1IC

VL

0505

101V

150F

R

18000pC344

C338 1u

HS_EAR_L

HS_EAR_R

SPK_RCV-

SPK_RCV+


EAR_REAR_L

SPKRPSPKRN

BEARPBEARN

TP1

TP2

TOUCH_Y- : GND line shielding to CN

272829

3

3031323334

456789

1314151617 18

19

2

20212223242526

CAM_AVDD_2V8

ENBY0040301GB042-34S-H10-E3000

CN5031

101112

0.1uC525

CAM_DVDD_1V8

C5230.1u

TOUCH_Y+TOUCH_Y-

CI_RES_n

SYSCLK0

TOUCH_X+TOUCH_X-

APP_GP_VGA_SDNAPP_I2C_SDA

APP_I2C_SCL

CI_DATA[1]

CI_DATA[3]

CI_HSYNC

CI_DATA[6]

CI_DATA[0]

CI_DATA[2]

CI_DATA[4]

CI_VSYNCSPK_RCV+SPK_RCV- CI_PCLK

CI_DATA[7]

CI_DATA[5]

TP3

TP4

CN9021

2

SPK_RCV-

SPK_RCV+

TP5



4. TROUBLE SHOOTING

Measured 1khz Sine Wave Signal

1

3

2





4. TROUBLE SHOOTING

4.9.2. Speaker (Voice Loud Speaker,Midi, MP3,Key Tone)

• Signals to the speaker

– Speaker signals are generated at AB3100

• SPKRP, SPKRN

– Speaker path :

• 1.AB3100 (SPKRP, SPKRN)

• 2. C343, C344 on the main board

• 3. U301(audio amp) on the main board

• 4. C352, C353 on the main board

• 5. Speaker

Note : It is recommanded that engineer should check the soldering of R, L, C along the corresponding path before every step.



4. TROUBLE SHOOTING

START


Equipment and setup call

Setup 1KHz tone out


at C343(TP1),C344(TP2)? Change the main board


at U301 ? Change the U301


at R352(TP3),R353(TP4) ?

YES

YES

YES

NO

NO

NO

Can you hear sine wave

out of a speaker ?Change each Speaker

END

YES

NO

Change the U301

1

3

2

The sine wave not appear

4




4. TROUBLE SHOOTING

1 32

TP1

TP2

U301

TP3 TP4


1%

Audio Subsystem

Audio Subsystem

1%

C343

B3

B1

VD

D

A3

VS

S

18000p

A4

C1PA5

D3

GN

D

HPLA2

HPRA1

INA1D2

INA2D1

C2INB1

C1INB2

D5OUT+

B5OUT-

C4

PG

ND

C5

PV

DD

RXIN+D4B4

RXIN-

SCLC3

SDA


B2BIAS

C1N

C342 1u

C3340.1u

C3541u

C3331u

15R323

VA30

0IC

VL

0505

101V

150F

RVBAT

15R322

C332

1u

C35

322

p

C33

61u

C35

222

p

C339 1u

VA30

1IC

VL

0505

101V

150F

R

18000pC344

C338 1u

HS_EAR_L

HS_EAR_R

SPK_RCV-

SPK_RCV+


EAR_REAR_L

SPKRPSPKRN

BEARPBEARN

TP1TP3

TP4

TP2



4. TROUBLE SHOOTING


4




4. TROUBLE SHOOTING

4.9.3. Microphone (Voice call, Voice Recorder, Video Recorder)

• Microphone Signal Flow

– MIC is enable by MIC Bias

– CCO, MIC1P, MIC1N signals to AB3100

• Check Points

– Microphone bias

– Audio signal level of the microphone

– Soldering of components

• Signal from the mic

– MIC

– C625,C626 on main board

– AB3100



4. TROUBLE SHOOTING

START

Change the MIC

Does it work properly ?

END

Yes

Yes

NoDoes not open Tx path about Mic?

No

Yes

1




4. TROUBLE SHOOTING

1

MIC



4. TROUBLE SHOOTING

4.9.4. Headset Receiver (Voice call, Video Telephony,MP3 )

START


Equipment and setup callSetup 1KHz tone out

Insert Headset.Does the Headset icon

display on the main LCD?

Can you hear sine waveout of the receiver ?

Change the main B’d

END

YES

YES

YES

NO

NO

NO

Does the level of R502(TP1) under 0.5Volt ?

NO

Resolder R502(TP1) And try again from the start

YES

Does the sine wave appearat R505(TP4),R506(TP5) ?

Resolder CN501 Pinsor change the Headset

1

5

7

Does the sine wave appearat R339(TP2),R342(TP3) ?4

YES

Change the U301

Change the main B,d

NO

Change the U501



YES

NO

2

`

3

Does the sine wave appearat TP6, TP7 at CN501 ?

NOChange the U501

6




4. TROUBLE SHOOTING

4.9.5. Headset MIC(Voice call, Video Telephony )

START


Equipment and setup callSetup 1KHz tone out



YES

NODoes the level of R502(TP1) under 0.5Volt ?

NO

Resolder R502(TP1) And try again from the start

YES

1

NO

Change the U501



YES

2

`

3

Does it work properly ?? Try again from the start

END

YES

YES

NO

NO


Check the signal level

at C505(TP8) at the putting

Audio signal in MIC

Resolder C505(TP8)and try again.If fail again,


A few hundred of mV Of the signal measured at C505(TP8) ?

4

5

6

Change the main B,d



4. TROUBLE SHOOTING

4.9.6. Headset


TI : PD = USB, PU = UART

MUIC

If TI, then 10nFClose to MUIC

MAXIM : NA = USB, PU = UART

C5094.7u

C508

22p

2.2K

R51

1

VDDE_1V8

22p

C507

C50

31u

10R506

VBAT

VBAT

R505 10DNIR507

ICC3

INT

B2

A2ISET

A1MIC

B1RES

SC

LC

2C

1S

DA

B3U1U2

A3B4

UID

VBD5

U501

D4AUD1

D3AUD2

D2BAT

CAPD1

COM1C5B5

COM2

A4DN1

A5DP2

GNDC4

MAX14526EEWP_TCC6

C506

22p

FB502

FB500C505 0.1u

R508 DNI

R503 0

TP602

0R501

VBUS

2.2K

R504

FB501

C5041u

0R502

HS_EAR_RHS_EAR_L

USW_ID

MIC2P

APP_ACC_UART_RXAPP_ACC_UART_TX

USW_DMUSW_DPUSB_DP

APP_GP_USW_INT

APP_GP_USW_SCLAPP_GP_USW_SDA

USB_DM

1%

Audio Subsystem

Audio Subsystem

1%

C343

B3

B1

VD

D

A3

VS

S

18000p

A4

C1PA5

D3

GN

D

HPLA2

HPRA1

INA1D2

INA2D1

C2INB1

C1INB2

D5OUT+

B5OUT-

C4

PG

ND

C5

PV

DD

RXIN+D4B4

RXIN-

SCLC3

SDA


B2BIAS

C1N

C342 1u

C3340.1u

C3541u

C3331u

15R323

VA30

0IC

VL

0505

101V

150F

R

VBAT

15R322

C332

1u

C35

322

p

C33

61u

C35

222

p

C339 1u

VA30

1IC

VL

0505

101V

150F

R

18000pC344

C338 1u

HS_EAR_L

HS_EAR_R

SPK_RCV-

SPK_RCV+


EAR_REAR_L

SPKRPSPKRN

BEARPBEARN

6

7

8

9

CN501

1

10

11

12

13

14

15

2345

USW_IDUSW_DPUSW_DM

TP8

TP4

TP5

TP1

TP6TP7TP2

TP3




4. TROUBLE SHOOTING

TP7

U501

CN501

U301

TP1

TP2

TP3

TP4 TP5

TP6

TP8



4. TROUBLE SHOOTING

4.10 Charger Trouble Shooting

Main Battery Charging Path

• Charging Procedure

- Connecting TA and Charger Detection

- Control the charging current by AB1000

- Charging current flows into the battery

• Check Point

- Connection of TA

- Charging current path

- Battery

• Trouble shooting setup

- Connect TA and battery to the phone

• Trouble Shooting Procedure

- Check the charger connector

- Check the Charging current Path

- Check the battery


Charging



USB charging pathDischarging




Charging Circuit

22pC337

VBUS

2

C1

1

D302

KDS221E_RTK

A1_C2

3A2

VBAT_H

1/4WR324

VBAT

2012

1% 0.025

D1

D2

D3

D4

G1

G2

S1

S2

Q300 SIA911DJ

300KR320

C33022p

C33133u

1%1/4W2012

0.1R316

D1

D2

1 2 3

CN

300

R314

0 CHS-

BDATA

FGS+

CHREG

DCIO_INT

FGS-

CHS+




4. TROUBLE SHOOTING

start

Check the pin(TP1) and batteryconnect terminals of I/O

connector

Connection OK? Change I/O connectorNO

YES

Change Main boardNO

YES

Is it charging properlyEND

YES

NO

Change Main board

1

2

3

start

connect terminals of I/Oconnector

Connection OK? Change I/O connectorNO

YES

Is the VBUS voltage(TP3) 5.1V?NO

YES

Is it charging properly

after changing Q400(TP4)?END

NO

2

3

Trouble Shooting - Charging

YESYES

Is the TA voltage(TP2) 5.1V? Change TANO

Change TANO

34



4. TROUBLE SHOOTING

Main Board ( Bottom side)

- I/O connector and FET

TP1

TP2

TP3

TP4

Charging

VBUS

D1

D2

D3

D4

G1

G2

S1

S2

Q300 SIA911DJ

CHREG

DCIO_INT

2012

Close by uUSB CONN

L500

82nHU500

NUS3065MUTAG

CNTRL3

4DRAIN

DRAIN_THERMAL9

GATE6

GND2

IN1

7OUT

5SRC

8VCC

G24

IN 1OUT2

22p

C511

FL500NFM21PC105B1A3

3G1

6

7

8

9

CN501

1

10

11

12

13

14

15

2345

ULCE0505C015FR

VA500

DNI

C502

SD

12T

1G

ZD

500

9

INS

TPA

R

CN5001

2

1 uF

C510

VBUS

USW_ID

FM_ANT

USW_DPUSW_DM

TP2

TP1

TP3




4. TROUBLE SHOOTING

4.11 Bluetooth Trouble

Bluetooth IC (STLC2593) gets power from PMIC (AB3100) and clock (MCLK) from RFIC. (RF3300)After checking them, Bluetooth RF path should be examined.

4.11.1 Bluetooth Power path

TP2

TP1

start

1. Check

BT IC Block

TP1: 1.8V , TP2 : 2.75V

2. Check

Mainboard Connector

TP3: 1.8V , TP4 : 2.75V

1

1

2

Go to 4.11.2OK

NG

Replace Sub PCB

OK

NG

Check AB3100 (U300)

Sub PCB

Main PCB (Bottom side)

2

TP3(2nd pin from the end of the connector)

TP4(3rd pin from the end of the connector)

VDDK_2V75VDD_BT

C73

50.

1u

C73

60.

1u

D4NC1NC2

F7F8

NC3NC4

L4

C1C2

BT_RSVR_NBT_RSVR_RF

M2

E6BT_VDD_CLDBT_HVD

N7

BT_REG_CTRLJ4

BT_RSVR_CL1B2

BT_RSVR_CL2C3M8


0R

742

TP1

TP2

5960

G1 G2

5 5657583

4

2

CN601

1

VDDE_1V8

R63

8

0

VDDK_2V75

TP3

TP4



4. TROUBLE SHOOTING

4.11.2 Bluetooth Clock path

TP2

TP1

start

1. Check BTCLK

(Buffered MCLKSEC)

TP1: 26MHz

2. Check

MCLKSEC

TP2: 26MHz

1

2

TP3(4th pin from the end of the connector)

1

2

Go to 4.11.3OK

NG

Replace U730OK

NG

3. Check

Mainboard Connector

TP3: 26MHz

Replace Sub PCB

OK

NG

Check RF3300 (U111)


Sub PCB

A23 GND

5VCC

Y4

1 _OE


C7300.1u 4.7u

C731

R730

33

R73

1

100K

VDD_BT

BT_CLKREQ_n

BT_CLKMCLKSEC

TP1TP2

G3 G4

30 3132333435363724

2526272829

FM_ANT

MCLKSEC

RTCCLK

TP3




4. TROUBLE SHOOTING

4.11.3 Bluetooth RF path

Check Power level

at BT IC Output (C732) with Spectrum Analyzer

TP1: Range

0 ~ 4dBm ?

No

Yes

Replace BT Chip (U731)

TP2: Range

0~4dBm ?

Check Power level

at RF SW Output (C701) with Spectrum Analyzer

Replace ANT780

No

Yes

Replace RF Switch (FL700)

start

TP2

TP1

DEA212450BT-7043C15

BP1

4BP2 BP_DC

2

3G

16

G2

1U_BP

FL730 100pC732

VSS_BT_RF

BT_TXRX

R78

1

0

WIFI_RF_GWIFI_RF_G

VSS_BT_RF

4.7n

H

R78

0

XM0830SK-TL1301TMP

ANT5

GND11

GND24

GND36

GND49

GND51113

PGND

8PORT1PORT2

2

RFGND13

RFGND27

12VCTL

10VDD

0 FL700

C707

R70

0

1u

4pC706C705

4pC704DNI

100pC701

R701 0

WIFI_RF_GWIFI_RF_G

C7021p

VDDK_2V75

C700

0DUMMY FEED

ANT780

BT_TXRXWIFI_TXRX

ANT_SEL_N

TP1

TP2



4. TROUBLE SHOOTING

4.12 Wi-Fi Trouble

Wi-Fi module (M710) gets power from 2 LDOs (U710, U711) and clock from oscillator inside the module.RF path is shared with Bluetooth RF.

4.12.1 Wi-Fi Power path

TP2

TP1

Sub PCB

TP3

start

1. Check VBAT

TP1: VBAT

2. Check 1.8V LDO

TP2: 1.8V

Change Sub PCB

No

Yes

Replace U710No

Yes

3. Check 3.3V LDO

TP3: 3.3V

Replace U711No

Yes

Go Next Step

POWER

VDD_WLAN_3V3

R71

7

0

0

R716

C722

3CE

2GND

5P

GN

DVDD4 1

VOUT

1u

RP101K182D U711

VDD_WLAN_1V8

VBAT

3CE

2GND

5P

GN

DVDD4 1

VOUT

RP101K332D U710

C7211u

C7231uC724

1u

ACC_GP_WLAN_EN

TP3

TP2TP1




4. TROUBLE SHOOTING

4.12.2 Wi-Fi RF path

TP2

TP1

Check Power level

at Wi-Fi module Output (C717) with Spectrum Analyzer

TP1: Range

13 ~ 17dBm

at 802.11b?

No

Yes

Replace Wi-Fi module (M710)

TP2: Range

13~17dBm

at 802.11b ?

Check Power level

at RF SW Output (C701) with Spectrum Analyzer

Replace ANT780

No

Yes

Replace RF Switch (FL700)

start

R78

1

0

WIFI_RF_GWIFI_RF_G

VSS_BT_RF

4.7n

H

R78

0

XM0830SK-TL1301TMP

ANT5

GND11

GND24

GND36

GND49

GND51113

PGND

8PORT1PORT2

2

RFGND13

RFGND27

12VCTL

10VDD

0 FL700

C707

R70

0

1u

4pC706C705

4pC704DNI

100pC701

R701 0

WIFI_RF_GWIFI_RF_G

C7021p

VDDK_2V75

C700

0DUMMY FEED

ANT780

BT_TXRXWIFI_TXRX

ANT_SEL_N

TP2

C725DNI

WIFI_RF_G

6SCLK

5SPI_SDO_S

7ESCN

GND11

GND23

GND38

ANT2

4ANT_SEL_P

TP713

100p

WIFI_RF_G

C717

WIFI_TXRX

TP1



4. TROUBLE SHOOTING

4.13 GPS Trouble

GPS IC (U751; BCM4750) gets power from a single 1.8V LDO (U752). Clock comes from TCXO (X750) and RFIC. (RF3300)After checking them, GPS RF path should be examined.

4.13.1 GPS Power path

TP2

TP1

1

1

2

Check AB3100 (U300)

Sub PCB

TP3

TP4

start

1. Check Voltage at GPS IC

TP1: 1.8V, TP2: 1.8V

Power OKGo to 4.13.2

Yes

No

Change Sub PCB

Yes

No

3. Check

Mainboard Connector

TP5: VBAT

Change U752Yese

No

2. Check Voltage at LDO

TP3: 1.8V, TP4: VBAT


2

TP5 (2nd and 3rd pin from the end of the connector)

VDDE_1V8

VD

DIO

1B

6G

3V

DD

IO2

VD

DIO

3G

7

VPDD5

CN

TIN

A3

LP

RE

GIN

F5

RT

CC

LK

YN

C_P

PS

E7

TC

XO

A2

C4

RF

RE

GIN

BMS0C6

F2

0R750

V8

5NC2

OUT4

VCC6

KT2520F16369ACW18T

C7510.1u2.2u

C750

C7521u

VGPS_1V8

R757

0

0

R755

C76

61u

VGPS_1V8

VBAT

1uC

765

3CE

2GND

5P

GN

DVDD4 1

VOUT

RP101K182D U752

TP2

TP3TP4

TP1

5960

G1 G2

5 5657583

4

2

CN601

1

VBAT

R64

4

100K

TP5




4. TROUBLE SHOOTING

TP2

4.13.2 GPS Clock path

start

2. Check Buffered MCLKSEC

TP2: 26MHz

3. Check

MCLKSEC

TP3: 26MHz

1

2

TP4(4th pin from the end of the connector)

2

Go to 4.11.3

No

Yes

Replace U750OK

NG

4. Check

Mainboard Connector

TP4: 26MHz

Replace Sub PCB

OK

NG

Check RF3300 (U111)


TP1

Sub PCB

TP31. Check TCXO output

TP1: 16.369MHz

1

Replace X750No

Yes

4.13.2 GPS Clock path

NT

IN

F5

CC

LK

_PP

SE

7

TC

XO

A2

F2VDDE_1V8

X7501

GND1

GND23

NC12 5

NC2

OUT4

VCC6

KT2520F16369ACW18T

C7510.1u2.2u

C750

R757

0

GPS Clock Buffer

R75

4

100K

0.1uC753

R75210

33

R753

C7542.2u

VDDE_1V8

A

GND

OE VCC

Y

NL17SZ126XV5T2GU750

MCLKSEC

GPS_CNTIN

ACC_GP_GPS_PON

TP1

TP2TP3

G3 G4

30 3132333435363724

2526272829

FM_ANT

MCLKSEC

RTCCLK

TP4



4. TROUBLE SHOOTING

4.13.3 GPS RF path

start

1. Check GPS Antenna pad

contact

1

2. Change the LNA (U750)

Change the sub PCB

1

1

2

3

3. Change GPS IC (U751)

2

3

GPS LNA block

100p

C77

2

C7710.1u

ALM-1612

FIL_OUT4 3

GNDRF_IN

2

1S

_D

VDD5

2.2u

U770

C770

C75

7N

A

L750 6.8nH

VDDE_1V8

VGPS_1V8

2.2n

HL

770

10n

HL

771

0R772

F1TESTMODE

VDDIFSYNTHD1

F6_LPREGOUT

VDDRFD2

VPDD5

RFINB1

E2RFREGOUT

E1RFSREGOUT

C7552.2nH

100n

HC

758

100nHL772

0R750

1CN750

1CN751

C7601u

C7521u

C75

60.

5p

1uC759

10

R770

ACC_GP_GPS_PON3 2 1




4. TROUBLE SHOOTING

4.14 RF Component

Main Board : Top side

U100

U109

U102

U107

FL104

FL103

U101

X100

U111

FL100

FL102

FL106

FL105

RF TransceiverU111RF Mobile SwitchSW100

DCDC ConverterU109WCDMA BC 1 Tx FilterFL106

WCDMA BC 8 PAMU107WCDMA BC 8 Tx FilterFL105

WCDMA BC 1 PAMU102GSM Low Band Rx FilterFL104

GSM PAM with ASMU101GSM High Band Rx FilterFL103

Power DetectorU100WCDMA BC 8 DuplexerFL102

X-talX100WCDMA BC 1 DuplexerFL100

DescriptionReferenceDescriptionReference



4. TROUBLE SHOOTING

4.15 Procedure to check

start

Oscilloscope setting

1. CheckPower Source Block

2. CheckVCXO Block

Agilent 8960 : Test mode (WCDMA)Ch. 9750 (Uplink)Ch. 10700 (Downlink)

4. CheckWCDMA Block

Agilent 8960 : Test mode (GSM)Ch. 190, P.L. 7 level settingCh. 190, -60dBm setting

5. CheckGSM Block

Redownload SW, Cal

3. CheckAnt. SW Module




4. TROUBLE SHOOTING

4.16 Checking Common Power Source Block

Step 2

GSM PAM Block

Step 3

WCDMA PAM Block

Main Board : Top side

- Common Source Block

GSM PA VBAT

WCDMA

DC/DC VBAT

Step 1

PAM VBAT Block



4. TROUBLE SHOOTING

4.16.1 Step 1 TP1

TP2

Main Board (bottom side)

- Power Source Block

Main Board (Top side)

- Step 1 : VBAT Block

TP5TP3

TP4


USB charging path

Discharging



22pC337

2

C1

1

D302

KDS221E_RTK

A1_C2

3A2

VBAT_H VBAT

300KR320

C33022p

C33133u

1%1/4W2012

0.1R316

D1

D2

1 2 3

CN

300

R314

0 CHS-

BDATA

CHS+

TP1

TP3

TP4

TP2




4. TROUBLE SHOOTING

3.7V OK?Step 1

Check Point (TP1) in

Power Source Block

To Check Power source to Check if main power source input or not

Yes

No

Proceed to the Step 2

3.7V OK?No

Yes

Check the Power Supply

Short? No

Yes

Soldering Check Component(CN300)

In Power Source Block

Check Point (TP2)

in Power Source Block

To Check Power source

Change Board

Check (TP1 & TP2)

in Block

to check inner line connectionFrom TP4 to TP3



4. TROUBLE SHOOTING

4.16.2 Step 2

Figure 4-6. Step 2 : GSM PAM Block

(Bottom)

GSM PAM

TP3

TP5

TP4

TP1

TP2



GSM PA WITH ASM

0R1140R115

0R112

33pC113

_TXEN8

LB_RF_IN3 9

MODE

PG

ND

131 32

PG

ND

2P

GN

D3

33 34P

GN

D4

RSVD10

RX11615

RX2RX3

1413

RX4

VAPC4

VBATT5

WCDMA11819

WCDMA2WCDMA3

20

BS176

BS2

GND12

27GND10GND11

2829

GND12GND13

30

11GND2GND3

1221

GND4GND5

22

GND623

GND72425

GND8GND9

26

1HB_RF_IN

SKY77521

U101

17ANT

C13

922

p

22pC112

VBAT

C14

022

p

DN

IR

106

R111 0 100pL102

KMS-518

SW100

AC G1

G2

C13

2D

NI

DN

IC

126

10u

C10

7

22pC114

47p

C10

9

C13

022

p

DNIR108

R105 0

22p

C12

9

22pC125ANT

G1G2

0.01

uC

108

SW101UFL-R-SMT10

WRF_BAND_2

WRF_BAND_1

GRX_1800GRX_1900

GTX_VAM

ANTSW3

ANTSW2

ANTSW0

ANTSW1

GTX_1800_1900GTX_850_900

WRF_BAND_8_5

GRX_850GRX_900

TP3 TP4 TP5




4. TROUBLE SHOOTING

Step 2Check VBATI (TP3,TP4,TP5)

in GSM PAM Block

to Check if main powersource input or not

Check (TP1&TP3,TP4,TP5)

in Block

to check inner line connectionFrom TP1 to TP3,TP4,TP5

Check Point (TP1)



3.7V OK?

Yes

No

Proceed to the Step 3

3.7V OK?No

Yes


Short? No

Yes



Change Board



4. TROUBLE SHOOTING

4.16.3 Step 3

TP1

TP2



TP4

TP5

TP3

Step 3 :WCDMA PAM Block

3.7V OK?Step 3

Check VBAT (TP3)

in WCDMA PAM Block Yes

No

See the Next Page

3.7V OK?No

Yes


Short ?

No

Yes



Check Point (TP1)



Change Board

Check (TP1 & TP3)

in Block ,to check inner line connectionFrom TP3 to TP1




4. TROUBLE SHOOTING

Main Board (Bottom side) : Power for Radio ASIC

4.16.4 Checking VCC

AB3100

TP1

TP2

2.8V OK?

No

Yes

1.8V OK?

Yes

No

Check the AB31000

Check the AB31000

Check PointVDIGRAD_1V8

(TP2)

Common Input Power is OKSee The Next Part

Check Point VRADA_2V8

(TP1)

to RF3300 digital




VDDA_2V8

VDDH_2V75 VDDF_2V5

0R303

R304 0

R305 0

2.2uC303 C304

2.2u

VDDC_2V65

OA_OUTK13

OD OUTL12

G14

C12EXT_LDO

0R302

C3022.2u

VDDK_2V75

VDDD_2V65 VBAT

VDDG_2V85


VBAT

EXT_LDO

VDDD_2V65

VDDA_2V8

VDDE_1V8

VDIGRAD_1V8

TP1

TP2

AB3100



4. TROUBLE SHOOTING

4.17 Checking VCXO Block

The reference frequency (26MHz) from U111(Transceiver RF3300) is used

WCDMA TX part and BB part, Bluetooth part. Therefore, 3 test points in the following figure should be checked.

Phone

Oscilloscope

Notebook to send TP command

Connection for Checking VCXO Block

Main board : bottom side

U111

Transceiver

U201

Digital Base Band

X100

CrystalDB3200RF3300

Main board : Top side




4. TROUBLE SHOOTING

Check 1. Crystal and RF3300 (Transceiver) part

If you already check this crystal part, you can skip check 1

Test Point (Crystal Part)

Schematic (Crystal Part)

Figure 4-15. 26MHz at TP1

TP1

WTXIN2423

WTXLP

WTXQN2625

WTXQP

XON1718

XOP

MCLKSEC20

STR10

13TESTOUT

VCCD21

D9

MCLK15

CLK12

14CLKREQ

11DATA

DN

IR

148

R15

0D

NI

2 GND1

GND24

1HOT1

HOT23

26MHzTN4-26562

X100

R14

9D

NI

0R144MCLK

RF_CTRL_CLK

RF_CTRL_DATA

RF_CTRL_STR_1

TESTOUTMCLKREQ

TP1

RF3300



4. TROUBLE SHOOTING

Check 3. 26MHz at BB part

Figure 4-19. Schematic (26MHz at BB Part)

Figure 4-20. 26MHz at TP1

Figure 4-18. Test point (26MHz at BB part)



MCLK

TP1

WTXIN2423

WTXLP

WTXQN2625

WTXQP

XON1718

XOP

MCLKSEC20

STR10

13TESTOUT

VCCD21

ND

9

MCLK15

CLK12

14CLKREQ

11DATA

DN

IR

148

R15

0D

NI

2 GND1

GND24

1HOT1

HOT23

26MHzTN4-26562

X100

R14

9D

NI

0R144MCLK

RF_CTRL_CLK

RF_CTRL_DATA

RF_CTRL_STR_1

TESTOUTMCLKREQ

R200 3.3K

RTCCLKINA15

SYSCLK0A18A17

SYSCLK1SYSCLK2

A19

B18SYSCLKREQN

E17MCLK

MCLKREQB17

MSACCIRQNC19

MSAPPIRQNC20

BT_CLKREQ_n

MCLK

SYSCLK0SYSCLK1

USB_XTAL1

RTCCLK

ACC_IRQ_nAPP_IRQ_n

MCLKREQ

TP1

DB3200RF3300




4. TROUBLE SHOOTING

Check TP1 No

Refer to Figure 4-15

Yes

VCXO part has a problem.Changing XTAL or U111

Checking 1, 326MHz at VCXO

VCXO part is O.K.

Check next stage



4. TROUBLE SHOOTING

4.18 Checking Front End Module Block

Figure 4-21. Front End Module Block

<Top>

Antenna Switch Module

(+ GSM/EDGE PA)

TP1

TP2

TP3

TP4

0R1140R115

0R112

_TXEN8

LB_RF_IN3 9

MODE

BS176

BS2

1HB_RF_IN

SKY77521

17ANT

C13

922

p

C14

022

p

R111 0

C13

022

p

22p

C12

9

ANTSW3

ANTSW2

ANTSW0

ANTSW1

GTX_1800_1900GTX_850_900

TP2TP1

TP3

TP4




4. TROUBLE SHOOTING

4.19 Checking Front End Module Block input logic

4.19.1 Mode Logic by TP Command

GSM850/EGSM Tx

ANTSW3

ANTSW1

ANTSW0/2

WCDMA 2100

DCS/PCS Tx

DCS Rx PCS Rx

ANTSW0/1

ANTSW2

ANTSW3

ANTSW0

ANTSW2

ANTSW3

EGSM Rx

ANTSW0

ANTSW2

ANTSW3

GSM850 Rx

WCDMA 900



4. TROUBLE SHOOTING

Table 4-1. Front End module Logic




4. TROUBLE SHOOTING

4.19.2 Checking Switch Block power source

※ Before Checking this part, must check common power source (through AB3100) part

TP Command

MODE=3

SWRX=190,3

Open?

High? OK? Resoldering

Check each modeBy TP command

Change the Board

No

No No

Yes

Yes Yes

Check soldering(C106)

Check Soldering

It is necessary to check short condition.

Using Tester. Check 3 capacitors

ANTSW0(TP2),ANTSW1(TP3)

ANTSW2(TP4)

Check ANTSW0(TP2)

To check Switch input power source



4. TROUBLE SHOOTING

A. GSM850 Rx mode

GSM850 Rx

MODE=3

SWRX=190,3

GSM850 RxLogic OK?

See the Next mode(EGSM Rx Mode)

Change the Board

No No

Yes Yes

Figure 4-22-1. GSM850 Rx Mode

Try 4.17 part4.17 part Check

OK?

ANTSW0

ANTSW2

ANTSW3Low

High

Low




4. TROUBLE SHOOTING

B. EGSM Rx mode

EGSM Rx

MODE=0

SWRX=49,3

EGSM RxLogic OK?

See the Next mode(GSM850/EGSM Tx Mode)

Change the Board

No No

Yes Yes

Figure 4-22-2. EGSM Rx Mode


OK?

ANTSW0

ANTSW2

ANTSW3 High

High

Low



4. TROUBLE SHOOTING

C. GSM850/EGSM Tx mode

GSM850/EGSM Tx

MODE=3

SWTX=190,64,7

GSM850/EGSM TxLogic OK?

See the Next mode(DCS Rx Mode)

No No

Yes Yes

Figure 4-23.GSM850/EGSM Tx Mode


OK?

ANTSW0/1:LowANTSW2:LowANTSW3:High

WON : Low

Change the Board

Change U101

ANTSW0/1

ANTSW2

ANTSW3

Low

High

Low

No

Yes




4. TROUBLE SHOOTING

D. DCS Rx mode

DCS Rx

MODE=2

SWRX=699,3

DCS RxLogic OK?

See the Next mode(DCS Tx Mode)

Change the Board

No No

Yes Yes

Figure 4-24. DCS Rx Mode


OK?

ANTSW0

ANTSW2

ANTSW3Low

High

High



4. TROUBLE SHOOTING

E. PCS Rx mode

PCS Rx

MODE=1

SWRX=661,3

PCS RxLogic OK?

See the Next mode(PCS Tx Mode)

Change the Board

No No

Yes Yes

Figure 4-25. PCS Rx Mode


OK?

ANTSW0

ANTSW2

ANTSW3High

High

High




4. TROUBLE SHOOTING

F. DCS / PCS Tx mode

DCS / PCS Tx

MODE=2

SWTX=1,699,0

Figure 4-26. DCS / PCS Tx Mode

DCS TxLogic OK?

WCDMA1900 Mode Change the Board

No No

Yes Yes


OK?

ANTSW0/1

ANTSW2

ANTSW3

High

High

Low



4. TROUBLE SHOOTING

G. WCDMA 2100 mode

WCDMA2100 Mode

MODE=4

WTXC=10700,1,890,903,542,557

Figure 4-27-1. WCDMA2100 Mode

WCDMA2100Logic OK?

Change the Board

No No

Yes Yes


OK?

ANTSW3

ANTSW1

ANTSW0/2

Low

High

Low

WCDMA900 Mode




4. TROUBLE SHOOTING

H. WCDMA 900 mode

WCDMA900 Mode

MODE=11

WTXC=3012,1,890,903,542,557

Figure 4-27-2. WCDMA900 Mode

WCDMA900Logic OK?

Input Signal and Power toFront End Module block is OK.

See the Next Page

Change the Board

No No

Yes Yes


OK?

ANTSW3

ANTSW1

ANTSW0/2

Low

High

Low



4. TROUBLE SHOOTING

4.20 Checking WCDMA Block

start

1. CheckVCXO Block

4. CheckRF TX Level

3. CheckControl Signal

Re-download SW, Cal

2. CheckFront End Module

6. CheckRF RX Level

5. CheckPAM Block

①

②

③

⑤

⑥

④




4. TROUBLE SHOOTING

4.20.1 Checking VCXO Block

Refer to 4.17

4.20.2 Checking Ant. SW module

Refer to 4.18

4.20.3 Checking Control Signal

First of all, control signal should be checked. (data, clk, strobe)

Figure 4-28-1. Test points (Control Signal)

Bottom View

TP3 [RF_CTRL_CLK]

TP2 [RF_CTRL_DATA]

TP1 [RF_CTRL_STR1]



4. TROUBLE SHOOTING

RF3300

Phone

Oscilloscope


Figure 4-29. Connection for Checking Control Signal

Figure 4-28-2. Schematic (Control Signal)

TP1 [RF_CTRL_STR1]

TP2 [RF_CTRL_DATA]

TP3 [RF_CTRL_CLK]

STR10

CLK12

11DATA

8EDATAAEDATAB

9

EDATAC6

EDATASTR7

U1RF3

R14

1D

NI

RF_CTRL_CLK

RF_CTRL_DATA

RF_CTRL_STR_1




4. TROUBLE SHOOTING

Similar ?

Control Signal is O.K.

Check next stage

Download the SW

Check TP1, TP2, TP3. Check shape and pk-pk level Refer to Figure 4-30

Yes

No

If signal is not OK even after downloading, Change the U201

Figure 4-30. Control Signal

TP Command

MODE=4

WTXC=9750, 1,754,643,418,568

SYCT=9750

TP1 (RF_CTRL_STR1)

TP2 (RF_CTRL_DATA)

TP3 (RF_CTRL_CLK)

TP1 (RF_CTRL_STR1)

TP2 (RF_CTRL_DATA)

TP3 (RF_CTRL_CLK)



4. TROUBLE SHOOTING

4.20.4 Checking RF TX Level

Figure 4-31. Test point (RF TX Level)

TP1

[WBAND 8

PAM Input]

TP2

[WBAND 1

PAM Input]

TP4

[RF3300 Output

BAND 1]

TP3

[RF3300 Output

BAND 8]

TP5

FEM Output

TP6

Ant. SW

TP7

Ant.

<Top side>

<Bottom side>




4. TROUBLE SHOOTING

NCEIVER

0R162

R16

8D

NI

R166 0

WTXHB129

WTXHB233

WTXHB331

35WTXLB

57PGND

GN

D15

34G

ND

16

0

R151

DN

IC

191 OUT


G1

2

G2

5

G33

IN1 4

DN

IC

187

DN

IR

158

DN

IR

164

0

R161

5

G33

IN1 4

OUT

G1

3

G2 G3

5

1IN OUT

4


G1

2

G2


2

DN

IC

185

DN

IR

155

R165

0

0R152

WTX_BAND_2_TO_PA

WTX_BAND_1_TO_PA

WTX_BAND_8_5_TO_PA

_TXEN8

9MODE

RSVD10

521

17ANT

100pL102

KMS-518

SW100

AC G1

G2

C13

2D

NI

DN

IC

126

DNIR108

22pC125ANT

G1G2

SW101UFL-R-SMT10

TP3

[RF3300 Output

BAND 8]

TP1

[WBAND 8

PAM Input]

TP2

[WBAND 1

PAM Input]

TP4

[RF3300 Output

BAND 1]

TP6

Ant. SW

TP7

Ant.

TP5

FEM Output



4. TROUBLE SHOOTING

Phone

Spectrum Analyzer


Fig. 4-32 Connection for Checking RF TX Level

Fig. 4-33-2 Output Level at RF3300 Output

( TP3&TP4)

Fig. 4-33-1 Output Level at PAM Input

( TP1&TP2)




4. TROUBLE SHOOTING

Fig. 4-33-5 Output Level at TP7 .Ant

Fig. 4-33-4 Output Level at RF test connector

( TP6)

Fig. 4-33-3 Output Level at FEM Output

(TP5)



4. TROUBLE SHOOTING

To verify that the phone fulfils requirements on maximum output power.

TP6

About 22~23dBm?RF TX Level is OKCheck next stage

Check output power at the TP6 with antenna Cable.

Refer to Figure 4-33-4

No

Yes

Set the FDD Test of the Agilent 8960Set the Maximum Power

Yes

The SW100 has any problem.

Change the SW100

TP5

About 15dBm?

Check the power at the TP5 with probe. Refer to Figure 4-33-3

No

Yes

The L102 will be broken.Change the L102

TP7

About 19dBm?

Check the power at the TP7.Ant with probe. Refer to Figure 4-33-5

No

Yes

The U102 has any problem.You have to check PAM block.

TP1&TP2About -6dBm?

Check the power at

the TP1/TP2 with probe. Refer to Figure 4-33-1

The U111 will be not operated.Change the board

No

TP Command

MODE=4

WTXC=9750, 1,754,643,418,568

SYCT=9750

TFTI=9750




4. TROUBLE SHOOTING

WCDMA band1

PAM

VCC_PA

(C103, C155)

from DC/DC

WPAM

input

(R162, R152)

Duplexer Output

(L601, C152)

4.20.5 Checking PAM Block

Figure 4-34. Test points of WCDMA TX PAM block

Bias_CTRL

(C115, C157)

DC/DC

converter

WCDMA band8

PAM



4. TROUBLE SHOOTING

Yes

No

TP Command

-mode =5

- WTXC=9750, 1,754,643,418,568

22dBm ?

Check Duplex output(L601, C152)

To Check PAMoutput

WCDMA PAM is OKSee the Next page

Level

< -10dBm?

NoDownload the SW

& Calibrate

Level

>2dBmCheck R162, R152To Check PAM Input level

Check the WCDMA RF Tx Chip (RF3300)

Yes

Yes

1.1V at

Po_max?

Check C115, C157To Check PAM control signal from AB3100 (Bias_CTRL)

Check the RF3300to WCDMA PAM Signal line

3.4V ?Check C103, C155To Check PAM VCC BIASfrom DC/DC converter(VCC_WPA)

No

No

No

Change the DC/DC

Yes

Yes

Change The PAM




4. TROUBLE SHOOTING

4.20.6 Checking RX I,Q

To verify the RX path you have to check the pk-pk level and the shape of the RX I,Q.

Feed a CW signal at 2142MHz with a power level of –60dBm.

Figure 4-36-1. RX I,Q signal (CW:2142MHz)

Figure 4-35. RF3300, WCDMA Transceiver (Bottom)

About 2 MHz

Figure 4-36-2. RX I, Q signal

WRX_Q_P (PIN 2)

WRX_Q_N (PIN 1)

WRX_I_N (PIN 3)

WRX_I_P (PIN 4)

WRX_I_P (PIN 4)

WRX_I_N (PIN 3)

WRX_Q_P(PIN 2)

WRX_Q_N(

PIN 1)



4. TROUBLE SHOOTING

About 130mVp-p? Change RF3300 (U111)

Check the pk-pk level at PIN 1, PIN 2, PIN 3, PIN 4With Oscilloscope.


Yes

No

Set the CW Mode of the Agillent 8960

Feed a CW signal at 1950MHzSet the RX Continuous mode

Check the Mean level at PIN 1, PIN 2, PIN 3, PIN 4With Oscilloscope.


Yes

No

Check the frequency at PIN 1, PIN 2, PIN 3, PIN 4With Oscilloscope.Refer to Figure 4-36-2

Yes

No

Verify whether the signal

was similar as Figure4-36-2 with Oscilloscope.

Yes

No

About 160mV?

About 2MHz?

Similar?

Check Next Stage

Change RF3300 (U111)



TP Command

MODE=4

WRXC=9750




4. TROUBLE SHOOTING

4.21 Checking GSM Block

start

2. CheckVCXO Block

5. CheckRF TX Path

4. CheckControl Signal

Re-download SW, Cal

3. CheckFEM Module

6. CheckRF RX Path

1. CheckVRAD_2V8

Figure 4-37-1. GSM Block (Bottom)

③

⑥⑤

④

②①



4. TROUBLE SHOOTING

4.21.1 Checking Regulator Circuit Refer to 4.16 Checking Power Source block

IF you already check this point while checking power source block (4.15), You can skip this test.

4.21.2 Checking VCXO Block Refer to 4.17 Checking VCXO block

IF you already check this point while checking VCXO block (4.17), You can skip this test.

4.21.3 Checking Front End Module Refer to 4.19.2 Checking Ant. SW Module

IF you already check this point while checking Ant. SW module (4.19.2), You can skip this test.




4. TROUBLE SHOOTING

4.21.4 Checking Control Signal

Test Program Script

MODE=3

SWTX=190,7,1024,1

STRBSTRB

CLKCLK

DATADATA

Figure 4-39. GSM RF Control signal

Figure 4-38. Test points of RF control signals

RF_CTRL_STRB (PIN10)

RF_CTRL_CLK (PIN12)

RF_CTRL_DATA(PIN11)

GSM

PAM

RF3300



4. TROUBLE SHOOTING

Similar?

Check PIN10,PIN11,PIN12 of RF3300.

Check if there is any Major difference.

Refer to Figure 4-39

Yes

NoRe-download SWShort?

Yes

No

Change the board

Control signal is OK.See next page to check




4. TROUBLE SHOOTING

4.21.5 Checking RF Tx Path

A. GSM Tx path Level

③

①

②

③′

GSM

/ED

GE

PA +

Ant

Sw

.

ANT

VA

PC

RA

DC

LK

RA

DD

AT

RA

DS

TR

VB

AT

2.75

VV

RA

D

1.8

VVI

O

PA

PA

GS

M85

0/90

0 In

put

DC

S/P

CS

Inpu

t

ES

D

2.75

VV

RA

D

LNA

LNA

LNA

LNA

LNA

AD

AD

0 90

LPF

+C

hPP

hD÷ N.M

VCO

LPF

ChP

PhD ÷ N.M

+0 90

+DA

C

DA

C

XO

DA

C

VCO

VCO

LNA

LNA

WC

DM

A L

B

WC

DM

A H

B

WC

DM

A H

B

WC

DM

A H

B

CLK

DA

TA

STR

OB

ES

eria

lC

ontro

l

WTx

QB

WTx

QA

WTx

IB

WTx

IA

GS

M/E

DG

E

AM

DA

C

RFC

trl1

RFC

trl2

RFC

trl1

RFC

trl2

GS

M/

ED

GE

HB

GS

M/

ED

GE

LB

WC

DM

A L

B

WC

DM

AH

B

WC

DM

A H

B

GS

M/E

DG

ELBG

SM

/ED

GE

LBGS

M/E

DG

EH

B

GS

M/E

DG

EH

BW

RxI

A

WR

xIB

WR

xQB

WR

xQA

EDat

aA

EDat

aB

ED

ataC

ED

ataS

tr

WC

DM

A/G

SM/G

PRS/

EDG

E TR

X

MC

LK

CLK

REQ

MC

LKS

ec

XO

XO

n

XO

p

26M

Hz

X-ta

l

VB

AT

Vcc

WP

A

Vcc

WP

A

Pow

erco

uple

r

Pow

erco

uple

r

Vcc

WP

A

Vcc

WP

A

RF

Pow

det

Det E

n

Bias

DE

TEn

Bias

DE

TE

n

Bias

DE

TE

n

UL:

192

0 –

1980

MH

zD

L: 2

110

–21

70 M

Hz

UL:

174

9.9

–17

84.9

MH

zD

L: 1

844.

9–

1879

.9 M

Hz

UL:

830

–84

0M

Hz

DL:

875

–88

5M

Hz

824

–91

5 M

Hz

1710

–19

10M

Hz

1930

–19

90M

Hz

1805

–18

80M

Hz

925

–96

0 M

Hz

869

–89

4 M

Hz

WD

CD

CR

EF

WP

OW

_DET

_EN

FB

Sw

itch

PWM

/PFM

En

Con

trol

Logi

c

RFC

trl1

③

①

②

③′

③

①

②

③′③

①

②

③′③

①

②

③′



4. TROUBLE SHOOTING

Figure 4-41. Test Points of GSM850/EGSM/DCS/PCS Tx Path

③③′

①

(Bottom)

②PIN 6,7,8,9

(Top)




4. TROUBLE SHOOTING

B. GSM Tx Output Level Check

Check GSM850/EGSM/DCS/PCS output power at ①.


Refer to Figure 4-42.

GSM850>32dBm

EGSM>32dBm

DCS>29dBm

PCS>29dBm

NoSee Next page to check Tx pathSimilar?

Yes

GSM850/EGSM/DCS/PCS Tx path OK. See Chapter 4.8.6 to check Rx path

v Agilent 8960 Setting: GSM BCH+TCH Mode

v Oscilloscope Setting

3. DCS TxMODE=2SWTX=699,0,1024,1

Test Program Script

1. GSM850 TxMODE=3SWTX=190,64,5,1024,1

4. PCS TxMODE=1SWTX=661,0,1024,1

Figure 4-42. GSM850/EGSM/DCS/PCS Tx Level at ①

2. EGSM TxMODE=0SWTX=49,5,1024,1



4. TROUBLE SHOOTING

C. GSM RF Transceiver Check

GSM850/EGSM/DCS/PCS>5dBm

See Next page to check Tx path

Check GSM RF Transceiver Output power at ①.

No

Yes

Redownload SW

Figure 4-43. GSM850/EGSM/DCS/PCS Transceiver (RF3300)

RF3300

(U111)

Vapc(PIN 52)

DCS/PCS Tx(R129)

①`

GSM Tx(R134)

①




4. TROUBLE SHOOTING

D. GSM PAM Check

GSM850/EGSM:32.0dBmDCS/PCS: 30.0dBm

Yes

Changing GSM PAM(U100)

Check GSM850/EGSM/DCS/PCS PAM output power at C111.

GSM Tx path OK. See Next page to check

Check Vapc level.



Yes

NoRedownload SW, CalGSM850/EGSM>1.5 V?

No

Figure 4-44-1. Test points of GSM850/EGSM/DCS/PCS Tx

DCS/PCS>1.3 V?

GSM/EDGE

PAM

(+Ant. SW)

U101

GSM850/EGSM/DCS/PCS Tx

(C125)

Vapc(PIN 52)

(Bottom)

(Top)



4. TROUBLE SHOOTING

4.21.6 Checking RF Rx Path

A. GSM Rx path Level

①

②

②

Figure 4-45. GSM/DCS/PCS Rx Path Level

①

②

②

GSM

/ED

GE

PA +

Ant

Sw

.

ANT

VA

PC

RA

DC

LK

RA

DD

AT

RA

DS

TR

VB

AT

2.75

VV

RA

D

1.8

VVI

O

PA

PA

GS

M85

0/90

0 In

put

DC

S/P

CS

Inpu

t

ES

D

2.75

VV

RA

D

LNA

LNA

LNA

LNA

LNA

AD

AD

0 90

LPF

+C

hPP

hD÷ N.M

VCO

LPF

ChP

PhD ÷ N.M

+0 90

+DA

C

DA

C

XO

DA

C

VCO

VCO

LNA

LNA

WC

DM

A L

B

WC

DM

A H

B

WC

DM

A H

B

WC

DM

A H

B

CLK

DA

TA

STR

OB

ES

eria

lC

ontro

l

WTx

QB

WTx

QA

WTx

IB

WTx

IA

GS

M/E

DG

E

AM

DA

C

RFC

trl1

RFC

trl2

RFC

trl1

RFC

trl2

GS

M/

ED

GE

HB

GS

M/

ED

GE

LB

WC

DM

A L

B

WC

DM

AH

B

WC

DM

A H

B

GS

M/E

DG

ELBG

SM

/ED

GE

LBGS

M/E

DG

EH

B

GS

M/E

DG

EH

BW

RxI

A

WR

xIB

WR

xQB

WR

xQA

EDat

aA

EDat

aB

ED

ataC

ED

ataS

tr

WC

DM

A/G

SM/G

PRS/

EDG

E TR

X

MC

LK

CLK

REQ

MC

LKS

ec

XO

XO

n

XO

p

26M

Hz

X-ta

l

VB

AT

Vcc

WP

A

Vcc

WP

A

Pow

erco

uple

r

Pow

erco

uple

r

Vcc

WP

A

Vcc

WP

A

RF

Pow

det

Det E

n

Bias

DE

TEn

Bias

DE

TE

n

Bias

DE

TE

n

UL:

192

0 –

1980

MH

zD

L: 2

110

–21

70 M

Hz

UL:

174

9.9

–17

84.9

MH

zD

L: 1

844.

9–

1879

.9 M

Hz

UL:

830

–84

0M

Hz

DL:

875

–88

5M

Hz

824

–91

5 M

Hz

1710

–19

10M

Hz

1930

–19

90M

Hz

1805

–18

80M

Hz

925

–96

0 M

Hz

869

–89

4 M

Hz

WD

CD

CR

EF

WP

OW

_DET

_EN

FB

Sw

itch

PWM

/PFM

En

Con

trol

Logi

c

RFC

trl1

①

②

GSM850 : -50dBm

EGSM : -50dBm

DCS : -50dBm

PCS : -50dBM

②

①

②

GSM850/EGSM : -51.5dBm

②

①

②

DCS/PCS : -51.7dBm

②

①

②

②

①

②

②

①

②

②`




4. TROUBLE SHOOTING

2. DCS/PCS RxSWRX=2,700,0,1024,1 (DCS)SWRX=1,700,0,1024,1 (PCS)

Test Program Script

1. GSM850/EGSM RxSWRX=3,190,5,1024,1 (GSM850)SWRX=0,65,5,1024,1 (EGSM)

v Agilent 8960 SettingCW ModeGSM850 : -50dBm@Ch190(881.6MHz)EGSM : -50dBm@Ch65(948MHz)DCS : -50dBm@Ch700(1842.8MHz)PCS : -50dBm@ch700(1967.8MHz)

v Oscilloscope Setting

Figure 4-46. Test Points of GSM/DCS/PCS Rx

GSM Transceiver

RF3300

U111

GSM/EDGE

PAM

U101

②DCS

Rx

PCS

Rx

EGSM

Rx

GSM8

50 Rx

①

(Bottom)

(Top)



4. TROUBLE SHOOTING

B. GSM RF Level Check

GSM Rx path OK.

Check GSM850/EGSM/DCS/PCS Rx signal level at ②.

Yes

GSM850/EGSM:-51.5dBmDCS/PCS:-51.7dBm

Change Ant. SW module(U101)

No

Figure 4-47. GSM850/EGSM/DCS/PCS Rx path

v Agilent 8960 SettingCW ModeGSM850 : -50dBm@Ch190(881.6MHz)EGSM : -50dBm@Ch65(948MHz)DCS : -50dBm@Ch700(1842.8MHz)PCS : -50dBm@ch700(1967.8MHz)

GSM Transceiver

RF3300

U111

GSM/EDGE

PAM

U101

②DCS

Rx

PCS

Rx

EGSM

Rx

GSM8

50 Rx

①

(Bottom)

(Top)




5. Download

5. Download

The downloading purpose is described below:

1) To make a phone operate at the first manufacturingA phone = Hardware + SoftwareA phone cannot operate with hardware alone.

The hardware with the suitable software can operate properly.2) To upgrade the software of the phone

The software of the phone may be changed to enhance the performance of the phone.The older version software of the phone can be replaced to the newer version.

5.1 Requirements

5.1.1 Download ItemsItems needed to download SW images with LGEDP.

A. Micro-USB Cable

B. Target( GT500 / GT505 Phone )

C. PC and LGEDP Software

D. SW Images

5.1.2 System RequirementThe table below shows the requirements for setting up.

You should check the requirements below first to set up your PC.

USB Driver cannot support Windows 98, Windows Me, and Windows XP Service

Pack 1. Although it can do, it cannot be guaranteed. So, highly recommend OS

upgrade.

5.1.3 Required ToolLGEDP : Download tool for GT500 / GT505 software

BBAA



5. Download

5.2 GT500 / GT505 DownloadInstall LGEDP USB Driver in the following order.

1) Go to the directory = ../LGEDP_U330_SVC_EURO_YYYYMMDD/wrapper_USBDriver

2) Click “installme.bat”

5.2.1. USB Driver Install* Please make sure that install this usb driver for download not for a pc sync driver.

There are two different type of usb driver. One for downloading , the other for PC sync.

If you use LGEDP Tool firstly, Error will happen because of USB Driver uninstalled.

If you see “Found New Hardware” when phone is connect after complete install,

and then follow as indicated blew.

when connect the phone, must be check that phone should be turn off and

battery should be full-gauge (At lease three(75%) more).

The installation procedure of LGEDP USB Driver is described below:

1) Push “the Next Button” in Found New Hardware Wizard




5. Download

2) Select “Search for the best driver in these locations” in Found New Hardware Wizard

3) Select “Include this location in the search” in Found New Hardware Wizard

4) Push “the Browse Button” , and then select “USB driver Information file”

This File is provided with LGEDP.



5. Download

5) Select “Mobile Equipment USB Flash” in Found New Hardware Wizard

6) Continue Anyway

You must be select this..!




5. Download

7) Please wait while the wizard installs the software..

8) Push “the Finish Button” in Found New Hardware Wizard



5. Download

6

5.2.2 Download Menu Selection.Download Menu Selection in the following order:

1) Click “Configuration” – “download” in Menu bar.




5. Download

5.2.3 LGEDP Configuration & SW & GDFS Image Selection.The installation procedure of Download Configuration is described below:

1) You must select “Window Size” 1 ~ 4. ( Defualt is 4 )

2) You must select “Chipset” U330 for GT500 / GT505.3) You can select SW image to download by clicking “Add…” button.

Select next two image files orderly. Order is important.

Main image : “cxc000000_APPLICATION_PHONE_SB_IAR-ARM-NAND.ssw”,

FileSystem image : “CXC_FS_CABS_LP_NAND.ssw”LGPXO image : “CXC_LGPXO_SYS_CABS_LP_NAND.ssw”

4) You can select GDFS map to download by clicking “Add…” button.

Select next two GDFS files.

Acc GDFS : “GT500 / GT505_Update_GDFS_Acc_XXXXXXXX.gdf”,App GDFS : “GT500 / GT505_Update_GDFS_App_XXXXXXXX.gdf”.

5) After choose all image to download, click “OK” button.

3)3)

4)4)

5)5)

1)1)



5. Download

5.2.4 Starting DownloadFollow the procedure described below to start download.

You should follow the instruction below and be sure to follow in right order.

1) If you have not detached Battery from the phone yet, detach Battery from the phone.

2) Connect your phone with Micro-USB cable.

3) Insert the Battery into phone.

4) In case of GT500/GT505, press Side-Up-Key. Keep pressing until step 6.5) Press Power-Key. And then Downloading will be started.

6) Release both Side-Up-Key and Power-Key after start downloading in GT500

7) If Downloading has not started yet, Repeat procedure 1) ~ 6).

< Before phone is turned on >




5. Download

5. 2.5 Download is on going

< After phone is turned on >



6. Block Diagram

6. Block Diagram

Figure 6-1 GT500 Block Diagram

- 179 -

7. CIRCUIT DIAGRAM

LGE Internal Use OnlyCopyright © 2009 LG Electronics. Inc. All right reserved.


D

5

E

12

A

E

G

C

D

G

107

9 10

4 5

F

7

Placement Notice:PGND must be isolated from Common GND on L1, L2 and L3

3

B

C

H

8

H

A

12

1 6 8 9

6

RF TRANCEIVER

DC-DC CONVERTER

EXTERNAL LDO

TEMP SENSOR

WCDMA PA Block

GSM PA WITH ASM

1 2

GT500 GND contact for ANT

B

4

closed to RF3300

11

3 11

F

2

0R162

C178

0R114

33p

0R115

R12

0

24

L100

18p

C12

2

R16

8D

NI

22p

R166 0

L120NA

C1581000p

0R112

NAC117

0.1u

VDDA_2V8

7GND4

8GND5

9GND6

1RX

TX3

C101

1OUT

4TER

FL100 SAYFP1G95AA0B00

ANT6

GND12

GND24

GND35

U103 LDC151G8620Q-359

COU3

IN2

R1283.9nH

3.6nHC124

22p

0

R156

C16

7

GND312

14GND4IN_BAND_2

2

6IN_BAND_5

13OUT_BAND_2

OUT_BAND_59

PGND15

10VBIAS

VC211

4VCC1

VCONT5

VEN_BAND_21

7VEN_BAND_5

SKY77175U105

3GND1

GND28

C13

8D

NI

4.3nH R125

C164 15p

WTXHB129

WTXHB233

WTXHB331

WTXIN24

35WTXLB

23WTXLP

WTXQN2625

WTXQP

XON1718

XOP

MCLKSEC20

57PGND

37RFCTRL1RFCTRL2

36

STR10

13TESTOUT

27VCCA1VCCA2

51

VCCD21

WRXHB138

WRXHB242

3WRXINWRXIP

4

WRXLB40

1WRXQNWRXQP

2

16G

ND

1019

GN

D11

GN

D12

22

GN

D13

28 30G

ND

1432

GN

D15

34G

ND

16

GN

D2

53

GN

D3

49

GN

D4

47 45G

ND

543

GN

D6

41G

ND

739

GN

D8

5G

ND

9

MCLK15

CLK12

14CLKREQ

11DATA

52EAMMOD

8EDATAAEDATAB

9

EDATAC6

EDATASTR7

48ERXHB1

50ERXHB2

ERXLB144

ERXLB246

56ETXHB

54ETXLB

GN

D1

55

U111RF3300

22p

DN

IC

151

C12

1

C1430.5p

0

R151

C1151000p 1000p

C116

DN

I

L108

C19

1

C133

3.3uH

DNI

L118 10nH

DN

IR

139

VRAD_2V8

1800FB100R124 390

33p

C16

0

R13

627

0

2.2nHL106

56

R11

7

33pC113

0.1uC154

GND3GND4GND5GND6

RX

TX

270

R13

1

ACMD-7407FL101

ANT

GND1GND2

DN

IR

148

OUT

10uC168


G1

2

G2

5

G33

IN1 4

DA

P7

4ENGND

3

OUT6

5REF

2RF_IN

VDD1

U100 LMV221

DNI

R160

R15

0D

NI

U104

3COU

2IN

OUT1

TER4

100pC135

LDC151G8620Q-359

1000

pC

137

C1734.7u

C18

110

0p

8

VCONT3

VEN4

DN

I

R11

3

U107 SKY77181

GND15

GND26

PGND9

2RF_IN

7RF_OUT

VBIAS1

VCC

R12

1

56

GND2GND3GND4

GND5GND6

RX

TX

22pC175

LT56BFL102

ANT

GND1

NAL114

L105NA

NAL109

DN

IC

187

PT

100

C106

4.7K

C16

5D

NI

33nF

NAL112

DN

IC

189

0.1uC149

R13

227

0

DNI

R145

_TXEN8

27R134

LB_RF_IN3 9

MODE

PG

ND

131 32

PG

ND

2P

GN

D3

33 34P

GN

D4

RSVD10

RX11615

RX2RX3

1413

RX4

VAPC4

VBATT5

WCDMA11819

WCDMA2WCDMA3

20

BS176

BS2

GND12

27GND10GND11

2829

GND12GND13

30

11GND2GND3

1221

GND4GND5

22

GND623

GND72425

GND8GND9

26

1HB_RF_IN

SKY77521

U101

17ANT

VDIGRAD_1V8

C16

9D

NI

DN

IR

159

0 R133

C14

222

p C13

922

p

C1501000p

DN

IR

158

3.9pC159

1.8nH

VBAT

100pC146

L101

22pC112

DN

IR

164

VBAT

C14

022

p

C179

10nH

DN

IR

106

2 GND1

GND24

1HOT1

HOT23

VBAT

26MHzTN4-26562

X100

8.2nHL110

100p

VRAD_2V8

C145

L103

DN

I

R12

7

8.2nHDNIC156

C152

R111

6.8nH

2.7p

0

C17

0

R135

220

10nH

100pL102

L113

GND5GND610

IN_881_51

IN_942_54

OUT_881_59

6OUT_942_5

FL104

SAWEN881MBA0F25

GND12

GND27

3GND3

8GND4

5

C119 100p

KMS-518

SW100

AC G1

G2

R10

0

DN

I

1000pC102

R14

9D

NI

C118NA

1000pC174

DN

I

C13

2D

NI

C18

8

0.1u

C134 100p

C110

DN

IC

126

L1155.6nH

R143560

0R130

0.1u

FC

120

10u

C10

7

R103

120

22p

C16

3

VDDA_2V8

C147 22p

22p

VBAT

R129 27

C114

0.01

uC

162

1718

23456789

270

R13

7

SC1

1 10111213141516

C157

A23 GND

5VCC

Y4

1 _OE

1000p

SN74LVC1G125DRLR

U108

3.3pC177

0

R161

5

G33

IN1 4

OUT

0R144

G1

3

G2 G3

5

1IN OUT

4


G1

2

G2


2

47p

C10

9

B1VDD

R116 DNI

U109 LM3208TL

ENC1

C3FB

PGNDA3

A1PVIN

SGNDB3

A2SW

VCONC2

R10

4

75

VBAT

C13

022

p

C10

522

p

10uC148

0R157

R11

80

R10

9

56

C183

VRAD_2V8

C1822.2u

DNI

1u

R108

RFIN6

RFOUT

4VBIAS VCC

5

VCTRL2

VENB1

10uC155

U102 SKY77182

7GND1

GND28

PGND9

3

R142 18p

L1043.3nH

C10

422

p1000pC153

R14

6

4.7K

GND12

GND27

3GND3

8GND4

5GND5GND6

10

IN_1842_51

IN_19604

OUT_1842_59

6OUT_1960

FL103

SAWEN1G84BC0F25

1K

R102

DN

IC

161

R14

1D

NI

DN

IC

185

DN

IR

155

2PG

ND

5

4VDD VOUT

1

R105 0

RP101K282D U110

CE3

GND

R165

0

1000

pC

141

C12

7

VRAD_2V8VDDA_2V8

L60

12.

2nH

3.3p

DN

I

C172

C10

30.

1uF

0R152

DN

IC

123

COU32

IN

OUT1

TER4

C16

60.

01u

U106 LDC15874M19Q-360

CN1981

R147

0

C17622p

R652

0

C10010u

DN

IR

138

C171

0.01u

R10

7

10

VBAT

560R123

39nH L116

22p

C12

9

1

22pC125

CN199

ANTG1G2

0.01

uC

108

SW101UFL-R-SMT10

1.5p

C12

8

0

R10

1

L1172.2nH

R140

C180

0

DNI

1.8pL119

C63

63.

3nH

DN

I

R15

3

R12

6

0

C11122p

NAL107

L111

C14

4

NA

22p

DN

IC

136

WRX_BAND_1WTX_BAND_2_EN

WTX_BAND_2_TO_PA

WRF_BAND_1

WRF_BAND_2

WRF_BAND_8_5

VCC_WPA

BIAS_CTRL

BIAS_CTRL

WTX_BAND_1_EN

WRX_BAND_1

WRX_BAND_2

WRX_BAND_8_5

TX_ADC_STRB_2V8

WTX_BAND_2_TO_PA

WTX_BAND_1_TO_PA

WPOW_DET_EN

WRF_BAND_2

WRF_BAND_1

WRX_BAND_8_5

WRX_BAND_2

WPOW_DET

GRX_1800GRX_1900

GTX_VAM

ANTSW3

ANTSW2

ANTSW0

ANTSW1

WTX_BAND_8_5_EN

WTX_BAND_8_5_TO_PA

BIAS_CTRL

GTX_1800_1900GTX_850_900

WRF_BAND_8_5

GRX_850GRX_900

VCC_WPA

DCDC_REF

VDDA_2V8

EXT_LDO

WTX_BAND_1_TO_PA

TX_ADC_STRB

MCLKSEC

WDCDC_EN

GRX_1800

GRX_850

GRX_900

GTX_1800_1900

GTX_850_900

MCLK

WTX_BAND_8_5_TO_PA

WTX_I_NWTX_I_P

WTX_Q_P

TX_ADC_STRB_2V8

GRX_1900


AMP_FREQ_LSBDATA_STR

WDCDC_EN

WRX_I_NWRX_I_P

WRX_Q_NWRX_Q_P

ADOUT

RTEMP

RF_CTRL_CLK

RF_CTRL_DATA

WTX_Q_N

RF_CTRL_STR_1

TESTOUTMCLKREQ

GTX_VAM

7. CIRCUIT DIAGRAM



GND

IN

OUT

9

7 96

H

I2C MAP

F

C

A

5

3

A

Added in the REV.D

2G v1.8 x8 NAND + 1G v1.8 x16 SDRAM(MCP)

10

E

12

1

C

5 8

DB3200 POWER

H

10

8

F

Service mode for WEB D/L

D

2

E

6

G

B

2

7

G

4 11

1 3 4

B

MCP 2G NAND 1G SDRAM

JTAG and ETM

12

11

D

C23

20.

1u

N4

B5VSS5

N5VSS6VSS7

N8

E2VSSQ1

J2VSSQ2

L2VSSQ3

_CASF7

_CEC6

E9_CS1_CS2

E8

E7_RAS

_REE5

D6_WE

F8_WED

_WPF5

NC

9

E6R__B

UDQMH3

VCC1B6N7

VCC2

VCCQN6

VDD1B4

VDD2G9

VDD3H2M2

VDD4

VDDQ1D2F2

VDDQ2K2

VDDQ3

C2VSS1VSS2

F9G2

VSS3VSS4

K6

NC

13K

7K

8N

C14

NC

15M

5M

6N

C16

NC

17M

7M

8N

C18

NC

19N

2

B7

NC

2

N9

NC

20

NC

3B

9F

3N

C4

NC

5J3

G4

NC

6G

5N

C7

NC

8G

6H

5

E3F4

DQ7J4

DQ8DQ9

K3

IO0J5

IO1L5J6

IO2L6

IO3IO4

J7

IO5L7J8

IO6L8

IO7

LDQMG3

NC

1B

2

NC

10H

6K

5N

C11

NC

12

N1

DN

U7

N10

P1

DN

U8

DN

U9

P2

B3DQ0

C4DQ1

K4DQ10DQ11

L3L4

DQ12DQ13

M3M4

DQ14N3

DQ15

DQ2C3D4

DQ3DQ4

D3E4

DQ5DQ6

H7H8

A9

ALED5

BA0D7D8

BA1

CKE1G8

CKE2F6

C5CLE

H4CLK

DN

U1

A2

P9

DN

U10

DN

U11

P10

DN

U2

A9

DN

U3

A10

B1

DN

U4

DN

U5

B10

DN

U6

KA100J00BA-AJYYU200

A0C7C8

A1

D9A10A11

H9

A12G7

A2C9B8

A3A4

M9

A5L9

A6K9

A7J9

A8

0.1u C227

0.1u

TP

221

C200

0.1u C224

3300

R20

9

R65

9D

NI

0.1u C239

RE

SIN

RT

CK

TC

K

TD

I

TD

O

TM

S

TR

ST

VC

C

C2370.1u

JTG

201

GN

D

PS

_HO

LD

C2310.1u

VDDE_1V8

VDDE_1V8

VDDF_2V5

R64

310

0K

0.1u

C23

3

R20

4

VDDE_1V8

TC

K

100K

R65

0D

NI

TM

U20

0

C212 33nF

VDDE_1V8

C23

40.

1u

0.1u C223

0.1uC207

0.1u C220

C2220.1u

R207 3300

R21

233

00

0.1u C218

KRC402E

Q200

B

C

E

R200 3.3K

C2061u

C2150.1u

J2USB_SE0_VM

B14

RF

_WC

DM

A_P

A_0

_EN

D14

RF

_WC

DM

A_P

A_1

_EN

RF

_WC

DM

A_P

WR

DE

T_E

C13

RTCCLKINA15

C2SCLK

B2SDAT

C18SERVICEN

SRSTNC4

SYSCLK0A18A17

SYSCLK1SYSCLK2

A19

B18SYSCLKREQN

TX

_AD

C_S

TR

BD

15

B6

TX

_PO

W

USB_DAT_VPK2

USB_OEL3

PD

I_D

6N

22

PD

I_D

7N

15

PD

I_R

ES

_NK

20

B10PWRRSTNRESOUT0N

J14B19

RESOUT1NE18

RESOUT2N

C16

RF

_CT

RL

_CL

KR

F_C

TR

L_D

AT

AC

17

D16

RF

_CT

RL

_ST

RB

1R

F_C

TR

L_S

TR

B2

C14

RF

_DA

TA

_AB

15B

16R

F_D

AT

A_B

C15

RF

_DA

TA

_C

A16

RF

_DA

TA

_ST

RB

B13

RF

_WC

DM

A_D

CD

C_E

N

E2PCMCLK

D3PCMDLD

PCMSYNE3

PCMULDD2

K23

PD

I_C

0P

DI_

C1

J16

PD

I_C

2K

22

PD

I_C

3K

16L

22P

DI_

C4

L21

PD

I_C

5P

DI_

D0

L23

L20

PD

I_D

1P

DI_

D2

M22 J20

PD

I_D

3M

23P

DI_

D4

K15

PD

I_D

5

J10

KE

YO

UT

1K

EY

OU

T2

K9

L9

KE

YO

UT

3J1

1K

EY

OU

T4

MC

CL

KT

22N

20M

CC

MD

P23

MC

CM

DD

IR

MC

DA

T0

R22

N21

MC

DA

T1

MC

DA

T2

P22

M21

MC

DA

T3

M20

MC

DA

TA

DIR

E17MCLK

MCLKREQB17

MSACCIRQNC19

MSAPPIRQNC20

D20

I2C

SD

A2

I2S0CLKG22

I2S0DLDF21G20

I2S0ULD

F22I2S0WS

G21I2S1CLK

I2S1DLDE22

I2S1ULDG19

I2S1WSE21

KE

YIN

0C

22D

22K

EY

IN1

D21

KE

YIN

2K

EY

IN3

F20

E20

KE

YIN

4F

19K

EY

IN5

KE

YO

UT

0J1

3

Y18EMIF2_D14EMIF2_D15

Y19

EMIF2_FBCLKT10

EMIF2_NFIF_READYY10

EMIF2_SDBS0_A14AA18AB19

EMIF2_SDBS1_A15

AC10EMIF2_SDCAS_RE_OEN

Y12EMIF2_SDCKEN0

AC9EMIF2_SDCKEN1

EMIF2_SDCLKY11

EMIF2_SDRAS_ADVNAC11

AB8EMIF2_WAITN

AB10EMIF2_WEN

I2C

SC

LB

20

B21

I2C

SC

L2

D19

I2C

SD

A

EMIF2_CS2NAC8AB9

EMIF2_CS3N

Y13EMIF2_D00EMIF2_D01

Y14T11

EMIF2_D02EMIF2_D03

AA12

EMIF2_D04AA13AA14

EMIF2_D05Y15

EMIF2_D06EMIF2_D07

AA16AA17

EMIF2_D08EMIF2_D09

Y16W17

EMIF2_D10EMIF2_D11

W18

EMIF2_D12Y17

EMIF2_D13Y20

EMIF2_A16AC19

AA20EMIF2_A19EMIF2_A20

AB21Y21

EMIF2_A21AA21

EMIF2_A22AB22

EMIF2_A23AA22

EMIF2_A24Y22

EMIF2_A25

EMIF2_ALE_A18AB20

EMIF2_BE0NAB12AB11

EMIF2_BE1N

EMIF2_CLE_A17AA19

AA10EMIF2_CLK

EMIF2_CRE_A26V21

EMIF2_CS0NAA7

EMIF2_CS1NAA9

EMIF1_SDCSNY2

EMIF1_SDRASNV2

EMIF1_WENW2

EMIF2_A01AC12AA11

EMIF2_A02EMIF2_A03

AB13

EMIF2_A04AC14

EMIF2_A05AB14AB15

EMIF2_A06EMIF2_A07

AA15AB16

EMIF2_A08EMIF2_A09

AC16AC17

EMIF2_A10EMIF2_A11

AB17

EMIF2_A12AB18AC18

EMIF2_A13

U5EMIF1_D13EMIF1_D14

U4

EMIF1_D15U3

EMIF1_D2L4K4

EMIF1_D3EMIF1_D4

M3

EMIF1_D5M4

EMIF1_D6P4P3

EMIF1_D7EMIF1_D8

R4N8

EMIF1_D9

EMIF1_SDBS0_A14U1V1

EMIF1_SDBS1_A15

Y3EMIF1_SDCASNEMIF1_SDCKEN

V4W3

EMIF1_SDCLK

U2EMIF1_A13

L2EMIF1_A2EMIF1_A3

M2

EMIF1_A4M1

EMIF1_A5N1N2

EMIF1_A6EMIF1_A7

P1

EMIF1_A8P2

EMIF1_A9R3

EMIF1_BE0NW1V3

EMIF1_BE1N

EMIF1_D0H4J4

EMIF1_D1

EMIF1_D10P8R8

EMIF1_D11EMIF1_D12

T4

W23

CI_

D7_

CL

K1_

PC

I_D

8_D

AT

1_M

W22

CI_

D9_

DA

T1_

PV

22

U23

CI_

HS

YN

C

U21

CI_

PC

LK

CI_

RE

S_N

T21

R20

CI_

VS

YN

C

DA

C_I

_NE

GE

7D

7D

AC

_I_P

OS

E6

DA

C_Q

_NE

GD

AC

_Q_P

OS

D6

C21DCON

EMIF1_A1L1

R2EMIF1_A10EMIF1_A11

T2T3

EMIF1_A12

APP_GPIO_24R23P20

APP_GPIO_25

H22APP_GPIO_3

J22APP_GPIO_4APP_GPIO_5

J21H23

APP_GPIO_6K21

APP_GPIO_7L16

APP_GPIO_8APP_GPIO_9

J23

U19

CI_

D0

CI_

D1

V19

V20

CI_

D2_

CL

K0_

MC

I_D

3_C

LK

0_P

W20

CI_

D4_

DA

T0_

MU

20T

20C

I_D

5_D

AT

0_P

CI_

D6_

CL

K1_

MV

23

APP_GPIO_0H20

APP_GPIO_1G23

APP_GPIO_10P15

APP_GPIO_11P16B22


R14

APP_GPIO_14N16

APP_GPIO_16R21R16


U22T13

APP_GPIO_19

H21APP_GPIO_2

APP_GPIO_20T14T15


T23P21

APP_GPIO_23

Y5ACC_GPIO_33_A27

ACC_GPIO_4K8F1


J8G3

ACC_GPIO_7H3


G2D

9A

DC

_I_N

EG

C9

AD

C_I

_PO

SA

DC

_Q_N

EG

C8

D8

AD

C_Q

_PO

S

AN

T_S

W0

H11

H13

AN

T_S

W1

H14

AN

T_S

W2

AN

T_S

W3

H15

APPSLEEPD18

G4ACC_GPIO_19

L8ACC_GPIO_2

C1ACC_GPIO_20

F4ACC_GPIO_21ACC_GPIO_22

F2

ACC_GPIO_23H2V5

ACC_GPIO_24AB3


AA4Y4


P9AC4

ACC_GPIO_29

G1ACC_GPIO_3

ACC_GPIO_30T9

AA5ACC_GPIO_31ACC_GPIO_32

R10

DB3200_A

U201-1

D17ACCSLEEP

J3ACC_GPIO_0ACC_GPIO_1

K3

ACC_GPIO_10H9E1


H10D1


F3D4

ACC_GPIO_15ACC_GPIO_16_USBPRB

C3G5


E4

0.1u C214

R295

R29

9

DN

I

0

R296 DNI

R298

DNI

C2050.1u

R21

433

00

R208 3300

0.1u

TP209

DN

IR

647

C202

C2090.1u

0.1u

C23

5

C2080.1u

0.1u C216

0.1uC201

C2040.1u

0 R216

10K

R20

2

3300

R21

0

1000pC203

R62

0

0

R206 3300

3300

R21

1

VDDE_1V8

VDDE_1V8

0.1u C229

VSS_PLLA8

M8

VS

S6

VS

S7

R11

R13

VS

S8

VS

S9

W19

B9VSSA_AD

VSSA_ADDAA5E5

VSSA_ADDA_ESDVSSA_ADDA_REF

B7B5

VSSA_ADGPVSSA_DA

C5

VSSA_PLL_13_208B11C11

VSSA_PLL_26_208VSSA_PLL_26_60

D11

VSSA_PLL_32_13A11D10

VSSA_PLL_ESD

B3VSS_ADDA_ESD

F5

VS

S10

VS

S11

T12 W5

VS

S12

R12

VS

S13

VS

S14

R9

M9

VS

S15

VS

S16

W21

L15

VS

S17

VS

S18

E19

M16

VS

S19

VS

S2

J9

VS

S20

J12

VS

S21

H12

VS

S3

N9

J15

VS

S4

VS

S5

M15

B4VDDC_ADDA_ESDVDDC_IO

D13A7

VDDC_PLL

VDDE1A3

E23VDDE10VDDE11

A20A13

VDDE12

H1VDDE2VDDE3

R1Y1

VDDE4AC5

VDDE5AC13

VDDE6VDDE7

AC20Y23

VDDE8VDDE9

F23

VS

S1

R15

VDDA_PLL_26_60D12A12

VDDA_PLL_32_13VDDA_PLL_ESD

C10

VDDC1J1

VDDC10C23A21

VDDC11VDDC12

A14A4

VDDC13

VDDC2K1T1

VDDC3AC3

VDDC4AC15

VDDC5VDDC6

AC21AA23

VDDC7VDDC8

N23D23

VDDC9

A9PLL_26_FILTVDD

PLL_26_VCONTA10

RT

CK

AA

1

TC

KA

A2

TD

IA

B4

AA

3T

DO

W4

TM

SA

B2

TR

ST

_N

VDDA_ADDAA6

VDDA_ADDA_ESDC7

VDDA_ADDA_REFB8

VDDA_ADGPC6

VD

DA

_AF

N4

D5VDDA_DA

C12VDDA_PLL_13_208VDDA_PLL_26_208

B12

EF

US

E_H

V4

N3

EM

U_M

OD

E_0

AC

1A

B1

EM

U_M

OD

E_1

ET

M_P

ST

AT

0A

B6

ET

M_P

ST

AT

1Y

7A

A6

ET

M_P

ST

AT

2

ET

M_T

CL

KA

B5

Y9

ET

M_T

PK

T0

ET

M_T

PK

T1

Y8

AB

7E

TM

_TP

KT

2A

A8

ET

M_T

PK

T3

AC

7E

TM

_TP

KT

4W

6E

TM

_TP

KT

5E

TM

_TP

KT

6A

C6

W7

ET

M_T

PK

T7

Y6

ET

M_T

SY

NC

DB3200_B

U201-2

AC

22D

U1

B23

DU

10A

C23

DU

2D

U3

B1

A1

DU

4D

U5

A2

A22

DU

6D

U7

A23

AB

23D

U8

DU

9A

C2

VD

DE

_1V

8

RB521CS-30D200

TP220

2.2K

R20

3

C2170.1u

VDDF_2V5

0.1u C226

R2150

1u C241

C2400.1u

0.1u C238

VCORE

0.1u

C21

0

C2130.1u

TC

KT

MU

201

C23

60.

1u

1uC

211

TP

222

3300R205

DNIR297

3

GND

1IN1

IN22

OUT4

VCC

5

DNI

R658

U202 NC7SZ08P5X

DN

IR

649

RB521CS-30D201

0

R63

9

C2190.1u

TP

223

0.1u

VDDE_1V8

C225

C2300.1u

R64

6D

NI

3300

R21

3

1uC

228

DNI

R657

R64

8D

NI

VDDE_1V8

VDDE_1V8

BT_CLKREQ_n

RESOUT2_n

SCLKSRST_n

SD_DATA(0) SD_ADDR(1)

0.1u C221

RT

CK

TC

K

TD

IT

MS

TC

K

RT

CK

TD

O

TD

IT

MS

TR

ST

_N

PW

RR

ST

_n

EM

U_M

OD

E_0

EM

U_M

OD

E_1

EM

U_M

OD

E_0

EM

U_M

OD

E_1

TD

O

TR

ST

_N

KE

YIN

3

MCLK

APP_GP_LCD_ID

WT

X_B

AN

D_2

_EN

APP_GP_TOUCH_LDO_ENAPP_GP_ISP_LDO_EN

SDAT

APP_GP_LCD_ALDO_EN

KEY_LED6

KEY_LED5

PWRRST_n

NF_READYNF_WE_N

NF_CS0_N

NF_OE_N

NF_ALENF_CLE

APP_GP_3AXIS_SDA

ACC_SPI_WLAN_CSn

ACC_GP_WLAN_RESETnACC_GP_WLAN_EN

ACC_GP_WLAN_PWR_DOWNn

LC

D_V

SY

NC

ACC_GP_GPS_RESETn

APP_GP_LCD_IF1

ACC_GP_SPI_WLAN_IRQn

APP_GP_FM_GPIO2

NF_IO(5)NF_IO(6)NF_IO(7)

NF_IO(0)NF_IO(1)NF_IO(2)NF_IO(3)NF_IO(4)NF_IO(5)NF_IO(6)NF_IO(7)

SD_CKE2

SD_CS2_nNF_OE_N

NF_CS0_N

NF_WE_N

NF_READY

SD_CKE2

RESOUT0_n

KE

YO

UT

0

APP_GP_MMC_DETn


APP_GP_TOUCH_SDAAPP_GP_TOUCH_SCL

APP_GP_LCD_DLDO_ENAPP_GP_BL_EN

APP_GP_CAM_LDO_EN

NF_IO(0:7)

NF_IO(0)NF_IO(1)NF_IO(2)NF_IO(3)NF_IO(4)

ACC_GP_GPS_PON

APP_GP_USW_SDA

APP_GP_TOUCH_SDAAPP_GP_TOUCH_SCL

APP_GP_USW_SCL

APP_GP_3AXIS_SCL

AMP_I2C_SDAAMP_I2C_SCL

APP_GP_3AXIS_SDA

APP_GP_USW_INT

KEYIN2

APP_GP_3AXIS_SCL

VPPFLASH

WT

X_B

AN

D_1

_EN

AP

P_I

2C_S

CL

AP

P_I

2C_S

DA

WR

X_Q

_P

KE

YO

UT

1K

EY

OU

T2

KE

YIN

0

KE

YIN

2

APP_GP_VGA_SDN

APP_GP_MOTORLDO_EN

QD

AT

A_A

MP

_MS

BID

AT

A_F

RE

Q_M

SB

AM

P_F

RE

Q_L

SB

DA

TA

_ST

R

WP

OW

_DE

T_E

N

WT

X_B

AN

D_8

_5_E

N

WT

X_I

_NW

TX

_I_P

WT

X_Q

_NW

TX

_Q_P

WR

X_I

_NW

RX

_I_P

WR

X_Q

_N

SD_CS_n

SD_RAS_n

SD_WE_n

SD_CS2_n

AN

TS

W0

AN

TS

W1

AN

TS

W2

RF

_CT

RL

_CL

KR

F_C

TR

L_D

AT

A

RF

_CT

RL

_ST

R_1

TX

_AD

C_S

TR

B

AN

TS

W3

SD_DATA(11)SD_DATA(12)SD_DATA(13)SD_DATA(14)SD_DATA(15)

SD_DATA(2)SD_DATA(3)SD_DATA(4)SD_DATA(5)SD_DATA(6)SD_DATA(7)SD_DATA(8)SD_DATA(9)

SD_DQML_nSD_DQMU_n

SD_CAS_n

SD_ADDR(12)SD_ADDR(13)

SD_ADDR(3)SD_ADDR(4)SD_ADDR(5)SD_ADDR(6)SD_ADDR(7)SD_ADDR(8)SD_ADDR(9)

SD_ADDR(10)

SD_BA0SD_BA1

SD_CKESD_CLK

SD_DATA(1)

SD_DATA(10)

SD_ADDR(13)

SD_DATA(0:15)

SD_DATA(0)SD_DATA(1)SD_DATA(2)SD_DATA(3)SD_DATA(4)SD_DATA(5)SD_DATA(6)SD_DATA(7)SD_DATA(8)SD_DATA(9)

SD_DATA(10)SD_DATA(11)SD_DATA(12)SD_DATA(13)SD_DATA(14)SD_DATA(15)

NF_CLE

SD_CS_nSD_CLK

SD_CAS_n

SD_WE_n

SD_CKE

SD_RAS_n

SD_DQML_nSD_DQMU_n

NF_ALE

SD_ADDR(2)

SD_ADDR(11)

LC

D_D

AT

A[4

]L

CD

_DA

TA

[5]

LC

D_D

AT

A[6

]L

CD

_DA

TA

[7]

LC

D_W

E_N

LC

D_R

SL

CD

_CS

_N

LC

D_R

ES

ET

_N

SD_ADDR(1:13)

SD_ADDR(1)SD_ADDR(2)SD_ADDR(3)SD_ADDR(4)SD_ADDR(5)SD_ADDR(6)SD_ADDR(7)SD_ADDR(8)SD_ADDR(9)

SD_ADDR(10)SD_ADDR(11)SD_ADDR(12)

CI_

DA

TA

[4]

CI_

DA

TA

[5]

CI_

PC

LK

CI_

VS

YN

CC

I_H

SY

NC

CI_

RE

S_n

CI_

DA

TA

[7]

CI_

DA

TA

[6]

CI_

DA

TA

[0]

CI_

DA

TA

[2]

LC

D_D

AT

A[0

]L

CD

_DA

TA

[1]

LC

D_D

AT

A[2

]L

CD

_DA

TA

[3]

SYSCLK0SYSCLK1

USB_XTAL1

ACC_USB_HS_STP

SH

AR

ED

_I2C

_SC

LS

HA

RE

D_I

2C_S

DA

MIC

RO

SD

_CL

KM

ICR

OS

D_C

MD

MIC

RO

SD

_DA

T0

MIC

RO

SD

_DA

T1

MIC

RO

SD

_DA

T3

MIC

RO

SD

_CM

D_D

IRM

ICR

OS

D_D

AT

_DIR

DB_I2S0_CLK

DB_I2S0_DLD

DB_I2S0_WSDB_I2S0_ULD

DB_I2S1_CLK

DB_I2S1_DLD

DB_I2S1_WSDB_I2S1_ULD


RTCCLK

ACC_IRQ_nAPP_IRQ_n

MCLKREQ

SD_BA1

MIC

RO

SD

_DA

T2

PCM_CLK

PCM_DLD

PCM_SYNCPCM_ULD

LC

D_R

D_N

RESOUT0_nRESOUT1_n

WP

OW

_DE

T

ACC_USB_HS_IN_CLKACC_USB_HS_NXT

ACC_USB_HS_DATA(4)ACC_USB_HS_DATA(5)ACC_USB_HS_DATA(6)ACC_USB_HS_DATA(7)

APPSLEEP

APP_UART_RXAPP_UART_TX

APP_MMC_FB_CLK


APP_GP_3AXIS_INT

CI_

DA

TA

[1]

CI_

DA

TA

[3]

DCON

SD_BA0ACCSLEEP

ACC_USB_HS_DIR


ACC_UART3_CTSACC_UART3_RTS

ACC_GP_USB_CSACC_GPS_START

ACC_USB_HS_DATA(3)

ACC_UART0_RX

ACC_SPI_MISOACC_SPI_MOSIACC_SPI_CLK

ACC_GP_SPI_BT_CSnACC_GP_SPI_BT_IRQ

ACC_UART0_TX

- 181 -

7. CIRCUIT DIAGRAM



1%

B, I : 100K : 12.1K : 0.286V

D, K : 100K : 27.0K : 0.563V

BLM18PG121SN1J

E

G, N : 100K : 68.0K : 1.073V

6 10

to RF3300 digital


120ohm 1608 2A 50mohm Bead

D

Charging

to Hall Switch and AB3100 BEAR

12

1.0 : 100K : 100K : 1.325V

5


F, M : 100K : 51.0K : 0.895V


11

1.4 : 100K : 680K : 2.31V

1.2 : 100K : 215K : 1.809V

C, J : 100K : 20.0K : 0.442V


to SD Card and LCD

to Bluetooth


3 4 10


2

2.8*2.6*1.0 0.7A 240mohm 20%

D

1 %

E

USB charging path

E, L : 100K : 39.0K : 0.744V

1

Discharging

A, H : 100K : 6.2K : 0.155V

to DB3210 CORE

1.1 : 100K : 150.0K : 1.59V

Parallel with VCORE

Audio Subsystem

4

A

6

C



1.3 : 100K : 390K : 2.109V

7 8

Close to ABB

8


B

GPA3:PCB_Rev_ADC

9

G

F

A

Use multiple via

C

7


5

LDO_C 2.65V 200mA

LDO_LP 2.20V

5%1.2VBUCK

Audio Subsystem

Audio Block

Audio BlockDigital Block

Audio Block

Audio Block

Charger Block

Charger Block

Charging Circuit

F

2

H

11

H

1608

G

3

to DB3100 analog

1%

to 3xis

B

12

1

9

Local ground plane

TP301

LDO_A 2.75V 150mA

LDO_D 2.65V 200mA

LDO_G 1.50~2.85V 100mA

LDO_E 1.80V 200mA

LDO_F 1.05~2.65V 30mA

LDO_H 1.20~1.80V 200mA

2.75V 100mA

LDO_K 1.80~2.75V 200mA

C343

B3

B1

VD

D

A3

VS

S

18000p

A4

C1PA5

D3

GN

D

HPLA2

HPRA1

INA1D2

INA2D1

C2INB1

C1INB2

D5OUT+

B5OUT-

C4

PG

ND

C5

PV

DD

RXIN+D4B4

RXIN-

SCLC3

SDA

VDDA_2V8


B2BIAS

C1N

C342

RTC_GND

1u

4.7uHL300

C3340.1u

C354

VBAT_H

C32

8

1u

22p

C333

TP304

C309

VDDH_2V75

1u

VDDF_2V5

1u

15R323

VA

300

ICV

L05

0510

1V15

0FR

R313

C323

27

1u

22pC337

24K

R31

9

VD

DD

_2V

65

VBAT

3300

pC

341

0R303

R304 0

15

VDDC_2V65

R305 0

VBUS

VDDE_1V8

R322

C63

122

p

C32

0

0R310

22p

C32

9

VBAT_C

2

C1

1

22p

D302

KDS221E_RTK

A1_C2

3A2

0.1uC346

C33522p

VDDD_2V65

R30

1

100K

C332

1u

VCORE

C35

322

p

TP303

VBAT_C

R307 0

VBAT

2.2uC303

C347

C33

6

1u

VBAT_H

1u

22p

C32

1

C3104.7u

VDD_REF

1/4WR324

C3042.2u

VBAT

2012

1% 0.025

0.1uC300

RB521S-30

VDDC_2V65

VBAT

D300

C305

4.7u

4.7u

VSS_BUCKB1

M7

VS

S_S

PK

RWS1

J3

WS2K1

XTAL1A10

XTAL2D11

B11XTAL_OUT

C301

VS

S57

L6

VS

S58

L7

L8

VS

S59

D10

VS

S6

L9

VS

S60

VS

S61

L10

VS

S62

L11

VS

S63

M6

VS

S64

M8

M9

VS

S65

M11

VS

S66

VS

S67

M12E

4V

SS

7E

5V

SS

8E

6V

SS

9

VS

S_B

EA

RN

5

VS

S42

J6 J7V

SS

43J8

VS

S44

J9V

SS

45J1

0V

SS

46J1

1V

SS

47V

SS

48K

5

VS

S49

K6

VS

S5

D9

K7

VS

S50

K8

VS

S51

K9

VS

S52

K10

VS

S53

VS

S54

K11

VS

S55

L4

VS

S56

L5

G10

VS

S28

G11

VS

S29

D6

VS

S3

G12

VS

S30

H4

VS

S31

VS

S32

H5

VS

S33

H6

VS

S34

H7

VS

S35

H8

VS

S36

H9

H10

VS

S37

H11

VS

S38

VS

S39

H12

VS

S4

D7

VS

S40

J4

VS

S41

J5

VS

S13

E10

VS

S14

F4

F5

VS

S15

F6

VS

S16

VS

S17

F7

VS

S18

F8

VS

S19

F9

D5

VS

S2

VS

S20

F10 G3

VS

S21

G4

VS

S22

G5

VS

S23

G6

VS

S24

G7

VS

S25

VS

S26

G8

VS

S27

G9

B2VBOOST

C1VBUCK

VBUSE2

C10

VD

D_A

DC

P13VDD_AUDIO

P3VDD_AUXO

VDD_BEARP6

VDD_IOA12

VDD_REFG1

VDD_SPKRP7

C14

VIB

R_O

UT

A13VREF

D4

VS

S1

VS

S10

E7

VS

S11

E8

VS

S12

E9

SRST_NM2

E3SW_BOOST

D12TEST

F2TRICKLE

A5

TX

ON

VBAT_AK12

K14VBAT_B

VBAT_CD1

VBAT_DG2

VBAT_EF14

VBAT_FM13

N14VBAT_G

VBAT_HF3

M3VBAT_K

B14VBAT_L

VBAT_MA1

N3SDAT

SDI1J1

K4SDI2

SDO1K2

L2SDO2

N2SIMCLKSIMDAT

P1

SIMLDO_OUTL1P2

SIMOFF_N

SIMRST_NN1

E11

SL

EE

P_A

D14

SL

EE

P_B

B10

SP

AR

E1

A2

SP

AR

E2

SPKRN_OUTN6

SPKRP_OUTN7

N8MIC3P

P10MIC4N

N11MIC4P

N4MIDR_OUT

B12MOD1

ON

SW

A_N

F13

ON

SW

B_N

F12

ON

SW

CF

11

PLL_DEC3H14

J12PLL_DEC4

E12

PW

RR

ST

_N

K3SCK1

L3SCK2

C13

SC

L

M1SCLK

SD

AB

13

M14LDOK_OUT

LDOLP_OUTD13

B4

LE

D1_

NA

4L

ED

2_N

D3

LE

D3_

NC

3L

ED

4_N

A3

LE

D5_

NB

3L

ED

6_N

P12LINEIN1

P11LINEIN2

MC

LK

H13

MIC1NM10

N10MIC1P

P9MIC2NMIC2P

N9

MIC3NP8

GP

A2

C9

B8

GP

A3

A8

GP

A4

C8

GP

A5

GP

A6

D8

GP

A7

B7

IREFA14

IRQ

A_N

E13

IRQ

B_N

E14

LDOA_OUTK13

LDOC_OUTN12

LDOD_OUTL12

G14LDOE_OUT

G13LDOF_OUTLDOG_OUT

L13

L14LDOH_OUT

H1CHSENSEP

A7DACO_0DACO_1

B6

A6DACO_2

C6DACO_3

DAC_CLKC4

DAC_DATC5

B5DAC_STR

F1DCIODCIO_INT

J2

C12EXT_LDO

J13FGSENSEN

J14FGSENSEP

GP

A0

A9

GP

A1

B9

GP

A12

C7

U300

C11

AD

_OU

T

AUXO1_OUTM4

AUXO2_OUTP4

BDATAA11

BEARN_OUTM5

BEARP_OUTP5

BOOST_ISND2

C2BOOST_ISP

E1BUCK_FB

CCO1N13

CCO2P14

CHREGH3

H2CHSENSEN

AB3100

C3111u

C34

047

n

D1

D2

D3

D4

G1

G2

S1

S2

R312

Q300 SIA911DJ

0

10u

TP302

0.1u

C315

C348

C35

222

p

2.2u

C339 1u

C307

C32

7

0.1u

C32

5

0R302

0.1u

R309 0

VA605varistor

0.1u

C32

6

1uC312

R30

0

100K

C3022.2u

C3190.1u10u

C317C3140.1u

VA

301

ICV

L05

0510

1V15

0FR

0R306

C3490.1u

300KR320

C33022p

C33133u

32.768KHz

X300

1 210u

VBAT

VDDK_2V75

C318

D301 RSX101VA-30TR

18000pC344

4.7K

R311

C34

51u

4.7u

VDDD_2V65 VBAT

C306

1%1/4W2012

0.1

TP305

VDDG_2V85

R316

D1

D2

1 2 3

CN

300

1u

FB300

C308

1u

R317

C338

VDD_REF

VBAT


1u

R32

110

0K

R314

0

0

DNI

R308

TP

300

C322

SPKRPSPKRN

EAR_REAR_L

HS_EAR_L

HS_EAR_R

TRICKLE

FGS+

FGS-

VBUS

KE

Y_L

ED

6K

EY

_LE

D5

VDDC_2V65

VDDH_2V75

VDDG_2V85

CHS-

BDATA

FGS+

DCIO_INT

OTP

CCO1

VBUS

CHREG

RF_CTRL_DATA


VDDF_2V5

CHREG

DCIO_INT

FGS-

PCB_VERSION

FM_RP

SPK_RCV-

SPK_RCV+


EAR_REAR_L

SPKRPSPKRN

BEARPBEARN

CHS+

MO

TO

R_P

WM

DB_I2S1_WS

VBAT

DB_I2S0_CLKDB_I2S0_WSDB_I2S0_ULDDB_I2S0_DLD

CHS+

DCDC_REFBIAS_CTRL

EXT_LDO

KE

Y_L

ED

2

FM_LP

DB_I2S1_CLK

DB_I2S1_ULDDB_I2S1_DLD

SIMRST_n

SY

SC

LK

1 PC

B_V

ER

SIO

N

BEARPBEARN

MIC1PMIC1NMIC2P

KE

Y_L

ED

1

BDATA

CHS-

VDDD_2V65

VDDA_2V8

VCORE

TE

ST

OU

TR

TE

MP

TX

_AD

C_S

TR

B

AD

OU

T

VB

AC

KU

P

SH

AR

ED

_I2C

_SD

AS

HA

RE

D_I

2C_S

CL

AC

CS

LE

EP

AP

PS

LE

EP

SIMVCC

SIMCLKSIMDAT

RTCCLK

ON

SW

A_n

VDDK_2V75

VDDE_1V8

VDIGRAD_1V8

VBACKUP

DC

ON

ON

SW

B_n

AC

C_I

RQ

_nA

PP

_IR

Q_n

PW

RR

ST

_n

SRST_nSCLK

SDAT

7. CIRCUIT DIAGRAM



E

11

5

LDO 3.3V For MOTOR150mA

6

10

1

F

H

1608

Hirose ( Micro-SD Socket, Normal ,T= 1.68)

C

MOTOR AMP

TOUCH LEVEL SHIFTER

64 7

C

D

B

7 8

EUSY0337101

MICROSD LEVEL SHIFTER

12

9

H

10

1 2

F

GG

TOUCH SCREEN DRIVER IC

12

9

11

2

Touchscreen Interface

Three-Axis Interface Motor Interface

Micro SD Card Interface

MICROSD SOCKET

54

D

E

B

Three-Axis Sensor

3

ENSY0020901

A

3

A

8

INT4

1NC1 NC2

10

NO

T1

11 12N

OT

2

6SCK

SDI8

SDO7

2VDD

9VDDIO

BMA150U401

5CSB

3GND

RS

B6.

8CS

T2R

ZD

402

ZD

403

RS

B6.

8CS

T2R

220K

R41

9

EV

LC

18S

0201

5

VA

403

B2A0

A1C2

A1AUX

GNDD2

PENIRQ-B1 D1

SCL

C1SDA

VDD_REFA2A3

X+C3

X-

Y+B3 D3

Y-

TSC2007IYZGRU405

150K

R402

390

R40

9

C4061u

VDDE_1V8

0

R65

6

RP103K281D-TR-F U406

3CE

2GND

5P

GN

DVDD4 1

VOUT

VA

402

EV

LC

18S

0201

5

0.01u

VBAT

R42

5

51K

C403

1uC414

ZD

401

RS

B6.

8CS

T2R

VA

405

VDD_TOUCH_2V8

DAT1AA2 D1

DAT1BB4

DAT2A DAT2BC4

A4DAT3A

D4DAT3B

GND1B3

GND2C3

A5VCCA

D5VCCB

EV

LC

18S

0201

5

SN74AVCA406EZXYRU403

A3CLKA

D3CLKB

CLK_FA1

CMDAB1

C2CMDB

CMD_DIRB5

B2DAT0A DAT0B

D2DAT0_DIR

C5

DAT123_DIRC1

SWA SWB

4

6

DM3AT-SF-PEJ

2

5

3

78

1

GND

0R423

S400

R416 2.2

VDDH_2V75

DN

IR

424 2.7K

R42

2

VDD_TOUCH_2V8

C40022n

R64

0

0

VDDE_1V8

R42

0

0

51KR411

0.1u

VDD_MOTOR_3V3

C412

R426 0

C409

EV

LC

18S

0201

5

VA

401

EVLC18S02003

VDD_MOTOR_3V3

0.1u

C3

B4

C4

B4GND

B3OE V

CC

AB

2

B1

VC

CB

VA406

U404TXS0104EZXUR

A1A1

A2A2

A3A3

A4

A4

C1B1

C2

B2

B3

EV

LC

18S

0201

5

VA

404

R42

12.

7K

C411

1u

1uC413

R408 51K

1u

VDDG_2V85

VDDE_1V8

RS

B6.

8CS

T2R

ZD

400

C407

TPA6205A1ZQVRU400

BYPASSC1

GNDB2

C2IN+

IN-C3 A3

VDD

VO+B3

VO-A1B1

_SHUTDOWN

R412

150K

VDD_TOUCH_2V8

VA

400

EV

LC

18S

0201

5

1u

C4010.1u

C404

2 4 6 8

1 3 5 7

C410

RA

400

100K

0.1u

1KR413

R414 1K

VDDE_1V8

0

R64

2

VDDG_2V85

VDD_MOTOR_3V3

10uC408

R42

9

100K

100K

R63

7

RP103K331D U402

3CE

2GND

5P

GN

DVDD4 1

VOUT

MOTOR_P

APP_GP_3AXIS_SDA

MICROSD_DAT3_2V85

MICROSD_CMD_2V85

MICROSD_DAT0_2V85


VBAT

MOTOR_N

APP_GP_TOUCH_SDA

APP_GP_TOUCH_SCL

APP_GP_3AXIS_SCL

APP_GP_TOUCH_LDO_EN

MICROSD_DAT0_2V85

MICROSD_CLK_2V85

MICROSD_DAT1_2V85

MICROSD_CLK_2V85

APP_MMC_FB_CLKMICROSD_CLK

MICROSD_CMD_DIRMICROSD_CMD

MICROSD_DAT_DIRMICROSD_DAT0

MICROSD_DAT1MICROSD_DAT2MICROSD_DAT3

MOTOR_PWM

TOUCH_Y+

TOUCH_X-

TOUCH_Y-

APP_GP_TOUCH_PENIRQn_2V75 APP_GP_TOUCH_SCL_2V75


APP_GP_TOUCH_SCL_2V75



APP_GP_TOUCH_PENIRQn_2V75

APP_GP_MMC_DETn

MICROSD_CMD_2V85


APP_GP_3AXIS_INT

APP_GP_MOTORLDO_EN

TOUCH_X+

- 183 -

7. CIRCUIT DIAGRAM



PWRURXDUTXD

3G2.5G

GNDRXTX

VCHARON_SW

VBAT

TOUCH_Y- : GND line shielding to CN

B

1 2


TI : PD = USB, PU = UART

2012

8

USB Transceiver

D

3

D

A

8

Close by uUSB CONN

11

G

E

5 9

DOWNLOAD POINT

9

4

4

10V

6

If VBUS not used, then remove

A

12

H

C

MUIC

12

1 2

B

G

If TI, then 10nF

E

3 7

6

High Speed USB Interface

ESD / EMI Filter OJ

Download Point And TP Test Point

Backlight Charge Pump

34 pin connector To VGA FPCB

MUIC Circuit Micro USB Interface

Close to MUIC

MAXIM : NA = USB, PU = UART

C

F

10

Test Point

1%

5

F

H

7

If VBUS not used, then remove

1110

C5094.7u

L500

82nH

272829

3

3031323334

456789

1314151617 18

19

2

20212223242526

CAM_AVDD_2V8

ENBY0040301GB042-34S-H10-E3000

CN5031

101112

C508

22p

U500

NUS3065MUTAG

CNTRL3

4DRAIN

DRAIN_THERMAL9

GATE6

GND2

IN1

7OUT

5SRC

8VCC

TP501

TP502

0

R515 0

R65

5

2.2K

R51

1

VDDE_1V8

VDDE_1V8

22p

C507

R509

1K

51K

OJ500

R50

0

0R631C

515

0.1u

C50

31u

10R506

VBAT

VBAT

R505 10DNIR507

DNIR518

TP608

TP609

TP607

VBAT

TP605

TP606

C51

4

ICC3

INT

B2

A2ISET

A1MIC

B1RES

SC

LC

2C

1S

DA

B3U1U2

A3B4

UID

VBD5

0.1u

U501

D4AUD1

D3AUD2

D2BAT

CAPD1

COM1C5B5

COM2

A4DN1

A5DP2

GNDC4

6VBAT

VBAT

MAX14526EEWP_TCC6

URT500

12CTS

10DSR

GND1

4NC1

NC278

NC3

NC49

5ON_SW

RTS11

2RX

TX3

C506

22p

R64

1

0

G24

IN 1OUT2

22p

C511

FL500NFM21PC105B1A3

3G1

0

R62

9

100K

R63

0

C6351u

C63

31u

0R517

0.1uC525

FB502

6

7

8

9

CN501

1

10

11

12

13

14

15

2345

FB500

VDDE_1V8

C505 0.1u

R508 DNI

ULCE0505C015FR

VA500

DNI

C502

R503 0

TP500

OJ501

TP604

TP602

12K

R51

0

CTS_ON_ED1

CTS_ON_I

B5DCIO_EDCIO_I

C5

A2DFMS_E

D3DFMS_I

A1DTMS_EDTMS_I

D2

GN

D1

B2

B3

GN

D2

GN

D3

B4

GN

D4

C1

C2

GN

D5

C4

VC

C

VPPFLS_EA5D5

VPPFLS_I

KNATTE2-C2 FL501

A4CFMS_ECFMS_I

D4

CTMS_EA3

CTMS_IC3

B1

4.7u

C51

6

CAM_DVDD_1V8

0R501

RREF

STPD6

TESTC4

F4VBUS

VC

CF

3

B5VCC_IO1VCC_IO2

B2

F5XTAL1XTAL2

F6

B6C6

DATA7

E5DIR

DMC1D1

DPFAULT

E2

GN

D1

C5

D2

GN

D2

GN

D3

E4

D3ID

NC

1F

1F

2N

C2

D5NXT PSW_N

D4

E6REF1V8

E3REG3V3

C2

CFG0E1

B4CFG1CFG2

B3

CHIP_SELC3A4

CLOCKDATA0

B1A1

DATA1DATA2

A2A3

DATA3DATA4

A5A6

DATA5DATA6

ISP1508AETU502

C5130.1u

VBUS

2.2K

R504

VBAT

1uC

632

SD

12T

1G

ZD

500

9

2.2u

C51

7

INS

TP

AR

C634

10GND

9IN

OUTCP6

PGND15

1u

U604 AAT3169IFO-T1

C1+4

5C1-

C2+7

C2-8

11D1D2

1213

D314

D41

D52

D6

EN_SET3

0.1uC500

CN5001

2

FB501

4.7uC501

4.7u

1 uF

C512

C504

C510

C523

1u

TP6030.1u

0R502

VBAT

R513 DNI

TOUCH_Y+TOUCH_Y-

OTP_A

APP_ACC_UART_TX

APP_ACC_UART_RX

CTS_ON

VPPFLASH_E

VBUS

CI_RES_n


APP_GP_BL_EN

WLED_PWR

WLED1

SYSCLK0

TOUCH_X+TOUCH_X-

APP_ACC_UART_TX

VPPFLASH_EVPPFLASH

CTS_ON

CTS_ON

ONSWB_n

HS_EAR_RHS_EAR_L

USW_ID

USW_ID

APP_GP_VGA_SDNAPP_I2C_SDA

APP_I2C_SCL

CI_DATA[1]

CI_DATA[3]

CI_HSYNC

CI_DATA[6]

CI_DATA[0]

CI_DATA[2]

CI_DATA[4]

CI_VSYNC

MIC2P

FM_ANT

APP_ACC_UART_RX

ACC_UART0_TX

APP_UART_TX

USW_DPUSW_DM

VPPFLASH_E

APP_ACC_UART_TXAPP_ACC_UART_RX

VBUS

VBUS

APP_ACC_UART_TX

SPK_RCV+

ACC_UART0_RX

APP_UART_RX

USW_DMUSW_DPUSB_DP

APP_GP_USW_INT


USB_DM


USB_XTAL1

APP_ACC_UART_RX

SPK_RCV- CI_PCLK

CI_DATA[7]

CI_DATA[5]

VBUS

USB_DPUSB_DM




ACC_USB_HS_DIR

7. CIRCUIT DIAGRAM



6 8

1

9

F

G

BT

11

SIM

7

C

KEY ESD Protection

H

11

WLAN

SPI

D

10

TP

5

A

D

LC Filter for power noise from GSM RF

8

E

FM

GPS

FLASH

6

LDO for ISP

10

2 3

9

H

E

4

LDO for 5M & VGA Camera

Close to ABB

7

5M Camera Interface

60 Pin Connector To Sub PCB50 Pin Connector To KEY and LCD FPCB

B LDO for LCD Power

SOCKET

12

B

5M CAMERA Conector

F

G

5M camera ISP(MTEK vision)

A

5 12

C

3 42

1

59

6

60

789

G1 G2

G3 G4

EV

LC

14S

0205

0V

A60

4

4546474849

5

5051525354555657583

30 313233343536373839

4

4041424344

1516171819

2

20212223242526272829

CN601

1

1011121314

C60

11u

0.1u

CAM_DVDD_1V8

PRSB6.8C

D601

C60

6

R62

810

K

0R

601

C625 47n

G2

10

INOUT_A11

2INOUT_A2

INOUT_A33

4INOUT_A4

9INOUT_B1

INOUT_B28

7INOUT_B3

INOUT_B46

9

8INOUT_B2

INOUT_B37

6INOUT_B4

FL601

EVRC14S03Q030050R

5G

1

EVRC14S03Q030050R

FL602

5G

1

G2

10

1INOUT_A1

INOUT_A22

3INOUT_A3

4INOUT_A4

INOUT_B1

CAM_AFVDD_2V8

5.6KR616

VOUT187

VOUT2

VDDE_1V8

R610 10K

RT9011-MGPQWU600

EN12

EN23

GND54

NC1NC2

6

PG

ND

9

1VIN

R60

310

K

C6VDDA_2_8RXVDDA_2_8TX

A7

VDDCOD3

VDDCO_ED4

VDDIO_2_8VE5

C5VSSA_RX

B7VSSA_TX

F1VSYNCO

47nC626

H4SDO4SDO5

G4SDO6

F4F5

SDO7

SEL1G8

H7SIMO_S_GPIO31

SMCKOF8

SOMI_S_GPIO30G7

D1SRESET

H6SS_S_SDO8

A8TCLKTCLKB

B8C7

TDATATDATAB

C8

A4TEST_0

F7TXD

PCLKOE1

RCLKA6B6

RCLKBA5

RDATARDATAB

B5

RGVDD_1_8VE4

RXDE7

SCLK_S_SDO9H8

SCL_M_SS_MA2

A3SCL_S

B2SDA_M_MISO_M

SDA_SB3

F2SDO0SDO1

H3G3

SDO2SDO3

F3

GPIO10_SCLK_MA1B1

GPIO11_MOSI_M

GPIO20_PWM0H1G2

GPIO21_PWM1H2

GPIO22_PWM2GPIO23_PWM3

D2

H5GPIO24_SCLK_M

GPIO25_SS_MF6G6

GPIO26_MISO_MG5

GPIO27_MOSI_M

GPIO28_SCL_MC1C2

GPIO29_SDA_M

HSYNCOE2

MCLKE8C3

NRESET

NSRESETG1

MV9319

D6AVDD

D5AVDDP

B4DGND1

C4DGND2

D7DGND3DGND4

D8

DGND5E3

DGND6E6

LCD_AVDD_2V8

U602

C60

70.

1u

VBAT

1u

ISP_DVDD_1V8

C60

3

4.3K

R61

9

FB603

100ohmR627

R614 47

1uC619

R60

00

FB

600

VA

602

RS

B6.

8CS

T2R

EV

LC

14S

0205

0V

A60

1

C6231u

INOUT_B37

6INOUT_B4

PRSB6.8C

D600

5G

110

G2

1INOUT_A1

INOUT_A22

3INOUT_A3

4INOUT_A4

INOUT_B19

8INOUT_B2

1P1

P22

3P3

P44 5

P5

6P6

P77

8P8

EVRC14S03Q030050R

FL600

ICMF214P101M

FL603

7.5p

R61

84.

3K

7

8

9

C610

13

14

15

16

17

18

19

2

20

21

22

23

24

3

4

5

6

CN603

GB042-24S-H10-E3000ENBY0034201

1

10

11

12

DN

IR

611

R645 10

R63

8

0

ZD

605

RS

B6.

8CS

T2R

C6151u

VBAT

VBAT

0.1uC609

LCD_DVDD_1V8

C61

31u

VDDK_2V75

PR

SB

6.8C

ZD

601

FB604FB605

R654 00R653

0.1uC616

1uC

604

TP601

ES

D9X

5.0S

T5G

ZD

603

INS

TP

AR

ZD

602

ES

D9X

5.0S

T5G

INS

TP

AR

P1

1 2P

23

P3

P4

45

P5

P6

6P

77

P8

8

D603PRSB6.8C

UL

CA

2114

C01

5FR

VA

600

CAM_AVDD_2V8

R626 100ohm

0

R635

0

R634

0

R62

1

PR

SB

6.8C

ZD

600

CAM_AFVDD_2V8

ISP_DVDD_1V8

C618

4.7K

R60

9

1u

PRSB6.8CD602

R625

5.6K

C60

21u

ISP_DVDD_1V8

CAM_AVDD_2V8

1uC628

1uC

611

NC1NC2

6

PG

ND

9

1VIN VOUT1

87

VOUT2

RT9011-MGPQWU601

EN12

EN23

GND54

47nH

ISP_AVDD_2V8

L600

BLM15AG100PN1FB602

0R632

R64

4

100K

2.2uC638

100K

R62

2

10K

R60

4

FB

601

VBAT

CAM_DVDD_1V8R

SB

6.8C

ST

2RZ

D60

6

C620

LCD_AVDD_2V8

1u

9P

GN

D

VIN1 8

VOUT1VOUT2

7

C6271u

U603 RT9011-MGPQW

2EN1

3EN2

5GNDNC1

46

NC2

1u

1uC608

C629

R617 100ohm

1uC630

C61

21u

C6171u

0.1uC624

LCD_DVDD_1V8

ISP_AVDD_2V8

R60

8D

NI

C622

VDDE_1V8

VA

603

ICV

S05

14X

350F

R

2.2u

ES

D9X

5.0S

T5G

ZD

604

INS

TP

AR

10K

R60

7

VBAT

1uC

614

C60

51u

414243444546474849

5

50

6789

272829

3

30313233343536373839

4

401213141516171819

2

202122232425 26

51 52

53 54

1

1011

0R633

CN604

TP600

OTP

ACC_GPS_START

ISP_GP_FLASH_EN

APP_GP_LCD_DLDO_ENAPP_GP_LCD_ALDO_EN

OTP_A

C621220p

LCD_DATA[7]

LCD_DATA[3]


LCD_DATA[0]

ISP_GP_FLASH_SET

ISP_GP_FLASH_INH

SIMCLK

SIMDATSIMVCC

APP_GP_ISP_LDO_EN

ONSWA_nKEYIN2

KEYIN2

LCD_DATA[4]


WLED_PWR

WLED1

KEYIN0

CCO1

KEYOUT0

KEYOUT2

KEY_LED1

TRICKLE

LCD_VSYNC

LCD_RESET_N

APP_GP_LCD_IF1


APP_GP_LCD_ID

FM_RP

ACC_GP_GPS_RESETn

MOTOR_NMOTOR_P

KEYOUT1

KEYIN3

MIC1P

KEYOUT2KEYOUT1KEYOUT0

KEYIN0KEYIN3

ACC_SPI_MISOSIMRST_n

APP_ACC_UART_TXAPP_ACC_UART_RXVPPFLASH_ECTS_ON

ACC_SPI_WLAN_CSnACC_GP_SPI_WLAN_IRQn


ACC_GP_WLAN_EN

VBACKUP

LCD_RD_N

LCD_RS

APP_I2C_SDAAPP_I2C_SCL

FM_LP

FM_ANT

MCLKSEC

RTCCLK

ISP_SENS_I2C_SCL

CLKN

DATAN

ISP_SENS_I2C_SDA

CLKP

DATAP


ISP_GP_FLASH_SETISP_GP_FLASH_ENISP_GP_FLASH_INHACC_GP_WLAN_RESETn

ACC_SPI_MOSIACC_SPI_CLKACC_GP_SPI_BT_CSn

BT_CLKREQ_nRESOUT2_n

PCM_ULDPCM_DLD

PCM_SYNCPCM_CLK

ACC_GP_GPS_PONACC_UART3_RXACC_UART3_TX

ACC_UART3_RTSACC_UART3_CTS

ISP_SENS_I2C_SDA

APP_GP_CAM_LDO_EN

RESOUT1_nAPP_GP_FM_GPIO2

ACC_GP_SPI_BT_IRQ

CI_DATA[6]CI_DATA[5]CI_DATA[4]

5MCAM_RESET_N

ISP_SENS_I2C_SCL

DATANCLKP

DATAP

CLKN ISP_SENS_MCLK


CI_DATA[7]SYSCLK0

CI_HSYNCCI_VSYNC

CI_RES_n

CI_PCLK

5MCAM_RESET_N

ISP_SENS_MCLK

LCD_WE_N

LCD_CS_N

KEY_LED2

MIC1N


- 185 -

7. CIRCUIT DIAGRAM



2

Keep away from noise signals

H

10

B

D

C

9

10

GPS Power

11

E

3

D

6

on L1, L2 and L3

A A

5

7 93

1 2

12

4

70x: BT/WiFi RF path78x: BT/WiFi Antenna Pattern

71x~72x: WiFi

77x: GPS LNA

for WLAN-BT coexistenceB

11

1

G

8

C

73x~74x: Bluetooth

75x~76x: A-GPS

Reference Number

12

4

E

F

BT+FMWLAN

GPS Clock Buffer

GPS LNA block

A-GPS

Common GND on L1, L2 and L3

5

POWER

H

76

8

G

F

Careful routing of BT_CLK

Analog GND must be Isolated from

RF GND: Isolate from Common GND

C725

R75

4

100K

VDD_BT

DNI

C7181u

R73

4

100K

C7340.1u

100p

C77

2

C7710.1u

120p

C74

3

ALM-1612

FIL_OUT4 3

GNDRF_IN

2

1S

_D

VDD5

2.2u

U770

R78

1

0

C770

WIFI_RF_GWIFI_RF_G

10u

VDD_WLAN_3V3

DEA212450BT-7043C15

BP1

4BP2 BP_DC

2

3G

16

G2

1U_BP

C71

4VDDE_1V8

WIFI_RF_G

VDD_WLAN_1V8

FL730C71

01u

VBAT

TP751

R739

110

R71

7

0

0

R716

0

R73

5

VSS_BT_RF

SPI_SINTN_SD_DAT2

23T_R3_N

T_R

_N36

18V

DD

12

17V

DD

18

25VDD18A

27V

DD

30

VD

D_H

OS

T_I

O9

VD

D_P

A28

WL_

AC

TIV

E30

PGND2PGND3

3940

PGND4

41PGND5

42PGND6

43PGND7

44PGND8

45PGND9

RE

SE

TN

32

6SCLK

SD

_DA

T3

1235

SLE

EP

_CLK

14S

PI_

CL

K_S

D_C

LK

SPI_SCSN_SD_DAT021

SPI_SDI_SD_CMD20

5SPI_SDO_SD_DAT1

22

BT

_PR

IOR

ITY

29B

T_S

TA

TE

7ESCN

GND11

GND23

GND38

GND419

GND526

GP

IO0

34

GP

IO1

1613G

PIO

2

GP

IO4

15

GP

IO5

1110G

PIO

6

PD

N31

PGND13738

LBWA18HNVZ-305M710ANT

2

ANT_SEL_N244

ANT_SEL_P

33

4.7n

H

R78

0

C722

3CE

2GND

5P

GN

DVDD4 1

VOUT

1u

XM0830SK-TL1301TMP

ANT5

GND11

GND24

GND36

GND49

GND51113

PGND

8PORT1PORT2

2

RFGND13

RFGND27

12VCTL

10VDD

RP101K182D U711

0 FL700

C707

R70

0

1u

4pC706C705

4pC704

0

R755

DNI

110

R741

VDDK_2V75

VDD_WLAN_1V8

C75

7N

A

L750 6.8nH

VSS_BT_ANA

C7641u

10p

C74

2

VDDE_1V8

C76

61u

100K

R73

2

A23 GND

5VCC

Y4

1 _OE


C7621u

100pC701

VGPS_1V8

100K

R71

4

2.2n

HL

770

VDD_WLAN_1V8

VDD_BT

10n

HL

771

0R772

TP711

VBATVDD_WLAN_1V8

R701 0

1u

VDD_WLAN_1V8

C71

5

VGPS_1V8

10u

C71

6

C72

01u

C739

R71

010

0K

3CE

2GND

5P

GN

DVDD4 1

VOUT

0.1u

VS

SD

1V

SS

D2

D3

D7

VS

SD

3E

4V

SS

D4

VS

SD

5E

5

VS

SD

6F

4

VS

SIF

SU

BB

3C

1V

SS

RF

SY

NT

H

RP101K332D U710

TDO

F1TESTMODE

TMSA5

TRST_NA6

G6TX_SDA_MISO

D4VDDCORE1VDDCORE2

D6E3

VDDCORE3VDDCORE4

E6

VDDIFSYNTHD1

VD

DIO

1B

6G

3V

DD

IO2

VD

DIO

3G

7

F6VDDLP_LPREGOUT

VDDRFD2

VPDD5

B5

CN

TIN

G1CTS_N_I2C_GRP1_SCS_N

F7INTR_N

A3

LP

RE

GIN

RESET_NG4

RFINB1

E2RFREGOUT

E1RFSREGOUT

F5

RT

CC

LK

RTS_N_I2C_GRP0_MOSIG5

RX_SCL_SCKG2

F3STANDBY_N

SY

NC

_PP

SE

7

A7TCK

TC

XO

A2

TDIC7B7

U751

ATEST0B2

ATEST1C3

BBREGOUTA4

C4

BB

RF

RE

GIN

BMS0C6B4

BMS1_I2C_A0BMS2_UARTCS_N

C5

F2

VDDK_2V75

TP713

BCM4750

C7211u

FB730

VBAT

60

C7552.2nH

FB

710

100n

HC

758

VDDE_1V8

100K

R71

5

100K

R73

8

DNIR733

1uC

765

100nHL772

C73

50.

1u

C730

0.1uC753

0.1u

100K

R71

1

C7231u

C73

60.

1u

WIFI_RF_G

R74

0

0

22n

C74

1

100p

WIFI_RF_G

0R750

C717

C761

TP712

WIFI_RF_G

1u

VDDE_1V8

VDDE_1V8

C7021p

1uC763

VDDE_1V8

VDD_WLAN_3V3

VDDE_1V8

VDDE_1V8

TP753

4.7uC731

R730

33

C71

2

VDDK_2V75

1CN750

1

10u

R752

CN751

10

X7501

GND1

GND23

NC12 5

NC2

OUT4

VCC6

R7370

KT2520F16369ACW18T

FB

711

1uC737

100K

VSS_BT_ANA

VDDE_1V8

R75

6 TP752

33

R753

100pC732

C71

1

C7510.1u

VSS_BT_RF

1u

C7601u

VSS_BT_RF

VSS_BT_RF

1uC738

2.2uC750

R73

1

C7542.2u

100K

3CE

2GND

5P

GN

DVDD4 1

VOUT

WIFI_RF_GRP101K182D U752

C7521u

C75

60.

5p

TP710

VDDE_1V8

C700

C74

022

n

VSS_BT_ANA

0

VDDE_1V8

C7330.1u

1uC759

A

GND

OE VCC

Y

VGPS_1V8

VDD_WLAN_1V8

NL17SZ126XV5T2GU750

10

R770

L5L6

NC6

R757

0

A5

FM_LOUTB5

FM_RCLKD7

C8FM_RFGND

C5FM_ROUT

C9FM_RSTB

E9FM_SCLK

FM_SDIOD8

FM_SENBD9

FM_VAA4

FM_VDB3

FM_VIOD6

D4NC1NC2

F7F8

NC3NC4

L4

NC5

H1L1

BT_VSSRF2BT_VSSRF3

J2K2

BT_VSSRF4

BT_WAKEUPL9

B8FM_FMIP

FM_GND1A3B4

FM_GND2FM_GND3

B6

FM_GND4B7C4

FM_GND5C6

FM_GND6C7

FM_GND7FM_GND8

D5

FM_GPIO1A7A6

FM_GPIO2FM_GPIO3

G4H3

BT_VSSANA11H4

BT_VSSANA12

D2BT_VSSANA2BT_VSSANA3

E3

BT_VSSANA4F1F2

BT_VSSANA5BT_VSSANA6

F3F4

BT_VSSANA7G1

BT_VSSANA8G3

BT_VSSANA9

H6BT_VSSDIG1

H7BT_VSSDIG2BT_VSSDIG3

H8K8

BT_VSSDIG4L8

BT_VSSDIG5

BT_VSSRF1

C1C2

BT_RSVR_NBT_RSVR_RF

M2

BT_TEST1H2G2

BT_TEST2

BT_UART_CTSK6

J6BT_UART_RTS

BT_UART_RXDH9

G7BT_UART_TXD

E6BT_VDD_CLD

M6BT_VIO_ABT_VIO_B

J9

BT_VIO_CN3N5

BT_VIO_DBT_VIO_E

G8

BT_VSSANA1D1

BT_VSSANA10

E2E4

BT_HVA5BT_HVD

N7

BT_LP_CLKK9

BT_PCM_AK5M5

BT_PCM_B

M4BT_PCM_CLK

N4BT_PCM_SYNC

BT_REF_CLK_INF6

BT_REG_CTRLJ4

K7BT_RESETN

J1BT_RFNBT_RFP

K1

BT_RSVR_CL1B2

BT_RSVR_CL2C3M8


BT_CLK_REQ_IN_2

J7BT_CLK_REQ_OUT_1

J8BT_CLK_REQ_OUT_2

BT_CONFIG_1L7

BT_CONFIG_2M7N6

BT_CONFIG_3

BT_GPIO_0G9

K4BT_GPIO_10

K3BT_GPIO_11

BT_GPIO_16J3L3

BT_GPIO_8

BT_GPIO_9M3

BT_HOST_WAKEUPE8

BT_HVA1L2D3

BT_HVA2BT_HVA3

E1

BT_HVA4

STLC2593U731

BT_AF_PRGG6

BT_CLK_REQ_IN_1E7F9

C71

322

p

C71

90.

1u

C724

100K

R71

3

1u

DUMMY FEED

VDD_BT

ANT780

0R

742

ACC_GP_GPS_PON

RESOUT2_n

PCM_DLDPCM_ULD

PCM_CLKPCM_SYNC

ACC_GP_WLAN_RESETn

BT_CLKREQ_n

ANT_SEL_N

BT_TXRX


WIFI_TXRX

WIFI_TXRX

BT_TXRX

RESOUT1_n

MCLKSEC

GPS_CNTIN

ACC_GP_GPS_PON

GPS_CNTIN

PTA_WLAN_ACTIVE

ACC_UART3_TX

ACC_SPI_WLAN_CSn

FM_LPFM_RP

ACC_GP_GPS_PON

ACC_GPS_STARTRTCCLK

ACC_UART3_CTS

ACC_GP_GPS_RESETn

ACC_UART3_RTS

ACC_UART3_RX


BT_CLKREQ_n

BT_CLKMCLKSEC

ACC_GP_GPS_PON

ACC_SPI_CLK

ACC_GP_SPI_BT_CSn

RTCCLK

APP_I2C_SCL

APP_I2C_SDA

BT_CLK

FM_ANT

WLAN_SLEEPn

ACC_SPI_MOSI

PTA_WLAN_ACTIVE

ACC_GP_SPI_BT_IRQ

RTCCLK

ACC_SPI_CLK

ACC_SPI_MISO

APP_GP_FM_GPIO2

WLAN_SLEEPn


ACC_SPI_MOSI

ACC_SPI_MISO

ACC_GP_SPI_WLAN_IRQn

RTCCLK

ACC_GP_WLAN_EN

ANT_SEL_N

7. CIRCUIT DIAGRAM



8

BT

For Product inspection TP(7PIN)

B

10

D

7

8 9

PLUG

3 4 5

E

SIM

SPI

71

WLAN

FM

H

3 9

2

to be separated when routing

1 2

10

5

BACKUP BATTERY

6

A

G

CAMERA FLASH LED

A

GPS

F

11

11

12

B

6

H

F

G

4

C

FLASH

TP

12

SIM CONNECTOR

60 Pin Connector From Main PCB

SIM InterfaceBoost Converter for Camera Flash

Backup Battery

Motor

D

SIMDAT and SIMCLK Siganls

E

C

VBAT

R80

610

0K

AGND4

1CT

2EN_SETFLEN

3 12FLGND

FLINH10

FLOUTA13

FLOUTB11

GND9

15G

_SL

UG

IN5

LX6

OUT87

PGND

14RSET

L8001u

U800 AAT1270IFO-T1

53545556575859

6

60

789

G1 G2

G3 G4

39

4

40414243444546474849

5

505152

2526272829

3

30 3132333435363738

1

10111213141516171819

2

2021222324

1

2

CN800

VDDK_2V75

CN801

33p

VA806EVLC14S02050

C805

EV

LC

18S

0200

3V

A80

0

TP802

10K

R80

3

SIMVCCSIMVCC

22p

C803R805

5VPP

TP800

0

J800

3CLK

GND4

7GND1GND2

86

I_ORST

2VCC

1

0

TP804

R814

EVLC14S02050VA807

33p

C800

C802

2.2u

VBAT

TP801

100K

R80

7

1u

C804

TP803

200K

R80

1

DNIC806

VA

801

EV

LC

18S

0200

3

VDDE_1V8

EV

LC

18S

0200

3V

A80

2

LD800

C80147n

BAT800

2.2uC807

PCM_DLDPCM_SYNC

PCM_CLKACC_GP_GPS_PON


ACC_UART3_RTSACC_UART3_CTSACC_GPS_START

ACC_GP_GPS_RESETnFM_LPFM_RP

CTS_ON

APP_ACC_UART_TX

VPPFLASH_E


ISP_GP_FLASH_INH

MOTOR_N

RESOUT1_nAPP_GP_FM_GPIO2


VBACKUPOTP_SUBMOTOR_P

ACC_GP_SPI_BT_IRQACC_GP_SPI_BT_CSn

BT_CLKREQ_nRESOUT2_n

PCM_ULD

FM_ANT

RTCCLK

ACC_SPI_MOSIACC_SPI_CLKACC_SPI_MISO

ACC_GP_WLAN_ENACC_GP_SPI_WLAN_IRQnACC_SPI_WLAN_CSnACC_GP_WLAN_PWR_DOWNnACC_GP_WLAN_RESETn

SIMCLKSIMVCCSIMDATSIMRST_n

APP_ACC_UART_RX


ISP_GP_FLASH_INH

VBACKUP

OTP_SUB

APP_ACC_UART_TX

CTS_ON

VPPFLASH_E

APP_ACC_UART_RX

MOTOR_P

MOTOR_N

MCLKSEC

SIMDAT SIMCLKSIMRST_n

- 187 -

7. CIRCUIT DIAGRAM



4 5 6 7

7 8

SEND CLEAR KEY

12

C

D

E

F

D

11

9 1 0 11

GG

H

C

D

E

F

12

A

G

5

H

VOLUME KEY

5 12

B

C

END KEY

10

4

8

AUTO FOCUS KEY

11 12

A

C

1 2 3

2 3

HALF SHUTTER

6

4 5 6 9

TOUCH LOCK KEY

7 8

SOCKET

FULL SHUTTER

B

2 3 41

D

E

F


Key Matrix Main Key LED ( 4ea)

ANT FeedingMain MIC

40 Pin Connector To LCD

6 7 8

E

F

1 2 3

G

H H

1 9 10

10

119

9

40

41

42

43

44

45

46

47

48

49

5

50

6

7

8

25 26

27

28

29

3

30

31

32

33

34

35

36

37

38

39

4

11

12

13

14

15

16

17

18

19

2

20

21

22

23

24

CN251 52

53 54

1

10

C1002DNI

VBAT

LCD_DVDD_1V8

OUT100

0

LCD_AVDD_2V8

LD1003

R3

SSC-TWH104-HL

LCD_AVDD_2V8

VB

AT

VOLUME_UP

R60

0R123

DNIC1004

LCD_DVDD_1V8

SW1001

ANTG1G2

OUT101

UFL-R-SMT10

SSC-TWH104-HL

LD1001

LD1002

SSC-TWH104-HL

LD1000

SSC-TWH104-HL

39

22

40

23242526272829

456789

21

303132333435363738

1

10111213141516171819

2

20

3

VOLUME_DOWN

CN1

SEND

C100047p

A

B B_

C C_

D

R4

EVPAHBD6ASW1000

LOCK

0

RB521S-30

D1000

3

O4

P1

ENDCLR

MIC100

SPU0410HR5H-PB

G12

G2

LCD_DATA[5]

LCD_IF0

LCD_RESET_N

APP_GP_LCD_IF1

KEYIN0KEYIN2

LCD_WE_N

LCD_CS_N

WLED1WLED_PWR

LCD_VSYNC

APP_GP_LCD_ID


LCD_DATA[7]

KEYIN2

KEY_LED1

KEYOUT2

WLED1

WLED2

WLED3

WLED4

LCD_DATA[3]

LCD_DATA[1]

LCD_DATA[6]

LCD_RS

LCD_DATA[4]

LCD_DATA[2]

LCD_DATA[0]

LCD_RD_NLCD_DATA[5] KEYIN0

MIC1P

KEYOUT1

LCD_CS_N

LCD_DATA[6]

LCD_RS

LCD_DATA[4]

LCD_DATA[2]

LCD_DATA[0]

LCD_RESET_N

APP_GP_LCD_ID

APP_GP_LCD_IF1

WLED_PWR

LCD_VSYNC

LCD_WE_N

KEY_LED2

ONSWA_n

LCD_DATA[7]

LCD_RD_N

LCD_IF0

WLED5

KEYOUT0

KEY_LED2

ONSWA_n

KEYIN3

MIC1N

CCO1

LCD_DATA[1]

LCD_DATA[3]

KEY_LED1

KEYIN3

KEYIN0

KEYOUT1

KEYOUT0

ONSWA_n

KEYOUT2

KEYIN0

KEYIN3

KEYOUT2

KEYOUT1CCO1

MIC1NMIC1P

7. CIRCUIT DIAGRAM



C C

12

PLUG

B

6 7

E

F

E

F

G

5 7

11 12

A

B

H

1 2 3

D

8 9 10 11

1 2 3 4 5

4

8

6


VGA Camera TOUCH CONNECTOR

G

H

A

D

9 1 0

51R904

28

29

3

30

31

32

33

34

4

5

6

7

8

9

13

14

15

16

17 18

19

2

20

21

22

23

24

25

26

27

CAM_DVDD_1V8

CN9011

10

11

12

G2

G3 G4

CAM_DVDD_1V8

conn_axk7l10225CN400

1 102345 6

789

G1

47R910

VDD15_1A5

VDD15_2E4

D2VSYNC

0.1uC913

DATA6C3D4

DATA7

A3DCLK

DVDDB6

B5EXTCLK

GND1A4

GND2C4

GND3E2E3

GND4

HSYNCD1

IOVDDA2

F1

PG

ND

C6PWRDWN

D3RESET

D6SCLSDA

C5

U901TCM9000MD

E5AVDD

B3DATA0

B1DATA1DATA2

B2

DATA3B4C1

DATA4DATA5

C2

C9000.1u

CAM_AVDD_2V8

CAM_AVDD_2V8

0.1uC901

CN9021

2

CI_PCLK

CI_RES_n

SPK_RCV-

SPK_RCV+

TOUCH_Y+

TOUCH_X+

TOUCH_X-

TOUCH_Y-

TOUCH_Y+

TOUCH_X+ TOUCH_Y-

TOUCH_X-

CI_DATA[1]

CI_DATA[5]

CI_DATA[3]

SYSCLK0

SPK_RCV-

SPK_RCV+

APP_I2C_SCL

APP_I2C_SDA

CI_RES_n

SYSCLK0

APP_GP_VGA_SDN

CI_DATA[0]

CI_DATA[7]

CI_DATA[6]

CI_VSYNC

CI_HSYNC


CI_HSYNC

APP_GP_VGA_SDN


CI_VSYNC

CI_PCLK

CI_DATA[2]

CI_DATA[4]




8. BGA Pin Map

8. BGA Pin Map

DB3200 ( Digital BB)

: NC pin



8. BGA Pin Map

AB3100 (Analog Baseband)

: NC pin




8. BGA Pin Map

MCP (2G NAND / 1G SDRAM)



8. BGA Pin Map

RF3300




8. BGA Pin Map

Bluetooth

STLC2593

Top View

NC pin



8. BGA Pin Map

GPS

BCM4750

Top View

BMS0

BMS1_I2C_A0

BMS2_UARTCS_N

TX_SDA_MISO

RX_SCL_SCK

CTS_N_I2C_GRP1_SCS_N

RTS_N_I2C_GRP0_MOSI

INTR_N

RESET_N

STANDBY_N

TCK TDO

ATEST0

VSSD1

VSSD2

VSSD3

VSSD4

VSSD5

VSSD6

VSSRFSYNTH

VSSIFSUB

VDDCORE4

VDDCORE3

VDDCORE2

VDDCORE1BBREGOUT

VDDLP_LPREGOUT

VDDIFSYNTH RFSREGOUT

VDDRF RFREGOUT

RFIN

LPREGIN

VDDIO3

VDDIO2

VDDIO1

BBRFREGIN

TCXO

RTCCLK

SYNC_PPS

CNTIN

Not use

TRST_N

TDI

TMS

ATEST1

TESTMODE

VPD

U602 ISP chipsetNo 5M camera

FL501 EMI/ESD filterNo UART communicationNo download

U404 Touch Level shifterNo touch operation

U405 Touch screen driver ICNo touch operation

U406 LDO for touchNo touch operation

U601 LDO for cameraNo VGA cameraNo 5M camera

U603 LDO for ISPNo 5M camera

U400 Motor Amp No motor operation

U402 LDO for MotorNo Motor operation

U403 MicroSD level shifterNo SD card operation

S400 SD card socketNo SD card operation

U401 3-Axis sensorNo 3-Axis sensor operation

X100 26M CrystalNo bootingNo service

U111 RFICNo service

U101 FEM + GSM PANo service

U102 WCDMA band I PANo service

U107 WCDMA band VIII PANo service

U109 DC/DC converterNo service

- 195 -

9. PCB LAYOUT



9. PCB LAYOUT



CN500 5Pin Micro USB Con.No ChargingNo headsetNo download

U604 Backlight charge pumpNo display

CN603 5M camera Con.No 5M camera

U500 OVP ICNo charging

U501 MUICNo downloadNo headset

U502 USB transceiverNo downloadNo data service

CN503 VGA FPCB Con.No VGA cameraNo touch operationNo sound

CN601 60Pin Sub Con.No SIMNo GPS operationNo Wi-Fi operationNo BT operationNo FM radio operationNo Flash

U200 MemoryNo booting

U201 DBBNo bootingNo serviceNo display

U300 PMICNo power onNo serviceNo chargingNo sound

X300 crystalNo power on

U301 Audio Amp No Sound

U600 LDO for LCDNo display

SW100No service SW101

No service

CN604 50Pin Con.No displayNo keypad inputNo power onNo mic input

- 197 -

9. PCB LAYOUT



CN801 Motor padNo motor operation

J800 SIM socketNo SIM

LD800No flash

U770 GPS LNANo GPS

U751 GPS ICNo GPS

X750 TCXO for GPSNo GPS

M710 Wi-Fi ModuleNo wi-fiservice

U731 BT+FM radio ICNo BT connectionNo FM radio

ANT780No BT connectionNo Wi-Fi service

U800 bust converterNo flash

CN800 60Pin Sub Con.No SIMNo GPS operationNo Wi-Fi operationNo BT operationNo FM radio operationNo Flash

CN750/CN751 GPS ant. padNo GPS

9. PCB LAYOUT



MIC100No mic

CN2 50Pin Con.No displayNo keypad inputNo power onNo mic input

SW100No service

LD1001No power on

- 199 -

9. PCB LAYOUT



CN1 40Pin Con.No display

9. PCB LAYOUT



CN400 touch con.No touch operation

U901 VGA cameraNo VGA operation

CN901 VGA FPCB Con.No VGA cameraNo touch operationNo sound

- 201 -

9. PCB LAYOUT



CN902 speaker padNo sound




10. CALIBRATION

10. CALIBRATION

10.1 General DescriptionThis document describes the installation and software usage for the calibration of LG’s

GSM/GPRS/EDGE/WCDMA Multimedia Mobile Phone. The calibration menu and it’s result is displayed in PC

terminal by Mobile phone.

10.2 Environment

10.2.1 H/W Environment- PC with RS-232 Interface & GPIB card installed

- GSM/GPRS/EDGE/WCDMA Multimedia Mobile Set

- Agilent 8960 Series 10 E5515C Instrument (E1987A above version A.05.28)

- Tektronix PS2521G Power Supply or Agilent A66311B

- ETC (GPIB cable, Serial cable, RF cable, Power cable, Dummy battery)

10.2.2 S/W Environment- National Instrument GPIB & VISA (version 2.60 full) driver install

- Agilent 8960 VXI driver(E1960) install

- HotKimchi EXE files

- OS : Window98, Window2000, WindowXP

10.2.3 Configuration Diagram of Calibration Environment

Figure 10-1. Calibration Configuration

KF757



10. CALIBRATION

10.3 Calibration EnvironmentEnsure that the following conditions are maintained throughout the duration of the tests and calibrations

described within this document.

Parameter Min Typical Max Unit

Temperature 15 25 30 C

Relative

Humidity20 40 75 %

Vbatt 3.6 3.7 3.8 V

Supply current 0 3 A

Table 10-1. Nominal Environmental Test Conditions




10. CALIBRATION

10.4 Program Operation

10.4.1 HotKimchi Program OverviewWhen trying to calibrate the mobile phone, the service engineers make a configuration of calibration

environment like Figure10-1. And if you finish making configuration, please execute the HotKimchi

program.

See Figure 10-2.

HotKimchi supports following functions.

- Calibration of GSM850/900/1800/1900, WCDMA 2100/900

- Instrument (Agilent8960, Tektronix PS2521G) control

- UART communication with mobile phone

GT500

Figure 10-2. HotKimchi Window



10. CALIBRATION

10.4.2 SETTINGSelect a Ezlooks menu.

Select “OFF-LINE” in the EZLOOKS Mode.




10. CALIBRATION

Select a Line System menu.

Select “MANUAL” in the RUN MODE.

Select “NO” in the MULTI CAL SYSTEM.

GT500



10. CALIBRATION

Select a Logic Operation menu.

Select LOGIC MODE that you want.

1. CAL only

2. AUTO only

3. CAL + AUTO

Select UART Port for only S/B1 to communicate with mobile phone.

GT500




10. CALIBRATION

10.4.3 Calibration Procedure

Select a model name – GT500.

Click the START button.

※ RF Calibration steps as follow :

DCS → PCS → PCS → GSM850 → WCDMA2100 → WCDMA900

When RF calibration is finished, the result of judgment will be displayed.

GT500

GT500

- 211 -

11. EXPLODED VIEW & REPLACEMENT PART LIST

11.1 EXPLODED VIEW



65 2

1

5

4 9

1819

20 6325

26 27 28

3264

30

31

60

67

29

33

6314

59

317

16

1510

11

61

2221

38

3536

34

37

51

4547

48

46

49

666

50

3940

68

4142 43

4452

53

7

2413

585756

54

5512

8

ASS’Y EXPLODED VIEW



A

B

C

D

E

FEDCBA

F





by SBOM standard on GCSC

LevelLocation

No.Description Part Number Spec Color Remark

2 AAAY00 ADDITION AAAY0395901WITHOUT

COLOR

3 AMBA00 MANUAL ASSY,OPERATION AMBA0155801 GT500 manual assy for TMUWITHOUT

COLOR

4 MCHZ00 COMPACT DISK MCHZ0078101 COMPLEX, (empty), , , , ,SILVERSNOW

4 MMBB00 MANUAL,OPERATION MMBB0343001 PRINTING, (empty), , , , ,WITHOUT

COLOR

3 APKA00 PEN ASSY,STYLUS APKA0001101 BLACK D, 12

3 MBAD00 BAG,VINYL(PE) MBAD0008404 COMPLEX, (empty), , , , ,WITHOUT

COLOR

3 MCJA00 COVER,BATTERY MCJA0082401 MOLD, PC LUPOY SC-1004A, , , , , BLACK F, 7

3 MPHY00 PROTECTOR MPHY0016901 COMPLEX, (empty), , , , ,WITHOUT

COLOR

2 APAY00 PACKAGE APAY0131205GT500 TMU(TR1/3018&4541 LB/WD-9501/Angle/P-LB2ea/Seal/Bag)

WITHOUTCOLOR

3 APLY00 PALLET ASSY APLY0002303 TR1 Angle Palletizing (Angle/WD-9501/400ea)WithoutColor

4 MCJZ00 COVER MCJZ0030520 COVER(for TR 1 Angle_COVER_GSM)WithoutColor

4 MPCY00 PALLET MPCY0009501 PALLET(G7100 for Orange UK_EUR) BLACK

3 BSEA00 SUPPLEMENTARY PART BSEA0003901 PACKING-LIST ENVELOPE

3 MBAD00 BAG,VINYL(PE) MBAD0005204 COMPLEX, (empty), , , , ,WithoutColor

3 MLAC00 LABEL,BARCODE MLAC0004541 PRINTING, (empty), , , , ,WithoutColor

3 MLAC01 LABEL,BARCODE MLAC0003018 PRINTING, (empty), , , , ,WithoutColor

3 MLAJ00 LABEL,MASTER BOX MLAJ0004402 LABEL,MASTER BOX(for CGR TDR 2VER. mbox_label)WithoutColor

3 MLAZ LABEL MLAZ0048203 PRINTING, (empty), , , , ,WITHOUT

COLOR

3 MLAZ00 LABEL MLAZ0050901 PRINTING, (empty), , , , ,WITHOUT

COLOR

3 MPAE00 PACKING,BLISTER MPAE0007803 COMPLEX, (empty), , , , , Red

11.2 Replacement Parts Note: This Chapter is used for reference, Part order is ordered

<Mechanic component>




LevelLocation


2 APEY00 PHONE APEY0750101 BLACK

3 ACGM00 COVER ASSY,REAR ACGM0129501 BLACK C

4 MCCE00 CAP,RECEPTACLE MCCE0049201 MOLD, PC LUPOY SC-1004A, , , , , BLACK 54

4 MCCF00 CAP,MOBILE SWITCH MCCF0060901 COMPLEX, (empty), , , , ,WITHOUT

COLOR

4 MCCG00 CAP,MULTIMEDIA CARD MCCG0019101 MOLD, PC LUPOY SC-1004A, , , , , BLACK 52

4 MCJN00 COVER,REAR MCJN0098701 MOLD, PC LUPOY SC-1004A, , , , , BLACK 53

4 MDAD00 DECO,CAMERA MDAD0045101 ELECTROFORMING, Cu, , , , , BLACK 58

4 MGAD01 GASKET,SHIELD FORM MGAD0197801 COMPLEX, (empty), , , , ,WITHOUT

COLOR 46

4 MHCY00 HANGER MHCY0003101 MOLD, Urethane Rubber S195A, , , , , BLACK 44

4 MLAB03 LABEL,A/S MLAB0003601 COMPLEX, (empty), , , , ,WITHOUT

COLOR 6

4 MLCE00 LENS,FLASH MLCE0012701 MOLD, PMMA HI835M, , , , , BLACK 48

4 MPBF00 PAD,FLEXIBLE PCB MPBF0041401 COMPLEX, (empty), , , , ,WITHOUT

COLOR 41

4 MPBJ00 PAD,MOTOR MPBJ0062001 COMPLEX, (empty), , , , , BLACK 43

4 MPBT00 PAD,CAMERA MPBT0072101 COMPLEX, (empty), , , , , BLACK 49

4 MPBZ00 PAD MPBZ0225101 COMPLEX, (empty), , , , , BLACK 47

4 MPBZ01 PAD MPBZ0228201 COMPLEX, (empty), , , , , BLACK 45

4 MTAA00 TAPE,DECO MTAA0188101 COMPLEX, (empty), , , , ,WITHOUT

COLOR 57

4 MTAB00 TAPE,PROTECTION MTAB0332701 COMPLEX, (empty), , , , ,WITHOUT

COLOR 66

4 MTAK00 TAPE,CAMERA MTAK0024701 COMPLEX, (empty), , , , ,WITHOUT

COLOR 56

4 MWAE00 WINDOW,CAMERA MWAE0045001 CUTTING, PMMA MR 200, , , , , BLACK 13

3 ACGV00 COVER ASSY,BAR ACGV0004301 BLACK A

4 ABGF00 BUTTON ASSY,MAIN ABGF0012901 SILVER 3

4 ACGK00 COVER ASSY,FRONT ACGK0130701 BLACK

5 MBJL00 BUTTON,SIDE MBJL0081801 MOLD, PC LUPOY SC-1004A, , , , , BLACK 15

5 MBJL01 BUTTON,SIDE MBJL0081701 MOLD, PC LUPOY SC-1004A, , , , , BLACK 14

5 MCJK01 COVER,FRONT MCJK0102001 MOLD, PC LUPOY SC-1004A, , , , , BLACK 9

5 MDAG01 DECO,FRONT MDAG0046701 MOLD, PC LUPOY SC-1004A, , , , , SILVER 4





LevelLocation


5 MDAK01 DECO,REAR MDAK0018001 MOLD, PC LUPOY SC-1004A, , , , , BLACK 11

5 MFBC01 FILTER,SPEAKER MFBC0048501 COMPLEX, (empty), , , , , BLACK 20

5 MFBD01 FILTER,MIKE MFBD0038201 COMPLEX, (empty), , , , ,WITHOUT

COLOR 17

5 MPBT01 PAD,CAMERA MPBT0075501 COMPLEX, (empty), , , , ,WITHOUT

COLOR 19

5 MPBU01 PAD,CONNECTOR MPBU0063501 COMPLEX, (empty), , , , ,WITHOUT

COLOR 18


COLOR 10


COLOR


COLOR 68

5 MTAK01 TAPE,CAMERA MTAK0024601 COMPLEX, (empty), , , , ,WITHOUT

COLOR 63

4 ADBY00 DECO ASSY ADBY0015001WITHOUT

COLOR

5 MBFZ00 BRACKET MBFZ0035501 CUTTING, STS, , , , ,WITHOUT

COLOR 22

5 MTAD00 TAPE,WINDOW MTAD0109001 COMPLEX, (empty), , , , ,WITHOUT

COLOR 21

4 AFBZ00 FRAME ASSY AFBZ0012701 LCD BRACKET assyWITHOUT

COLOR

5 MBFF00 BRACKET,LCD MBFF0024501 PRESS, STS, , , , , BLACK 28


COLOR 64


COLOR 62


COLOR 32

4 AHCZ00 HOLDER ASSY AHCZ0002101 BLACK

5 MDAH00 DECO,RECEIVER MDAH0025801 MOLD, PC LUPOY SC-1004A, , , , , BLACK 31

5 MPBN00 PAD,SPEAKER MPBN0068601 COMPLEX, (empty), , , , , BLACK 30

4 GMEY00 SCREW MACHINE,BIND GMEY00192011.4 mm,1.8 mm,SWCH18A ,N ,+ , ,; ,[empty] ,+ , , ,CR-7,WHITE ,[empty] ,[empty]

WHITESILVER 29


COLOR 59

4 MPBG01 PAD,LCD MPBG0089501 COMPLEX, (empty), , , , , BLACK 5




LevelLocation


4 MPBG02 PAD,LCD MPBG0096401 COMPLEX, (empty), , , , ,WITHOUT

COLOR 61


COLOR 67


COLOR 2, 16


COLOR 65

4 MTAC01 TAPE,SHIELD MTAC0091301 COMPLEX, (empty), , , , ,WITHOUT

COLOR 60

4 MWAC01 WINDOW,LCD MWAC0114501 CUTTING, Tempered Glass, , , , , BLACK 1

3 GMEY SCREW MACHINE,BIND GMEY0011201 1.4 mm,3 mm,MSWR3(BK) ,N ,+ ,NYLOKWITHOUT

COLOR E, 24

3 MLAA00 LABEL,APPROVAL MLAA0062304 COMPLEX, (empty), , , , ,WITHOUT

COLOR

5 AFBA00 FRAME ASSY,SHIELD AFBA0012001 BLACK

6 MFEA00 FRAME,SHIELD MFEA0027701 MOLD, PC LUPOY SC-1004A, , , , , BLACK 38

6 MPBU00 PAD,CONNECTOR MPBU0063301 COMPLEX, (empty), , , , , BLACK 37

6 MTAF00 TAPE,MOTOR MTAF0025201 COMPLEX, (empty), , , , , BLACK

5 AFBA01 FRAME ASSY,SHIELD AFBA0013901 GT505 SHIELD CAN COVER ASSYWITHOUT

COLOR

6 MCBA00 CAN,SHIELD MCBA0043301 PRESS, STS, , , , ,WITHOUT

COLOR 34


COLOR

7 MPBU00 PAD,CONNECTOR MPBU0063201 COMPLEX, (empty), , , , ,WITHOUT

COLOR 50

7 MPBU01 PAD,CONNECTOR MPBU0063401 COMPLEX, (empty), , , , , BLACK

7 MTAC00 TAPE,SHIELD MTAC0087801 COMPLEX, (empty), , , , , BLACK

5 MLAZ00 LABEL MLAZ0038301 PID Label 4 ArrayWITHOUT

COLOR






LevelLocation


1 IMT,BAR/FLIP TIMT0005201 BLACK

4 SNGF00 ANTENNA,GSM,FIXED SNGF0046101 3.0 ,-2.0 dBd, ,GPS, FPCB ,; ,SINGLE ,-2.0 ,50 ,3.0

4 SNGF01 ANTENNA,GSM,FIXED SNGF0046203 3.0 ,-2.0 dBd, ,GSM850/GSM900/DCS/PCS/Band1/Band8,INTERNAL ,; ,MULTI ,-2.0 ,50 ,3.0

4 SACY00 PCB ASSY,FLEXIBLE SACY0090901

5 SACE00 PCB ASSY,FLEXIBLE,SMT SACE0083501

6 SACC00PCB ASSY,FLEXIBLE,SMTBOTTOM SACC0058701

7 C900 CAP,CHIP,MAKER ECZH0003103 0.1 uF,10V ,K ,X7R ,HD ,1005 ,R/TP



7 R904 RES,CHIP,MAKER ERHZ0000490 51 ohm,1/16W ,J ,1005 ,R/TP


6 SACD00PCB ASSY,FLEXIBLE,SMTTOP SACD0071701

7 CN400CONNECTOR,BOARD TOBOARD ENBY0018601 10 PIN,.4 mm,STRAIGHT , ,H=0.9, SOCKET

7 CN901CONNECTOR,BOARD TOBOARD ENBY0040201 34 PIN,0.4 mm,ETC , ,H=1.0, Plug

7 U901 CAMERA SVCY0019901 CMOS ,VGA ,Toshiba(1/10"), 4x4x2.23t, Reflow Type

6 SPCY00 PCB,FLEXIBLE SPCY0175001 POLYI ,0.3 mm,MULTI-3 , ,; , , , , , , , , ,




7 CN1CONNECTOR,BOARD TOBOARD ENBY0036001 40 PIN,0.4 mm,ETC , ,H=1.0, Socket

6 SACD00PCB ASSY,FLEXIBLE,SMTTOP SACD0071801

7 C1000 CAP,CERAMIC,CHIP ECCH0000122 47 pF,50V,J,NP0,TC,1005,R/TP

7 C1002 CAP,CHIP,MAKER ECZH0000802 1 pF,50V ,C ,NP0 ,TC ,1005 ,R/TP

11.2 Replacement Parts Note: This Chapter is used for reference, Part order is ordered

<Main component>




LevelLocation


7 CN2CONNECTOR,BOARD TOBOARD ENBY0042001

50 PIN,0.4 mm,STRAIGHT , , ,; , ,0.40MM ,STRAIGHT,MALE ,SMD ,P/TR , ,

7 D1000 DIODE,SWITCHING EDSY0011901EMD2 ,30 V,1 A,R/TP ,VF=1.5V(IF=200mA) ,IR=30uA(VR=10V)

7 LD1000 DIODE,LED,CHIP EDLH0011901 WHITE ,1608 ,R/TP ,PB-FREE(ZENER)




7 MIC100 MICROPHONE SUMY0010609UNIT ,-42 dB,3.76*2.95*1.1 ,mems smd mic ,; , , ,OMNI,[empty] , ,[empty]



7 R4 INDUCTOR,CHIP ELCH0004726 1.5 nH,J ,1005 ,R/TP ,


7 SW1000 SWITCH,TACT ESCY000610115 V,20 mA,HORIZONTAL ,1 G, ,; ,1C1P ,[empty] ,[empty],[empty] , ,[empty]

7 SW1001 CONN,RF SWITCH ENWY0003901 ,SMD , dB,

6 SPCY PCB,FLEXIBLE SPCY0174901 POLYI ,0.3 mm,MULTI-3 , ,; , , , , , , , , ,

4 SUSY00 SPEAKER SUSY0027506 ASSY ,8 ohm,90 dB,1812 mm,10mm ,; , , , , , , ,[empty]

4 SVLM00 LCD MODULE SVLM0035301Main ,3.0 inch ,240*400 ,74.9*44.88*2.0t ,262K ,TFT ,TM,NEC(uPD161710) , ,

4 SWCC00 CABLE,COAXIAL SWCC000650165 mm, LINE, ,; ,[empty] ,[empty] ,[empty] , ,[empty] ,,[empty]

3 SAFY00 PCB ASSY,MAIN SAFY0316001

4 SAFB00 PCB ASSY,MAIN,INSERT SAFB0103801

5 BRAH00 RESIN,PC BRAH0001301 ; , , , ,[empty] Black


6 SACB00PCBASSY,FLEXIBLE,INSERT SACB0056001



8 ANT780 ANTENNA,GSM,FIXED SNGF00465013.0 ,-2.0 dBd, ,BLUETOOTH, SMD, 3.2*1.6*1.2 ,; ,SINGLE,-2.0 ,50 ,3.0





LevelLocation


8 BAT800 BATTERY,CELL,LITHIUM SBCL00017012 V,0.5 mAh,CYLINDER ,Reflow type BB, Max T 1.67, phi4.8, Pb-Free

8 C700 RES,CHIP,MAKER ERHZ0000401 0 ohm,1/16W ,J ,1005 ,R/TP

8 C701 CAP,CHIP,MAKER ECZH0000813 100 pF,50V ,J ,NP0 ,TC ,1005 ,R/TP

8 C702 CAP,CHIP,MAKER ECZH0000802 1 pF,50V ,C ,NP0 ,TC ,1005 ,R/TP

8 C705 CAP,CERAMIC,CHIP ECCH0000105 4 pF,50V,C,NP0,TC,1005,R/TP

8 C706 CAP,CERAMIC,CHIP ECCH0000105 4 pF,50V,C,NP0,TC,1005,R/TP

8 C707 CAP,CERAMIC,CHIP ECCH0004904 1 uF,6.3V ,K ,X5R ,TC ,1005 ,R/TP



8 C712 CAP,CERAMIC,CHIP ECCH000560410000000 pF,6.3V ,M ,X5R ,TC ,1608 ,R/TP , , ,[empty],[empty] ,[empty] ,[empty] ,[empty] ,[empty] ,0.8 mm














8 C731 CAP,CERAMIC,CHIP ECCH0007802 4.7 uF,10V ,M ,X5R ,TC ,1608 ,R/TP








LevelLocation






8 C740 CAP,CERAMIC,CHIP ECCH0000179 22 nF,16V ,K ,X5R ,HD ,1005 ,R/TP


8 C742 CAP,CERAMIC,CHIP ECCH0000110 10 pF,50V,D,NP0,TC,1005,R/TP


8 C750 CAP,CERAMIC,CHIP ECCH0000198 2.2 uF,6.3V ,M ,X5R ,TC ,1005 ,R/TP





8 C755 INDUCTOR,CHIP ELCH0004721 2.2 nH,S ,1005 ,R/TP ,

8 C756 CAP,CHIP,MAKER ECZH0001002 0.5 pF,50V ,B ,NP0 ,TC ,1005 ,R/TP

8 C758 INDUCTOR,CHIP ELCH0004727 100 nH,J ,1005 ,R/TP ,












8 C800 CAP,CERAMIC,CHIP ECCH0005603 2.2 uF,10V ,K ,X5R ,TC ,1608 ,R/TP

8 C801 CAP,CERAMIC,CHIP ECCH0000163 47 nF,10V,K,X5R,HD,1005,R/TP






LevelLocation






8 CN750 CONNECTOR,ETC ENZY0018801 PIN, mm,ETC , ,RCS=1.35



60 PIN,0.4 mm,STRAIGHT , , ,; , ,0.40MM ,STRAIGHT,MALE ,SMD ,[empty] , ,

8 FB710 FILTER,BEAD,CHIP SFBH0008101 600 ohm,1005 ,



8 FL700 FILTER,SEPERATOR,SPDT SFAC0002101800 , MHz,0.3 dB,30 dB,25000 , MHz,0.3 dB,32 dB,SMD,ETC ,2.5x2.5x0.75

8 FL730 FILTER,SAW SFSY0027301 2450 MHz,2.0*1.5*1.0 ,SMD ,Pb-free_B/T_SAW

8 J800 CONN,SOCKET ENSY0018101 6 PIN,ETC , ,2.54 mm,H=1.5

8 L750 INDUCTOR,CHIP ELCH0001408 6.8 nH,J ,1005 ,R/TP ,Pb Free

8 L770 INDUCTOR,CHIP ELCH0005001 2.2 nH,S ,1005 ,R/TP ,

8 L771 INDUCTOR,CHIP ELCH0001041 10 nH,J ,1005 ,R/TP ,PBFREE

8 L772 INDUCTOR,CHIP ELCH0004727 100 nH,J ,1005 ,R/TP ,

8 L800 INDUCTOR,SMD,POWER ELCP00080091 uH,N ,2.5x2.0x1.2 ,R/TP ,MLCI,power inductor ,; ,1uH,30% ,; ,; ,; ,; ,; ,[empty] ,2.5X2MM ,[empty] ,[empty],Inductor,Wire Wound,Chip

8 LD800 DIODE,LED,MODULE EDLM0009401 WHITE ,1 LED,3.5X2.8X0.6T ,R/TP ,

8 M710 MODULE,ETC SMZY0022701 WiFi Module(Marvell8686), 8.2x8.4x1.0 ,; ,WLAN

8 R710 RES,CHIP,MAKER ERHZ0000406 100 Kohm,1/16W ,J ,1005 ,R/TP











LevelLocation



















8 R770 RES,CHIP,MAKER ERHZ0000206 10 ohm,1/16W ,F ,1005 ,R/TP


8 R780 INDUCTOR,CHIP ELCH0004704 4.7 nH,S ,1005 ,R/TP ,


8 R801 RES,CHIP,MAKER ERHZ0000238 200 Kohm,1/16W ,F ,1005 ,R/TP






8 U710 IC EUSY0367001DFN1612-4B ,4 ,R/TP ,300mA 3.3V LDO ,; ,IC,LDO VoltageRegulator






LevelLocation


8 U730 IC EUSY0245902 DRL ,5 PIN,R/TP ,SINGLE,BUFFER,3STATE,1.7X1.7

8 U731 IC EUSY0358701WFBGA ,100 PIN,R/TP ,Bluetooth+FM 5*7.5*0.8 ,;,IC,Bluetooth

8 U750 IC EUSY0149403SOT553-5 ,5 ,R/TP ,1.6X1.6 , SINGLE,BUFFER,Non-inverting,3STATE,High active ,; ,IC,Buffer

8 U751 IC EUSY0380101 WLBGA ,81 ,R/TP ,Pb-free_GPS IC ,; ,IC,GPS


8 U770 MODULE,ETC SMZY0016502 LNA Module(GPS LNA+B/P Filter) ,; ,RF Module

8 U800 IC EUSY0264502DFN ,14 PIN,R/TP ,700mA Boost converter ,; ,IC,DC,DCConverter

8 VA800 VARISTOR SEVY0004001 18 V, ,SMD ,3pF, 1005





8 X750 TCXO EXST000200116.369 MHz,0.5 PPM,10 pF,SMD ,25X20X0.8 ,Sirf GPSchip clock, 16.369MHz, 1.7~3.5V, Pb-Free ,; ,16.369MHz,[empty] ,1.8V , , , , ,SMD ,R/TP

7 SPCY PCB,FLEXIBLE SPCY0171401 POLYI ,0.33 mm,BUILD-UP 4 , ,; , , , , , , , , ,

5 SJMY00 VIBRATOR,MOTOR SJMY0007112 2 V,40 mA,10*3.0 ,Quick response 17mm ,; ,3V , , , , , , ,

5 SVCY00 CAMERA SVCY0017301CMOS ,MEGA ,5M AF [FPCB, Sony 5M 1/3.2"(IMX034),CCP2]

4 SAFF00 PCB ASSY,MAIN,SMT SAFF0229201

5 SAFC00PCB ASSY,MAIN,SMTBOTTOM SAFC0125301












LevelLocation




































LevelLocation








6 C301 CAP,CERAMIC,CHIP ECCH0006201 4.7 uF,6.3V ,K ,X5R ,TC ,1608 ,R/TP


























LevelLocation





6 C331 CAP,TANTAL,CHIP ECTH000520333 uF,10V ,M ,STD ,2012 ,R/TP ,; , ,[empty] ,[empty] ,,[empty] , ,[empty] ,[empty] ,[empty] ,[empty]

6 C332 CAP,CHIP,MAKER ECZH0001215 1 uF,10V ,K ,X5R ,TC ,1005 ,R/TP








6 C340 CAP,CERAMIC,CHIP ECCH0002002 47000 pF,10V ,K ,B ,HD ,1005 ,R/TP

6 C341 CAP,CERAMIC,CHIP ECCH0000149 3.3 nF,50V,K,X7R,HD,1005,R/TP


6 C343 CAP,CHIP,MAKER ECZH0001102 18000 pF,16V ,K ,X7R ,HD ,1005 ,R/TP

6 C344 CAP,CHIP,MAKER ECZH0001102 18000 pF,16V ,K ,X7R ,HD ,1005 ,R/TP

















LevelLocation







6 C510 CAP,CERAMIC,CHIP ECCH00003911000000 pF,50V ,Z ,Y5V ,HD ,2012 ,R/TP , , ,[empty],[empty] ,[empty] ,[empty] ,[empty] ,[empty] ,1.25 mm
















6 C621 CAP,CERAMIC,CHIP ECCH0000133 220 pF,50V ,K ,X7R ,HD ,1005 ,R/TP











LevelLocation



6 CN300 CONNECTOR,ETC ENZY0023701 3 ,2.5 mm,ETC ,- ,-

6 CN500 BRACKET MBFZ0033201 PRESS, STS, , , , , Silver

6 CN501 CONNECTOR,I/O ENRY00088015 , mm,ANGLE , , ,; , ,0.64MM ,ANGLE ,[empty] ,DIP,[empty] ,

6 CN503CONNECTOR,BOARD TOBOARD ENBY0040301 34 PIN,0.4 mm,ETC , ,H=1.0, Socket


60 PIN,0.4 mm,STRAIGHT , , ,; , ,0.40MM ,STRAIGHT,FEMALE ,SMD ,[empty] , ,

6 CN603CONNECTOR,BOARD TOBOARD ENBY0034201 24 PIN,0.4 mm,ETC , ,GB042 H=1.0, Socket


50 PIN,0.4 mm,STRAIGHT , ,H=1.0,SOCKET ,; , ,0.40MM,STRAIGHT ,FEMALE ,SMD ,P/TR , ,

6 D300 DIODE,SWITCHING EDSY0011901EMD2 ,30 V,1 A,R/TP ,VF=1.5V(IF=200mA) ,IR=30uA(VR=10V)

6 D301 DIODE,SWITCHING EDSY0018401TUMD2 ,30 V,1 A,R/TP , ,; ,1A ,30V , ,5A , , ,[empty] ,[empty],2P ,1

6 D302 DIODE,SWITCHING EDSY0014001 SMT ,20 V,200 A,R/TP ,

6 D600 DIODE,TVS EDTY0008606 DFN-2 ,7.82 V,150 mW,R/TP ,PB-FREE


6 FB300 FILTER,BEAD,CHIP SFBH0002302 120 ohm,1608 ,CHIP BEAD, 2000mA

6 FB500 FILTER,BEAD,CHIP SFBH0008102 1800 ohm,1005 ,Bead



6 FB601 FILTER,BEAD,CHIP SFBH0007102 10 ohm,1005 ,Ferrite Bead




6 FL500 FILTER,EMI/POWER SFEY0006501 SMD ,3 TERMINAL EMI FILTER

6 FL600 FILTER,EMI/POWER SFEY0013101 SMD ,1608 ,EMI-ESD Filter, 4ch, 14V, 15pF, 50ohm



6 FL603 FILTER,EMI/POWER SFEY0015601 SMD ,Pb-free_Common mode filter ,; ,Filter,LCR

6 L102 CAP,CHIP,MAKER ECZH0000813 100 pF,50V ,J ,NP0 ,TC ,1005 ,R/TP





LevelLocation


6 L300 INDUCTOR,SMD,POWER ELCP0009401 4.7 uH,M ,2.8*2.6*1.0 ,R/TP ,



6 Q300 TR,FET,P-CHANNEL EQFP0009101SC70-6 ,6.5 W,-20 V,-4.5 A,R/TP ,P channel FET ,; ,P-CHANNEL ,MOSFET ,-20 ,8 ,-4.5 ,0.153 ,6.5 ,SC70 ,R/TP,6P

6 Q501 TR,BJT,NPN EQBN0007601 SOT-23 ,0.15 W,R/TP ,EMT3













6 R215PCB ASSY,MAIN,PADSHORT SAFP0000501



6 R299 PCB ASSY,MAIN,PAD OPEN SAFO0000401 0OHM DNI









LevelLocation






6 R313 RES,CHIP ERHY0000193 27 ohm,1/16W ,F ,1005 ,R/TP


6 R316 RES,CHIP,MAKER ERHZ0003901 0.1 ohm,1/4W ,F ,2012 ,R/TP ,; ,0.1 ,1% ,1/4W ,2012 ,R/TP

6 R317 CAP,CERAMIC,CHIP ECCH0004904 1 uF,6.3V ,K ,X5R ,TC ,1005 ,R/TP






6 R324 RES,CHIP ERHY0017201 0.025 ohm,1/4W ,F ,2012 ,R/TP
















LevelLocation






6 R609 RES,CHIP ERHY0000254 4.7K ohm,1/16W,J,1005,R/TP





6 R626 RES,CHIP ERHY0003301 100 ohm,1/16W ,J ,1005 ,R/TP














6 R657 PCB ASSY,MAIN,PAD OPEN SAFO0000501 0OHM_1005_DNI




LevelLocation



6 SW100 CONN,RF SWITCH ENWY0005301,SMD , dB,H=1.85 ,; ,3.00MM ,STRAIGHT ,RF ADAPTER,SMD ,R/TP ,AU , ,

6 SW101 CONN,RF SWITCH ENWY0003901 ,SMD , dB,

6 U200 IC EUSY0316508FBGA ,107 ,ETC ,FULLY 1.8V 2G(LB/256Mx8)NAND+1G(2CS/16Mx4x16) SDRAM ,; ,IC,MCP

6 U201 IC EUSY0363001BGA ,323 ,R/TP ,HSDPA Digital Baseband ,; ,IC,DigitalBaseband Processor

6 U300 IC EUSY0331701 BGA ,196 PIN,R/TP ,8x8 EMP U360 ABB

6 U301 IC EUSY0360201CSP ,20 ,R/TP ,Class D(mono) + Capless HP + A/S ,;,IC,Audio Sub System

6 U500 IC EUSY0333701 TLLGA ,8 PIN,R/TP ,OVP

6 U501 IC EUSY0371201WLP ,20 ,R/TP ,MUIC for 5Pin Micro USB ,; ,IC,AnalogSwitch

6 U502 IC EUSY0320201 TFBGA ,36 PIN,R/TP ,USB2.0 Transceiver, 3.5X3.5X0.8

6 U600 IC EUSY0319001 WDFN-8L ,8 PIN,R/TP ,300mA/300mA 2.8V/1.8V Dual LDO

6 U604 IC EUSY0336502 , PIN,R/TP , ,; ,IC,Charge Pump

6 VA300 VARISTOR SEVY0003601 5.6 V, ,SMD ,100pF, 1005

6 VA301 VARISTOR SEVY0003601 5.6 V, ,SMD ,100pF, 1005

6 VA500 VARISTOR SEVY0007301 5 V,<0.5pF ,SMD ,

6 VA600 VARISTOR SEVY000880114 V, ,SMD ,2012055, LC 10uA, 0.5pF@1MHz, IL0.05@2GHz, Rt 1ns ,; ,14 , , ,2.0*1.2*0.55 ,[empty] ,SMD,R/TP



6 X300 X-TAL EXXY002430132.768 KHz,20 PPM,12.5 pF,70 Kohm,SMD ,3.2*1.5*0.9 ,-40'C ~ +85'C, C0 1.05pF, C1 fF ,; ,32.768 ,20PPM ,12.5 , ,,SMD ,R/TP

6 ZD500 DIODE,TVS EDTY0007401 SMD ,12 V,350 W,R/TP ,

6 ZD600 DIODE,TVS EDTY0008606 DFN-2 ,7.82 V,150 mW,R/TP ,PB-FREE

6 ZD601 DIODE,TVS EDTY0008606 DFN-2 ,7.82 V,150 mW,R/TP ,PB-FREE

6 ZD602 DIODE,TVS EDTY0009101 SOD-923 ,5 V,150 mW,R/TP ,1.0*0.6*0.4


6 ZD605 DIODE,TVS EDTY0009401VMN2 ,5 V,10 W,R/TP ,1.0*0.6*0.4 ,; , ,7.82V , , ,100mW,[empty] ,[empty] ,2P ,1





LevelLocation



5 SAFD01 PCB ASSY,MAIN,SMT TOP SAFD0123001




6 C103 CAP,CHIP,MAKER ECZH0004402100000 pF,16V ,Z ,X7R ,TC ,1005 ,R/TP , , ,[empty] ,[empty],[empty] ,[empty] ,[empty] ,[empty]














6 C124 INDUCTOR,CHIP ELCH0003816 3.6 nH,S ,1005 ,R/TP ,












LevelLocation





6 C152 INDUCTOR,CHIP ELCH0001049 6.8 nH,J ,1005 ,R/TP ,PBFREE






6 C159 CAP,CERAMIC,CHIP ECCH0000195 3.9 pF,50V ,C ,NP0 ,TC ,1005 ,R/TP








6 C170 CAP,CERAMIC,CHIP ECCH0000175 2.7 pF,50V ,B ,NP0 ,TC ,1005 ,R/TP









6 C179 INDUCTOR,CHIP ELCH0001048 10 nH,J ,1005 ,R/TP ,PBFREE







LevelLocation



















6 C610 CAP,CERAMIC,CHIP ECCH0010501 7.5 pF,50V ,D ,X7R ,TC ,1005 ,R/TP ,; ,C0G TYPE(No X7R),[empty] ,[empty] ,[empty] ,[empty] ,[empty] ,[empty]















LevelLocation









6 D200 DIODE,SWITCHING EDSY0018101VMN2 ,30 V,100 mA,R/TP ,1.0x0.6 ,; , , , , , , ,[empty],[empty] ,2P ,1



6 FB100 FILTER,BEAD,CHIP SFBH0008105 1800 ohm,1005 ,Chip bead ,; ,1800ohm ,; ,[empty] ,R/TP



6 FL100 DUPLEXER,IMT SDMY0001901

1950 MHz,2140 MHz,1.8 dB,2.4 dB,52 dB,43dB,2.5*2.0*0.55 ,SMD ,Band1, 2520size, SAW, Rx unbal ,;,2140 ,2110 to 2170 ,1950 ,1920 to 1980 ,2.4 ,1.8,2.5x2.0x0.55 ,DUAL ,SMD ,R/TP

6 FL102 DUPLEXER,IMT SDMY0002001

897.5 MHz,942.5 MHz,3.1 dB,3.5 dB,52 dB,45dB,2.5*2.0*0.5 ,SMD ,SAW, Band8, Rx unbal ,; ,942.5,927.4 to 957.6 ,897.5 ,882.4 to 912.6 ,3.5 ,3.1 ,2.5x2.0x0.5,DUAL ,SMD ,R/TP

6 FL103 FILTER,SAW,DUAL SFSB0001901

1842.5 MHz,75 MHz,2.6 dB,12 dB,1960 MHz,60 MHz,2.6dB,12 dB,1.8*1.35*0.5 ,SMD,1805M~1880M,1930M~1990M,10p,U,50,50,LH,DCS+PCSRx ,; , ,1.8*1.35*0.5 ,SMD ,R/TP

6 FL104 FILTER,SAW,DUAL SFSB0001801

881.5 MHz,25 MHz,2.6 dB,30 dB,942.5 MHz,35 MHz,2.6dB,25 dB,1.8*1.35*0.5 ,SMD,869M~894M,925M~960M,10p,U,50,50,LH,GSM850+EGSM Rx ,; , ,1.8*1.35*0.5 ,SMD ,R/TP

6 FL105 FILTER,SAW SFSY0037501897.5 MHz,1.4*1.1*0.6 ,SMD ,880.48M~914.52M, IL 4.0,5pin, U-U, 50-50, W-BAND VIII Tx ,; ,897.5 ,1.4*1.1*0.6,SMD ,R/TP

6 FL106 FILTER,SAW SFSY0028101 1950 MHz,1.4*1.1*0.6 ,SMD ,1920M~1980M, IL 2.9, 5pin,U-U, 50-50, W-BAND I Tx , ,1950 ,1.4*1.1*0.6 ,SMD ,R/TP

6 FL501 IC EUSY0269001CSP ,20 PIN,R/TP ,ESD protection & Filtering for analogsignals, Pb-free

6 L100 CAP,CERAMIC,CHIP ECCH0000113 18 pF,50V,J,NP0,TC,1005,R/TP

6 L103 INDUCTOR,CHIP ELCH0004705 8.2 nH,J ,1005 ,R/TP ,





LevelLocation


6 L104 INDUCTOR,CHIP ELCH0003826 3.3 nH,S ,1005 ,R/TP ,chip


6 L108 INDUCTOR,SMD,POWER ELCP0008003 3.3 uH,M ,2.5*2.0*1.0 ,R/TP ,Chip power

6 L110 INDUCTOR,CHIP ELCH0004705 8.2 nH,J ,1005 ,R/TP ,





6 L119 CAP,CERAMIC,CHIP ECCH0000183 1.8 pF,50V ,C ,NP0 ,TC ,1005 ,R/TP


6 PT100 THERMISTOR SETY0007101 NTC ,4700 ohm,SMD ,1005 J B:3500K

6 Q200 TR,BJT,NPN EQBN0012401 ESM ,100 mW,R/TP ,NPN TRANSISTOR


















LevelLocation





6 R125 INDUCTOR,CHIP ELCH0004733 4.3 nH,S ,1005 ,R/TP ,Coil


6 R128 INDUCTOR,CHIP ELCH0001057 3.9 nH,S ,1005 ,R/TP ,PBFREE











6 R142 CAP,CERAMIC,CHIP ECCH0000113 18 pF,50V,J,NP0,TC,1005,R/TP













LevelLocation



















6 R416 RES,CHIP,MAKER ERHZ0000456 2.2 ohm,1/16W ,J ,1005 ,R/TP











LevelLocation























6 RA400 RES,ARRAY,R ERNR0000404 100 Kohm,100 Kohm,8 PIN,J ,1/16W ,SMD ,R/TP

6 S400 CONN,SOCKET ENSY0020901 8 PIN,STRAIGHT , , mm,

6 SC1 FRAME,SHIELD MFEA0027901 PRESS, STS, , , , , BLACK

6 SPFY PCB,MAIN SPFY0197201 FR-4 ,0.8 mm,STAGGERED-10 , ,; , , , , , , , , ,





LevelLocation


6 U100 IC EUSY0299401 ,6 PIN,R/TP ,0.3_2v

6 U101 RF MODULE,HANDSET SMRH0004901 MHz, MHz, ,Tx Module(ASM + PAM) - WCDMA TriMode

6 U102 PAM SMPY001860128 dBm, %, A, dBc, dB,3x3x1 ,SMD ,EMP U330 Band 1PAM ,; ,3.6 , , , , , , ,R/TP ,R/TP ,8

6 U103 COUPLER,RFDIRECTIONAL

SCDY000430120.5 dB,0.22 dB,34 dB,1.0*0.5*0.4 ,SMD,Pb_free_KPCS+USPCS+WCDMA ,; ,[empty] ,1865MHz,230MHz ,SMD ,R/TP

6 U106 COUPLER,RFDIRECTIONAL

SCDY000440119.4 dB,0.25 dB,32 dB,1.0*0.5*0.4 ,SMD ,Pb-free_DCN+JCDMA ,; ,[empty] ,874.5MHz ,101MHz ,SMD,R/TP

6 U107 PAM SMPY001850128 dBm, %, A, dBc, dB,3x3 ,SMD ,EMP U300 ,; , , , , , , ,,R/TP ,R/TP ,

6 U108 IC EUSY0245902 DRL ,5 PIN,R/TP ,SINGLE,BUFFER,3STATE,1.7X1.7

6 U109 IC EUSY0222103 MicroSMD ,8 PIN,R/TP ,DCDC for PAM 650mA, ~3.4V


6 U111 IC EUSY0357401HVQFN ,56 PIN,R/TP ,GSM,EDGE,WCDMA Transceiver,7X7 mm. ,; ,IC,CMOS

6 U400 IC EUSY0349001 BGA ,8 PIN,R/TP ,Class AB SPK AMP ,; ,IC,Audio Amplifier

6 U401 IC EUSY03452013*3 QFN ,10 PIN,R/TP ,3xis Accelerometer ,; ,IC,A/DConverter

6 U402 IC EUSY0353801PLP1010-4 ,4 PIN,R/TP ,1x1 LDO, 3.3V , 150mA ,; ,IC,LDOVoltage Regulator

6 U403 IC EUSY0334202BGA ,20 PIN,R/TP ,Levelshifter,sdcard,6ch ,; ,IC,BusController

6 U404 IC EUSY0334201BGA ,12 PIN,R/TP ,4-BIT BIDIRECTIONAL VOLTAGE-LEVEL TRANSLATOR (ZXU type)

6 U405 IC EUSY0337101CSP ,12 PIN,R/TP ,Touchscreen Controller IC , ,IC,A/DConverter

6 U406 IC EUSY0355701PLP1010-4 ,4 PIN,R/TP ,150mA 2.8V Single LDO ,;,IC,Voltage Regulator


6 U602 IC EUSY0321201 BGA ,64 PIN,R/TP ,6*6 ISP


6 VA400 VARISTOR SEVY0003801 18 V, ,SMD ,





LevelLocation







6 VA602 DIODE,TVS EDTY0009401VMN2 ,5 V,10 W,R/TP ,1.0*0.6*0.4 ,; , ,7.82V , , ,100mW,[empty] ,[empty] ,2P ,1

6 X100 X-TAL EXXY002610126 MHz,10 PPM,14 pF,25 ohm,SMD ,32*25*0.6 ,EMPReference X-Tal, CF360, Pb-Free ,; ,26MHz ,10PPM ,14 , ,,SMD ,R/TP











LevelLocation


3 SBPL00 BATTERY PACK,LI-ION SBPL00987013.7 V,1000 mAh,1 CELL,PRISMATIC,553446,INNERPACK,WW ,; ,3.7 ,1000 ,200 ,PRISMATIC,5.5X34X46 ,6.1X47X36.5 ,BLACK ,INNERPACK ,

BLACK

BATTERY PACK,LI-ION SBPL00980013.7 V,1000 mAh,1 CELL,PRISMATIC ,553446, INNERPACK,; ,3.7 ,1000 ,200 ,PRISMATIC ,5.5X34X46 ,6.1X37X47,BLACK ,INNERPACK ,

3 SGDY00 DATA CABLE SGDY0014302; ,[empty] ,[empty] ,1.2M , ,BLACK ,1.2m, 4, Shield caseMicroUSB, ID resistor open ,N

3 SGEY00 EAR PHONE/EAR MIKE SET SGEY0003741

; ,RMS 20mW(0.56V,RMS) ,16Ohm+-2.4Ohm 1KHZ,116dB+-3dB 1KHZ,3mW ,116dB 1KHZ ,96dB 100HZ,[empty] ,BLACK ,5P MICRO USB CONNECTOR , MICROUSB 5P ,Earphone,Stereo

3 SSAD00 ADAPTOR,AC-DC SSAD0032901100-240V ,5060 Hz,5.1 V,0.7 A,CE ,AC-DC ADAPTOR ,;,90Vac~264Vac ,4.75Vdc~5.25Vdc ,700mA ,5060 , ,WALL3P ,USB ,

ADAPTOR,AC-DC SSAD0032902100-240V ,5060 Hz,5.1 V,0.7 A,CE ,AC-DC ADAPTOR ,;,90Vac~264Vac ,4.75Vdc~5.25Vdc ,700mA ,5060 , ,WALL2P ,USB ,

11.3 Accessory Note: This Chapter is used for reference, Part order is ordered

LG GT500 GT505 Service Manual

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Transcript of LG GT500 GT505 Service Manual