Lei Yang, Hui Liu, C.-J Richard Shi Transactions on Circuits and Systems 2006
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Transcript of Lei Yang, Hui Liu, C.-J Richard Shi Transactions on Circuits and Systems 2006
Code Construction and FPGA Implementation of a Low-Error-Floor Multi-Rate Low-Density Parity-Check Code Decoder
Lei Yang, Hui Liu, C.-J Richard Shi
Transactions on Circuits and Systems 2006
Outline
Code Design and Rates Log-BP and MSC FUs Result Conclusion Comment
Code Design and Rates
Regular rate 5/8 code N=149 x 82 = 9536 M=3 x 8 x 149 = 3576
Regular rate 7/8 code N=17 x 242 = 9792 M=3 x 24 x 17 = 1224
Irregular rate 1/2 code N=251 x 36 = 9036 M=18 x 251 = 4518
Code
Regular code
H3 consists of randomly located permutation matrix.
TTTT HHH 321
Mb x L=18 x 251
Nb x L = 36 x 251Irregular Code
Log-BP
Check Node Computation
Variable Node Computation
Min-Sum with Correction
Check Node Computation
Variable Node Computation
Finite Precision (6:3)
CNU (4CU)
VNU
Architecture
Mb x L
Nb x L = 36 x 251
Result
40Mbps @ 100MHz (24 iterations)
15Mbps @ 100MHz (60 iterations)
Conclusion
Offer a configurable 9-kbit multi-rate LDPC decoder. (00, 01 and 10 can work at rate 1/2, 5/8 and 7/8 respectively)
Archive BER 10-5 @ 1.4dB when irregular 1/2 is operating.
Comment
Min-Sum with Correction vs. Scaling Min-Sum
Irregular Code Decoding Rate compatible Decoder
ComparisonOurs (96x) Presented (36x)
N 12288 9036
Rate 1/2 1/2 ,(5/8 and 7/8)
Algorithm Scaling min-sum Min-sum with correction
Memory 12288*(4*6+1)
307,200bit
117*512*7 + 4.5K*32
1,859,328bit
Fmax59.48MHz 100MHz
Throughput 203Mbps 15Mbps (64Mbps)
Gain 10-5 at 1.6 10-5 at 1.4
(block error rate 10-7 at 1.8)