Lecturer PSOE Dan Garcia cs.berkeley/~ddgarcia
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![Page 1: Lecturer PSOE Dan Garcia cs.berkeley/~ddgarcia](https://reader038.fdocuments.in/reader038/viewer/2022110402/56812a54550346895d8da68b/html5/thumbnails/1.jpg)
CS 61C L21 Caches II (1) Garcia, Spring 2004 © UCB
Lecturer PSOE Dan Garcia
www.cs.berkeley.edu/~ddgarcia
inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures
Lecture 21 – Caches II
2004-03-10
US buys world’s biggestRAM disk. 2.5TB! 10,000 x
the size of the RAM on your PC. They’ll use it for warez^h^h^h^h^h
database queries. It cost 4.7 M$! Tera-RamSan. 10,000 Watts!
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CS 61C L21 Caches II (2) Garcia, Spring 2004 © UCB
Review: Direct-Mapped Cache
• Cache Location 0 can be occupied by data from:• Memory location 0, 4, 8, ...
• 4 blocks => any memory location that is multiple of 4
MemoryMemory Address
0123456789ABCDEF
4 Byte Direct Mapped Cache
Cache Index
0123
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CS 61C L21 Caches II (3) Garcia, Spring 2004 © UCB
Review: Issues with Direct-Mapped•Since multiple memory addresses map to same cache index, how do we tell which one is in there?
•What if we have a block size > 1 byte?
•Result: divide memory address into three fields
ttttttttttttttttt iiiiiiiiii oooo
tag index byteto check to offsetif have select
within correct block blockblock
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CS 61C L21 Caches II (4) Garcia, Spring 2004 © UCB
Direct-Mapped Cache Terminology•All fields are read as unsigned integers.
• Index: specifies the cache index (which “row” of the cache we should look in)
•Offset: once we’ve found correct block, specifies which byte within the block we want
•Tag: the remaining bits after offset and index are determined; these are used to distinguish between all the memory addresses that map to the same location
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CS 61C L21 Caches II (5) Garcia, Spring 2004 © UCB
Caching Terminology• When we try to read memory,
3 things can happen:
1. cache hit: cache block is valid and contains proper address, so read desired word
2. cache miss: nothing in cache in appropriate block, so fetch from memory
3. cache miss, block replacement: wrong data is in cache at appropriate block, so discard it and fetch desired data from memory (cache always copy)
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CS 61C L21 Caches II (6) Garcia, Spring 2004 © UCB
Direct-Mapped Cache Example (1/3)•Suppose we have a 16KB of data in a direct-mapped cache with 4 word blocks
•Determine the size of the tag, index and offset fields if we’re using a 32-bit architecture
•Offset• need to specify correct byte within a block
• block contains 4 words = 16 bytes
= 24 bytes
• need 4 bits to specify correct byte
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CS 61C L21 Caches II (7) Garcia, Spring 2004 © UCB
Direct-Mapped Cache Example (2/3)• Index: (~index into an “array of
blocks”)• need to specify correct row in cache
• cache contains 16 KB = 214 bytes
• block contains 24 bytes (4 words)
• # blocks/cache = bytes/cache
bytes/block
= 214 bytes/cache 24 bytes/block
= 210 blocks/cache
• need 10 bits to specify this many rows
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CS 61C L21 Caches II (8) Garcia, Spring 2004 © UCB
Direct-Mapped Cache Example (3/3)•Tag: use remaining bits as tag• tag length = addr length – offset - index
= 32 - 4 - 10 bits = 18 bits
• so tag is leftmost 18 bits of memory address
•Why not full 32 bit address as tag?• All bytes within block need same address (4b)
• Index must be same for every address within a block, so its redundant in tag check, thus can leave off to save memory (10 bits in this example)
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CS 61C L21 Caches II (9) Garcia, Spring 2004 © UCB
Accessing data in a direct mapped cache• Ex.: 16KB of data, direct-mapped, 4 word blocks
• Read 4 addresses1. 0x000000142. 0x0000001C3. 0x000000344. 0x00008014
• Memory values on right:
• only cache/ memory level of hierarchy
Address (hex)Value of WordMemory
0000001000000014000000180000001C
abcd
... ...
0000003000000034000000380000003C
efgh
0000801000008014000080180000801C
ijkl
... ...
... ...
... ...
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CS 61C L21 Caches II (10) Garcia, Spring 2004 © UCB
Accessing data in a direct mapped cache•4 Addresses:•0x00000014, 0x0000001C, 0x00000034, 0x00008014
•4 Addresses divided (for convenience) into Tag, Index, Byte Offset fields
000000000000000000 0000000001 0100
000000000000000000 0000000001 1100
000000000000000000 0000000011 0100
000000000000000010 0000000001 0100
Tag Index Offset
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CS 61C L21 Caches II (11) Garcia, Spring 2004 © UCB
16 KB Direct Mapped Cache, 16B blocks• Valid bit: determines whether anything is stored in that row (when computer initially turned on, all entries are invalid)
...
ValidTag 0x0-3 0x4-7 0x8-b 0xc-f
01234567
10221023
...
Index00000000
00
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CS 61C L21 Caches II (12) Garcia, Spring 2004 © UCB
1. Read 0x00000014
...
ValidTag 0x0-3 0x4-7 0x8-b 0xc-f
01234567
10221023
...
• 000000000000000000 0000000001 0100
Index
Tag field Index field Offset
00000000
00
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CS 61C L21 Caches II (13) Garcia, Spring 2004 © UCB
So we read block 1 (0000000001)
...
ValidTag 0x0-3 0x4-7 0x8-b 0xc-f
01234567
10221023
...
• 000000000000000000 0000000001 0100
Index
Tag field Index field Offset
00000000
00
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CS 61C L21 Caches II (14) Garcia, Spring 2004 © UCB
No valid data
...
ValidTag 0x0-3 0x4-7 0x8-b 0xc-f
01234567
10221023
...
• 000000000000000000 0000000001 0100
Index
Tag field Index field Offset
00000000
00
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CS 61C L21 Caches II (15) Garcia, Spring 2004 © UCB
So load that data into cache, setting tag, valid
...
ValidTag 0x0-3 0x4-7 0x8-b 0xc-f
01234567
10221023
...
1 0 a b c d
• 000000000000000000 0000000001 0100
Index
Tag field Index field Offset
0
000000
00
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CS 61C L21 Caches II (16) Garcia, Spring 2004 © UCB
Read from cache at offset, return word b• 000000000000000000 0000000001 0100
...
ValidTag 0x0-3 0x4-7 0x8-b 0xc-f
01234567
10221023
...
1 0 a b c d
Index
Tag field Index field Offset
0
000000
00
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CS 61C L21 Caches II (17) Garcia, Spring 2004 © UCB
2. Read 0x0000001C = 0…00 0..001 1100
...
ValidTag 0x0-3 0x4-7 0x8-b 0xc-f
01234567
10221023
...
1 0 a b c d
• 000000000000000000 0000000001 1100
Index
Tag field Index field Offset
0
000000
00
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CS 61C L21 Caches II (18) Garcia, Spring 2004 © UCB
Index is Valid
...
ValidTag 0x0-3 0x4-7 0x8-b 0xc-f
01234567
10221023
...
1 0 a b c d
• 000000000000000000 0000000001 1100
Index
Tag field Index field Offset
0
000000
00
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CS 61C L21 Caches II (19) Garcia, Spring 2004 © UCB
Index valid, Tag Matches
...
ValidTag 0x0-3 0x4-7 0x8-b 0xc-f
01234567
10221023
...
1 0 a b c d
• 000000000000000000 0000000001 1100
Index
Tag field Index field Offset
0
000000
00
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CS 61C L21 Caches II (20) Garcia, Spring 2004 © UCB
Index Valid, Tag Matches, return d
...
ValidTag 0x0-3 0x4-7 0x8-b 0xc-f
01234567
10221023
...
1 0 a b c d
• 000000000000000000 0000000001 1100
Index
Tag field Index field Offset
0
000000
00
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CS 61C L21 Caches II (21) Garcia, Spring 2004 © UCB
3. Read 0x00000034 = 0…00 0..011 0100
...
ValidTag 0x0-3 0x4-7 0x8-b 0xc-f
01234567
10221023
...
1 0 a b c d
• 000000000000000000 0000000011 0100
Index
Tag field Index field Offset
0
000000
00
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CS 61C L21 Caches II (22) Garcia, Spring 2004 © UCB
So read block 3
...
ValidTag 0x0-3 0x4-7 0x8-b 0xc-f
01234567
10221023
...
1 0 a b c d
• 000000000000000000 0000000011 0100
Index
Tag field Index field Offset
0
000000
00
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CS 61C L21 Caches II (23) Garcia, Spring 2004 © UCB
No valid data
...
ValidTag 0x0-3 0x4-7 0x8-b 0xc-f
01234567
10221023
...
1 0 a b c d
• 000000000000000000 0000000011 0100
Index
Tag field Index field Offset
0
000000
00
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CS 61C L21 Caches II (24) Garcia, Spring 2004 © UCB
Load that cache block, return word f
...
ValidTag 0x0-3 0x4-7 0x8-b 0xc-f
01234567
10221023
...
1 0 a b c d
• 000000000000000000 0000000011 0100
1 0 e f g h
Index
Tag field Index field Offset
0
0
0000
00
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CS 61C L21 Caches II (25) Garcia, Spring 2004 © UCB
4. Read 0x00008014 = 0…10 0..001 0100
...
ValidTag 0x0-3 0x4-7 0x8-b 0xc-f
01234567
10221023
...
1 0 a b c d
• 000000000000000010 0000000001 0100
1 0 e f g h
Index
Tag field Index field Offset
0
0
0000
00
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CS 61C L21 Caches II (26) Garcia, Spring 2004 © UCB
So read Cache Block 1, Data is Valid
...
ValidTag 0x0-3 0x4-7 0x8-b 0xc-f
01234567
10221023
...
1 0 a b c d
• 000000000000000010 0000000001 0100
1 0 e f g h
Index
Tag field Index field Offset
0
0
0000
00
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CS 61C L21 Caches II (27) Garcia, Spring 2004 © UCB
Cache Block 1 Tag does not match (0 != 2)
...
ValidTag 0x0-3 0x4-7 0x8-b 0xc-f
01234567
10221023
...
1 0 a b c d
• 000000000000000010 0000000001 0100
1 0 e f g h
Index
Tag field Index field Offset
0
0
0000
00
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CS 61C L21 Caches II (28) Garcia, Spring 2004 © UCB
Miss, so replace block 1 with new data & tag
...
ValidTag 0x0-3 0x4-7 0x8-b 0xc-f
01234567
10221023
...
1 2 i j k l
• 000000000000000010 0000000001 0100
1 0 e f g h
Index
Tag field Index field Offset
0
0
0000
00
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CS 61C L21 Caches II (29) Garcia, Spring 2004 © UCB
And return word j
...
ValidTag 0x0-3 0x4-7 0x8-b 0xc-f
01234567
10221023
...
1 2 i j k l
• 000000000000000010 0000000001 0100
1 0 e f g h
Index
Tag field Index field Offset
0
0
0000
00
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CS 61C L21 Caches II (30) Garcia, Spring 2004 © UCB
Do an example yourself. What happens?• Chose from: Cache: Hit, Miss, Miss w. replace
Values returned: a ,b, c, d, e, ..., k, l• Read address 0x00000030 ? 000000000000000000 0000000011 0000• Read address 0x0000001c ? 000000000000000000 0000000001 1100
...
ValidTag 0x0-3 0x4-7 0x8-b 0xc-f01234567...
1 2 i j k l
1 0 e f g h
Index0
0
0000
Cache
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CS 61C L21 Caches II (31) Garcia, Spring 2004 © UCB
Administrivia
•Midterm
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CS 61C L21 Caches II (32) Garcia, Spring 2004 © UCB
Upcoming Calendar
Week # Mon Wed Thurs Lab Fri
#8
This week
DanCaches I
Midterm
DanCaches IIOH today outside!
(follow after class)
ExamsBack &Discuss
DanCaches III
/ VM I
#9
Next week
DanVM II
DanVM III Caches
No Dan OH
ChemaIntro to Sync
Digital#9+
Spring Break!
It’s Party Time Woo Hoo!
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CS 61C L21 Caches II (33) Garcia, Spring 2004 © UCB
Answers•0x00000030 a hit
Index = 3, Tag matches, Offset = 0, value = e
•0x0000001c a missIndex = 1, Tag mismatch, so replace from memory, Offset = 0xc, value = d
•Since reads, values must = memory values whether or not cached:
• 0x00000030 = e
• 0x0000001c = d
Address Value of WordMemory
0000001000000014000000180000001c
abcd
... ...
0000003000000034000000380000003c
efgh
0000801000008014000080180000801c
ijkl
... ...
... ...
... ...
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CS 61C L21 Caches II (34) Garcia, Spring 2004 © UCB
Peer Instructions
1. All caches take advantage of spatial locality.
2. All caches take advantage of temporal locality.
3. On a read, the return value will depend on what is in the cache.
ABC1: FFF2: FFT 3: FTF4: FTT5: TFF6: TFT7: TTF8: TTT
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CS 61C L21 Caches II (35) Garcia, Spring 2004 © UCB
Peer Instruction Answers
1. All caches take advantage of spatial locality.
2. All caches take advantage of temporal locality.
3. On a read, the return value will depend on what is in the cache.
T R U EF A L S E
1. Block size = 1, no spatial!2. That’s the idea of caches;
We’ll need it again soon.
3. It better not! If it’s there,use it. Oth, get from mem
F A L S E ABC1: FFF2: FFT 3: FTF4: FTT5: TFF6: TFT7: TTF8: TTT
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CS 61C L21 Caches II (36) Garcia, Spring 2004 © UCB
And in Conclusion…•Mechanism for transparent movement of data among levels of a storage hierarchy
• set of address/value bindings• address index to set of candidates• compare desired address with tag• service hit or miss
- load new block and binding on miss
ValidTag 0x0-3 0x4-7 0x8-b 0xc-f
0123...
1 0 a b c d
000000000000000000 0000000001 1100address: tag index offset