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Lecture 9

ARM Instruction Set (& ARM Based Microcontrollers)

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In this lecture

ARM Instruction Set ARM Based Microcontrollers

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Load-Store Instructions

Transfer data between memory and processor registers

Three types : Single-register transfer Multiple-register transfer Swap

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Single Register Data Transfer Used for moving a single data item Several types:

LDR STR Word

LDRB STRB Byte

LDRH STRH Halfword

LDRSB Signed byte load

LDRSH Signed halfword load

Syntax: LDR{<cond>}{<size>} Rd, <address> STR{<cond>}{<size>} Rd, <address>

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Single Register Data Transfer…cntd

Addressing Modes: Preindexed with write back

E.g. LDR r0, [r1,#4]! (r0 ←[r1+4]) then r1 = r1+4)

Preindexed addressingE.g. LDR r0, [r1,#4] (r0 ←[r1+4], r1 does not change)

Postindexed addressingE.g. LDR r0, [r1], #4 (r0←[r1] then r1 = r1 +4)

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Multiple Register Data Transfer

Syntax:<LDM|STM>{<cond>}<addressing_mode> Rb{!}, <register list> Rb = Base register

Four addressing modes: LDMIA / STMIA (Load multiple/ store multiple, increment after)

E.g. LDMIA r0, {r1-r3} (r1←[r0], r2←[r0+4], r3←[r0+8])

LDMIB / STMIB increment before E.g. LDMIB r0, {r1-r3} (r1←[r0+4], r2←[r0+8], r3←[r0+12])

LDMDA / STMDA decrement after E.g. LDMDA r0, {r1-r3} (r3←[r0], r2←[r0-4], r1←[r0-8])

LDMDB / STMDB decrement before E.g. LDMDB r0, {r1-r3} (r3←[r0-4], r2←[r0-8], r1←[r0-12])

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Software Interrupt Instruction(SWI)

Causes a software interrupt exception The SWI handler can examine the SWI number to decide

what operation has been requested By using the SWI mechanism, an operating system can

implement a set of privileged operations which applications running in user mode can request

Syntax: SWI{<cond>} <SWI number>

2831 2427 0

Cond 1 1 1 1 SWI number (ignored by processor)

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Condition Field

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Branch : B{<cond>} label Label is a 24 bit offset The processor core shifts the offset field left by 2 positions, sign-

extends it and adds it to the PC (PC←PC+(offset<<2)) This gives ± 32 Mbyte range

Branch with Link : BL{<cond>} subroutine_label Similar to Branch, but overrides LR (link register) with a return address It can be used to call subroutines. To return from the subroutine restore

the value of PC from LR E.g. BL subroutine ; branch to subroutine, LR←PC+4

…

subroutine:

<subroutine code>

MOV PC, LR ; restore PC (return)

Branch instructions

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Thumb

Thumb is a 16-bit instruction set Optimized for code density from C code (~65% of ARM code size) Improved performance from narrow memory Subset of the functionality of the ARM instruction set

015

31 0ADDS r2,r2,#1

ADD r2,#1

32-bit ARM Instruction

16-bit Thumb Instruction

For most instructions generated by compiler: Conditional execution is not used Source and destination registers identical Constants are of limited size Inline barrel shifter not used

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ARM Based Microcontrollers

(LPC2148)

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LPC2148

Based on ARM7TDMI-S 512KB on-chip flash memory (non-

volatile memory) 32KB on-chip SRAM Several peripherals Up to 60MHz CPU clock Operating voltage range: 3.0V-3.6V 64 pins

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LPC2148 – Block Diagram

ARM7TDMI-S

512KB FLASH

32KB SRAM

Interrupt Controller

ARM7 Local Bus

AHB

Peripherals GPIO A/D Converters D/A Converters PWM Capture/Compare Real Time Clock UART SPI I2C USB

The microcontroller can be seen as an ARM based system

APB

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Flash memory Non-volatile Used to store code and data Can be programed using JTAG interface using In System Programming

(ISP), or by means of In Application Programming (IAP) Minimum of 100,000 erase/write cycles

Static RAM Volatile Can be used to store code and data

Peripherals (Input/Outpt) Each peripheral has registers used to communicate with the ARM core

LPC2148 – Block Diagram…cntd

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The microcontroller has a 4GB address space (PC is 32 bits) Peripheral registers are also addressed as memory locations

Memory Mapping

AHB Peripherals

APB Peripherals

32KB SRAM

512kB Flash

0x00000000

0x0007FFFF

0x40000000

0x40007FFF

0xE000000

0xF000000

0xFFFFFFFF

0.0GB

1GB

3.5GB

4GB

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Peripherals are controlled by writing into or reading from the appropriate registers

Which registers to write to or to read from are given on the device (LPC2148) datasheet /user manual

E.g. LPC2148 has two General Purpose I/O (GPIO) ports (PORT0 and PORT1)

To configure a pin on PORT0 as an input or as an output, write appropriate values to register IO0DIR (address of 0xE0028008)

To set (make logical 1) a pin on PORT0, set the appropriate bit on register IO0SET (address 0xE0028004)

To read the value of a pin on PORT0, read appropriate bit on register IO0PIN (address of 0xE0028000)

Peripherals

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Hardware and Software Tools for Labs

LPC2148 Education Board IAR for ARM Proteus

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More Readings ARM System Developer’s Guide (chapters 3) LPC214x User Manual