Lecture7 MOS Tp AndP

8/3/2019 Lecture7 MOS Tp AndP

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Propagation Delay

Power Dissipation

EE141- Sp rin g 2003Lecture 7

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CMOS Inv erter Prop agation Delay

VDD

Vout

Vin = V DD

Ron

CL

tpHL = f(Ron.CL)

= 0.69 RonCL

t

Vout

VDD

RonCL

1

0.5

ln(0.5)

0.36


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0 0.5 1 1.5 2 2.5

x 10-10

-0.5

0

0.5

1

1.5

2

2.5

3

t (sec)

Vout(

V)

Transient Response

tp = 0.69 CL (Req n+Req p)/2

?

tpLHtpH L

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Design for Performance

Keep capacitances small

Increase transistor sizes

watch out for self-loading!

Increase VDD (?)


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Delay as a function of VDD

0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.41

1.5

2

2.5

3

3.5

4

4.5

5

5.5

VDD

(V)

t p(normalized)

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2 4 6 8 10 12 142

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

3.8x 1 0

-11

S

t p(sec)

Device Sizing

(for fixed load)

Self-loading effect:

Intrinsic capacitances

dominate


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1 1.5 2 2.5 3 3.5 4 4.5 53

3.5

4

4.5

5x 1 0

-11

t p(sec)

N MOS/ PMOS ratio

tpLH tpHL

tp = Wp/ Wn

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Impact of Rise Time on Delay

tpHL(nsec)

0.35

0.3

0.25

0.2

0.15

trise (nsec)10.80.60.40.20

tp = tstep(i) + tstep(i-1)


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The Sub-Micron MOS Transistor

Threshold Variations

Subthreshold Conduction

Parasitic Resistances

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Threshold Variations

VT

L

Long-channel threshold Low VDS threshold

Threshold as a function of

the length (for lowVDS)

Drain-induced barrier lowering (DIBL)

(for low L)

VDS

VT


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Sub-Threshold Conduction

0 0.5 1 1.5 2 2.510

-12

10-10

10-8

10-6

10-4

10-2

VGS(V)

ID(A)

VT

Linear

Exponential

Quadratic

Typical values for S:

60 .. 100 mV/ decade

The Slope Factor

ox

DnkT

qV

DC

CneII

GS

+= 1,~ 0

S is VGS for ID2/ ID1 =10

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Sub-Threshold ID vs VGS

VDS from 0 to 0.5V

=

kT

qV

nkT

qV

D

DSGS

eeII 10


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Sub-Threshold ID

vs VDS

( )DSkTqV

nkT

qV

D VeeIIDSGS

+

=

110

VGS from 0 to 0.3V

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Power Dissipation


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Where Does Power Go in CMOS?

Dynamic Power Consumption

Short Circuit Currents

Leakage

Charging and Discharging Capacitors

Short Circuit Path between Supply Rails during Switching

Leaking diodes and transistors

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Dynam ic Power Dissip ation

Energy/transition = CL * Vdd2

Power = Energy/transition *f = CL * Vdd2

* f

Need to reduce CL, Vdd, andf to reduce power.

Vin Vout

CL

Vdd

Not a function of transistor sizes!


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Modification for Circuits with Reduced Swing

CL

Vdd

Vdd

Vdd-Vt

E0 1

CL

Vdd

Vdd

Vt( )=

Can exploit reduced swin g to low er pow er

(e.g., reduced bit-line swing in memory)

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Adiabatic Charging

22

2


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Adiabatic Charging

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Node Transition Activity and PowerNode Transition Activity and PowerConsider switching a CMOS gate for N clock cycles

EN

CL

Vd d

2 n N( )=

n(N): the number of 0->1 transition in N clock cycles

EN : the en ergy consumed for Nclock cycles

Pa vg

N lim

EN

N-------- f

cl k=

n N( )N

------------N

lim

CL

Vdd

2

fclk

=

0 1n N

( )N------------N lim=

Pav g

= 0 1

CL

Vdd

2 fclk


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Short Circuit Currents

Vin Vout

CL

Vdd

IVDD(mA)

0.15

0.10

0.05

Vin (V)5.04.03.02.01.00.0

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How to keep Short-Circuit Currents Down?

Short circuit current goes to zero if t fall >> trise,

but cant do this for cascade logic, so ...


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Minimizing Short-Circuit Power

0 1 2 3 4 50

1

2

3

4

5

6

7

8

tsin

/tsout

Pnorm

Vdd =1.5

Vdd =2.5

Vdd =3.3

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Leakage

Vout

Vdd

Sub-ThresholdCurrent

Drain JunctionLeakage

Sub-threshold current one of most compelling issues

in low-energy circuit design!


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Reverse-Biased Diode Leakage

Np+ p

+

Reverse Leakage Current

+

-Vdd

GATE

IDL = JS A

JS = 10-100 pA/m2 at 25 deg C for 0.25 m CMOSJS doubles for every 9 deg C!

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Subthreshold Leakage Component


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Static Power Consumption

Vin =5V

Vo ut

CL

Vd d

Istat

Pstat = P(In=1).Vdd . Istat

Wasted energy

Should be avoided in most cases,

but could help reducing energy in others (e.g. sense amps)

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Principles for Power Reduction

Prime choice: Reduce voltage!

Recent years have seen an acceleration in

supply voltage reduction

Design at very low voltages still open

question (0.6 0.9 V by 2010!)

Reduce switching activity

Reduce physical capacitance


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N ext Lectu re

Optimizing for Performance and Power

Lecture7 MOS Tp AndP

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