Lecture6-ComplexLogicbwrcs.eecs.berkeley.edu/.../Lecture6-ComplexLogic.pdfEE141 12 EECS141EE141...

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EE141 EECS141 1 Lecture #6


  Lab 3 this week   Midterm on Friday February 19

  Open book   Covering material from start up to complex logic

optimization (this lecture and next)

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 Last lecture   Sizing inverters

 Today’s lecture  Complex logic  Optimizing complex logic

 Reading (2.3, 3.3.1-3.3.2)


Output = f ( In ) Output = f ( In, Previous In )

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At every point in time (except during the switching transients) each gate output is connected to either VDD or VSS via a low resistive path.

The outputs of the gates assume at all times the value of the Boolean function implemented by the circuit (ignoring, once again, the transient effects during switching periods).

(Will contrast this later to dynamic circuit style.)


VDD

F(In1,In2,…InN)

In1 In2

InN

In1 In2

InN

PUN

PDN

PMOS only

NMOS only

PUN and PDN are dual logic networks PUN and PDN functions are complementary

…

…

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Y = X if A AND B

Y = X if A OR B

  Transistor ↔ switch controlled by its gate signal   NMOS switch closes when switch control input is high

  NMOS transistors pass a “strong” 0 but a “weak” 1

A B

X Y

X Y

A

B

AND

OR


  PMOS switch closes when switch control is low

  PMOS transistors pass a “strong” 1 but a “weak” 0

X Y

A B

A

B X Y

NOR

NAND

Y = X if A AND B = A + B

Y = X if A OR B = AB

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VDD

VDD → 0 PDN

0 → VDD

CL

CL

PUN

VDD

0 → VDD - VTn

CL

VDD

VDD

VDD → |VTp|

CL

S

D S

D

VGS

S

S D

D

VGS


  PUP is the dual to PDN (can be shown using DeMorgan’s Theorems)

  Static CMOS gates are always inverting

A + B = AB

AB = A + B

AND = NAND + INV

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  PDN: G = AB ⇒ Conduction to GND   PUN: F = A + B = AB ⇒ Conduction to VDD

  G(In1,In2,In3,…) ≡ F(In1,In2,In3,…)


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OUT = D + A • (B + C)

D A

B C

D

A B

C


  Full rail-to-rail swing   Symmetrical VTC   Propagation delay function of load

capacitance and resistance of transistors   No static power dissipation   Direct path current during switching

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 All of these are decoders  Which one is “best”?

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  Is it better to drive a big capacitive load directly with the NAND gate, or after some buffering?

  Method to answer both of these questions:   Logical effort   Extension of buffer sizing problem

CL CL


For given N: Ci+1/Ci = Ci/Ci-1 To find N: Ci+1/Ci ~ 4 How to generalize this to any logic path?

CL = CN+1

In Out

1 2 N

fi = Ci+1/Ci

C1 C2 CN

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tpNAND = kR(Cint + CL)

= k(Rmin/W)(WCdnand + CL) = k(RminCgnand)(Cdnand /Cgnand +CL/(WCgnand))

= k(RminCgnand)(γ3/2 +CL/(WCgnand)) = tinv (2γ + (4/3)f)

2

2

2 2 Cdnand = 6CD

Cgnand = 4CG = (4/3) Cginv

CD/CG= γ


tpNAND = kR(Cint + CL)

= k(Rmin/W)(WCdnor + CL) = k(RminCgnor)(Cdnor /Cgnor +CL/(WCgnor))

= k(RminCgnor)(γ6/5 +CL/(WCgnor)) = tinv (2γ + (5/3)f)

1

Cdnor = 6CD

Cgnor = 5CG = (5/3) Cginv

CD/CG= γ

1

4

4

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Measure everything in units of tinv (divide by tinv):

p – intrinsic delay (kγg) - gate parameter ≠ f(W) LE – logical effort (k) – gate parameter ≠ f(W) f – electrical effort (effective fanout)

Normalize everything to an inverter: LEinv =1, pinv = γ

tpgate = tinv (pγ + LE×f)


Gate delay:

Delay = EF + p (measured in units of tinv)

effective fanout intrinsic delay

Effective fanout:

EF = LE f

logical effort electrical fanout = Cout/Cin

Logical effort is a function of topology, independent of sizing Effective fanout is a function of load/gate size

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  Inverter has the smallest logical effort and intrinsic delay of all static CMOS gates

  Logical effort LE is defined as:   (Req,gateCin,gate)/(Req,invCin,inv)   Easiest way to calculate (usually):

–  Size gate to deliver same current as an inverter, take ratio of gate input capacitance to inverter capacitance

  LE increases with gate complexity


Calculating LE by sizing for same drive strength:

LE = 1 LE = 4/3 LE = 5/3

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Fan-out (f)

Nor

mal

ized

del

ay (d

) t

1 2 3 4 5 6 7

pINV t pNAND

LE= p= d=

LE= p= d=

p = γ·Fan-in (for top input)


Fan-out (f)

Nor

mal

ized

del

ay (d

)

t

1 2 3 4 5 6 7

pINV t pNAND

LE=1 p=γ d=f+γ

LE=4/3 p=2γ d=(4/3)f+2γ

p = γ·Fan-in (for top input)

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From Sutherland, Sproull


  Need to set a convention:   What does a gate of size ‘2’ mean?

  For an inverter it is clear:   Cinv = 2, Rinv = ½

  For a gate, two possibilities:   Cgate = 2Cinv   Rgate = Rinv/2

  In my notes, size ≡ Cgate/Cinv   Size 2 gate has twice the input capacitance of a unit

inverter

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Branching effort:

CL,on_path

CL,off_path


Effective fanout: EFi = LEifi Path electrical fanout: F = Cout/Cin

Path logical effort: ΠLE = LE1LE2…LEN

Branching effort: ΠB = b1b2…bN

Path effort: PE = ΠLE ΠΒ F

Path delay D = Σdi = Σpi + ΣEFi

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When each stage bears the same effort:

Minimum path delay

Effective fanouts: LE1f1 = LE2f2 = … = LENfN


For a given load, and given input capacitance of the first gate Find optimal number of stages and optimal sizing

The ‘best effective fanout’

Remember: we can always add inverters to the end of the chain

is still around 4 (3.6 with γ=1)

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Electrical fanout, F = Π LE = PE = EF/stage = a = b = c =

LE = 1 f = a

LE = 5/3 f = b/a

LE = 5/3 f = c/b

LE = 1 f = 5/c


Electrical fanout, F = 5 Π LE = 1·(5/3)·(5/3)·1 = (25/9) PE = (Π LE)·F = (125/9) EF/stage = (125/9)^(1/4) = 1.93 a = 1.93 b = 2.23 c = 2.59

LE = 1 f = a

LE = 5/3 f = b/a

LE = 5/3 f = c/b

LE = 1 f = 5/c

5/c = 1.93 (5/3)c/b = 1.93 (5/3)b/a = 1.93

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LE=10/3 1 ΠLE = 10/3 P = 8 + 1

LE=2 5/3 ΠLE = 10/3 P = 4 + 2

LE=4/3 5/3 4/3 1 ΠLE = 80/27 P = 2 + 2 + 2 + 1


Branching effort:

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5 15

15

90

90

LE = FO = PE = SE1 = SE2 = PE =

1 90/5 = 18 18 (wrong!) (15+15)/5 = 6 90/15 = 6 36, not 18!

Introduce new kind of effort to account for branching:

•  Branching Effort:

•  Path Branching Effort:

Con-path + Coff-path

Con-path b =

Π bi B = Now we can compute the path effort: •  Path Effort: PE = ∏LE·FO·B

Branching Example 1


Select gate sizes y and z to minimize delay from A to B

Logical Effort: LE =

Electrical Effort: FO =

Branching Effort: B =

Path Effort: PE =

Best Stage Effort: SE =

Delay: D =

(4/3)3

Cout/Cin = 9

2•3 = 6

∏LE·FO·B= 128

PE1/3 ≈ 5

3•5 + 3•2 = 21

Work backward for sizes:

5 z = 9C•(4/3) = 2.4C

5 y = 3z•(4/3) = 1.9C

Branching Example 2

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  Compute the path effort: PE = (ΠLE)BF   Find the best number of stages N ~ log4PE   Compute the effective fanout/stage EF = PE1/N

  Sketch the path with this number of stages   Work either from either end, find sizes:

Cin = Cout*LE/EF

Reference: Sutherland, Sproull, Harris, “Logical Effort, Morgan-Kaufmann 1999.

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