1EE241 - Spring 2013Advanced Digital Integrated Circuits

Lecture 3: Features of Modern Technologies

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AgendaPrevious lecture

Scaling issuesTechnology scaling trendsFeatures of modern technologies

Todays lectureFinish lithographyTypical 32/28nm process

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Pop QuizAccording to Dennards 1974 paper when the scaling stops?

C. 32/28nm Technology Features - Lithography

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Litho: How to Enhance Resolution?1. Immersion2. Off-axis illumination3. Resolution enhancement/Optical proximity correction4. Restricted design rules (RDR)5. Phase-shifting masks6. Double patterning

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Litho (1): ImmersionProject through a drop of liquidnwater = 1.47

IBM

min 1 1930.25 351.35nmCD k nm

NA

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Litho (2): Illumination

Amplifies certain pitches/rotations at expense of others

Regular Illumination

Many off-axis designs (OAI)

Annular

Quadrupole / Quasar

Dipole +

or

Based on A.Kahng, ICCAD03

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Litho (3): Resolution Enhancement

J.Hartmann, ISSCC07

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OPCOptical Proximity Correction (OPC) modifies layout to compensate for process distortions

Add non-electrical structures to layout to control diffraction of lightRule-based (past) or model-based

A.Kahng, ICCAD03Design Mask

OPC Fracture

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Litho (4): Restricted Design Rules

J.Hartmann, ISSCC07

Also: note poly density rules

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Litho (5): Phase-Shift Masks

Phase Shifting Masks (PSM)Creates interference fringes on the wafer Interference effects boost contrast Phase Masks can make extremely small lines

conventional maskglass Chrome

Electric field at mask

Intensity at wafer

phase shifting mask

Phase shifter

A.Kahng, ICCAD03

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Litho (6): Double PatterningDouble exposure double etch

Double exposure double etchPitch split

Double exposure single etchDipole decomposition (DDL)Pack-unpack for contactResist freeze technologySidewall image transfer (SIT)

From Colburn, VLSI Technology 2008 Workshop

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Double-Exposure Double-EtchStarting layout Line + cut split Cut over line

Result:SRAM image from K. Mistry, IEDM07

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Pitch Split Double ExposureStarting layout Split pattern Overlay

With overlay misalignment

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32nm ExamplesSingle exposure Double exposure

IEDM08

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Litho: Design ImplicationsForbidden directions

Depends on illumination typePoly lines in other directions can exist but need to be thicker

Forbidden pitchesNulls in the interference pattern

Forbidden shapes in PSMAssist features

If a transistor doesnt have a neighbor, lets add a dummy

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Litho: Current Options (Beyond 22nm)Immersion lithography

Use high index (NA ~ 1.6-1.7, k1 < 0.3)Double patterning

NA ~ 1.2-1.35EUV lithography (?)

= 13.5nm

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D. Typical 32/28nm Process

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Some of the Process Features1. Shallow-trench isolation2. High-k/Metal-gate technology3. Strained silicon4. Thin-body devices (28nm, and beyond)5. Copper interconnects with low-k dielectrics

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1. Shallow Trench IsolationLess space needed for isolationSome impact on stress

p-well n-well

p+

p-epi

SiO2

AlCu

poly

n+

SiO2

p+

gate-oxide

Tungsten

TiSi2

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2. Hi-k/Metal gate

Replacement gate technology (Intel)

S. Natarajan, IEDM08

K. Mistry, IEDM07

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3. Strained SiliconHigh

Stress Film

NMOS

SiGe SiGe

PMOS

Compressive channel strain Tensile channel strain30% drive current increase 10% drive current increasein 90nm CMOS in 90nm CMOS

Intel

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Intels Strained Si Numbers

90 nm 65 nm

NMOS PMOS NMOS PMOS

20% 55% 35% 90%

IDSAT 10% 30% 18% 50%

IDLIN 10% 55% 18% 80%

Performance gains:

S. Thompson, VLSI06 Tutorial

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Strained SiliconNo strain Strained Si

OutIn

VDD

M2

M1

OutIn

VDD

M2

M1W1 = 1

W2 ~ 2

W1 = 1

W2 = 1.6

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5. Thin-Body Devices28nm FDSOI 22nm finFET

N. Planes, VLSI2012 C. Auth, VLSI2012

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5. Interconnect

J. Hartmann, ISSCC07

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Interconnect: CMP

Ta barrier layerto prevent Cu fromdiffusing into Si

Etch stop (SiN)

Mi

Mi-1

Cu interconnect: Dual damascene process

Metal density rules (20%-80%)Slotting rulesAlso: Antenna rules

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