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Analog Electronics(Course Code: EE314)

Lecture 29: OPAMP Basics

Indian Institute of Technology Jodhpur, Year 2018

Course Instructor: Shree Prakash TiwariEmail: sptiwari@iitj.ac.in

Webpage: http://home iitj ac in/~sptiwari/Webpage: http://home.iitj.ac.in/~sptiwari/

Course related documents will be uploaded on http://home.iitj.ac.in/~sptiwari/EE314/

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Note: The information provided in the slides are taken form text books for microelectronics (including Sedra & Smith, B. Razavi), and various other resources from internet, for teaching/academic use only

Amplifier Design requires specialized knowledge

R1 RC

VCC

CE Amplifier 20K2K

+12V

Q2

R2 CE

CC

RE

CB

VS

RL

vo

Vin1

-12V

0.1mA 10mA

137K

Q1aQ1b

Q2

Q3

It is not possible for every user to design his/her own amplifier !

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Why can’t we have experts design and implement amplifiers and make it available to everybody else !

Although this is done, it does not satisfy all the users due to diverse requirements

Design

Custom

Semi‐Custom

Standard

Semi‐custom: partially completed design which is customized by the user

Op‐amp is a good illustration of the advantages of semi‐custom approach

X

v11 2 0v v

short

i 0i

X

v2

shortX open

Can something be both a short as well as open circuit ?

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‐An amplifier that is sensitive to difference in input voltages and insensitive to what is common.

vo

vin1

vin2

Difference Amplifier

1 2

1 22

id in in

in inic

v v v

v vv

o d id cm icv A v A v

: Differential mode gain

: Common mode gaind

cm

A

A

d cmA A

Common Mode Rejection Ratio: d

cm

ACMRR

A

vo

v1

v2

Operational Amplifier

A special kind of difference amplifier

1. Very High Differential‐mode voltage gain2 V Hi h C d R j ti ti2. Very High Common mode Rejection ratio3. Very High Input Resistance4. Very Low output Resistance5. ….

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vo

v1

v2

Ideal Operational Amplifier

1. Infinite Differential‐mode voltage gain2. Infinite Common mode Rejection ratio3. Infinite Input Resistance4 Zero output Resistance4. Zero output Resistance5. ….

Common Mode Rejection Ratio (CMRR)

c

d

A

ACMRR

A

c

d10 A

A20logCMRR(log)or,

cccc

ccddo

vA1vA

vA1vA

vAvAvNow,

8

d

cdd

dddd

dddd

v

v

CMRR

11vA

vA1vA

vA1vA

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Example: Determine the output voltage of an op‐amp for input voltages of vi1 = 150µV, vi2=140µV. The amplifier has a differential gain of Ad=4000 and the value of CMRR is 100.

d

cddo v

v

CMRR

11vAvSolution :

Vvv

μVvvv

ii

iid

145

10

21

21

9mV.μV

v

μVv

o

iic

84545800

10

145

100

11104000

1452

21

Example: LM 741

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Inside the opamp, there is a complicated circuit containing several transistors and resistors.

Simple equivalent circuit model of an op‐amp

vo

v1

v2

+viRi

v1

R0vo

AO v+

0Ω-i AOL vi

v2

-

~105

~10Ω

~106 ΩThis assumes very high CMRR

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v1

v2

vo

+VCC

-VCC

+vi-

Ri

v1

R0vo

AOL vi

v2

+-

vo

vi

o ol iv A v VCC

‐VCCOpamp is said to be saturated

+vi-

Ri

v1

R0vo

AOL vi

v2

+-

vo

v1

v2

vo

+ve

+ve

vo

+ve‐ve

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How do we amplify this signal?

vSv1

v2

vo

+12V

1 ( )sv mV Sin t-12V

vSvO

vSvO

+vi-

Ri

v1

R0vo

AOL vi

v2

+-

+vi-

Ri

R0vo

AOL vi

+-

vS210 ( )o ol Sv A v Sin t

But opamp voltage is limited to 12V

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How do we amplify this signal then ?

vS vSvO

v1

v2

vo

+12V

-12V

1 ( )sv mV Sin t

-12V

1. Attenuate the signal to 0.1mV and then amplify ?22. …….

R1

R2

A Better Solution

2v RVOVS

2

1

o

S

v R

v R

Amplifier has feedback

If the feedback signal helps the input voltage we have positivefeedback, otherwise negative.

Amplifier has feedback

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Feedback

vIN voutAV

vINvoutAVΣ outAV

Feedbacknetwork

Negative and Positive feedback

vINvoutAVΣ

vfb

+

‐

VIN ‐ Vfb

Feedbacknetwork

fb

Negative feedback

v + V + VvINvoutAV

Feedbacknetwork

Σ

vfb

+

+

Positive feedback

VIN + Vfb

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Negative and positive feedback

-+

Avi vO

v

vfb

v

-+

vi

vfb

vO

v-A

Opamp circuits classification

Closed loop

Negative feedback

Opamp circuits

C osed oopOr feedback

Open loop

Positive feedback

Open loop

Most Op‐amp Circuits employ negative feedback

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Ideal Op‐Amp analysis (in a circuit)

+vi-

Ri

v1

R0vo

AOL vi

v2

+-

i) Ri = ∞, No current enters into op‐amp

Voltage Gain A =∞ or v / v =∞ (V = V )

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Voltage Gain A = ∞ or, vo/ vd= ∞ (Vd = Vi)or, vd = vo/∞ = 0 [since vo is finite]→ v1 ‐ v2 = 0or, ii) v1 = v2

R1

R2

+

Like ‘Ground’ too

i i

Virtual ground

VOVS

+Vi=0‐

vx

i

i

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Practical OP‐AMP Circuits

Using KVL,

v i R 0

1. Inverting Amplifier

v1 – i1R1 = 0

i1 = v1/R1&

0 – i1Rf – vo = 0

or, vo = ‐i1Rf = ‐v1Rf/R1

25

o 1 f 1 f 1

v0/v1 = ‐Rf/R1

2. Non Inverting Amplifier

26

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2. Non Inverting Amplifier

ii

i

27

o

f1o

1fo

vior

0RRivor,

0iRiRv

i

f1 RRior,

1ff1

oo

1fo

0vRRR

vvor,

0viRvAgain,

i

28

1f1

fo

f1

vRR

R1vor,

RR

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1

f1

1o

RR

vRR

Rvor,

1

f1o

1

f11o

R

R1vvor,

R

RRvvor,

29

Examples

VO

1K

10K

10mV

VO

1K

10K

10mV

2

1100o

oS

v Rv mV

v R 2

11 110o

oS

v Rv mV

v R

0

1mA

0

01

10ov mAK

10ov V

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3. Voltage Follower

vo = v1

31

4. Summing Amplifier

32

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i1

i2

i

2

i3

33

i = i1+ i2+ i3

3

3

2

2

1

1

f

0

321

R

v

R

v

R

v

R

v0or,

iiii

3

3

2

2

1

1fo

3

3

2

2

1

1

f

o

R

v

R

v

R

vRvor,

R

v

R

v

R

v

R

vor,

34

3

3

f2

2

f1

1

fo v

R

Rv

R

Rv

R

Rvor,

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Design Example

1 2 310 4 5o s s sv v v v

Design a circuit that would generate the following output given three input voltages vs1, vs2 and vs3.

Rf

VO

R1

R2

VS2

VS1 1 21 2

f fo s s

R Rv v v

R R

Rf

R1 R2f f fR R R

VO

VS1

R1 R2

R3

VS2

VS3

1 2 31 2 3

f f fo s s sv v v v

R R R

Choose : 10fR K1 1R K

2 2.5R K 3 2R K

Rf

R4

Adder Example

VO

Rf

VS1

R1

R2 R3

R4

VO

VS1

VS2

R1

R2 R3

VO

Rf

R1

R4

O

VS2

R2 R3

2 31

2 3 1o s

R Rv v

R R R

4(1 )

fR

R

1 32

1 3 2s

R Rv

R R R

4(1 )

fR

R

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Rf

R42 3

12 3 1

o sR R

v vR R R

(1 )fR

R

Adder Example

VO

VS1

VS2

R1

R2 R3

2 3 1R R R 4R

1 32

1 3 2s

R Rv

R R R

4(1 )

fR

R

High entropy expression !

1 2 3PR R R R 1 21 2 4

( ) (1 )p p f

o s sR R R

v v vR R R

Low entropy expression !

Subtractor

R1

Rf

32

2 3s

Rv

R R3

1 22 3

1

s sR

v vR R

R

31 2

2 3

1

s sR

v vR R

R

VO

1

VS1

VS2 R3

R23

22 3

sR

vR R

3 32 1 2

2 3 2 3

1

s o s s

f

R Rv v v v

R R R R

R R

3

22 1

3 1 1

2

(1 ) ( )(1 )

f fo s s

RR RR

v v vR R RR

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VO

R1

Rf

VS1 RS1

VS2 R3

R2

3

22 1(1 ) ( )

f fo s s

RR RR

v v vR R R

3ChoosefRR

3 1 1

2(1 )

R R RR

2 1Choose

R R

2 11

( )f

o s sR

v v vR

Subtractor: Alternative Analysis

VO

R1

Rf

VS1

VO

R1

Rf

VS1

R3

R2

S1

VS2 R3

R2

Use superposition theoremVO

R1

Rf

VS1

VS2 R3

R2

Inverting amplifier

1( )fR

v v +3

2 ( )sR

v (1 )fR

Analysis is made simpler by Re‐Using results derived earlier

11

( )o sv vR

+

Non‐inverting amplifier

23 2( )s R R 1

(1 )R

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Adder/Subtractor

R1

Rf

VS2

R2

VOVS1

VS4

R3

R4 R5VS3

11

( )f

o sR

v vR

+ 22

( )f

sR

vR

5 43

5 4 3s

R Rv

R R R+1 2

(1 )fR

R R

+ 5 34

5 3 4s

R Rv

R R R 1 2(1 )

fR

R R

Adder/Subtractor

R1

Rf

VS2

R2

VOVS1

VS4

R3

R4 R5VS3 3 4 5PR R R R

11

( )f

o sR

v vR

+ 22

( )f

sR

vR

33

PsR

vR+

1 2(1 )

fR

R R

+ 44

PsR

vR 1 2

(1 )fR

R R

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Example

VO

R1

Rf

VS2

R2

VS1R3

1 2 3 410 4 5 2o s s s sv v v v v

VS4

R4 R5VS3

1 2 3 41 2 1 2 3 1 2 4

( ) ( ) (1 ) (1 )f f f fP P

o s s s sR R R RR R

v v v v vR R R R R R R R

3 4 5PR R R R

Choose : 10fR K 1 1R K 2 2.5R K

30.33PR

R

40.133PR

R

4

32.5

R

R

Choose : 3 1R K 4 2.5R K 0.33PR K 5 0.625R K

C

+VCC

Integrator

/sv R

/sv R

-VCC

VOR

VS

1( )S O

O S

V dVC V t V dt

R dt RC

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Differentiator

+VCCC

R

SdvCdt

SdvCdt

CC

-VCC

VO

VS

( )O S SO

V dV dVC V t RC

R dt dt

Log Amplifier

+V

D( 1)T

VV

SI I e

/sv R

/sv R

+VCC

-VCC

VOR

VS

( 1) ln(1 ) ln( )O

T

V

VS S SS O T T

S S

V V VI e V V V

R RI RI

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+VCCD

R

AntiLog Amplifier

( 1)

S

T

VV

SI I e

( 1)

S

T

VV

SI I e

-VCC

VO

VS

( 1) ( 1)S S S

T T T

V V V

V V VOS O S S

VI e V RI e RI e

R

Comparator: Op‐amp under open Loop condition

+VCC

VO

VS1

V

+vi-

vo

+-

R0

-AOL viRi

vS1

vS2

-VCC

VS2vS2

VO

VCC

VS2 ‐VS1

‐VCC

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+12V

12V

5V

5.5V

VO=? ~ ‐12V

-12V

+12V

V =? ~ +12V

-12V

VO=?

5mV

+12V

1K

1F

+5V+5V

v

1 (2 ); 1inv V Sin ft f KHz

Example

VOVIN

-5V-5V

1 5 0

5 0O in

in

V V if v

V if v

vo1

VIN

1V

-5V

time (ms)

time (ms)

5V

VO1

10.5VO

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VO

D

1V

1K

+12V

Example

-12V

1V

+12V +12V

1V1V

1K

-12V

VO

-12V

VO

1V

~ ‐12V

VO

VS2

VS1

R

R

R

1 2( )o s sv v v

Appendix: Loading effect

VS2

VS1

R

R

R

R

R

VO

VO1

1 1 2 ( )o s sv v v 1 o ov v 1 2( )o s sv v v

Have we made some assumption here ?

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Example

R

Rvs

vo1

R

R

vx vO

1 0.5o

s

v

v 0.5o

x

v

v

v v1 o xv v

1

1 0.5 0.5 0.25o o o

s o s

v v v

v v v

10.5o o

x o

v v

v v

BUT

vs R R

RRvo

0.2o

s

v

v

Where is the error ?

R

Rvs

vo1

R

R

vx vO

1 o xv v

1 0.5o

s

v

v 0.5o

x

v

v1 0.5o

s

v

v

Circuit‐1 gets ‘loaded’ by circuit‐2 and its output vs. input characteristics get modified.

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Loading Effect

vs

vo

Circuit

vs

voCircuit Load

s

Vo in general gets altered when we connect a load to it

s

Under what conditions is change in VO small upon connection ofa load ?

Example

vs

vo1

1K

1K

vx vO

1M

1M

1 0.5o

s

v

v

1 0.5o

s

v

v

We can describe this effect in terms of output resistanceWe can describe this effect in terms of output resistance

vs

vo1

1K

1K

0.5oR K 2LR M

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Loading Effect

Whenever output resistance of a circuit is much smaller than the load resistance, the loading effect is minimal.

o LR R

VO

VS2

VS1

R

R

R

1 2( )o s sv v v

VS2

VS1

R

R

R

R

R

VO

VO1

1 1 2 ( )o s sv v v 1 o ov v 1 2( )o s sv v v

The assumption made here is that there is no loading which is reasonable because op‐amps have very low output resistance

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Example

R

R

R

R

2R

R

VO

VO1

1V

2V

1 1 2 3oR R

v VR R

1

21 9o

oo

v Rv V

v R

Next

• OPAMP

• Frequency response