Lecture2

Lecture 2

The 8086 Microprocessor Architecture

[Register level organization]

Zelalem Birhanu, AAiT 1

In this lecture

• The 8086 internal architectureThe Execution Unit

The Bus Interface Unit

Physical Address Generation


The Basic Arch.

The simplest microprocessor at least contains: Program and data address bus (separate or unified) Address decoder and generator Instruction decoder Arithmetic and Logic Unit (ALU) A set of basic registers

Program Counter (PC)Instruction Register (IR) Accumulator or Working Register (AC)Flag register (FR)Input and output registersGeneral purpose (temporary)registers (GPRs)


The 8086 Internal Architecture


8086

• 40 pins• 16-bit architecture• Clock Rate : 10MHz max


IBM PC

IBM PC (1981) was based on 8088 which is identical to 8086 except the data bus

• Memory: 16kB – 256 kB• CPU: Intel 8088 @ 4.77MHz• $3000 at the time


8086 Internal Arch.


8086 Internal Arch….cntd

Two functional partsExecution Unit (EU)

Bus Interface Unit (BIU)


The Execution Unit (EU)

The EU contains :

• Control Circuitry: Directs internal operations

• A Decoder : Translates instructions fetched from memory into a series of actions which the EU carries out

• 16-bit Arithmetic Logic Unit (ALU) : Does arithmetic and logic operations (add, subtract, multiply, OR, AND,…)

• Registers : General purpose, flag


Flag register

• Consists of bits that show the status of the CPU or control the operation of the CPU


Status Flags

• Carry Flag (C) This flag is set when there is a carry out of MSB in case of

unsigned addition or a borrow in case of unsigned subtraction

• Zero Flag (Z) This flag is set when the result of an arithmetic operation is

zero

• Sign Flag (S) This flag is set when the result an arithmetic operation is negative For signed computations, the sign flag equals the MSB of the result


Status Flags…cntd

• Parity Flag (P) This flag is set when the lower byte of a result contains even

number of 1s.

• Overflow Flag (O) This flag is set, if an overflow occurs, i.e. if the result of a

signed operation is either too large or too small to fit into a destination

• Auxiliary Cary Flag (AC) This is set if there is a carry from the lowest nibble, i.e. bit

three, during addition or borrow for the lowest nibble, i.e. bit three, during subtraction.


Control Flags

• Interrupt Flag (I) If this flag is set, the maskable interrupts are acknowledged

by the CPU, otherwise they are ignored.

• Direction Flag (D) This is used by string manipulation instructions.

If this flag bit is '0’ the string is processed beginning from the lowest to the highest address (auto-incrementing mode). Otherwise, the string is processed from the highest to the lowest address (auto-decrementing mode).


General Purpose Registers (GPRs)

• The EU has eight 16-bit general purpose registersAX, BX, CX, DX, BP, SP, SI, DI

• AX, BX, CX and DX can be addressed as two separate 8-bit values

AH-AL, BH-BL, CH-CL, and DH-DL.

• Usually used as: A - accumulator, B - base, C - counter, D -data

AX

AH AL

8 8

16


The Bus Interface Unit (BIU)


Instruction Byte Queue

• While the EU is decoding or executing an instruction, which does not require use of the buses, the BIU fetches up to six instruction bytes for the following instructions

• The BIU stores these pre-fetched bytes in a first-in-first-out register set called a queue. When the EU is ready for its next instruction, it simply reads the instruction byte(s) for the instruction from the queue in the BIU


Segment Registers

• The four 16-bit segment registers : Code segment (CS) register

Data segment (DS) register

Stack segment (SS) register

Extra segment (ES) register

• Used to address memory (up to 1048576 bytes (1MB) )

8086Memory

20-bit Address

16-bit Data


Physical address generation• In 8086 system memory was

divided into 64kB units called segments

• Memory is addressed using a combination of a segment register and an offset register

00000H

10000H

20000H

80000H

90000H

F0000H

FFFFFH

64K

64K

64K

64K

80000H

8FFFFH

8F000H

F000H (offset)


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Physical address generation…cntd



• E.g. If the segment address is 1005h and the offset is 5555h, then the physical address is calculated as follows

Segment address --------- 1005hOffset address------------- 5555h

Segment address--------- 1005h --------- 0001 0000 0000 0101Shifted by 4 bit positions---------- 0001 0000 0000 0101 0000Offset address----------------------- + 0101 0101 0101 0101

Physical address ------------------- 0001 0101 0101 1010 01011 5 5 A 5 h



• A typical program has three segments: code, data and stack

CS contains the 16-bit code segment address

DS contains the 16-bit data segment address

SS contains the 16-bit stack segment address

ES can point to alternate data segments


Instruction Pointer (IP)

• The IP contains the distance or offset from the base address in Code Segment (CS) to the next instruction byte to be fetched

• The 16-bit offset in IP is added to the 16-bit segment base address in CS to produce the 20-bit physical address.

• Location of the next instruction in memory is, thereforeaddress of next instruction = (CS << 4) + IP or (CS:IP)


Instruction Pointer (IP)…cntd

• E.g. Let CS holds 348Ah, and IP holds 4214h. Now the actual address in the physical memory space is given by CS:IP and calculated as:

• CS is first shifted left four times

CS <<4= 348A0h

Then the offset in IP is added

348A0h

+ 4214h

Actual address 38AB4h


Other Registers

Stack Pointer

• A stack is a section of memory set aside to store addresses and data while a subprogram is executing

• The 8086 allow you to set aside an entire 64KB segment as a stack. The upper 16 bits of the starting address for this segment are kept in the stack segment register (SS)

• The stack pointer (SP) register holds the 16-bit offset from the start of the segment to the memory location where a word was most recently stored on the stack (Top of stack)

address of top of stack = (SS << 4) + SP or (SS:SP)


Other Registers…cntd

• E.g. Let SS hold 5000h, and SP hold FFE0h

• Now the actual address in the physical memory space is given by SS:SP and calculated as:

• SS is first shifted left four times

SS<<4 = 50000h

Then the offset in SP is added 50000h

+ FFE0h

Top of stack 5FFE0h


Other Registers…cntd

Base Pointer and Index Registers

• In addition to the SP, the EU contains a 16-bit base pointer (BP) register, a 16-bit source index (SI) register and a 16-bit destination Index (DI) register.

• The base pointer can be used to hold the 16-bit offset of a data word in one of the segments. Index registers are very useful in string manipulation.

• These three registers can be used for temporary storage of data just as the general-purpose registers described above


Summary of 8086 registers


After 8086

IA-32

• Starting from 80386

• 32 bit registers (extended registers)

• 32 bit address bus

AX

AH AL

8 8

16

EAX

32


After 8086…cntd

On chip Floating Point Unit (FPU)


Pipelining


Superscalar, MMX

• Starting from Pentium


Next Class

• 8086 Pinouts

• 8086 Memory Interfacing


More Readings

1. Dr. Manoj’s Handout, Chapter 1

2. Kip R. Irvine, “Assembly Language For Intel-Based Computers”, Chapter 2

3. 8086 Datasheet, Intel


Lecture2

Documents

Transcript of Lecture2