EL 511 VLSI1

EL 512 VLSI Subsystem Design

Instructor: Mazad S. Zaveri

Faculty Block 4, Room 4206Email: mazad_zaveri@daiict.ac.in

http://intranet.daiict.ac.in/~mazad_zaveri/

EL 511 VLSI2

Pulse Generators (for Pulsed Latch)

See scanned notes

EL 511 VLSI3

Time borrowing (FF based system) FF based system

Data departs the first FF on the rising edge of the clock and must setup at the second FF before the nest rising edge

If data arrives early, then it is blocked (or waits) until the next clock edge, and the remaining time goes unused

If data arrives late (within the setup window), then wrong data will be stored Hence, borrowing the unused time may not be possible in such systems

EL 511 VLSI4

Time Borrowing (2-phase Latch) Borrowing time is possible

For the pipeline architecture Could borrow time from the current stages half-cycle, and also from next stage

For loopy (FSM-like) architectures Could borrow time from the current stages cycle only

EL 511 VLSI5

Maximum amount of time borrowing (2-phase latch) Borrow time, is roughly the pulse width minus the setup

time It can be maximized by making the pulse width almost =

(Tc / 2), i.e. by making tnonoverlap almost zero (tnonoverlap cannot be zero, because then both latches may be ON,

and data could race through)

EL 511 VLSI6

Time borrowing (pulsed latch)

Equation is for pulse-width > setup time condition

This equation is similar to that of the 2-phase latch system, (i.e. pulse width minus setup time) So it means we should increase pulse width for larger

borrow time However, doing that will increase your effective hold time (for

the min-delay constraint), and cause min-delay constraint failure

EL 511 VLSI7

Clock Skew (FF)

Clock skew is undesirable When it decreases the time available for logic

propagation tpd (in the max-delay constraint) It will eat up some of the clock-period time, or effectively

reduce it It increases the effective hold time, hence, increasing

the min. logic contamination time tcd (in min-delay constraint)

EL 511 VLSI8

Clock skew (2-phase latch) Clock skew will affect the min-delay, and borrowing time How will clock skew affect max-delay?

Authors assumption: It does not affect the max-delay, because the data still has an available window (within the transparent pulse width) in which it can arrive

However, those windows are now smaller, so carefully designing the logic (with skew budget in mind) the data arrival can be controlled within those windows

Hence, from that perspective, we call this system skew-tolerant (and NOT skew-independent) for max-delay

Effectively increases hold time

Effectively reduces borrowing time

EL 511 VLSI9

Clock skew (Pulsed latch) If the pulse width is narrow, skew can adversely affect

min-delay constraint and borrowing time For max-delay,

If pulse width is large, skew can be tolerated, because there is a transparent window during which the data can arrive

If pulse width is narrow, skew will affect the max-delay

10

Topics to read

From the DJVU file 7.2 (Pg. 384) 7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 7.3.1 (Fig. 7.17)