Lecture Outline ESE 570: Digital Integrated Circuits and VLSI ...ese570/spring2019/handouts/...Q=CV=...
Transcript of Lecture Outline ESE 570: Digital Integrated Circuits and VLSI ...ese570/spring2019/handouts/...Q=CV=...
1
ESE 570: Digital Integrated Circuits and VLSI Fundamentals
Lec 10: February 19, 2019 MOS Inverter: Dynamic Characteristics
Penn ESE 570 Spring 2019 – Khanna
Lecture Outline
! Inverter Power ! Dynamic Characteristics
" Delay
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Inverter Power
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Power
! P = I×V
! Tricky part: " Understanding I " (pairing with correct V)
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Static Current
! P = Istatic×VDD
! Static current determined by subthreshold current
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Switching Currents
! Dynamic current flow:
! If both transistor on: " Current path from Vdd
to Gnd " Short circuit current
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2
Switching
Dynamic Power
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Switching Currents
! Itotal(t) = Istatic(t)+Iswitch(t)
! Iswitch(t) = Isc(t) + Idyn(t)
8
Isc
Istatic
Idyn
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Charging
! Idyn(t) – why is it changing? " Ids = f(Vds,Vgs) " and Vgs, Vds changing
9
€
IDS = µnCOXWL
"
# $
%
& ' VGS −VT( )VDS −
VDS2
2)
* +
,
- .
€
IDS ≈νsatCOXW VGS −VT −VDSAT
2%
& '
(
) *
Penn ESE 570 Spring 2019 - Khanna
Switching Energy – focus on Idyn(t)
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Isc
Istatic
Idyn
Switching Energy – focus on Idyn(t)
E = P(t)dt∫= I(t)Vdd dt∫=Vdd I(t)dt∫
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Idyn
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Switching Energy
12
! Do we know what this is?
Idyn
Idyn (t)dt∫
E = P(t)dt∫= I(t)Vdd dt∫=Vdd I(t)dt∫
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Switching Energy
13
! Do we know what this is?
Idyn
Q = Idyn (t)dt∫
E = P(t)dt∫= I(t)Vdd dt∫=Vdd I(t)dt∫
Penn ESE 570 Spring 2019 - Khanna
Switching Energy
14
! Do we know what this is?
! What is Q? Idyn
Q = Idyn (t)dt∫
E = P(t)dt∫= I(t)Vdd dt∫=Vdd I(t)dt∫
Penn ESE 570 Spring 2019 - Khanna
Switching Energy
15
! Do we know what this is?
! What is Q? Idyn
Q = Idyn (t)dt∫
E = P(t)dt∫= I(t)Vdd dt∫=Vdd I(t)dt∫
€
Q = CV = I(t)dt∫
Penn ESE 570 Spring 2019 - Khanna
Switching Energy
16
! Do we know what this is?
! What is Q? Idyn
Q = Idyn (t)dt∫
E = P(t)dt∫= I(t)Vdd dt∫=Vdd I(t)dt∫
€
Q = CV = I(t)dt∫
€
E = CVdd2
Capacitor charging energy
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Switching Power
! Every time output switches 0#1 pay: " E = CV2
! Pdyn = (# 0#1 trans) × CV2 / time
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Switching Power
! Every time output switches 0#1 pay: " E = CV2
! Pdyn = (# 0#1 trans) × CV2 / time
! # 0#1 trans = ½ # of transitions
! Pdyn = (# trans) × ½CV2 / time
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4
Switching
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Short Circuit Power
Short Circuit Power
! Between VTN and Vdd - VTP
" Both N and P devices conducting
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Short Circuit Power
! Between VTN and Vdd - VTP
" Both N and P devices conducting
! Roughly:
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Isc
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Vin
time
Vout
Isdp
time
time
time
Vthn
Vdd
Vdd
Vdd-Vthp
Isc
tsc tsc
Peak Current
! Ipeak around Vdd/2 " If |VTN|=|VTP| and sized equal rise/fall
22
€
IDS ≈νsatCOXW VGS −VT −VDSAT
2%
& '
(
) *
Penn ESE 570 Spring 2019 - Khanna
Vin
time
Vout
Isdp
time
time
time
Vthn
Vdd
Vdd
Vdd-Vthp
Isc
tsc tsc
Peak Current
! Ipeak around Vdd/2 " If |VTN|=|VTP| and sized equal rise/fall
23
€
IDS ≈νsatCOXW VGS −VT −VDSAT
2%
& '
(
) *
€
I(t)dt∫ ≈ Ipeak × tsc ×12%
& ' (
) *
Penn ESE 570 Spring 2019 - Khanna
Vin
time
Vout
Isdp
time
time
time
Vthn
Vdd
Vdd
Vdd-Vthp
Isc
tsc tsc
Vin
time
Vout
Isdp
time
time
time
Vthn
Vdd
Vdd
Vdd-Vthp
Isc
tsc tsc
Peak Current
! Ipeak around Vdd/2 " If |VTN|=|VTP| and sized equal rise/fall
24
€
IDS ≈νsatCOXW VGS −VT −VDSAT
2%
& '
(
) *
€
I(t)dt∫ ≈ Ipeak × tsc ×12%
& ' (
) *
€
E =Vdd × Ipeak × tsc ×12#
$ % &
' (
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Dynamic Characteristics
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Inverter Delay
! Caused by charging and discharging the capacitive load " What is the load?
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Inverter Delay
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Inverter Delay
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Inverter Delay
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Cgb = Cgbn+ Cgbp
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Inverter Delay
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Cload = C#dbn + C#
dbp + C#gdn + C#
gdp + Cint + Cgb
Cgb = Cgbn+ Cgbp
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Inverter Delay
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Cload ≈ C#dbn + C#
dbp + Cint + Cgb
Usually Cdb >> Cgd Csb >> Cgs
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Cload ≈ Cdbn + Cdbp + Cint + nCgb
n = fan-out ≥ 1
Inverter Delay
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Propagation Delay Definitions
33
VDD
0 t
VDD
0
V50% = VDD/2 Penn ESE 570 Spring 2019 – Khanna
Propagation Delay Definitions
34
t
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Propagation Delay Definitions
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Rise/Fall Times
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MOS Inverter Dynamic Performance
! ANALYSIS (OR SIMULATION): For a given MOS inverter schematic and Cload, estimate (or measure) the propagation delays
! DESIGN: For given specs for the propagation delays and Cload*,
determine the MOS inverter schematic
37
Assume Vin ideal
Penn ESE 570 Spring 2019 – Khanna
MOS Inverter Dynamic Performance
! ANALYSIS (OR SIMULATION): For a given MOS inverter schematic and Cload, estimate (or measure) the propagation delays
! DESIGN: For given specs for the propagation delays and Cload*,
determine the MOS inverter schematic
38
3 METHODS: 1. Average Current Model
Assume Vin ideal
τPHL ≈CloadΔVHLIavg ,HL
τPLH ≈CloadΔVLHIavg ,LH
Penn ESE 570 Spring 2019 – Khanna
MOS Inverter Dynamic Performance
! ANALYSIS (OR SIMULATION): For a given MOS inverter schematic and Cload, estimate (or measure) the propagation delays
! DESIGN: For given specs for the propagation delays and Cload*,
determine the MOS inverter schematic
39
3 METHODS: 2. Differential Equation Model
Assume Vin ideal
iC =CloaddVoutdt
⇒ dt∫ =CloaddVoutiC
∫dt ≈ τ PHL or τ PLH
Penn ESE 570 Spring 2019 – Khanna
MOS Inverter Dynamic Performance
! ANALYSIS (OR SIMULATION): For a given MOS inverter schematic and Cload, estimate (or measure) the propagation delays
! DESIGN: For given specs for the propagation delays and Cload*,
determine the MOS inverter schematic
40
3 METHODS: 3. 1st Order RC delay Model
Assume Vin ideal
τ PHL ≈ 0.69 ⋅Cload ⋅Rnτ PLH ≈ 0.69 ⋅Cload ⋅Rp
Penn ESE 570 Spring 2019 – Khanna
Method 1
Average Current Model
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Calculation of Propagation Delays
42
τ PHL ≈ CloadΔVHLIavg,HL
=CloadVOH −V50%Iavg,HL
τ PLH ≈ CloadΔVLHIavg,LH
=CloadV50% −VOLIavg,LH
Penn ESE 570 Spring 2019 – Khanna
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Calculation of Propagation Delays
43
τ PHL ≈ CloadΔVHLIavg,HL
=CloadVOH −V50%Iavg,HL
τ PLH ≈ CloadΔVLHIavg,LH
=CloadV50% −VOLIavg,LH
Penn ESE 570 Spring 2019 – Khanna
Calculation of Propagation Delays
44
τ PHL ≈ CloadΔVHLIavg,HL
=CloadVOH −V50%Iavg,HL
τ PLH ≈ CloadΔVLHIavg,LH
=CloadV50% −VOLIavg,LH
Penn ESE 570 Spring 2019 – Khanna
Calculation of Rise/Fall Times
45
τ fall ≈ CloadΔV90%−10%Iavg,90%−10%
=CloadV90% −V10%Iavg,90%−10%
τ rise ≈ CloadΔV10%−90%Iavg,10%−90%
=CloadV90% −V10%Iavg,10%−90%
Penn ESE 570 Spring 2019 – Khanna
Calculation of Rise/Fall Times
46 Penn ESE 570 Spring 2019 – Khanna
τ fall ≈ CloadΔV90%−10%Iavg,90%−10%
=CloadV90% −V10%Iavg,90%−10%
τ rise ≈ CloadΔV10%−90%Iavg,10%−90%
=CloadV90% −V10%Iavg,10%−90%
Calculation of Rise/Fall Times
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τ fall ≈ CloadΔV90%−10%Iavg,90%−10%
=CloadV90% −V10%Iavg,90%−10%
τ rise ≈ CloadΔV10%−90%Iavg,10%−90%
=CloadV90% −V10%Iavg,10%−90%
Method 2
Differential Equation Model
Penn ESE 570 Spring 2019 – Khanna
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Calculating Propagation Delays
49
Two Cases 1. Vin abruptly rises => Vout falls => 2. Vin abruptly falls => Vout rises =>
Assume Vin is an ideal pulse-input
iDP - iDn
τ PHLτ PLH
Penn ESE 570 Spring 2019 – Khanna
Case 1: Vin Abruptly Rises - τPHL
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Case 1: Vin Abruptly Rises - τPHL
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Case 1: Vin Abruptly Rises - τPHL
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≈
≈
Penn ESE 570 Spring 2019 – Khanna
Case 1: Vin Abruptly Rises - τPHL
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≈
≈
Penn ESE 570 Spring 2019 – Khanna
Case 1: Vin Abruptly Rises - τPHL
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V out= V DD− V T0n
≈
≈
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Case 1: Vin Abruptly Rises - τPHL
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V out= V DD− V T0n
≈
CloaddVoutdt
≈ −iDn
dt =Cload−dVoutiDn
τ PHL = dtt=t0
t=t50%∫ =Cload−1iDn
$
%&
'
()
Vout=VDD
Vout=VDD /2∫ dVout
τ PHL =Cload−1iDn
$
%&
'
()
VDD
VDD−VT 0n∫ dVout +Cload−1iDn
$
%&
'
()
VDD−VT 0n
VDD /2∫ dVout
Penn ESE 570 Spring 2019 – Khanna
Case 1: Vin Abruptly Rises - τPHL
56
V out= V DD− V T0n
≈
CloaddVoutdt
≈ −iDn
dt =Cload−dVoutiDn
τ PHL = dtt=t0
t=t50%∫ =Cload−1iDn
$
%&
'
()
Vout=VDD
Vout=VDD /2∫ dVout
τ PHL =Cload−1iDn
$
%&
'
()
VDD
VDD−VT 0n∫ dVout +Cload−1iDn
$
%&
'
()
VDD−VT 0n
VDD /2∫ dVout
t0#t1 t1#t50% Penn ESE 570 Spring 2019 – Khanna
Case 1: Vin Abruptly Rises - τPHL
57
V out= V DD− V T0n
τ PHL =Cload−1iDn
"
#$
%
&'
VDD
VDD−VT 0n∫ dVout +Cload−1iDn
"
#$
%
&'
VDD−VT 0n
VDD /2∫ dVout
t0#t1 t1#t50%
saturation linear
Penn ESE 570 Spring 2019 – Khanna
Case 1: Vin Abruptly Rises - τPHL
58
V out= V DD− V T0n
τ PHL =Cload−1iDn
"
#$
%
&'
VDD
VDD−VT 0n∫ dVout +Cload−1iDn
"
#$
%
&'
VDD−VT 0n
VDD /2∫ dVout
t0#t1 t1#t50%
saturation linear
saturation: iDn =kn2(Vin −VT 0n )
2
τ PHL,sat =Cload−1
kn2(VDD −VT 0n )
2
"
#
$$$
%
&
'''
VDD
VDD−VT 0n∫ dVout
τ PHL,sat =−Cload
kn2(VDD −VT 0n )
2dVoutVDD
VDD−VT 0n∫
τ PHL,sat =2CloadVT 0n
kn (VDD −VT 0n )2
Penn ESE 570 Spring 2019 – Khanna
Case 1: Vin Abruptly Rises - τPHL
59
V out= V DD− V T0n
τ PHL =Cload−1iDn
"
#$
%
&'
VDD
VDD−VT 0n∫ dVout +Cload−1iDn
"
#$
%
&'
VDD−VT 0n
VDD /2∫ dVout
t0#t1 t1#t50%
saturation linear
linear: iDn =kn2(Vin −VT 0n )Vout −V
2out( )
τ PHL,lin =Cload−1
kn22(VDD −VT 0n )Vout −V
2out( )
"
#
$$$
%
&
'''
VDD−VT 0n
VDD /2∫ dVout
τ PHL,lin =2Cload
kn
−12(VDD −VT 0n )Vout −V
2out( )
"
#$$
%
&''VDD−VT 0n
VDD /2∫ dVout
τ PHL,lin =2Cload
kn⋅
−12(VDD −VT 0n )
ln Vout2(VDD −VT 0n )−Vout( )
"
#$$
%
&''Vout=VDD−VT 0n
Vout=VDD /2
Penn ESE 570 Spring 2019 – Khanna
Case 1: Vin Abruptly Rises - τPHL
60
τ PHL,lin =2Cload
kn⋅
−12(VDD −VT 0n )
ln Vout2(VDD −VT 0n )−Vout( )
#
$%%
&
'((Vout=VDD−VT 0n
Vout=VDD /2
τ PHL,lin =Cload
kn (VDD −VT 0n )ln 2(VDD −VT 0n )−VDD 2
VDD 2#
$%
&
'(
Penn ESE 570 Spring 2019 – Khanna
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Case 1: Vin Abruptly Rises - τPHL
61
V out= V DD− V T0n
τ PHL =Cload−1iDn
"
#$
%
&'
VDD
VDD−VT 0n∫ dVout +Cload−1iDn
"
#$
%
&'
VDD−VT 0n
VDD /2∫ dVout
t0#t1 t1#t50%
saturation linear
τ PHL,sat =2CloadVT 0n
kn (VDD −VT 0n )2 τ PHL,lin =
Cload
kn (VDD −VT 0n )ln 2(VDD −VT 0n )−VDD 2
VDD 2"
#$
%
&'
τ PHL = 2CloadVT 0n
kn (VDD −VT 0n )2 +Cload
kn (VDD −VT 0n )ln 2(VDD −VT 0n )−VDD 2
VDD 2"
#$
%
&'
Penn ESE 570 Spring 2019 – Khanna
Case 1: Vin Abruptly Rises - τPHL
62
V out= V DD− V T0n
τ PHL =Cload−1iDn
"
#$
%
&'
VDD
VDD−VT 0n∫ dVout +Cload−1iDn
"
#$
%
&'
VDD−VT 0n
VDD /2∫ dVout
t0#t1 t1#t50%
saturation linear
τ PHL,sat =2CloadVT 0n
kn (VDD −VT 0n )2
τ PHL = 2CloadVT 0n
kn (VDD −VT 0n )2 +Cload
kn (VDD −VT 0n )ln 2(VDD −VT 0n )−VDD 2
VDD 2"
#$
%
&'
τ PHL,lin =Cload
kn (VDD −VT 0n )ln 2(VDD −VT 0n )−VDD 2
VDD 2"
#$
%
&'
τ PHL =Cload ⋅1
kn (VDD −VT 0n )2VT 0n
(VDD −VT 0n )+ ln 2(VDD −VT 0n )
VDD 2−1
#
$%
&
'(
)
*+
,
-.
Penn ESE 570 Spring 2019 – Khanna
Case 1: Vin Abruptly Rises - τPHL
63
V out= V DD− V T0n
τ PHL =Cload−1iDn
"
#$
%
&'
VDD
VDD−VT 0n∫ dVout +Cload−1iDn
"
#$
%
&'
VDD−VT 0n
VDD /2∫ dVout
t0#t1 t1#t50%
saturation linear
τ PHL,sat =2CloadVT 0n
kn (VDD −VT 0n )2
τ PHL = 2CloadVT 0n
kn (VDD −VT 0n )2 +Cload
kn (VDD −VT 0n )ln 2(VDD −VT 0n )−VDD 2
VDD 2"
#$
%
&'
τ PHL,lin =Cload
kn (VDD −VT 0n )ln 2(VDD −VT 0n )−VDD 2
VDD 2"
#$
%
&'
τ PHL =Cload ⋅1
kn (VDD −VT 0n )2VT 0n
(VDD −VT 0n )+ ln 2(VDD −VT 0n )
VDD 2−1
#
$%
&
'(
)
*+
,
-.
Rn
Penn ESE 570 Spring 2019 – Khanna
64
Recall from static CMOS Inverter:
(1) Vth → kR; (2) τPHL → kn; (3) kR & kn → kp DESIGN:
τ PHL =Cload ⋅1
kn (VDD −VT 0n )2VT 0n
(VDD −VT 0n )+ ln 2(VDD −VT 0n )
VDD 2−1
#
$%
&
'(
)
*+
,
-.
Vth =VT 0n +
1kR
VDD +VT 0 p( )
1+ 1kR
kR =VDD +VT 0 p −VthVth −VT 0n
"
#$
%
&'
2
Case 1: Vin Abruptly Rises - τPHL
Penn ESE 570 Spring 2019 – Khanna
65
Recall from static CMOS Inverter:
(1) Vth → kR; (2) τPHL → kn; (3) kR & kn → kp DESIGN:
τ PHL =Cload ⋅1
kn (VDD −VT 0n )2VT 0n
(VDD −VT 0n )+ ln 2(VDD −VT 0n )
VDD 2−1
#
$%
&
'(
)
*+
,
-.
Vth =VT 0n +
1kR
VDD +VT 0 p( )
1+ 1kR
kR =VDD +VT 0 p −VthVth −VT 0n
"
#$
%
&'
2
Case 1: Vin Abruptly Rises - τPHL
Penn ESE 570 Spring 2019 – Khanna
(1) Vth → kR; (2) τPLH → kp; (3) kR & kp → kn
66
τ PHL =Cload ⋅1
kn (VDD −VT 0n )2VT 0n
(VDD −VT 0n )+ ln 2(VDD −VT 0n )
VDD 2−1
#
$%
&
'(
)
*+
,
-.
Differential Model Approximation
τ PHL =Cload−1iDn
"
#$
%
&'
VDD
VDD−VT 0n∫ dVout +Cload−1iDn
"
#$
%
&'
VDD−VT 0n
VDD /2∫ dVout
t0#t1 t1#t50%
saturation linear
Approximate by assuming in saturation:
Penn ESE 570 Spring 2019 – Khanna
12
67 Δ is less than 10%
τ PHL =Cload ⋅1
kn (VDD −VT 0n )2VT 0n
(VDD −VT 0n )+ ln 2(VDD −VT 0n )
VDD 2−1
#
$%
&
'(
)
*+
,
-.
Differential Model Approximation
τ PHL =Cload−1iDn
"
#$
%
&'
VDD
VDD−VT 0n∫ dVout +Cload−1iDn
"
#$
%
&'
VDD−VT 0n
VDD /2∫ dVout
t0#t1 t1#t50%
saturation linear
τ PHL ≈ Cload−1iDn,sat
#
$%%
&
'((VDD
VDD /2∫ dVout =−Cload
kn2(VDD −VT 0n )
2
#
$
%%%
&
'
(((
VDD
VDD /2∫ dVout
τ PHL ≈CloadVDD
kn (VDD −VT 0n )2 ∝RnCload
Approximate by assuming in saturation:
Penn ESE 570 Spring 2019 – Khanna
68
Δ is less than 10%
τ PHL =Cload ⋅1
kn (VDD −VT 0n )2VT 0n
(VDD −VT 0n )+ ln 2(VDD −VT 0n )
VDD 2−1
#
$%
&
'(
)
*+
,
-.
Differential Model Approximation
τ PHL =Cload−1iDn
"
#$
%
&'
VDD
VDD−VT 0n∫ dVout +Cload−1iDn
"
#$
%
&'
VDD−VT 0n
VDD /2∫ dVout
t0#t1 t1#t50%
saturation linear
τ PHL ≈ Cload−1iDn,vsat
#
$%%
&
'((VDD
VDD /2∫ dVout
=−Cload
vsatCOXW VDD −VT 0n −Vdsat2
*
+,-
./
#
$
%%%%
&
'
((((
VDD
VDD /2∫ dVout
τ PHL ≈CloadVDD
2vsatCOXW VDD −VT 0n −Vdsat2
#
$%
&
'(∝RnCload
Approximate by assuming in velocity saturation:
Vdsat ≈Lvsatµn
Penn ESE 570 Spring 2019 – Khanna
Example 1:
! Consider a CMOS inverter with Cload=1pF and VDD=5V. The nMOS transistor has VT0n=1V and kn=625uA/V2.
! Assume Vin is an ideal step pulse with instant rise/fall times. Calculate the delay time necessary for the inverter output to fall from its initial value of 5V to 2.5V.
69 Penn ESE 570 Spring 2019 – Khanna
Example 1:
! Consider a CMOS inverter with Cload=1pF and VDD=5V. The nMOS transistor has VT0n=1V and kn=625uA/V2.
! Assume Vin is an ideal step pulse with instant rise/fall times. Calculate the delay time necessary for the inverter output to fall from its initial value of 5V to 2.5V.
70
τ PHL =Cload ⋅1
kn (VDD −VT 0n )2VT 0n
(VDD −VT 0n )+ ln 2(VDD −VT 0n )
VDD 2−1
#
$%
&
'(
)
*+
,
-.
Penn ESE 570 Spring 2019 – Khanna
Example 1:
! Consider a CMOS inverter with Cload=1pF and VDD=5V. The nMOS transistor has VT0n=1V and kn=625uA/V2.
! Assume Vin is an ideal step pulse with instant rise/fall times. Calculate the delay time necessary for the inverter output to fall from its initial value of 5V to 2.5V.
71
τ PHL =Cload ⋅1
kn (VDD −VT 0n )2VT 0n
(VDD −VT 0n )+ ln 2(VDD −VT 0n )
VDD 2−1
#
$%
&
'(
)
*+
,
-.
τ PHL =1×10−12 ⋅
1(625×10−6 )(5−1)
2(5−1)
+ ln 2(5−1)2.5
−1#
$%
&
'(
)
*+
,
-.
τ PHL = 0.52ns
Penn ESE 570 Spring 2019 – Khanna
Example 1:
72
τ PHL =Cload ⋅1
kn (VDD −VT 0n )2VT 0n
(VDD −VT 0n )+ ln 2(VDD −VT 0n )
VDD 2−1
#
$%
&
'(
)
*+
,
-.
τ PHL =1×10−12 ⋅
1(625×10−6 )(5−1)
2(5−1)
+ ln 2(5−1)2.5
−1#
$%
&
'(
)
*+
,
-.
τ PHL = 0.52ns
τ PHL ≈CloadVDD
kn (VDD −VT 0n )2 ∝RnCload
Approximate by assuming in saturation:
Penn ESE 570 Spring 2019 – Khanna
13
Example 1:
73
τ PHL =Cload ⋅1
kn (VDD −VT 0n )2VT 0n
(VDD −VT 0n )+ ln 2(VDD −VT 0n )
VDD 2−1
#
$%
&
'(
)
*+
,
-.
τ PHL =1×10−12 ⋅
1(625×10−6 )(5−1)
2(5−1)
+ ln 2(5−1)2.5
−1#
$%
&
'(
)
*+
,
-.
τ PHL = 0.52ns
τ PHL ≈CloadVDD
kn (VDD −VT 0n )2 ∝RnCload
τ PHL ≈1×10−12 (5)
625×10−6 (5−1)2= 0.5ns
Approximate by assuming in saturation:
Δ < 3%
Penn ESE 570 Spring 2019 – Khanna
Example 2:
! Consider a CMOS inverter with Cload=1pF and VDD=5V. The nMOS transistor has VT0n=1V, k’n=20uA/V2, and W/L=10.
! Use the average current method to calculate the fall time. Assume VOH=VDD, and VOL=0V.
74
Usefull equations:
τ fall ≈ CloadΔV90%−10%Iavg,90%−10%
=CloadV90% −V10%Iavg,90%−10%
ID,sat =k 'n2WLVGS −VT 0n( )2
ID,lin =k 'n2WL2 VGS −VT 0n( )VDS −V 2
DS( )
Penn ESE 570 Spring 2019 – Khanna
Example 2:
! Consider a CMOS inverter with Cload=1pF and VDD=5V. The nMOS transistor has VT0n=1V, k’n=20uA/V2, and W/L=10.
! Use the average current method to calculate the fall time. Assume VOH=VDD, and VOL=0V.
75
Iavg, fall =12ic (Vin =VOH ,Vout =V90%)+ ic (Vin =VOH ,Vout =V10%)[ ]
Iavg, fall =12ic (Vin = 5V,Vout = 4.5V )+ ic (Vin = 5V,Vout = 0.5V )[ ]
Iavg, fall =12k 'n2WLVin −VT 0n( )2 + k 'n
2WL2 Vin −VT 0n( )Vout −V 2
out( )"
#$%
&'
Iavg, fall =1220×10−6
2(10) 5−1( )2 + 20×10
−6
2(10) 2 5−1( )(0.5)− (0.5)2( )
"
#$
%
&'
Iavg, fall = 0.988mAPenn ESE 570 Spring 2019 – Khanna
Example 2:
! Consider a CMOS inverter with Cload=1pF and VDD=5V. The nMOS transistor has VT0n=1V, k’n=20uA/V2, and W/L=10.
! Use the average current method to calculate the fall time. Assume VOH=VDD, and VOL=0V.
76
Iavg, fall =12ic (Vin =VOH ,Vout =V90%)+ ic (Vin =VOH ,Vout =V10%)[ ]
Iavg, fall =12ic (Vin = 5V,Vout = 4.5V )+ ic (Vin = 5V,Vout = 0.5V )[ ]
Iavg, fall =12k 'n2WLVin −VT 0n( )2 + k 'n
2WL2 Vin −VT 0n( )Vout −V 2
out( )"
#$%
&'
Iavg, fall =1220×10−6
2(10) 5−1( )2 + 20×10
−6
2(10) 2 5−1( )(0.5)− (0.5)2( )
"
#$
%
&'
Iavg, fall = 0.988mAPenn ESE 570 Spring 2019 – Khanna
Example 2:
! Consider a CMOS inverter with Cload=1pF and VDD=5V. The nMOS transistor has VT0n=1V, k’n=20uA/V2, and W/L=10.
! Use the average current method to calculate the fall time. Assume VOH=VDD, and VOL=0V.
77
Iavg, fall = 0.988mA
τ fall ≈ CloadΔV90%−10%Iavg,90%−10%
=CloadV90% −V10%Iavg,90%−10%
τ fall ≈1×10−12 4.5− 0.50.988×10−3
= 4ns
Penn ESE 570 Spring 2019 – Khanna
Example 2:
! Consider a CMOS inverter with Cload=1pF and VDD=5V. The nMOS transistor has VT0n=1V, k’n=20uA/V2, and W/L=10.
! Use the differential equation method to calculate the fall time. Assume VOH=VDD, and VOL=0V.
78
Usefull equations:
iC =CloaddVoutdt
⇒ dt∫ =CloaddVoutiC
∫
Penn ESE 570 Spring 2019 – Khanna
id ,sat =12k 'nWLVGS −VT 0n( )
2
id ,lin =12k 'nWL2(VGS −VT 0n )VDS −V
2DS( )
14
Example 2:
! Consider a CMOS inverter with Cload=1pF and VDD=5V. The nMOS transistor has VT0n=1V, k’n=20uA/V2, and W/L=10.
! Use the differential equation method to calculate the fall time. Assume VOH=VDD, and VOL=0V.
79
iC =CloaddVoutdt
= −12k 'nWLVin −VT 0n( )
2
dt = −2Cload
k 'n W L( ) VDD −VT 0n( )2dVout
dt = − 2∗1×10−12
20×10−6 10( ) 5−1( )2dVout = −6.25×10
−10dVout
dtt=t90%
t=tsat
∫ = −6.25×10−10 dVoutVout=4.5
Vout=4.0
∫ = 0.313ns
Penn ESE 570 Spring 2019 – Khanna
Example 2:
! Consider a CMOS inverter with Cload=1pF and VDD=5V. The nMOS transistor has VT0n=1V, kn=20uA/V2, and W/L=10.
! Use the differential equation method to calculate the fall time. Assume VOH=VDD, and VOL=0V.
80
t90% → tsat = 0.313nsiC =Cload
dVoutdt
= −12k 'n
WL2(Vin −VT 0n )Vout −V
2out( )
dt = − 2Cload
k 'n W L( ) 2(VDD −VT 0n )Vout −V 2out( )
dVout
dtt=tsat
t=t10%
∫ = −2Cload
k 'n W L( )1
2(VDD −VT 0n )Vout −V2out( )
dVoutVout=4
Vout=0.5
∫
dtt=tsat
t=t10%
∫ =Cload
k 'n W L( )⋅
1Vin −VT 0n
ln 2(Vin −VT 0n )−V10%V10%
$
%&
'
()
dtt=tsat
t=t10%
∫ =1×10−12
20×10−6 10( )⋅15−1
ln 2(5−1)− 0.50.5
$
%&
'
()= 3.39ns
Example 2:
! Consider a CMOS inverter with Cload=1pF and VDD=5V. The nMOS transistor has VT0n=1V, kn=20uA/V2, and W/L=10.
! Use the differential equation method to calculate the fall time. Assume VOH=VDD, and VOL=0V.
81
t90% → tsat = 0.313nsiC =Cload
dVoutdt
= −12k 'n
WL2(Vin −VT 0n )Vout −V
2out( )
dt = − 2Cload
k 'n W L( ) 2(VDD −VT 0n )Vout −V 2out( )
dVout
dtt=tsat
t=t10%
∫ = −2Cload
k 'n W L( )1
2(VDD −VT 0n )Vout −V2out( )
dVoutVout=4
Vout=0.5
∫
dtt=tsat
t=t10%
∫ =Cload
k 'n W L( )⋅
1Vin −VT 0n
ln 2(Vin −VT 0n )−V10%V10%
$
%&
'
()
dtt=tsat
t=t10%
∫ =1×10−12
20×10−6 10( )⋅15−1
ln 2(5−1)− 0.50.5
$
%&
'
()= 3.39ns
t90% → t10% = 3.7ns
Avg method: 4ns
Case 2: Vin Abruptly Falls - τPLH
82
τ PLH =Cload1iDp
!
"##
$
%&&0
−VT 0 p∫ dVout +Cload1iDp
!
"##
$
%&&−VT 0 p
V50%∫ dVout
t0#t1 t1#t50%
saturation linear
Penn ESE 570 Spring 2019 – Khanna
τ PLH =Cload ⋅1
kp(VDD− |VT 0 p |)2 |VT 0 p |
(VDD− |VT 0 p |)+ ln
2(VDD− |VT 0 p |)VDD 2
−1#
$%
&
'(
)
*++
,
-..
Case 2: Vin Abruptly Falls - τPLH
83
τ PLH =Cload1iDp
!
"##
$
%&&0
−VT 0 p∫ dVout +Cload1iDp
!
"##
$
%&&−VT 0 p
V50%∫ dVout
t0#t1 t1#t50%
saturation linear
Penn ESE 570 Spring 2019 – Khanna
Rp
τ PLH ≈CloadVDD
kp(VDD− |VT 0 p |)2
τ PLH =Cload ⋅1
kp(VDD− |VT 0 p |)2 |VT 0 p |
(VDD− |VT 0 p |)+ ln
2(VDD− |VT 0 p |)VDD 2
−1#
$%
&
'(
)
*++
,
-..
RpCload
Differential Equation Model
84
CONDITIONS for Balanced CMOS Propagation Delays, i.e.
τ PLH =Cload ⋅1
kp(VDD− |VT 0 p |)2 |VT 0 p |
(VDD− |VT 0 p |)+ ln
2(VDD− |VT 0 p |)VDD 2
−1#
$%
&
'(
)
*++
,
-..
τ PHL =Cload ⋅1
kn (VDD −VT 0n )2VT 0n
(VDD −VT 0n )+ ln 2(VDD −VT 0n )
VDD 2−1
#
$%
&
'(
)
*+
,
-.
WL
!
"#
$
%&p
= µn
µp
WL
!
"#
$
%&n
#
Penn ESE 570 Spring 2019 – Khanna
15
Delay Observations
85
τ PLH =Cload ⋅1
kp(VDD− |VT 0 p |)2 |VT 0 p |
(VDD− |VT 0 p |)+ ln
2(VDD− |VT 0 p |)VDD 2
−1#
$%
&
'(
)
*++
,
-..
τ PHL =Cload ⋅1
kn (VDD −VT 0n )2VT 0n
(VDD −VT 0n )+ ln 2(VDD −VT 0n )
VDD 2−1
#
$%
&
'(
)
*+
,
-.
Penn ESE 570 Spring 2019 – Khanna
86
τ PLH =Cload ⋅1
kp(VDD− |VT 0 p |)2 |VT 0 p |
(VDD− |VT 0 p |)+ ln
2(VDD− |VT 0 p |)VDD 2
−1#
$%
&
'(
)
*++
,
-..
τ PHL =Cload ⋅1
kn (VDD −VT 0n )2VT 0n
(VDD −VT 0n )+ ln 2(VDD −VT 0n )
VDD 2−1
#
$%
&
'(
)
*+
,
-.
Delay Design Equations
Penn ESE 570 Spring 2019 – Khanna
87
Delay Design Equations w/ Saturation Approximation
τ PHL ≈CloadVDD
kn (VDD −VT 0n )2
τ PLH ≈CloadVDD
kp(VDD− |VT 0 p |)2
WL
!
"#
$
%&n
≈CloadVDD
τ PHLµnCox (VDD −VT 0n )2
WL
!
"#
$
%&p
≈CloadVDD
τ PLHµpCox (VDD− |VT 0 p |)2
Penn ESE 570 Spring 2019 – Khanna
Design for Delays with More Realistic Model for Cload
88
Cload Cdbn + Cdbp + Cint + Cgb i≈ i
i≈ iCload Cdbn(Wn) + Cdbp(Wp) + Cint + Cgb
Penn ESE 570 Spring 2019 – Khanna
89
Cdbn (Wn) = [Wn (Y + xj)] Cj0n Keqn + (Wn + 2Y) Cjswn Keqn(sw)
Cdbp (Wp) = [Wp (Y + xj)] Cj0p Keqp + (Wp + 2Y) Cjswp Keqp(sw)
Design for Delays with More Realistic Model for Cload
90
Cload = α0 + αnWn + αpWp
α0 = 2YCjswnKeqn + 2YCjswpKeqp + Cint + Cgb
αn = (Y + xj)Cj0nKeqn + CjswnKeqn
αp = (Y + xj)Cj0pKeqp + CjswpKeqp
Cdbn (Wn) = [Wn (Y + xj)] Cj0n Keqn + (Wn + 2Y) Cjswn Keqn(sw)
Cdbp (Wp) = [Wp (Y + xj)] Cj0p Keqp + (Wp + 2Y) Cjswp Keqp(sw)
Design for Delays with More Realistic Model for Cload
16
91
and
Design for Delays with More Realistic Model for Cload
τ PLH =Cload ⋅1
kp(VDD− |VT 0 p |)2 |VT 0 p |
(VDD− |VT 0 p |)+ ln
2(VDD− |VT 0 p |)VDD 2
−1#
$%
&
'(
)
*++
,
-..
τ PHL =Cload ⋅1
kn (VDD −VT 0n )2VT 0n
(VDD −VT 0n )+ ln 2(VDD −VT 0n )
VDD 2−1
#
$%
&
'(
)
*+
,
-.
τPHL = ΓnCload (Wn )Wn
τPLH = ΓpCload (Wp )Wp
Penn ESE 570 Spring 2019 – Khanna
92
and
Design for Delays with More Realistic Model for Cload
τ PLH =Cload ⋅1
kp(VDD− |VT 0 p |)2 |VT 0 p |
(VDD− |VT 0 p |)+ ln
2(VDD− |VT 0 p |)VDD 2
−1#
$%
&
'(
)
*++
,
-..
τ PHL =Cload ⋅1
kn (VDD −VT 0n )2VT 0n
(VDD −VT 0n )+ ln 2(VDD −VT 0n )
VDD 2−1
#
$%
&
'(
)
*+
,
-.
const.
Γn and ΓP are set largely by process parameters and VDD
Penn ESE 570 Spring 2019 – Khanna
τPHL = ΓnCload (Wn )Wn
τPLH = ΓpCload (Wp )Wp
Design for Delays with More Realistic Model for Cload
93 Penn ESE 570 Spring 2019 – Khanna
τPHL = ΓnCload (Wn )Wn
τPLH = ΓpCload (Wp )Wp
Design for Delays with More Realistic Model for Cload
94
Cload = α0 + αnWn + αpWp
Penn ESE 570 Spring 2019 – Khanna
τPHL = ΓnCload (Wn )Wn
τPLH = ΓpCload (Wp )Wp
Design for Delays with More Realistic Model for Cload
95
Cload = α0 + αnWn + αpWp Cload = α0 + αnWn + (αpWp/Wn)Wn Cload = α0 + [αn + αpR]Wn
Penn ESE 570 Spring 2019 – Khanna
where R = Wp/Wn = constant
τPHL = ΓnCload (Wn )Wn
τPLH = ΓpCload (Wp )Wp
Design for Delays with More Realistic Model for Cload
96
Cload = α0 + αnWn + αpWp Cload = α0 + αnWn + (αpWp/Wn)Wn Cload = α0 + [αn + αpR]Wn
where R = Wp/Wn = constant (Recall: when Lp=Ln) Vth = 1kR=µpWp
µnWn
Penn ESE 570 Spring 2019 – Khanna
τPHL = ΓnCload (Wn )Wn
τPLH = ΓpCload (Wp )Wp
17
Design for Delays with More Realistic Model for Cload
97
Cload = α0 + αnWn + αpWp Cload = α0 + αnWn + (αpWp/Wn)Wn Cload = α0 + [αn + αpR]Wn
Cload = α0 + αnWn + αpWp Cload = α0 + (αnWn/Wp)Wp + αpWp Cload = α0 + [αn/R + αp]Wp
where R = Wp/Wn = constant (Recall: when Lp=Ln) Vth = 1kR=µpWp
µnWn
Penn ESE 570 Spring 2019 – Khanna
τPHL = ΓnCload (Wn )Wn
τPLH = ΓpCload (Wp )Wp
Design for Delays with More Realistic Model for Cload
98
Cload = α0 + αnWn + αpWp Cload = α0 + αnWn + (αpWp/Wn)Wn Cload = α0 + [αn + αpR]Wn
Cload = α0 + αnWn + αpWp Cload = α0 + (αnWn/Wp)Wp + αpWp Cload = α0 + [αn/R + αp]Wp
where R = Wp/Wn = constant
α0 + [αn + αpR]Wn
Wn
τPHL = Γn τPLH = Γp
α0 + [αn/R + αp]Wp
Wp
(Recall: when Lp=Ln) Vth = 1kR=µpWp
µnWn
Penn ESE 570 Spring 2019 – Khanna
τPHL = ΓnCload (Wn )Wn
τPLH = ΓpCload (Wp )Wp
Design for Delays with More Realistic Model for Cload
99
where R (constant) = aspect ratio = Wp/Wn
α0 + [αn + αpR]Wn
Wn
τPHL = Γn τPLH = Γp
α0 + [αn/R + αp]Wp
Wp
Penn ESE 570 Spring 2019 – Khanna
Design for Delays with More Realistic Model for Cload
100
where R (constant) = aspect ratio = Wp/Wn
= limit τPHL = Γn [αn + αp R] Wn → large absolute
minimum delays = limit τPLH = Γp [αn/R + αp]
Wp → large
Hence increasing Wn and Wp will have diminishing influence on τPHL and τPLH as they become large, i.e.
α0 + [αn + αpR]Wn
Wn
τPHL = Γn τPLH = Γp
α0 + [αn/R + αp]Wp
Wp
τPHL
τPLH
Penn ESE 570 Spring 2019 – Khanna
101
Design for Delays with More Realistic Model for Cload
Penn ESE 570 Spring 2019 – Khanna 102
Design for Delays with More Realistic Model for Cload
Penn ESE 570 Spring 2019 – Khanna
18
Taking Into Account Non-Ideal Input Waveform
103
ideal Vin non-ideal Vin Vout to ideal Vin Vout to non-ideal Vin
Penn ESE 570 Spring 2019 – Khanna
MOS Inverter Dynamic Performance
! ANALYSIS (OR SIMULATION): For a given MOS inverter schematic and Cload, estimate (or measure) the propagation delays
! DESIGN: For given specs for the propagation delays and Cload*,
determine the MOS inverter schematic
104
METHODS: 1. Average Current Model
2. Differential Equation Model
3. 1st Order RC delay Model
Assume Vin ideal
τ PHL ≈ CloadΔVHLIavg,HL
=CloadVOH −V50%Iavg,HL
Penn ESE 570 Spring 2019 – Khanna
iC =CloaddVoutdt
⇒ dt∫ =CloaddVoutiC
∫dt ≈ τ PHL or τ PLH
τ PHL ≈ 0.69 ⋅Cload ⋅Rn
Idea
! Ptot = Pstatic + Pdyn+ Psc
" Can’t ignore Static Power (aka. Leakage power)
! Propogation Delay " Average Current Model " Differential Equation Model " 1st Order Model
" More next time…
105 Penn ESE 570 Spring 2019 – Khanna
Admin
! HW 5 out " Due 3/1
! Quiz next lecture Thursday 2/21 " First 15 minutes of class " Starts at 1:30pm exactly " Closed book " Covers lecture 1-9
106 Penn ESE 570 Spring 2019 – Khanna