Lecture Notes in Engineering Edited by С A. Brebbia and S. A. Orszag

66

M.A. Jabri

An Artificial Intelligence Approach to Integrated Circuit Floorplanning

Springer-Verlag Berlin Heidelberg New York London Paris Tokyo Hong Kong Barcelona Budapest

Contents

Acknowledgements iii

Preface iv

1 Overview 1

1.1 Introduction 1

1.2 Full Custom Design Approach 2

1.3 Structured Design 2

1.3.1 Separated Hierarchies 3

1.3.2 Interconnections and River Routing 4

1.3.3 Top-Down Approach 4

1.4 The Problem 4

1.5 This Volume 7

2 Integrated Circuit Floorplanning 9

2.1 Introduction 9

2.2 Top-Down Design Process 10

2.2.1 Process Description 10

2.2.2 Backtracking and Design Iteration 15

2.2.3 Top-Down Design Automation 16

2.3 Bottom-Up Design Process 20

2.3.1 Process Description 20

2.3.2 Bottom-Up Design Automation 21

2.4 Limitations of Algorithmic Floorplanning Approaches: Domain Knowledge 23

2.4.1 Non-Algorithmic Floorplanning Tasks 24

VI

2.4.2 Complexity Management 25

2.4.3 Pruning the Solution Space 25

2.4.4 Propagating "Bottom-up" Constraints 26

2.5 Knowledge-Based Space-Planning 26

2.5.1 Similarities between Building and Chip Floorplanning 26

2.5.2 AI in Automatic Space-Allocation 27

2.5.3 Differences Between Architectural and 1С Floorplanning 28

2.6 Limitations of a Purely KBS Approach 29

2.6.1 Algorithms and State Resolution 29

2.6.2 Knowledge Engineering Complexity 30

2.6.3 Computational Constraints 30

2.7 Discussion & Conclusion 30

3 P I A F : A Combined K B S / A l g o r i t h m i c Floorplanning S y s t e m 32

3.1 Introduction 32

3.2 The Combined KBS/Algorithmic Approach 32

3.3 The Floorplanning Strategy 33

3.3.1 Floorplanning Process Interfaces 34

3.3.2 Process Overview 34

3.4 The Communication Solving Process 35

3.4.1 Domain Knowledge in Communication Solving 36

3.5 Generation of Rectangular Topologies 37

3.6 Solution Selection 37

3.6.1 Domain Knowledge in Solution Marking 38

3.7 Communication Border Estimation 40

3.8 Block Dimension Calculation 41

3.9 Estimating Block Area Adjustment 41

3.10 Satisfying Block Area and Routing Adjustments 42

3.11 Prototype System Design 43

3.11.1 Design Considerations 43

3.11.2 The PIAF Modular Architecture 43

3.12 Conclusion 45

V I I

4 Implementat ion and Operation with a Case S tudy 51

4.1 Introduction 51

4.2 Design Issues for PIF 51

4.2.1 Multiple Representation Schemes 51

4.2.2 Context Adjustment 52

4.3 The Structure and Implementation of PIF 52

4.3.1 The Expertise of the Knowledge Engineer 52

4.3.2 Selecting a KBS Programming Language 53

4.3.3 Quality Factors 54

4.3.4 Knowledge Representation 55

4.3.5 The Inference Engine 59

4.3.6 Current Context Memory Structure 60

4.3.7 User Interface 63

4.3.8 Explanation System 64

4.4 The Input to PIAF 65

4.4.1 FBDs as Text Files 66

4.4.2 The FBD Graphic Editor 67

4.5 KBS Task Implementation 68

4.5.1 Communication Solving in PIF 68

4.5.2 Implementation of the Rectangular Solution Selection Process . . . . 72

4.5.3 Investigation of Minimal Block Dimensions 80

4.5.4 Final Area and Adjustment Tuning 82

4.6 Conclusion 86

4.7 Conclusion 87

5 The Algorithm Library 89

5.1 Introduction 89

5.2 Graph Clustering Algorithm 89

5.3 An Algorithm for Building RACGs 91

5.3.1 The Algorithm's Input 93

5.3.2 Exterior Representation 93

5.3.3 The Algorithm 94

V I I I

5.3.4 Algorithm Evaluation 99

5.3.5 Run Time Examples 100

5.4 Rectangular Dualisation of Graphs 100

5.5 Algorithms for Topological Information Extraction 103

5.5.1 Algorithm for Slice Generation 103

5.5.2 Finding the Surrounds 106

5.6 Optimisation 106

5.6.1 Determination of Block Dimensions 106

5.6.2 Satisfying Area Constraints 108

5.6.3 Satisfying Aspect-Ratio Constraints 108

5.7 Interface to Chip Assembly Tools 109

5.7.1 Join/Join-Top Composition Generation 109

5.7.2 Checking for Pinwheels I l l

5.8 Interface to the KBS I l l

5.9 Conclusion 112

6 Conclusion ' 113

6.1 Introduction 113

6.2 Overview of Achievements 113

6.2.1 The Combined Approach to 1С Floorplanning 113

6.2.2 PIAF Prototype 114

6.3 Direction for Future Work 115

6.3.1 A Critical Review 115

6.3.2 Important Tasks 115

6.4 Conclusion 116

A Pr imer on G r a p h s 117

A.l Introduction 117

A.2 Undirected Graphs 117

A.3 Palm Tree, Tree Arcs and Fronds 117

A.4 Paths 117

A.5 Faces 118

A.6 Connectivity 118

IX

A.7 Biconnectivity, Articulation Points 118

A.8 Planarity 118

A.9 Short-Cuts, Corner Implying Paths, Block Neighbourhood Graphs 118

A.10 Rectangular Duals of a Graph 119

В An F B D Example 121

С Rule Examples 131

C.l Some RACG Building Rules 131

C.2 Some Rectangular Topology Selection Rules 140

C.3 Examples of a Communication Border Evaluation Rule 142

Bibliography 145