Lecture ASIP 6
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Transcript of Lecture ASIP 6
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VLSI Architecture :: MEL G642
MEL G642
Dr. A. Amalin Prince
BITS Pilani K.K. Birla Goa Campus
Department of Electrical , Electronics and Instrumentation Engineering
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Memory addressing
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Memory addressing
Datapath, the addressing path and memory subsystemare separated and work in parallel
The memory should be accessed just before the datapathoperate on accessed data
The memory access to store the result should be
MEL G642
Latency or delay of address computing shall beminimized.
The separation of datapath and addressing path shouldnot introduce an excessive HW cost.
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Memory addressing modes
Addressing Algorithm Specification
Implied addressing Implicitly specified in the OP code
Memory direct A
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G642
singcircuitin
eral
Addresscalculation
logic circuit
gfeedb
ack
KeeperInitialaddress
Inputs
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ME
L
Memoryaddre
gen
Address pointer
Address
i
Registered
output
Combinational
output
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General addressing circuits
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General addressing circuits
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Modulo addressing of FIFO buffer
Implicitly using post ++ or -- addressing
Implicitly checking / assigning of FIFO bottom and top
registers Implicitly checking that the address pointer isbottom
< address pointer < top
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Hardware Accelerated Memory Addressing
Specification of implied addressing for convolution:1. Coefficient memory supplying coefficients without modulo addressing.
2. Data memory supplying data within a FIFO. The FIFO has:
1. BTMR to avoid underflow of the FIFO addressing.
2. TOPR to avoid overflow of the FIFO addressing.
3. DAR, data address pointer, pointing to data within the FIFO.
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. os ncremen ecremen a ress ng w en:
1. reaching the top of the FIFO, jump to the bottom of the FIFO.
2. reaching the bottom of the FIFO, jump to the top of the FIFO.
4. Two memories supply data and coefficient simultaneously.
5. All address operations should be executed in parallel with the dataprocessing.
6. Data and coefficients must be available before computing.
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Modulo++ addressing circuit
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Modulo addressing circuit
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RF fundamentals
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General register file
A general register file (RF) consists of a group of registers used as the first level of computing storagebuffers.
A physical data memory (with a single read/write port)can access one data at a time, read and write cannot beexecuted simultaneousl .
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A register file supports simultaneous reads and writes inone clock cycle, unlimited number of operands can besupplied by a RF at the same time.
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General register file
The RF gets data from data memories by running loadinstructions while preparing for an execution of asubroutine.
While running a subroutine, the register file is used ascomputing buffers.
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,
stored into data memories by running store instructions.
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Register file
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G642
sterfile
Write circuitRead circuit
reg_select
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MEL
RF:reg
Store circuit
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Physical design: Gate count problem
The gate count of RF will be more than a simple MAC
Consider a register file with 32 registers of 16-bit
contains 3216 = 512 flip-flops.o The gate count of512 flip-flops is about 5.12k gates.
o The gate count for all 3216b keepers is 3216 6 = 3.1kgates.
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The gate count for operand selection including OPA and OPB is216 (32+16+8+4+2+1)=2.1kgates.
The gate count of the data selection control is at least 16
(8+4+2+1) = 0.24kgates.
the total gate count of the register file without driving buffers is
about 10.6kgates.
Including extra driving buffers, the gate count of this register file
will be around 15k.
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Physical design: fan-in fan-out problem
The fan-out of the operand selection control pin from CP
to RF is very high.
Consider a register file with 32 registers of 16-bit Fan-out of512 is very heavy,
o this is a typical hidden critical path between control path and
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atapat .
o It might not be recognized until reaching the logic synthesis of the
RTL codes because the critical path cannot be identified from the
datapath schematic.
It is a typical mistake of an inexperienced design team.
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Physical design: fan-in fan-out problem
Fan-out of the control signal
For the first stage: 16*16*2 = 512
Fan-out of the control signal
For the second stage: 16*8*2 = 256
From 32 registers in a register file
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an-out o t e contro s gna
For the third stage: 16*4*2 = 128
Fan-out of the control signal
For the fourth stage: 16*2*2 = 64
Fan-out of the control signal
For the fivth stage: 16*1*2 = 32
Selected operand
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How to manage critical path
Pipeline around register file includes the pipeline of
result store (toward RF) and the pipeline of operand fetch
(from RF). RF>>memory?
o An operand might be data to be stored to a data memory.
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o a a memory m g e a oca e ar away rom e reg s er e.
RF
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Special registers in general register file
Registers in a RF can be either general registers or
special registers.
Special registers could be allocated inside a general register file.o In case a register is a general register carrying special register
functions, extra logic circuits will be added around the register.
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ALU computing.
o For example, if a register in the register file is both a general
register and an address pointer, addressing logic will be added
around this register. (figure in next slide)
A register file consisting of general and special registers is called
a multiple-function RF.
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Special registers in general register file
A general register in a register file
A special register in a register file
Specific
function
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Register input
Register output
Register input
Register output
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G642
ngene
ralregister
e
Address
calculation
logic for aspecial register
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MEL
Specialregisters
i
fi
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Special function registers are in RF?
Not all special registers can be integrated inside the
general register file.
For example, special registers of peripheral devices usually areallocated in peripheral modules.
Loop counter and stack registers usually are allocated in the
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.
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Special function registers are in RF?
If a special register is not integrated in the general
register file, it cannot be used as an operand supplying
data directly to ALU. In this case, the data process for a special register is:
1) Move the data in a special register to a general register.
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rocess e a a an s ore n e genera reg s er.
3) Move the result stored in the general register to the special
register.
Three clock cycles are needed for one data manipulation in this
case. Decision is based on the data in a special register is needed very
frequently or not.
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RF multiple data write
double-precision data from the MAC accumulator
register
Swap instruction
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The End :: Thank you for your attention
Questions?
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