Gates and Logic: From switches to Transistors , Logic Gates and Logic Circuits
Lecture A: Logic Design and Gates - 1680x1050.com · Lecture A: Logic Design and Gates ... Lab...
50
Lecture A: Logic Design and Gates • Syllabus – My office hours 9.15-10.35am T,Th or [email protected] 333G WERC – Text: Brown and Vranesic “Fundamentals of Digital Logic,” » Buy it.. Or borrow it » Other book: Katz – I have one copy – Grading » Three Hour exams: H1-20%, H2-20%, H3-25% » Lab 20%, Homework 10%, Pop quizzes 5% – No Cheating » Cheaters will not be tolerated • Class STARTS AT 8am – I will NOT repeat lectures or material covered during lecture • Help Desk Hours/Sessions will be announced • Reading Announcements – Get hold of the Reading List – Stay ahead – Pull together some questions – Review what you’ve read after the lecture • Lab Starts NEXT WEEK
Transcript of Lecture A: Logic Design and Gates - 1680x1050.com · Lecture A: Logic Design and Gates ... Lab...
Lectu
re A
: L
og
ic D
esig
n a
nd
Gate
s
•S
yll
ab
us
–M
y o
ffic
e h
ou
rs 9
.15-1
0.3
5am
T,T
ho
r g
ch
oi@
ece.t
am
u.e
du
333G
WE
RC
–T
ext:
Bro
wn
an
d V
ran
esic
“F
un
dam
en
tals
of
Dig
ital L
og
ic,”
»B
uy i
t.. O
r b
orr
ow
it
»O
ther
bo
ok:
Katz
–I h
ave o
ne c
op
y–
Gra
din
g»
Th
ree H
ou
r exam
s:
H1-2
0%
, H
2-2
0%
, H
3-2
5%
»L
ab
20
%,
Ho
mew
ork
10
%,
Po
p q
uiz
zes 5
%–
No
Ch
eati
ng
»C
heate
rs w
ill n
ot
be t
ole
rate
d
•C
lass S
TA
RT
S A
T 8
am
–I w
ill N
OT
rep
eat
lectu
res o
r m
ate
rial co
vere
d d
uri
ng
lectu
re
•H
elp
Desk H
ou
rs/S
essio
ns w
ill b
e a
nn
ou
nced
•
Read
ing
An
no
un
cem
en
ts–
Get
ho
ld o
f th
e R
ead
ing
Lis
t–
Sta
y a
head
–P
ull t
og
eth
er
so
me q
uesti
on
s–
Revie
w w
hat
yo
u’v
e r
ead
aft
er
the lectu
re
•L
ab
Sta
rts N
EX
T W
EE
K
Co
urs
e O
utl
ine 2
007
•W
eek 1
Lo
gic
Ga
tes
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--•
Week 2
TT
L 2
Bo
ole
an A
lge
bra
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--•
Week 3
Syste
m
K-M
ap
s
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--
•W
eek 4
Bou
nce
Mu
lti-
level C
ircu
its
•--
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--
•W
eek 5
Add
ers
M
ulti-
leve
l C
ircu
its
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•W
eek 6
Shift-
Add
A
dd
ers
•--
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--
•F
IRS
T E
XA
M,
Fe
bru
ary
22
in
cla
ss
•W
eek 7
Boa
rd C
lock 5
Mu
ltip
liers
•--
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--•
Week 8
Mu
ltip
lier
6 M
ultip
lexe
rs,
Deco
de
rs, e
tc.
•--
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--
•W
eek 9
8 P
rio
rity
En
co
de
r 8
Syn
ch
rono
us S
equ
ential C
kts
•S
EC
ON
D E
XA
M,
Ma
rch
23
, in
cla
ss
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--•
Week 1
0 T
-Bir
d 8
Syn
ch
rono
us S
equ
ential C
kts
.
•T
ail
Lig
hts
•W
eek 1
1 S
ynch
ron
ous S
eq
uen
tial C
kts
.•
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•W
eek 1
2 L
ED
7 F
lip-f
lop
s
Pin
g-p
ong
•W
eek 1
3 C
ou
nte
rs
•W
eek 1
4 N
MO
S a
nd
CM
OS
Lo
gic
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--•
--T
HIR
D E
XA
M,
Ap
ril
26
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Read
ing
Lis
t•
Chap
ter
1 R
ead
on
lyH
igh
-le
ve
l in
trodu
ction
•C
hap
ter
2
•2
.1 –
2.7
Rea
d a
nd
Stu
dy
Fu
nd
am
en
tals
of
Co
mb
ina
tio
na
l L
og
ic D
es
ign
•2
.8 –
2.9
Read
on
lyC
AD
To
ols
and
VH
DL
•C
hap
ter
4
•4
.1 –
4.8
Rea
d a
nd
Stu
dy
Ka
rna
ug
hM
ap
s a
nd
Mu
lti-
leve
l lo
gic
cir
cu
its
•4
.9 –
4.1
2 R
ead
on
lyC
ub
es a
nd
CA
D to
ols
•C
hap
ter
5
•5
.1 –
5.4
Rea
d a
nd
Stu
dy
Lo
gic
cir
cu
its
fo
r a
dd
itio
n
•5
.5 R
ead
on
lyC
AD
Too
ls
•5
.6 –
5.8
Rea
d a
nd
Stu
dy
Mu
ltip
lic
ati
on
an
d o
the
r d
ata
re
pre
se
nta
tio
ns
•C
hap
ter
6
•6
.1 –
6.5
Rea
d a
nd
Stu
dy
MS
I le
ve
l lo
gic
pri
mit
ive
s•
6.6
Read
on
lyV
HD
L lang
uage
•C
hap
ter
8
•8
.1 –
8.3
Rea
d a
nd
Stu
dy
Ba
sic
Syn
ch
ron
ou
s S
eq
ue
nti
al
Cir
cu
it D
es
ign
•8
.4 R
ead
on
lyC
AD
tools
•8
.5.1
–8
.5.2
Re
ad
an
d S
tud
yM
ea
ly a
nd
Mo
ore
Seri
al
Ad
de
rs
•8
.5.3
–8
.6 R
ead
on
lyV
HD
L a
nd
sta
te m
inim
iza
tio
n
•8
.7 –
8.9
Rea
d a
nd
Stu
dy
De
sig
n E
xam
ple
s a
nd
An
aly
sis
Me
tho
ds
•8
.10
–8
.11
Rea
d o
nly
Alg
orith
mic
Sta
te M
ach
ine
s
•C
hap
ter
7
•7
.1 –
7.1
1 R
ea
d a
nd
Stu
dy
La
tch
es
, F
lip
-flo
ps
, R
eg
iste
rs,
an
d C
ou
nte
rs
•7
.12
–7
.14
Rea
d o
nly
CA
D t
oo
ls a
nd
VH
DL
•C
hap
ter
3
•3
.1 –
3.3
Rea
d a
nd
Stu
dy
NM
OS
an
d C
MO
S t
ran
sis
tor
sw
itc
hes
•3
.4 –
3.8
Read
on
lyIm
ple
me
nta
tion
de
tails
•3
.9 R
ea
d a
nd
Stu
dy
Tra
ns
mis
sio
n g
ate
s
•3
.10
Read
on
lyIm
ple
me
nta
tion
de
tails
Befo
re W
e B
eg
in..
•N
um
ber
Sys
tem
an
d L
og
ic–
Recall w
hen
yo
u w
ere
a k
id (
were
yo
u?
)
»L
earn
ing
ho
w t
o c
ou
nt
»T
ree
»T
ree R
easo
nin
g
»T
hin
kin
g lo
gic
all
y <
om
it u
ncert
ain
titi
es>
•L
og
ic D
esig
n–
As
str
aig
ht
forw
ard
as i
t g
ets
–F
or
sim
ple
min
ds
–W
hen
do
ne w
ith
th
is c
lass,
yo
u’l
l m
as
ter
90
% d
esig
n m
eth
od
olo
gie
s
•A
dvan
ced
Desig
n Issu
es
–C
AD
–S
pecif
ica
tio
n
–V
eri
fica
tio
n
–T
esti
ng
–F
ab
rica
tio
n
–M
ark
eti
ng
We w
ill le
arn
in
EL
EN
248 …
Lo
gic
Ga
tes
an
d B
oo
lea
n A
lge
bra
Co
mb
ina
tio
na
l L
og
ic
Ari
thm
eti
c C
irc
uit
s a
nd
Co
mm
on
MS
I L
og
ic
Cir
cu
its
Syn
ch
ron
ou
s S
eq
ue
nti
al
Cir
cu
it D
es
ign
La
tch
es
, F
lip
-flo
ps
, R
eg
iste
rs,
an
d C
ou
nte
rs
NM
OS
an
d C
MO
S-B
as
ed
Lo
gic
Ga
tes
Co
mp
ute
r O
rga
niz
ati
on
Wh
at
is lo
gic
desig
n?
•D
esig
n issu
es
–G
iven
a s
pecif
icati
on
, d
eri
ve
a s
olu
tio
n u
sin
g a
vail
ab
le c
om
po
nen
ts
–W
hil
e m
eeti
ng
cri
teri
a f
or
siz
e,
co
st,
po
wer,
beau
ty,
ele
gan
ce,
etc
.
•W
hat
is lo
gic
desig
n?
–C
ho
ose d
igit
al
log
ic c
om
po
nen
ts t
o p
erf
orm
sp
ecif
ied
co
ntr
ol, d
ata
m
an
ipu
lati
on
, o
r co
mm
un
icati
on
fu
ncti
on
an
d t
heir
in
terc
on
necti
on
–W
hic
h lo
gic
co
mp
on
en
ts t
o c
ho
ose?
Man
y i
mp
lem
en
tati
on
tech
no
log
ies (
fixed
-fu
ncti
on
co
mp
on
en
ts,
pro
gra
mm
ab
le d
evic
es,
ind
ivid
ual
tran
sis
tors
on
a c
hip
, etc
.)
–D
esig
n o
pti
miz
ed
/tra
nsfo
rmed
to
meet
desig
n c
on
str
ain
ts
close switch (if A is “1” or asserted)
and turn on light bulb (Z)
AZ
open switch (if A is “0” or unasserted)
and turn off light bulb (Z)
Sw
itch
es:
basic
ele
men
t o
f p
hysic
al
log
ic im
ple
men
tati
on
s
•Im
ple
men
tin
g a
sim
ple
cir
cu
it (
arr
ow
sh
ow
s a
cti
on
if
wir
e c
han
ges t
o “
1”):
Z
≡A
AZ
AND
OR
Z ≡
A andB
Z ≡
A orB
AB
A
B
Co
mp
uti
ng
wit
h S
wit
ch
es
•C
om
po
se s
wit
ch
es in
to m
ore
co
mp
lex (B
oo
lean
) fu
ncti
on
s:
Tw
o f
un
dam
en
tal
str
uctu
res:
seri
es (
AN
D)
an
d p
ara
llel
(OR
)
inputs
outputs
system
Co
mb
inati
on
al
vs. seq
uen
tial d
igit
al
cir
cu
its
•S
imp
le m
od
el
of
a d
igit
al
syste
m i
s a
un
it w
ith
in
pu
ts a
nd
ou
tpu
ts:
•C
om
bin
ati
on
al
mean
s "
mem
ory
-les
s"
–d
igit
al cir
cu
it is c
om
bin
ati
on
al
if i
ts o
utp
ut
valu
es
on
ly d
ep
en
d o
n i
ts in
pu
ts
easy to implement
with CMOS transistors
(the switches we have
available and use most)
Co
mb
inati
on
al lo
gic
sym
bo
ls
•C
om
mo
n c
om
bin
ati
on
al lo
gic
syste
ms h
ave
sta
nd
ard
sym
bo
ls c
alled
lo
gic
gate
s
–B
uff
er,
NO
T
–A
ND
, N
AN
D
–O
R,
NO
RZ
A BZ Z
A A B
Seq
uen
tial lo
gic
•S
eq
uen
tial s
yste
ms
–E
xh
ibit
beh
avio
rs (
ou
tpu
t va
lues)
that
dep
en
d
on
cu
rren
t as w
ell
as
pre
vio
us i
np
uts
•A
ll r
eal
cir
cu
its a
re s
eq
uen
tial
–O
utp
uts
do
no
t ch
an
ge in
sta
nta
neo
usly
aft
er
an
in
pu
t ch
an
ge
–W
hy n
ot,
an
d w
hy i
s i
t th
en
seq
uen
tial?
•F
un
dam
en
tal
ab
str
acti
on
of
dig
ital d
esig
n is t
o r
easo
n
(mo
stl
y)
ab
ou
t ste
ad
y-s
tate
beh
avio
rs–
Exam
ine o
utp
uts
on
ly a
fter
su
ffic
ien
t ti
me h
as e
lap
sed
fo
r th
e
syste
m t
o m
ake i
ts r
eq
uir
ed
ch
an
ges a
nd
sett
le d
ow
n
Syn
ch
ron
ou
s s
eq
uen
tial d
igit
al
syste
ms
•C
om
bin
ati
on
al
cir
cu
it o
utp
uts
dep
en
d o
nly
on
cu
rren
t in
pu
ts–
Aft
er
su
ffic
ien
t ti
me h
as e
lap
sed
•S
eq
uen
tial cir
cu
its h
ave m
em
ory
–E
ven
aft
er
wait
ing
fo
r tr
an
sie
nt
acti
vit
y t
o f
inis
h
•S
tead
y-s
tate
ab
str
acti
on
: m
ost
desig
ners
use i
t w
hen
co
nstr
ucti
ng
seq
uen
tial cir
cu
its:
–M
em
ory
of
syste
m i
s i
ts s
tate
–C
han
ges i
n s
yste
m s
tate
on
ly a
llo
wed
at
sp
ecif
ic t
imes
co
ntr
oll
ed
by a
n e
xte
rnal
peri
od
ic s
ign
al
(th
e c
lock)
–C
lock p
eri
od
is e
lap
sed
tim
e b
etw
een
sta
te c
han
ges
su
ffic
ien
tly l
on
g s
o t
hat
sys
tem
rea
ch
es s
tead
y-s
tate
befo
re
next
sta
te c
ha
ng
e a
t en
d o
f p
eri
od
Wh
at
makes D
igit
al S
yste
ms t
ick?
Co
mb
ina
tio
nal
Lo
gic
tim
e
clk
Le
t’s
go
ba
ck
an
d R
em
em
be
r th
e n
um
be
r s
ys
tem
s..
•B
inary
vari
ab
les ju
st
like o
ther
vari
ab
les w
e k
no
w
of…
uh
.. It’
s t
he s
am
e!
–B
inary
vari
ab
les a
re a
“cla
ss” o
f g
en
era
l va
riab
les
–E
xam
ple
: A
po
inte
r o
r co
nta
iner
of
field
•O
pera
tio
ns?
E
xp
ressio
ns o
f o
pera
tio
ns?
–A
rith
meti
c o
pera
tio
ns
»X
= y
+ 1
y =
1x =
10
etc
–L
og
ical/
Bin
ary
/Bo
ole
an
op
era
tio
ns
X =
Y +
1+
..is
“O
R”
x..is
“A
ND
”
Y =
1X
= Y
1 =
1 +
..u
h
XY
Z0
00
01
01
00
11
1
XY
01
10
XY
Z0
00
01
11
01
11
1
XY
X XY Y
Z Z
Bo
ole
an
ex
pre
ss
ion
s a
nd
lo
gic
ga
tes
•N
OT
X'
X~
X S
ym
bo
l T
ruth
Tab
le
•A
ND
X •
YX
YX
+Y
•O
RX
+ Y
X +
Y
X YZ
XY
Z0
01
01
11
01
11
0
XY
Z0
01
01
01
00
11
0
ZX Y X Y
Z
XY
Z0
01
01
01
00
11
1
XY
Z0
00
01
11
01
11
0
ZX Y
X xorY = X Y' + X' Y
X or Y but not both
("inequality", "difference")
X xnorY = X Y + X' Y'
X and Y are the same
("equality", "coincidence")
Bo
ole
an
exp
ressio
ns a
nd
lo
gic
gate
s
•N
AN
D
•N
OR
•X
OR
X ⊕
⊕
⊕
⊕
Y
•X
NO
RX
= Y
T1T2
use of 3-input gate
A B C DT2
T1
ZA B C D
Z
Bo
ole
an
exp
ressio
ns a
nd
lo
gic
gate
s
•M
ore
th
an
on
e w
ay t
o m
ap
exp
ressio
ns t
o g
ate
s
–e.g
., Z
= A
' •
B' •
(C +
D)
= (
A' •
(B' •
(C +
D))
)
Desig
n R
ep
resen
tati
on
Tru
th T
able
Bo
ole
anE
xpre
ssio
n
gat
ere
pre
sen
tati
on
(sc
hem
atic
)
??
uniq
ue
not
uniq
ue
not
uniq
ue
[conven
ient fo
r m
anip
ula
tion]
[clo
se to
imple
men
tato
n]
Fo
r a g
ive
n f
un
cti
on
, th
ere
is O
NE
un
iqu
e t
ruth
tab
le. H
ow
ever,
th
ere
m
ay b
e m
ore
th
an
on
e b
oo
lean
exp
ressio
n o
r th
e g
ate
desig
n
XY
X nandY
00
1
11
0
XY
X nor Y
00
1
11
0
X n
and
Y≡
not
( (
not
X)
nor
(not
Y)
)
X n
or
Y≡
not
( (n
ot
X)
na
nd
(not
Y)
)
Min
imal set
of
fun
cti
on
s
•Im
ple
men
t an
y l
og
ic f
un
cti
on
s f
rom
NO
T, N
OR
, an
d
NA
ND
?
–F
or
exam
ple
, im
ple
men
tin
g
X
an
dY
is t
he s
am
e a
s i
mp
lem
en
tin
g
no
t(X
nan
dY
)
•D
o i
t w
ith
on
ly N
OR
or
on
ly N
AN
D
–N
OT
is ju
st
a N
AN
D o
r a N
OR
wit
h b
oth
in
pu
ts t
ied
to
geth
er
–an
d N
AN
D a
nd
NO
R a
re "
du
als
", i.e
., e
asy t
o i
mp
lem
en
t o
ne u
sin
g
the o
ther
•B
ased
on
th
e m
ath
em
ati
cal fo
un
dati
on
s o
f lo
gic
: B
oo
lean
Alg
eb
ra
An
alg
eb
raic
str
uctu
re
•A
n a
lge
bra
ic s
tru
ctu
re c
on
sis
ts o
f–
a s
et
of
ele
men
ts B
–b
inary
op
era
tio
ns {
+ , •
}
–an
d a
un
ary
op
era
tio
n {
' }
–su
ch
th
at
the f
ollo
win
g a
xio
ms h
old
:
1. set
B c
on
tain
s a
t le
ast
two
ele
men
ts, a, b
, su
ch
th
at
a ≠ ≠≠≠
b2. clo
su
re:
a +
b is in
Ba •
b is in
B3. co
mm
uta
tivit
y:
a +
b =
b +
aa •
b =
b •
a4. asso
cia
tivit
y:
a +
(b
+ c
) =
(a +
b)
+ c
a •
(b
• c
) =
(a •
b)
• c
5. id
en
tity
:a +
0 =
aa •
1 =
a6. d
istr
ibu
tivit
y:
a +
(b
• c
) =
(a +
b)
• (a
+ c
) a •
(b
+ c
) =
(a •
b)
+ (
a •
c)
7. co
mp
lem
en
tari
ty:
a +
a' =
1a •
a' =
0
Bo
ole
an
alg
eb
ra
•B
oo
lean
alg
eb
ra–
B =
{0,
1}
–+
is lo
gic
al
OR
, •
is lo
gic
al A
ND
–' is
lo
gic
al
NO
T
•A
ll a
lgeb
raic
axio
ms h
old
X, Y are Boolean algebra variables
XY
X •Y
00
00
10
10
01
11
XY
X'
Y'
X •Y
X' •Y'( X •Y ) + ( X' •Y' )
00
11
01
10
11
00
00
10
01
00
01
10
01
01
( X •Y ) + ( X' •Y' ) ≡
X =Y
XY
X'
X' • Y
00
10
01
11
10
00
11
00
Boolean expression that is
true when the variables X
and Y have the same value
and false, otherwise
Lo
gic
fu
nc
tio
ns
an
d B
oo
lea
n a
lge
bra
•A
ny l
og
ic f
un
cti
on
th
at
can
be e
xp
ress
ed
as a
tr
uth
tab
le c
an
be w
ritt
en
as a
n e
xp
ressio
n in
B
oo
lean
alg
eb
ra u
sin
g t
he o
pera
tors
: ', +
, an
d •
XY
16 possible functions (F0–F15)
00
00
00
00
00
11
11
11
11
01
00
00
11
11
00
00
11
11
10
00
11
00
11
00
11
00
11
11
01
01
01
01
01
01
01
01
X YF
XY
X norY
not(X orY)
X nandY
not(X andY)
10
notX
X andY
X orY
notY
X xorY
X =
Y
Po
ssib
le lo
gic
fu
ncti
on
s o
f tw
o v
ari
ab
les
•16 p
ossib
le f
un
cti
on
s o
f 2 in
pu
t vari
ab
les:
–2**
(2**
n)
fun
cti
on
s o
f n
in
pu
ts
Axio
ms &
th
eo
rem
s o
f B
oo
lean
alg
eb
ra
•Id
en
tity
1. X
+ 0
= X
1D
. X
• 1
= X
•N
ull 2. X
+ 1
= 1
2D
. X
• 0
= 0
•Id
em
po
ten
cy:
3. X
+ X
= X
3D
. X
• X
= X
•In
vo
luti
on
:4. (X
')' =
X
•C
om
ple
me
nta
rity
:5. X
+ X
' =
15D
. X
• X
' =
0
•C
om
mu
tati
vit
y:
6. X
+ Y
= Y
+ X
6D
. X
• Y
= Y
• X
•A
sso
cia
tivit
y:
7. (X
+ Y
) +
Z =
X +
(Y
+ Z
)7D
. (X
• Y
) •
Z =
X •
(Y
• Z
)
Axio
ms a
nd
th
eo
rem
s o
f B
oo
lean
alg
eb
ra
(co
nt’
d)
•D
istr
ibu
tivit
y:
8. X
• (
Y +
Z)
= (
X •
Y)
+ (
X •
Z)
8D
. X
+ (
Y •
Z)
= (
X +
Y)
• (X
+ Z
)
•U
nit
ing
:9. X
• Y
+ X
• Y
' =
X9D
. (X
+ Y
) •
(X +
Y')
= X
•A
bso
rpti
on
:10. X
+ X
• Y
= X
10D
. X
• (
X +
Y)
= X
11. (X
+ Y
') •
Y =
X •
Y11D
. (
X •
Y')
+ Y
= X
+ Y
•F
acto
rin
g:
12. (X
+ Y
) •
(X' +
Z)
=12D
. X
• Y
+ X
' •
Z =
X
• Z
+ X
' •
Y(X
+ Z
) •
(X' +
Y)
•C
on
cen
su
s:
13. (X
• Y
) +
(Y
• Z
) +
(X
' •
Z)
=
13D
. (X
+ Y
) •
(Y +
Z)
• (X
' +
Z)
=X
• Y
+ X
' •
Z(X
+ Y
) •
(X' +
Z)
Axio
ms a
nd
th
eo
rem
s o
f B
oo
lean
alg
eb
ra
(co
nt’
)
•d
e M
org
an
's:
14. (X
+ Y
+ ...)'
= X
' •
Y' •
...
14D
. (X
• Y
• ...)'
= X
' +
Y'
+ ...
•g
en
era
lized
de M
org
an
's:
15. f'
(X1,X
2,...,X
n,0
,1,+
,•)
= f(
X1',X
2',...,X
n',1,0
,•,+
)
•esta
bli
sh
es r
ela
tio
nsh
ip b
etw
een
• a
nd
+
Axio
ms &
th
eo
rem
s o
f B
oo
l. A
lg. -
Du
ality
•D
uali
ty–
Du
al
of
a B
oo
lean
exp
res
sio
n i
s d
eri
ved
by r
ep
lacin
g •
by +
, +
by •
, 0 b
y 1
, an
d 1
by 0
, an
d l
ea
vin
g v
ari
ab
les u
nch
an
ged
–A
ny t
heo
rem
th
at
can
be p
roven
is t
hu
s a
lso
pro
ven
fo
r it
s d
ual!
–M
eta
-th
eo
rem
(a t
heo
rem
ab
ou
t th
eo
rem
s)
•d
uality
:16. X
+ Y
+ ... ⇔ ⇔⇔⇔
X •
Y •
...
•g
en
era
lized
du
ality
:17. f
(X1,X
2,...,X
n,0
,1,+
,•)
⇔ ⇔⇔⇔f(
X1,X
2,...,X
n,1
,0,•
,+)
•D
iffe
ren
t th
an
deM
org
an
’sL
aw
–th
is i
s a
sta
tem
en
t ab
ou
t th
eo
rem
s
–th
is i
s n
ot
a w
ay t
o m
an
ipu
late
(re
-wri
te)
exp
res
sio
ns
Pro
vin
g t
heo
rem
s (
rew
riti
ng
)
•U
sin
g t
he a
xio
ms o
f B
oo
lean
alg
eb
ra:
–e.g
., p
rove t
he
th
eo
rem
: X
• Y
+ X
• Y
' =
X
–e.g
., p
rove t
he
th
eo
rem
: X
+ X
• Y
=
X
distributivity(8)
X •Y + X •Y'
= X • (Y + Y')
complementarity(5)
X • (Y + Y')
= X •(1)
identity (1D)
X •(1)
= X �
identity (1D)
X + X • Y
= X • 1 + X • Y
distributivity(8)
X • 1 + X • Y
= X • (1 + Y)
identity (2)
X • (1 + Y)
= X •(1)
identity (1D)
X • (1)
= X �
(X + Y)' = X' • Y'
NOR is equivalent to AND
with inputs complemented
(X • Y)' = X' + Y'
NAND is equivalent to OR
with inputs complemented
XY
X'Y'
(X + Y)'
X' • Y'
00
11
01
10
10
01
11
00
XY
X'Y'
(X • Y)'
X' + Y'
00
11
01
10
10
01
11
00
Pro
vin
g t
heo
rem
s (
perf
ect
ind
ucti
on
)•
De M
org
an
’s L
aw
–co
mp
lete
tru
th t
ab
le,
exh
au
sti
ve p
roo
f
1 0 0 0 1 1 1 0
1 0 0 0 1 1 1 0
=
=
Pu
sh
in
v.
bu
bb
le f
rom
ou
tpu
t to
in
pu
t an
d c
han
ge s
ym
bo
l
A s
imp
le e
xam
ple
•1-b
it b
inary
ad
der
–in
pu
ts:
A,
B,
Carr
y-i
n
–o
utp
uts
: S
um
, C
arr
y-o
ut
A B
Cin
Cout
S
AB
CinS
Cout
00
00
01
01
00
11
10
01
01
11
01
11
0 1 1 0 1 0 0 1
0 0 0 1 0 1 1 1
Cout= A' B Cin+ A B' Cin+ A B Cin' + A B Cin
S = A' B' Cin+ A' B Cin' + A B' Cin' + A B Cin
Ap
ply
th
e t
heo
rem
s t
o s
imp
lify
exp
ressio
ns
•T
he t
heo
rem
s o
f B
oo
lean
alg
eb
ra c
an
sim
plify
B
oo
lean
exp
res
sio
ns
–e.g
., f
ull a
dd
er'
s c
arr
y-o
ut
fun
cti
on
(sam
e r
ule
s a
pp
ly t
o a
ny
fun
cti
on
)
Cout
= A' B Cin+ A B' Cin+ A B Cin' + A B Cin
= A' B Cin+ A B' Cin+ A B Cin' + A B Cin
+ A B Cin
= A' B Cin+ A B Cin
+ A B' Cin+ A B Cin' + A B Cin
= (A' + A) B Cin
+ A B' Cin+ A B Cin' + A B Cin
= (1)B Cin
+ A B' Cin+ A B Cin' + A B Cin
= B Cin
+ A B' Cin+ A B Cin' + A B Cin+ A B Cin
= B Cin+ A B' Cin+ A B Cin+ A B Cin' + A B Cin
= B Cin+ A (B' + B) Cin
+ A B Cin' + A B Cin
= B Cin+ A (1) Cin
+ A B Cin' + A B Cin
= B Cin+ A Cin+ A B (Cin' + Cin)
= B Cin+ A Cin+ A B (1)
= B Cin+ A Cin+ A B
time
change in Y takes time to "propagate" through gates
Wavefo
rm v
iew
of
log
ic f
un
cti
on
s
•Ju
st
a s
idew
ays t
ruth
tab
le–
bu
t n
ote
ho
w e
dg
es d
on
't lin
e u
p e
xactl
y
–it
takes t
ime f
or
a g
ate
to
sw
itch
its
ou
tpu
t!
AB
CZ
00
00
00
11
01
00
01
11
10
00
10
11
11
01
11
10
Ch
oo
sin
g d
iffe
ren
t re
alizati
on
s o
f a
fun
cti
on
two-level realization
(we don't count NOT gates)
XOR gate (easier to draw
but costlier to build)
multi-level realization
(gates with fewer inputs)
Wh
ich
realizati
on
is b
est?
•R
ed
uc
e n
um
ber
of
inp
uts
–li
tera
l: i
np
ut
vari
ab
le (
co
mp
lem
en
ted
or
no
t)
»can
ap
pro
xim
ate
co
st
of
log
ic g
ate
as 2
tra
nsis
tors
per
lite
ral
»w
hy n
ot
co
un
t in
vert
ers
?
–F
ew
er
lite
rals
mean
s l
ess t
ran
sis
tors
»sm
all
er
cir
cu
its
–F
ew
er
inp
uts
im
pli
es f
aste
r g
ate
s
»g
ate
s a
re s
ma
ller
an
d t
hu
s a
lso
faste
r
–F
an
-in
s (
# o
f g
ate
in
pu
ts)
are
lim
ited
in
so
me t
ech
no
log
ies
•R
ed
uc
e n
um
ber
of
gate
s–
Few
er
gate
s (
an
d t
he p
ackag
es t
hey c
om
e i
n)
mean
s s
mall
er
cir
cu
its
»d
irectl
y i
nfl
uen
ces m
an
ufa
ctu
rin
g c
osts
Wh
ich
is t
he b
est
realizati
on
?
(co
nt’
d)
•R
ed
uc
e n
um
ber
of
levels
of
gate
s–
Few
er
level
of
gate
s i
mp
lies r
ed
uced
sig
nal
pro
pag
ati
on
d
ela
ys
–M
inim
um
dela
y c
on
fig
ura
tio
n t
yp
icall
y r
eq
uir
es m
ore
gate
s
»w
ider,
less d
eep
cir
cu
its
•H
ow
do
we e
xp
lore
tra
deo
ffs b
etw
een
in
cre
as
ed
cir
cu
it d
ela
y a
nd
siz
e?
–A
uto
mate
d t
oo
ls t
o g
en
era
te d
iffe
ren
t so
luti
on
s
–L
og
ic m
inim
izati
on
: re
du
ce n
um
ber
of
gate
s a
nd
co
mp
lexit
y
–L
og
ic o
pti
miz
ati
on
: re
du
cti
on
wh
ile t
rad
ing
off
ag
ain
st
dela
y
Are
all r
ealizati
on
s e
qu
ivale
nt?
•U
nd
er
the s
am
e i
np
uts
, th
e a
ltern
ati
ve i
mp
lem
en
tati
on
s
have a
lmo
st
the s
am
e w
avefo
rm b
eh
avio
r–
dela
ys a
re d
iffe
ren
t
–g
litc
hes (
hazard
s)
ma
y a
ris
e
–va
riati
on
s d
ue t
o d
iffe
ren
ce
s i
n n
um
ber
of
gate
le
vels
an
d s
tru
ctu
re
•T
hre
e i
mp
lem
en
tati
on
s a
re f
un
cti
on
ally e
qu
ivale
nt
Imp
lem
en
tin
g B
oo
lean
fu
ncti
on
s
•T
ech
no
log
y i
nd
ep
en
den
t–
Can
on
ical
form
s
–T
wo
-le
vel
form
s
–M
ult
i-le
vel
form
s
•T
ech
no
log
y c
ho
ices
–P
ackag
es o
f a f
ew
gate
s
–R
eg
ula
r lo
gic
–T
wo
-le
vel
pro
gra
mm
ab
le l
og
ic
–M
ult
i-le
vel
pro
gra
mm
ab
le l
og
ic
Can
on
ical fo
rms
•T
ruth
tab
le i
s t
he u
niq
ue s
ign
atu
re o
f a B
oo
lean
fu
ncti
on
•M
an
y a
ltern
ati
ve g
ate
reali
zati
on
s m
ay h
ave t
he
sam
e t
ruth
tab
le
•C
an
on
ical fo
rms
–S
tan
dard
fo
rms f
or
a B
oo
lean
exp
res
sio
n
–P
rovid
es a
un
iqu
e a
lgeb
raic
sig
natu
re
AB
CF
F'
00
00
10
01
10
01
00
10
11
10
10
00
11
01
10
11
01
01
11
10
F = F' = A'B'C' + A'BC' + AB'C'
Su
m-o
f-p
rod
ucts
can
on
ical fo
rms
•A
lso
kn
ow
n a
s d
isju
ncti
ve n
orm
al
form
•A
lso
kn
ow
n a
s m
inte
rmexp
an
sio
n
F = 001 011 101 110 111
+ A'BC+ AB'C+ ABC'+ ABC
A'B'C
short-hand notation for
mintermsof 3 variables
AB
Cminterms
00
0A'B'C'm0
00
1A'B'C
m1
01
0A'BC'm2
01
1A'BC
m3
10
0AB'C'm4
10
1AB'C
m5
11
0ABC'm6
11
1ABC
m7
F in canonical form
:
F(A, B, C)=
Σm(1,3,5,6,7)
= m1 + m3 + m5 + m6 + m7
= A'B'C + A'BC + AB'C + ABC' + ABC
canonical form
≠minimal form
F(A, B, C)= A'B'C + A'BC + AB'C + ABC + ABC'
= (A'B' + A'B + AB' + AB)C + ABC'
= ((A' + A)(B' + B))C + ABC'
= C + ABC'
= ABC' + C
= AB + C
Su
m-o
f-p
rod
uc
ts c
an
on
ica
l fo
rm (
co
nt’
d)
•P
rod
uct
term
(o
r m
inte
rm)
–A
ND
ed
pro
du
ct
of
lite
rals
–in
pu
t co
mb
inati
on
fo
r w
hic
h o
utp
ut
is t
rue
–E
ach
va
riab
le a
pp
ears
ex
actl
y o
nce,
in t
rue o
r in
vert
ed
fo
rm (
bu
t n
ot
bo
th)
AB
CF
F'
00
00
10
01
10
01
00
10
11
10
10
00
11
01
10
11
01
01
11
10
F = 000 010 100
F =
F' = (A +
B +
C') (A +
B' + C') (A' + B +
C') (A' + B' + C) (A' + B' + C')
Pro
du
ct-
of-
su
ms c
an
on
ical fo
rm
•A
lso
kn
ow
n a
s c
on
jun
cti
ve n
orm
al
form
•A
lso
kn
ow
n a
s m
axte
rmexp
an
sio
n
(A + B + C)(A + B' + C)(A' + B + C)
AB
Cmaxterms
00
0A+B+C
M0
00
1A+B+C'
M1
01
0A+B'+C
M2
01
1A+B'+C'
M3
10
0A'+B+C
M4
10
1A'+B+C'
M5
11
0A'+B'+C
M6
11
1A'+B'+C'
M7
short-hand notation for
maxtermsof 3 variables
F in canonical form:
F(A, B, C)=
ΠM(0,2,4)
= M0 • M2 • M4
= (A + B + C) (A + B' + C) (A' + B + C)
canonical form
≠minimal form
F(A, B, C)= (A + B + C) (A + B' + C) (A' + B + C)
= (A + B + C) (A + B' + C)
(A + B + C) (A' + B + C)
= (A + C) (B + C)
Pro
du
ct-
of-
su
ms c
an
on
ical fo
rm (
co
nt’
d)
•S
um
term
(o
r m
axte
rm)
–O
Red
su
m o
f lite
rals
–in
pu
t co
mb
inati
on
fo
r w
hic
h o
utp
ut
is f
als
e
–each
vari
ab
le a
pp
ears
ex
actl
y o
nce,
in t
rue o
r in
vert
ed
fo
rm (
bu
t n
ot
bo
th)
S-o
-P, P
-o-S
, an
d d
e M
org
an
’s t
heo
rem
•S
um
-of-
pro
du
cts
–F
' =
A'B
'C' +
A'B
C' +
AB
'C'
•A
pp
ly d
e M
org
an
's–
(F')
' =
(A
'B'C
' +
A'B
C' +
AB
'C')
'
–F
= (
A +
B +
C)
(A +
B' +
C)
(A' +
B +
C)
•P
rod
uct-
of-
su
ms
–F
' =
(A
+ B
+ C
') (
A +
B' +
C')
(A
' +
B +
C')
(A
' +
B' +
C)
(A' +
B' +
C')
•A
pp
ly d
e M
org
an
's–
(F')
' =
( (
A +
B +
C')
(A +
B' +
C')
(A' +
B +
C')
(A' +
B' +
C)(
A'+
B' +
C')
)'
–F
= A
'B'C
+ A
'BC
+ A
B'C
+ A
BC
' +
AB
C
canonical sum-of-products
minimized sum-of-products
canonical product-of-sums
minimized product-of-sums
F1
F2
F3
BA C
F4
Fo
ur
alt
ern
ati
ve t
wo
-level im
ple
men
tati
on
so
f F
= A
B +
C
Wavefo
rms f
or
the f
ou
r alt
ern
ati
ves
•W
avefo
rms a
re e
ss
en
tiall
y i
den
tical
–E
xcep
t fo
r ti
min
g h
azard
s (
gli
tch
es)
–D
ela
ys a
lmo
st
iden
tical
(mo
dele
d a
s a
dela
y p
er
level,
no
t ty
pe
of
gate
or
nu
mb
er
of
inp
uts
to
gate
)
Map
pin
g b
etw
een
can
on
ical fo
rms
•M
inte
rmto
maxte
rmco
nvers
ion
–U
se m
axte
rms
wh
ose i
nd
ices d
o n
ot
ap
pear
in m
inte
rmexp
an
sio
n
–e.g
., F
(A,B
,C)
= Σ ΣΣΣ
m(1
,3,5
,6,7
) =
Π ΠΠΠM
(0,2
,4)
•M
axte
rmto
min
term
co
nvers
ion
–U
se m
inte
rms
wh
ose in
dic
es d
o n
ot
ap
pear
in m
axte
rmexp
an
sio
n
–e.g
., F
(A,B
,C)
= Π ΠΠΠ
M(0
,2,4
) =
Σ ΣΣΣm
(1,3
,5,6
,7)
•M
inte
rmexp
an
sio
n o
f F
to
min
term
exp
an
sio
n o
f F
'–
Use m
inte
rms
wh
ose in
dic
es d
o n
ot
ap
pear
–e.g
., F
(A,B
,C)
= Σ ΣΣΣ
m(1
,3,5
,6,7
) F
'(A
,B,C
) =
Σ ΣΣΣm
(0,2
,4)
•M
axte
rme
xp
an
sio
n o
f F
to
maxte
rmexp
an
sio
n o
f F
'–
Use m
axte
rms
wh
ose i
nd
ices d
o n
ot
ap
pear
–e.g
., F
(A,B
,C)
= Π ΠΠΠ
M(0
,2,4
) F
'(A
,B,C
) =
Π ΠΠΠM
(1,3
,5,6
,7)
AB
CD
WX Y
Z0
00
00
00
10
00
10
01
00
01
00
01
10
01
10
10
00
10
00
10
10
10
10
11
00
11
00
11
10
11
11
00
01
00
01
00
11
00
10
00
01
01
0X
XX
X1
01
1X
XX
X1
10
0X
XX
X1
10
1X
XX
X1
11
0X
XX
X1
11
1X
XX
X
off-set of W
these inputs patterns should
never be encountered in practice
–"don't care"about associated
output values, can be exploited
in minimization
Inco
mp
lete
ley
sp
ecif
ied
fu
ncti
on
s
•E
xam
ple
: b
inary
co
ded
decim
al in
cre
men
t b
y 1
–B
CD
dig
its e
nco
de d
ecim
al
dig
its 0
–9 in
bit
patt
ern
s 0
000 –
10
01
don't care (DC) set of W
on-set of W
No
tati
on
fo
r in
co
mp
lete
ly s
pecif
ied
fu
ncti
on
s
•D
on
't c
are
s a
nd
can
on
ical fo
rms
–S
o f
ar,
on
ly r
ep
resen
ted
on
-set
–A
lso
rep
resen
t d
on
't-c
are
-set
–N
eed
tw
o o
f th
e t
hre
e s
ets
(o
n-s
et,
off
-set,
dc-s
et)
•C
an
on
ical re
pre
sen
tati
on
s o
f th
e B
CD
in
cre
men
t b
y 1
fu
ncti
on
:
–Z
= m
0 +
m2 +
m4 +
m6 +
m8 +
d10 +
d11 +
d12 +
d13 +
d14 +
d15
–Z
= Σ ΣΣΣ
[ m
(0,2
,4,6
,8)
+ d
(10,1
1,1
2,1
3,1
4,1
5)
]
–Z
= M
1 •
M3 •
M5 •
M7 •
M9 •
D10 •
D11 •
D12 •
D13 •
D14 •
D15
–Z
= Π ΠΠΠ
[ M
(1,3
,5,7
,9)
• D
(10,1
1,1
2,1
3,1
4,1
5)
]
Sim
plifi
cati
on
of
two
-level co
mb
. lo
gic
•F
ind
ing
a m
inim
al su
m o
f p
rod
ucts
or
pro
du
ct
of
su
ms r
eali
zati
on
–E
xp
loit
do
n't
care
in
form
ati
on
in
th
e p
rocess
•A
lgeb
raic
sim
plifi
cati
on
–N
ot
an
alg
ori
thm
ic/s
yste
ma
tic p
roced
ure
–H
ow
do
yo
u k
no
w w
hen
th
e m
inim
um
reali
zati
on
has b
een
fo
un
d?
•C
om
pu
ter-
aid
ed
desig
n t
oo
ls–
Pre
cis
e s
olu
tio
ns r
eq
uir
e v
ery
lo
ng
co
mp
uta
tio
n t
imes,
esp
ecia
lly
for
fun
cti
on
s w
ith
man
y i
np
uts
(>
10)
–H
eu
risti
c m
eth
od
s e
mp
loyed
–"e
du
cate
d g
uesses"
to r
ed
uce
am
ou
nt
of
co
mp
uta
tio
n a
nd
yie
ld g
oo
d i
f n
ot
best
so
luti
on
s
•H
an
d m
eth
od
s s
till r
ele
van
t–
To
un
ders
tan
d a
uto
mati
c t
oo
ls a
nd
th
eir
str
en
gth
s a
nd
w
eakn
esses
–A
bil
ity t
o c
he
ck r
esu
lts (
on
sm
all
exam
ple
s)
Co
mb
inati
on
al lo
gic
su
mm
ary
•L
og
ic f
un
cti
on
s, tr
uth
tab
les,
an
d s
wit
ch
es
–N
OT
, A
ND
, O
R,
NA
ND
, N
OR
, X
OR
, . . .,
min
imal
set
•A
xio
ms a
nd
th
eo
rem
s o
f B
oo
lean
alg
eb
ra–
Pro
ofs
by r
e-w
riti
ng
an
d p
erf
ect
ind
ucti
on
•G
ate
lo
gic
–N
etw
ork
s o
f B
oo
lean
fu
ncti
on
s a
nd
th
eir
tim
e b
eh
avio
r
•C
an
on
ical fo
rms
–T
wo
-le
vel
an
d i
nco
mp
lete
ly s
pecif
ied
fu
ncti
on
s
•L
ate
r–
Tw
o-l
evel
sim
pli
ficati
on
usin
g K
-map
s
–A
uto
mati
on
of
sim
pli
ficati
on
–M
ult
i-le
vel
log
ic
–D
esig
n c
ase s
tud
ies
–T
ime b
eh
avio
r
![Gates and Logic: From Transistors to Logic Gates and Logic ......Gates and Logic: From Transistors to Logic Gates and Logic Circuits [Weatherspoon, Bala, Bracy, and Sirer] Prof. Hakim](https://static.fdocuments.in/doc/165x107/5fa95cb6eb1af8231472f381/gates-and-logic-from-transistors-to-logic-gates-and-logic-gates-and-logic.jpg)
