Lecture 7 Overview of Design Flow
Transcript of Lecture 7 Overview of Design Flow
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Xuan ‘Silvia’ Zhang
Washington University in St. Louis
http://classes.engineering.wustl.edu/ese566/
Lecture 7
Overview of Design Flow
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Application Specific Integrated Circuit (ASIC) Type
• Full-custom
– transistors are hand-drawn
– best performance (although almost extinct)
– still using to optimized standard cell
• Gate Array (for small volumes)
– use sea of gates (mask-programmable gate arrays)
– FPGA (reconfigurable)
• Standard Cell
– only use standard cell from the library
– dominate design style for ASIC (what we are going to
use)
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Outline
Standard-Cell-Based Design
SoC-Platform-Based Design
Methodology Comparison
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Standard-Cell-Based Design
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Example Standard Cell
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Standard-Cell-Based Flow CAD Algorithms
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Front-End Flow
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Back-End Flow
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Older Standard-Cell ASICs
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Modern Standard-Cell ASICs
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Standard-Cell Libraries
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Standard-Cell Libraries
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Standard-Cell Library Characterization
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Standard-Cell Electrical Characterization
• Characterization computes cell parameters
– e.g. delay, output current
– depend on input variables, i.e. output load, input
skew, etc.
• Characterization is performed under conditions
– combination of process, voltage, temperature (PVT)
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ST Microelectronics: 3-Input NAND Gate
• C = load capacitance
• T = input rise/fall time
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Standard-Cell Electrical Characterization (.lib)
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Standard-Cell Electrical Characterization (.lib)
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Standard-Cell Electrical Characterization (.lib)
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Standard-Cell Physical Characterization
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SAED 90nm Library: NAND Gate Data Sheet
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Outline
Standard-Cell-Based Design
SoC-Platform-Based Design
Methodology Comparison
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System-on-Chip (SoC) Platform-Based Design
• Integration
– standard cell block
– custom analog
– processor
– memory
• Standardized Bus
– AMBA, Sonics, …
• IP Business Model
– hard or soft IP from
3rd party provider
– e.g. ARM
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SoC Hardware/Software Co-Design
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SoC Hardware/Software Co-Design
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SoC Platform-Based Design
• Platform allows restriction
on design space
– limit implementation choice
– provide well-defined
abstraction of the underlying
technology for app developer
• New platform
– at architecture and micro-
architecture boundary
• Representation of
communication
– key to the platform design
approach
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Outline
Standard-Cell-Based Design
SoC-Platform-Based Design
Methodology Comparison
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Operation Binding Time
• Earlier the operation is bound, the less area,
delay, and energy required for implementation
• Later the operation is bound, the more flexible
the device
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Comparison of Specific Design Methodologies
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ASIC vs. FPGA
• Traditional Argument
– ASIC: high NRE ($2M for 0.35um),
low marginal cost, best efficiency
– FPGA: low NRE, high marginal
cost, lower efficiency
– crossover point: ~10,000
• Current Trends
– ASIC: increasing NRE ($40M for
90nm) due to design, verification,
and mask costs, etc.
– FPGA: better able to track
Moore’s law integrating fixed
function blocks
– crossover point: ~100,000
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Scale: ASIC with Pre-Placement & SRAMs
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T0: Full Custom with Standard Cells
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ASIC and Full Custom with Standard Cell
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Xilinx Vertex-II Pro: FPGA with Hard Processor
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Altera HardCopy: FPGA to Gate-Array-Like Tapeout
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Multi-Chip System: BrainSoC and PEU in RoboBee
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Design Principle in Automated Methodologies
• Modularity
– to enable mixing different custom and automated methods
• Hierarchy
– to efficiently handle automatically transforming large design
• Encapsulation
– significant higher emphasis on encapsulation in all domains
(behavioral, structural, physical) at all level of abstraction
(architecture, RTL, and gate-level)
• Regularity
– to create automated tools to generate structures like
datapaths and memories
• Extensibility
– automated methodologies enable more highly parameterized
and flexible implementation improving extensibility
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Questions?
Comments?
Discussion?
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Acknowledgement
Cornell University, ECE 5745
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